Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drm_irq.h>
35 #include <drm/drm_drv.h>
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "intel_drv.h"
40
41 /**
42  * DOC: interrupt handling
43  *
44  * These functions provide the basic support for enabling and disabling the
45  * interrupt handling support. There's a lot more functionality in i915_irq.c
46  * and related files, but that will be described in separate chapters.
47  */
48
49 static const u32 hpd_ilk[HPD_NUM_PINS] = {
50         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
51 };
52
53 static const u32 hpd_ivb[HPD_NUM_PINS] = {
54         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
55 };
56
57 static const u32 hpd_bdw[HPD_NUM_PINS] = {
58         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
59 };
60
61 static const u32 hpd_ibx[HPD_NUM_PINS] = {
62         [HPD_CRT] = SDE_CRT_HOTPLUG,
63         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
64         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
65         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
66         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
67 };
68
69 static const u32 hpd_cpt[HPD_NUM_PINS] = {
70         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
71         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
72         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
73         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
74         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
75 };
76
77 static const u32 hpd_spt[HPD_NUM_PINS] = {
78         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
79         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
80         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
81         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
82         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
83 };
84
85 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
86         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
87         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
88         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
89         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
90         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
91         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
92 };
93
94 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
95         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
96         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
97         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
98         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
99         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
100         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
101 };
102
103 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
104         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
105         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
106         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
107         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
108         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
109         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
110 };
111
112 /* BXT hpd list */
113 static const u32 hpd_bxt[HPD_NUM_PINS] = {
114         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
115         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
116         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
117 };
118
119 static const u32 hpd_gen11[HPD_NUM_PINS] = {
120         [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
121         [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
122         [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
123         [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
124 };
125
126 static const u32 hpd_icp[HPD_NUM_PINS] = {
127         [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
128         [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
129         [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
130         [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
131         [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
132         [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
133 };
134
135 /* IIR can theoretically queue up two events. Be paranoid. */
136 #define GEN8_IRQ_RESET_NDX(type, which) do { \
137         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
138         POSTING_READ(GEN8_##type##_IMR(which)); \
139         I915_WRITE(GEN8_##type##_IER(which), 0); \
140         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
141         POSTING_READ(GEN8_##type##_IIR(which)); \
142         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
143         POSTING_READ(GEN8_##type##_IIR(which)); \
144 } while (0)
145
146 #define GEN3_IRQ_RESET(type) do { \
147         I915_WRITE(type##IMR, 0xffffffff); \
148         POSTING_READ(type##IMR); \
149         I915_WRITE(type##IER, 0); \
150         I915_WRITE(type##IIR, 0xffffffff); \
151         POSTING_READ(type##IIR); \
152         I915_WRITE(type##IIR, 0xffffffff); \
153         POSTING_READ(type##IIR); \
154 } while (0)
155
156 #define GEN2_IRQ_RESET(type) do { \
157         I915_WRITE16(type##IMR, 0xffff); \
158         POSTING_READ16(type##IMR); \
159         I915_WRITE16(type##IER, 0); \
160         I915_WRITE16(type##IIR, 0xffff); \
161         POSTING_READ16(type##IIR); \
162         I915_WRITE16(type##IIR, 0xffff); \
163         POSTING_READ16(type##IIR); \
164 } while (0)
165
166 /*
167  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
168  */
169 static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv,
170                                     i915_reg_t reg)
171 {
172         u32 val = I915_READ(reg);
173
174         if (val == 0)
175                 return;
176
177         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
178              i915_mmio_reg_offset(reg), val);
179         I915_WRITE(reg, 0xffffffff);
180         POSTING_READ(reg);
181         I915_WRITE(reg, 0xffffffff);
182         POSTING_READ(reg);
183 }
184
185 static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv,
186                                     i915_reg_t reg)
187 {
188         u16 val = I915_READ16(reg);
189
190         if (val == 0)
191                 return;
192
193         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
194              i915_mmio_reg_offset(reg), val);
195         I915_WRITE16(reg, 0xffff);
196         POSTING_READ16(reg);
197         I915_WRITE16(reg, 0xffff);
198         POSTING_READ16(reg);
199 }
200
201 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
202         gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
203         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
204         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
205         POSTING_READ(GEN8_##type##_IMR(which)); \
206 } while (0)
207
208 #define GEN3_IRQ_INIT(type, imr_val, ier_val) do { \
209         gen3_assert_iir_is_zero(dev_priv, type##IIR); \
210         I915_WRITE(type##IER, (ier_val)); \
211         I915_WRITE(type##IMR, (imr_val)); \
212         POSTING_READ(type##IMR); \
213 } while (0)
214
215 #define GEN2_IRQ_INIT(type, imr_val, ier_val) do { \
216         gen2_assert_iir_is_zero(dev_priv, type##IIR); \
217         I915_WRITE16(type##IER, (ier_val)); \
218         I915_WRITE16(type##IMR, (imr_val)); \
219         POSTING_READ16(type##IMR); \
220 } while (0)
221
222 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
223 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
224
225 /* For display hotplug interrupt */
226 static inline void
227 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
228                                      u32 mask,
229                                      u32 bits)
230 {
231         u32 val;
232
233         lockdep_assert_held(&dev_priv->irq_lock);
234         WARN_ON(bits & ~mask);
235
236         val = I915_READ(PORT_HOTPLUG_EN);
237         val &= ~mask;
238         val |= bits;
239         I915_WRITE(PORT_HOTPLUG_EN, val);
240 }
241
242 /**
243  * i915_hotplug_interrupt_update - update hotplug interrupt enable
244  * @dev_priv: driver private
245  * @mask: bits to update
246  * @bits: bits to enable
247  * NOTE: the HPD enable bits are modified both inside and outside
248  * of an interrupt context. To avoid that read-modify-write cycles
249  * interfer, these bits are protected by a spinlock. Since this
250  * function is usually not called from a context where the lock is
251  * held already, this function acquires the lock itself. A non-locking
252  * version is also available.
253  */
254 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
255                                    u32 mask,
256                                    u32 bits)
257 {
258         spin_lock_irq(&dev_priv->irq_lock);
259         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
260         spin_unlock_irq(&dev_priv->irq_lock);
261 }
262
263 static u32
264 gen11_gt_engine_identity(struct drm_i915_private * const i915,
265                          const unsigned int bank, const unsigned int bit);
266
267 static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
268                                 const unsigned int bank,
269                                 const unsigned int bit)
270 {
271         void __iomem * const regs = i915->regs;
272         u32 dw;
273
274         lockdep_assert_held(&i915->irq_lock);
275
276         dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
277         if (dw & BIT(bit)) {
278                 /*
279                  * According to the BSpec, DW_IIR bits cannot be cleared without
280                  * first servicing the Selector & Shared IIR registers.
281                  */
282                 gen11_gt_engine_identity(i915, bank, bit);
283
284                 /*
285                  * We locked GT INT DW by reading it. If we want to (try
286                  * to) recover from this succesfully, we need to clear
287                  * our bit, otherwise we are locking the register for
288                  * everybody.
289                  */
290                 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
291
292                 return true;
293         }
294
295         return false;
296 }
297
298 /**
299  * ilk_update_display_irq - update DEIMR
300  * @dev_priv: driver private
301  * @interrupt_mask: mask of interrupt bits to update
302  * @enabled_irq_mask: mask of interrupt bits to enable
303  */
304 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
305                             u32 interrupt_mask,
306                             u32 enabled_irq_mask)
307 {
308         u32 new_val;
309
310         lockdep_assert_held(&dev_priv->irq_lock);
311
312         WARN_ON(enabled_irq_mask & ~interrupt_mask);
313
314         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
315                 return;
316
317         new_val = dev_priv->irq_mask;
318         new_val &= ~interrupt_mask;
319         new_val |= (~enabled_irq_mask & interrupt_mask);
320
321         if (new_val != dev_priv->irq_mask) {
322                 dev_priv->irq_mask = new_val;
323                 I915_WRITE(DEIMR, dev_priv->irq_mask);
324                 POSTING_READ(DEIMR);
325         }
326 }
327
328 /**
329  * ilk_update_gt_irq - update GTIMR
330  * @dev_priv: driver private
331  * @interrupt_mask: mask of interrupt bits to update
332  * @enabled_irq_mask: mask of interrupt bits to enable
333  */
334 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
335                               u32 interrupt_mask,
336                               u32 enabled_irq_mask)
337 {
338         lockdep_assert_held(&dev_priv->irq_lock);
339
340         WARN_ON(enabled_irq_mask & ~interrupt_mask);
341
342         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
343                 return;
344
345         dev_priv->gt_irq_mask &= ~interrupt_mask;
346         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
347         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
348 }
349
350 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
351 {
352         ilk_update_gt_irq(dev_priv, mask, mask);
353         POSTING_READ_FW(GTIMR);
354 }
355
356 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
357 {
358         ilk_update_gt_irq(dev_priv, mask, 0);
359 }
360
361 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
362 {
363         WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
364
365         return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
366 }
367
368 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
369 {
370         if (INTEL_GEN(dev_priv) >= 11)
371                 return GEN11_GPM_WGBOXPERF_INTR_MASK;
372         else if (INTEL_GEN(dev_priv) >= 8)
373                 return GEN8_GT_IMR(2);
374         else
375                 return GEN6_PMIMR;
376 }
377
378 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
379 {
380         if (INTEL_GEN(dev_priv) >= 11)
381                 return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
382         else if (INTEL_GEN(dev_priv) >= 8)
383                 return GEN8_GT_IER(2);
384         else
385                 return GEN6_PMIER;
386 }
387
388 /**
389  * snb_update_pm_irq - update GEN6_PMIMR
390  * @dev_priv: driver private
391  * @interrupt_mask: mask of interrupt bits to update
392  * @enabled_irq_mask: mask of interrupt bits to enable
393  */
394 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
395                               u32 interrupt_mask,
396                               u32 enabled_irq_mask)
397 {
398         u32 new_val;
399
400         WARN_ON(enabled_irq_mask & ~interrupt_mask);
401
402         lockdep_assert_held(&dev_priv->irq_lock);
403
404         new_val = dev_priv->pm_imr;
405         new_val &= ~interrupt_mask;
406         new_val |= (~enabled_irq_mask & interrupt_mask);
407
408         if (new_val != dev_priv->pm_imr) {
409                 dev_priv->pm_imr = new_val;
410                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
411                 POSTING_READ(gen6_pm_imr(dev_priv));
412         }
413 }
414
415 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
416 {
417         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
418                 return;
419
420         snb_update_pm_irq(dev_priv, mask, mask);
421 }
422
423 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
424 {
425         snb_update_pm_irq(dev_priv, mask, 0);
426 }
427
428 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
429 {
430         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
431                 return;
432
433         __gen6_mask_pm_irq(dev_priv, mask);
434 }
435
436 static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
437 {
438         i915_reg_t reg = gen6_pm_iir(dev_priv);
439
440         lockdep_assert_held(&dev_priv->irq_lock);
441
442         I915_WRITE(reg, reset_mask);
443         I915_WRITE(reg, reset_mask);
444         POSTING_READ(reg);
445 }
446
447 static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
448 {
449         lockdep_assert_held(&dev_priv->irq_lock);
450
451         dev_priv->pm_ier |= enable_mask;
452         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
453         gen6_unmask_pm_irq(dev_priv, enable_mask);
454         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
455 }
456
457 static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
458 {
459         lockdep_assert_held(&dev_priv->irq_lock);
460
461         dev_priv->pm_ier &= ~disable_mask;
462         __gen6_mask_pm_irq(dev_priv, disable_mask);
463         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
464         /* though a barrier is missing here, but don't really need a one */
465 }
466
467 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
468 {
469         spin_lock_irq(&dev_priv->irq_lock);
470
471         while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
472                 ;
473
474         dev_priv->gt_pm.rps.pm_iir = 0;
475
476         spin_unlock_irq(&dev_priv->irq_lock);
477 }
478
479 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
480 {
481         spin_lock_irq(&dev_priv->irq_lock);
482         gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
483         dev_priv->gt_pm.rps.pm_iir = 0;
484         spin_unlock_irq(&dev_priv->irq_lock);
485 }
486
487 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
488 {
489         struct intel_rps *rps = &dev_priv->gt_pm.rps;
490
491         if (READ_ONCE(rps->interrupts_enabled))
492                 return;
493
494         spin_lock_irq(&dev_priv->irq_lock);
495         WARN_ON_ONCE(rps->pm_iir);
496
497         if (INTEL_GEN(dev_priv) >= 11)
498                 WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
499         else
500                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
501
502         rps->interrupts_enabled = true;
503         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
504
505         spin_unlock_irq(&dev_priv->irq_lock);
506 }
507
508 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
509 {
510         struct intel_rps *rps = &dev_priv->gt_pm.rps;
511
512         if (!READ_ONCE(rps->interrupts_enabled))
513                 return;
514
515         spin_lock_irq(&dev_priv->irq_lock);
516         rps->interrupts_enabled = false;
517
518         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
519
520         gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
521
522         spin_unlock_irq(&dev_priv->irq_lock);
523         synchronize_irq(dev_priv->drm.irq);
524
525         /* Now that we will not be generating any more work, flush any
526          * outstanding tasks. As we are called on the RPS idle path,
527          * we will reset the GPU to minimum frequencies, so the current
528          * state of the worker can be discarded.
529          */
530         cancel_work_sync(&rps->work);
531         if (INTEL_GEN(dev_priv) >= 11)
532                 gen11_reset_rps_interrupts(dev_priv);
533         else
534                 gen6_reset_rps_interrupts(dev_priv);
535 }
536
537 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
538 {
539         assert_rpm_wakelock_held(dev_priv);
540
541         spin_lock_irq(&dev_priv->irq_lock);
542         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
543         spin_unlock_irq(&dev_priv->irq_lock);
544 }
545
546 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
547 {
548         assert_rpm_wakelock_held(dev_priv);
549
550         spin_lock_irq(&dev_priv->irq_lock);
551         if (!dev_priv->guc.interrupts_enabled) {
552                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
553                                        dev_priv->pm_guc_events);
554                 dev_priv->guc.interrupts_enabled = true;
555                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
556         }
557         spin_unlock_irq(&dev_priv->irq_lock);
558 }
559
560 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
561 {
562         assert_rpm_wakelock_held(dev_priv);
563
564         spin_lock_irq(&dev_priv->irq_lock);
565         dev_priv->guc.interrupts_enabled = false;
566
567         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
568
569         spin_unlock_irq(&dev_priv->irq_lock);
570         synchronize_irq(dev_priv->drm.irq);
571
572         gen9_reset_guc_interrupts(dev_priv);
573 }
574
575 /**
576  * bdw_update_port_irq - update DE port interrupt
577  * @dev_priv: driver private
578  * @interrupt_mask: mask of interrupt bits to update
579  * @enabled_irq_mask: mask of interrupt bits to enable
580  */
581 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
582                                 u32 interrupt_mask,
583                                 u32 enabled_irq_mask)
584 {
585         u32 new_val;
586         u32 old_val;
587
588         lockdep_assert_held(&dev_priv->irq_lock);
589
590         WARN_ON(enabled_irq_mask & ~interrupt_mask);
591
592         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
593                 return;
594
595         old_val = I915_READ(GEN8_DE_PORT_IMR);
596
597         new_val = old_val;
598         new_val &= ~interrupt_mask;
599         new_val |= (~enabled_irq_mask & interrupt_mask);
600
601         if (new_val != old_val) {
602                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
603                 POSTING_READ(GEN8_DE_PORT_IMR);
604         }
605 }
606
607 /**
608  * bdw_update_pipe_irq - update DE pipe interrupt
609  * @dev_priv: driver private
610  * @pipe: pipe whose interrupt to update
611  * @interrupt_mask: mask of interrupt bits to update
612  * @enabled_irq_mask: mask of interrupt bits to enable
613  */
614 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
615                          enum pipe pipe,
616                          u32 interrupt_mask,
617                          u32 enabled_irq_mask)
618 {
619         u32 new_val;
620
621         lockdep_assert_held(&dev_priv->irq_lock);
622
623         WARN_ON(enabled_irq_mask & ~interrupt_mask);
624
625         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
626                 return;
627
628         new_val = dev_priv->de_irq_mask[pipe];
629         new_val &= ~interrupt_mask;
630         new_val |= (~enabled_irq_mask & interrupt_mask);
631
632         if (new_val != dev_priv->de_irq_mask[pipe]) {
633                 dev_priv->de_irq_mask[pipe] = new_val;
634                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
635                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
636         }
637 }
638
639 /**
640  * ibx_display_interrupt_update - update SDEIMR
641  * @dev_priv: driver private
642  * @interrupt_mask: mask of interrupt bits to update
643  * @enabled_irq_mask: mask of interrupt bits to enable
644  */
645 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
646                                   u32 interrupt_mask,
647                                   u32 enabled_irq_mask)
648 {
649         u32 sdeimr = I915_READ(SDEIMR);
650         sdeimr &= ~interrupt_mask;
651         sdeimr |= (~enabled_irq_mask & interrupt_mask);
652
653         WARN_ON(enabled_irq_mask & ~interrupt_mask);
654
655         lockdep_assert_held(&dev_priv->irq_lock);
656
657         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
658                 return;
659
660         I915_WRITE(SDEIMR, sdeimr);
661         POSTING_READ(SDEIMR);
662 }
663
664 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
665                               enum pipe pipe)
666 {
667         u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
668         u32 enable_mask = status_mask << 16;
669
670         lockdep_assert_held(&dev_priv->irq_lock);
671
672         if (INTEL_GEN(dev_priv) < 5)
673                 goto out;
674
675         /*
676          * On pipe A we don't support the PSR interrupt yet,
677          * on pipe B and C the same bit MBZ.
678          */
679         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
680                 return 0;
681         /*
682          * On pipe B and C we don't support the PSR interrupt yet, on pipe
683          * A the same bit is for perf counters which we don't use either.
684          */
685         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
686                 return 0;
687
688         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
689                          SPRITE0_FLIP_DONE_INT_EN_VLV |
690                          SPRITE1_FLIP_DONE_INT_EN_VLV);
691         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
692                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
693         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
694                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
695
696 out:
697         WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
698                   status_mask & ~PIPESTAT_INT_STATUS_MASK,
699                   "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
700                   pipe_name(pipe), enable_mask, status_mask);
701
702         return enable_mask;
703 }
704
705 void i915_enable_pipestat(struct drm_i915_private *dev_priv,
706                           enum pipe pipe, u32 status_mask)
707 {
708         i915_reg_t reg = PIPESTAT(pipe);
709         u32 enable_mask;
710
711         WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
712                   "pipe %c: status_mask=0x%x\n",
713                   pipe_name(pipe), status_mask);
714
715         lockdep_assert_held(&dev_priv->irq_lock);
716         WARN_ON(!intel_irqs_enabled(dev_priv));
717
718         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
719                 return;
720
721         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
722         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
723
724         I915_WRITE(reg, enable_mask | status_mask);
725         POSTING_READ(reg);
726 }
727
728 void i915_disable_pipestat(struct drm_i915_private *dev_priv,
729                            enum pipe pipe, u32 status_mask)
730 {
731         i915_reg_t reg = PIPESTAT(pipe);
732         u32 enable_mask;
733
734         WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
735                   "pipe %c: status_mask=0x%x\n",
736                   pipe_name(pipe), status_mask);
737
738         lockdep_assert_held(&dev_priv->irq_lock);
739         WARN_ON(!intel_irqs_enabled(dev_priv));
740
741         if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
742                 return;
743
744         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
745         enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
746
747         I915_WRITE(reg, enable_mask | status_mask);
748         POSTING_READ(reg);
749 }
750
751 /**
752  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
753  * @dev_priv: i915 device private
754  */
755 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
756 {
757         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
758                 return;
759
760         spin_lock_irq(&dev_priv->irq_lock);
761
762         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
763         if (INTEL_GEN(dev_priv) >= 4)
764                 i915_enable_pipestat(dev_priv, PIPE_A,
765                                      PIPE_LEGACY_BLC_EVENT_STATUS);
766
767         spin_unlock_irq(&dev_priv->irq_lock);
768 }
769
770 /*
771  * This timing diagram depicts the video signal in and
772  * around the vertical blanking period.
773  *
774  * Assumptions about the fictitious mode used in this example:
775  *  vblank_start >= 3
776  *  vsync_start = vblank_start + 1
777  *  vsync_end = vblank_start + 2
778  *  vtotal = vblank_start + 3
779  *
780  *           start of vblank:
781  *           latch double buffered registers
782  *           increment frame counter (ctg+)
783  *           generate start of vblank interrupt (gen4+)
784  *           |
785  *           |          frame start:
786  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
787  *           |          may be shifted forward 1-3 extra lines via PIPECONF
788  *           |          |
789  *           |          |  start of vsync:
790  *           |          |  generate vsync interrupt
791  *           |          |  |
792  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
793  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
794  * ----va---> <-----------------vb--------------------> <--------va-------------
795  *       |          |       <----vs----->                     |
796  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
797  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
798  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
799  *       |          |                                         |
800  *       last visible pixel                                   first visible pixel
801  *                  |                                         increment frame counter (gen3/4)
802  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
803  *
804  * x  = horizontal active
805  * _  = horizontal blanking
806  * hs = horizontal sync
807  * va = vertical active
808  * vb = vertical blanking
809  * vs = vertical sync
810  * vbs = vblank_start (number)
811  *
812  * Summary:
813  * - most events happen at the start of horizontal sync
814  * - frame start happens at the start of horizontal blank, 1-4 lines
815  *   (depending on PIPECONF settings) after the start of vblank
816  * - gen3/4 pixel and frame counter are synchronized with the start
817  *   of horizontal active on the first line of vertical active
818  */
819
820 /* Called from drm generic code, passed a 'crtc', which
821  * we use as a pipe index
822  */
823 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
824 {
825         struct drm_i915_private *dev_priv = to_i915(dev);
826         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
827         const struct drm_display_mode *mode = &vblank->hwmode;
828         i915_reg_t high_frame, low_frame;
829         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
830         unsigned long irqflags;
831
832         /*
833          * On i965gm TV output the frame counter only works up to
834          * the point when we enable the TV encoder. After that the
835          * frame counter ceases to work and reads zero. We need a
836          * vblank wait before enabling the TV encoder and so we
837          * have to enable vblank interrupts while the frame counter
838          * is still in a working state. However the core vblank code
839          * does not like us returning non-zero frame counter values
840          * when we've told it that we don't have a working frame
841          * counter. Thus we must stop non-zero values leaking out.
842          */
843         if (!vblank->max_vblank_count)
844                 return 0;
845
846         htotal = mode->crtc_htotal;
847         hsync_start = mode->crtc_hsync_start;
848         vbl_start = mode->crtc_vblank_start;
849         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
850                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
851
852         /* Convert to pixel count */
853         vbl_start *= htotal;
854
855         /* Start of vblank event occurs at start of hsync */
856         vbl_start -= htotal - hsync_start;
857
858         high_frame = PIPEFRAME(pipe);
859         low_frame = PIPEFRAMEPIXEL(pipe);
860
861         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
862
863         /*
864          * High & low register fields aren't synchronized, so make sure
865          * we get a low value that's stable across two reads of the high
866          * register.
867          */
868         do {
869                 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
870                 low   = I915_READ_FW(low_frame);
871                 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
872         } while (high1 != high2);
873
874         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
875
876         high1 >>= PIPE_FRAME_HIGH_SHIFT;
877         pixel = low & PIPE_PIXEL_MASK;
878         low >>= PIPE_FRAME_LOW_SHIFT;
879
880         /*
881          * The frame counter increments at beginning of active.
882          * Cook up a vblank counter by also checking the pixel
883          * counter against vblank start.
884          */
885         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
886 }
887
888 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
889 {
890         struct drm_i915_private *dev_priv = to_i915(dev);
891
892         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
893 }
894
895 /*
896  * On certain encoders on certain platforms, pipe
897  * scanline register will not work to get the scanline,
898  * since the timings are driven from the PORT or issues
899  * with scanline register updates.
900  * This function will use Framestamp and current
901  * timestamp registers to calculate the scanline.
902  */
903 static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
904 {
905         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
906         struct drm_vblank_crtc *vblank =
907                 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
908         const struct drm_display_mode *mode = &vblank->hwmode;
909         u32 vblank_start = mode->crtc_vblank_start;
910         u32 vtotal = mode->crtc_vtotal;
911         u32 htotal = mode->crtc_htotal;
912         u32 clock = mode->crtc_clock;
913         u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
914
915         /*
916          * To avoid the race condition where we might cross into the
917          * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
918          * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
919          * during the same frame.
920          */
921         do {
922                 /*
923                  * This field provides read back of the display
924                  * pipe frame time stamp. The time stamp value
925                  * is sampled at every start of vertical blank.
926                  */
927                 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
928
929                 /*
930                  * The TIMESTAMP_CTR register has the current
931                  * time stamp value.
932                  */
933                 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
934
935                 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
936         } while (scan_post_time != scan_prev_time);
937
938         scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
939                                         clock), 1000 * htotal);
940         scanline = min(scanline, vtotal - 1);
941         scanline = (scanline + vblank_start) % vtotal;
942
943         return scanline;
944 }
945
946 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
947 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
948 {
949         struct drm_device *dev = crtc->base.dev;
950         struct drm_i915_private *dev_priv = to_i915(dev);
951         const struct drm_display_mode *mode;
952         struct drm_vblank_crtc *vblank;
953         enum pipe pipe = crtc->pipe;
954         int position, vtotal;
955
956         if (!crtc->active)
957                 return -1;
958
959         vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
960         mode = &vblank->hwmode;
961
962         if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
963                 return __intel_get_crtc_scanline_from_timestamp(crtc);
964
965         vtotal = mode->crtc_vtotal;
966         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
967                 vtotal /= 2;
968
969         if (IS_GEN(dev_priv, 2))
970                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
971         else
972                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
973
974         /*
975          * On HSW, the DSL reg (0x70000) appears to return 0 if we
976          * read it just before the start of vblank.  So try it again
977          * so we don't accidentally end up spanning a vblank frame
978          * increment, causing the pipe_update_end() code to squak at us.
979          *
980          * The nature of this problem means we can't simply check the ISR
981          * bit and return the vblank start value; nor can we use the scanline
982          * debug register in the transcoder as it appears to have the same
983          * problem.  We may need to extend this to include other platforms,
984          * but so far testing only shows the problem on HSW.
985          */
986         if (HAS_DDI(dev_priv) && !position) {
987                 int i, temp;
988
989                 for (i = 0; i < 100; i++) {
990                         udelay(1);
991                         temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
992                         if (temp != position) {
993                                 position = temp;
994                                 break;
995                         }
996                 }
997         }
998
999         /*
1000          * See update_scanline_offset() for the details on the
1001          * scanline_offset adjustment.
1002          */
1003         return (position + crtc->scanline_offset) % vtotal;
1004 }
1005
1006 static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1007                                      bool in_vblank_irq, int *vpos, int *hpos,
1008                                      ktime_t *stime, ktime_t *etime,
1009                                      const struct drm_display_mode *mode)
1010 {
1011         struct drm_i915_private *dev_priv = to_i915(dev);
1012         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1013                                                                 pipe);
1014         int position;
1015         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
1016         unsigned long irqflags;
1017         bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
1018                 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
1019                 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1020
1021         if (WARN_ON(!mode->crtc_clock)) {
1022                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
1023                                  "pipe %c\n", pipe_name(pipe));
1024                 return false;
1025         }
1026
1027         htotal = mode->crtc_htotal;
1028         hsync_start = mode->crtc_hsync_start;
1029         vtotal = mode->crtc_vtotal;
1030         vbl_start = mode->crtc_vblank_start;
1031         vbl_end = mode->crtc_vblank_end;
1032
1033         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1034                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
1035                 vbl_end /= 2;
1036                 vtotal /= 2;
1037         }
1038
1039         /*
1040          * Lock uncore.lock, as we will do multiple timing critical raw
1041          * register reads, potentially with preemption disabled, so the
1042          * following code must not block on uncore.lock.
1043          */
1044         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1045
1046         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1047
1048         /* Get optional system timestamp before query. */
1049         if (stime)
1050                 *stime = ktime_get();
1051
1052         if (use_scanline_counter) {
1053                 /* No obvious pixelcount register. Only query vertical
1054                  * scanout position from Display scan line register.
1055                  */
1056                 position = __intel_get_crtc_scanline(intel_crtc);
1057         } else {
1058                 /* Have access to pixelcount since start of frame.
1059                  * We can split this into vertical and horizontal
1060                  * scanout position.
1061                  */
1062                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1063
1064                 /* convert to pixel counts */
1065                 vbl_start *= htotal;
1066                 vbl_end *= htotal;
1067                 vtotal *= htotal;
1068
1069                 /*
1070                  * In interlaced modes, the pixel counter counts all pixels,
1071                  * so one field will have htotal more pixels. In order to avoid
1072                  * the reported position from jumping backwards when the pixel
1073                  * counter is beyond the length of the shorter field, just
1074                  * clamp the position the length of the shorter field. This
1075                  * matches how the scanline counter based position works since
1076                  * the scanline counter doesn't count the two half lines.
1077                  */
1078                 if (position >= vtotal)
1079                         position = vtotal - 1;
1080
1081                 /*
1082                  * Start of vblank interrupt is triggered at start of hsync,
1083                  * just prior to the first active line of vblank. However we
1084                  * consider lines to start at the leading edge of horizontal
1085                  * active. So, should we get here before we've crossed into
1086                  * the horizontal active of the first line in vblank, we would
1087                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1088                  * always add htotal-hsync_start to the current pixel position.
1089                  */
1090                 position = (position + htotal - hsync_start) % vtotal;
1091         }
1092
1093         /* Get optional system timestamp after query. */
1094         if (etime)
1095                 *etime = ktime_get();
1096
1097         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1098
1099         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1100
1101         /*
1102          * While in vblank, position will be negative
1103          * counting up towards 0 at vbl_end. And outside
1104          * vblank, position will be positive counting
1105          * up since vbl_end.
1106          */
1107         if (position >= vbl_start)
1108                 position -= vbl_end;
1109         else
1110                 position += vtotal - vbl_end;
1111
1112         if (use_scanline_counter) {
1113                 *vpos = position;
1114                 *hpos = 0;
1115         } else {
1116                 *vpos = position / htotal;
1117                 *hpos = position - (*vpos * htotal);
1118         }
1119
1120         return true;
1121 }
1122
1123 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1124 {
1125         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1126         unsigned long irqflags;
1127         int position;
1128
1129         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1130         position = __intel_get_crtc_scanline(crtc);
1131         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1132
1133         return position;
1134 }
1135
1136 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1137 {
1138         u32 busy_up, busy_down, max_avg, min_avg;
1139         u8 new_delay;
1140
1141         spin_lock(&mchdev_lock);
1142
1143         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1144
1145         new_delay = dev_priv->ips.cur_delay;
1146
1147         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1148         busy_up = I915_READ(RCPREVBSYTUPAVG);
1149         busy_down = I915_READ(RCPREVBSYTDNAVG);
1150         max_avg = I915_READ(RCBMAXAVG);
1151         min_avg = I915_READ(RCBMINAVG);
1152
1153         /* Handle RCS change request from hw */
1154         if (busy_up > max_avg) {
1155                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1156                         new_delay = dev_priv->ips.cur_delay - 1;
1157                 if (new_delay < dev_priv->ips.max_delay)
1158                         new_delay = dev_priv->ips.max_delay;
1159         } else if (busy_down < min_avg) {
1160                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1161                         new_delay = dev_priv->ips.cur_delay + 1;
1162                 if (new_delay > dev_priv->ips.min_delay)
1163                         new_delay = dev_priv->ips.min_delay;
1164         }
1165
1166         if (ironlake_set_drps(dev_priv, new_delay))
1167                 dev_priv->ips.cur_delay = new_delay;
1168
1169         spin_unlock(&mchdev_lock);
1170
1171         return;
1172 }
1173
1174 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1175                         struct intel_rps_ei *ei)
1176 {
1177         ei->ktime = ktime_get_raw();
1178         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1179         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1180 }
1181
1182 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1183 {
1184         memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1185 }
1186
1187 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1188 {
1189         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1190         const struct intel_rps_ei *prev = &rps->ei;
1191         struct intel_rps_ei now;
1192         u32 events = 0;
1193
1194         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1195                 return 0;
1196
1197         vlv_c0_read(dev_priv, &now);
1198
1199         if (prev->ktime) {
1200                 u64 time, c0;
1201                 u32 render, media;
1202
1203                 time = ktime_us_delta(now.ktime, prev->ktime);
1204
1205                 time *= dev_priv->czclk_freq;
1206
1207                 /* Workload can be split between render + media,
1208                  * e.g. SwapBuffers being blitted in X after being rendered in
1209                  * mesa. To account for this we need to combine both engines
1210                  * into our activity counter.
1211                  */
1212                 render = now.render_c0 - prev->render_c0;
1213                 media = now.media_c0 - prev->media_c0;
1214                 c0 = max(render, media);
1215                 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1216
1217                 if (c0 > time * rps->power.up_threshold)
1218                         events = GEN6_PM_RP_UP_THRESHOLD;
1219                 else if (c0 < time * rps->power.down_threshold)
1220                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1221         }
1222
1223         rps->ei = now;
1224         return events;
1225 }
1226
1227 static void gen6_pm_rps_work(struct work_struct *work)
1228 {
1229         struct drm_i915_private *dev_priv =
1230                 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1231         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1232         bool client_boost = false;
1233         int new_delay, adj, min, max;
1234         u32 pm_iir = 0;
1235
1236         spin_lock_irq(&dev_priv->irq_lock);
1237         if (rps->interrupts_enabled) {
1238                 pm_iir = fetch_and_zero(&rps->pm_iir);
1239                 client_boost = atomic_read(&rps->num_waiters);
1240         }
1241         spin_unlock_irq(&dev_priv->irq_lock);
1242
1243         /* Make sure we didn't queue anything we're not going to process. */
1244         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1245         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1246                 goto out;
1247
1248         mutex_lock(&dev_priv->pcu_lock);
1249
1250         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1251
1252         adj = rps->last_adj;
1253         new_delay = rps->cur_freq;
1254         min = rps->min_freq_softlimit;
1255         max = rps->max_freq_softlimit;
1256         if (client_boost)
1257                 max = rps->max_freq;
1258         if (client_boost && new_delay < rps->boost_freq) {
1259                 new_delay = rps->boost_freq;
1260                 adj = 0;
1261         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1262                 if (adj > 0)
1263                         adj *= 2;
1264                 else /* CHV needs even encode values */
1265                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1266
1267                 if (new_delay >= rps->max_freq_softlimit)
1268                         adj = 0;
1269         } else if (client_boost) {
1270                 adj = 0;
1271         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1272                 if (rps->cur_freq > rps->efficient_freq)
1273                         new_delay = rps->efficient_freq;
1274                 else if (rps->cur_freq > rps->min_freq_softlimit)
1275                         new_delay = rps->min_freq_softlimit;
1276                 adj = 0;
1277         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1278                 if (adj < 0)
1279                         adj *= 2;
1280                 else /* CHV needs even encode values */
1281                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1282
1283                 if (new_delay <= rps->min_freq_softlimit)
1284                         adj = 0;
1285         } else { /* unknown event */
1286                 adj = 0;
1287         }
1288
1289         rps->last_adj = adj;
1290
1291         /*
1292          * Limit deboosting and boosting to keep ourselves at the extremes
1293          * when in the respective power modes (i.e. slowly decrease frequencies
1294          * while in the HIGH_POWER zone and slowly increase frequencies while
1295          * in the LOW_POWER zone). On idle, we will hit the timeout and drop
1296          * to the next level quickly, and conversely if busy we expect to
1297          * hit a waitboost and rapidly switch into max power.
1298          */
1299         if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
1300             (adj > 0 && rps->power.mode == LOW_POWER))
1301                 rps->last_adj = 0;
1302
1303         /* sysfs frequency interfaces may have snuck in while servicing the
1304          * interrupt
1305          */
1306         new_delay += adj;
1307         new_delay = clamp_t(int, new_delay, min, max);
1308
1309         if (intel_set_rps(dev_priv, new_delay)) {
1310                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1311                 rps->last_adj = 0;
1312         }
1313
1314         mutex_unlock(&dev_priv->pcu_lock);
1315
1316 out:
1317         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1318         spin_lock_irq(&dev_priv->irq_lock);
1319         if (rps->interrupts_enabled)
1320                 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1321         spin_unlock_irq(&dev_priv->irq_lock);
1322 }
1323
1324
1325 /**
1326  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1327  * occurred.
1328  * @work: workqueue struct
1329  *
1330  * Doesn't actually do anything except notify userspace. As a consequence of
1331  * this event, userspace should try to remap the bad rows since statistically
1332  * it is likely the same row is more likely to go bad again.
1333  */
1334 static void ivybridge_parity_work(struct work_struct *work)
1335 {
1336         struct drm_i915_private *dev_priv =
1337                 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1338         u32 error_status, row, bank, subbank;
1339         char *parity_event[6];
1340         u32 misccpctl;
1341         u8 slice = 0;
1342
1343         /* We must turn off DOP level clock gating to access the L3 registers.
1344          * In order to prevent a get/put style interface, acquire struct mutex
1345          * any time we access those registers.
1346          */
1347         mutex_lock(&dev_priv->drm.struct_mutex);
1348
1349         /* If we've screwed up tracking, just let the interrupt fire again */
1350         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1351                 goto out;
1352
1353         misccpctl = I915_READ(GEN7_MISCCPCTL);
1354         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1355         POSTING_READ(GEN7_MISCCPCTL);
1356
1357         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1358                 i915_reg_t reg;
1359
1360                 slice--;
1361                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1362                         break;
1363
1364                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1365
1366                 reg = GEN7_L3CDERRST1(slice);
1367
1368                 error_status = I915_READ(reg);
1369                 row = GEN7_PARITY_ERROR_ROW(error_status);
1370                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1371                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1372
1373                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1374                 POSTING_READ(reg);
1375
1376                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1377                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1378                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1379                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1380                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1381                 parity_event[5] = NULL;
1382
1383                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1384                                    KOBJ_CHANGE, parity_event);
1385
1386                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1387                           slice, row, bank, subbank);
1388
1389                 kfree(parity_event[4]);
1390                 kfree(parity_event[3]);
1391                 kfree(parity_event[2]);
1392                 kfree(parity_event[1]);
1393         }
1394
1395         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1396
1397 out:
1398         WARN_ON(dev_priv->l3_parity.which_slice);
1399         spin_lock_irq(&dev_priv->irq_lock);
1400         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1401         spin_unlock_irq(&dev_priv->irq_lock);
1402
1403         mutex_unlock(&dev_priv->drm.struct_mutex);
1404 }
1405
1406 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1407                                                u32 iir)
1408 {
1409         if (!HAS_L3_DPF(dev_priv))
1410                 return;
1411
1412         spin_lock(&dev_priv->irq_lock);
1413         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1414         spin_unlock(&dev_priv->irq_lock);
1415
1416         iir &= GT_PARITY_ERROR(dev_priv);
1417         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1418                 dev_priv->l3_parity.which_slice |= 1 << 1;
1419
1420         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1421                 dev_priv->l3_parity.which_slice |= 1 << 0;
1422
1423         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1424 }
1425
1426 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1427                                u32 gt_iir)
1428 {
1429         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1430                 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1431         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1432                 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1433 }
1434
1435 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1436                                u32 gt_iir)
1437 {
1438         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1439                 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
1440         if (gt_iir & GT_BSD_USER_INTERRUPT)
1441                 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
1442         if (gt_iir & GT_BLT_USER_INTERRUPT)
1443                 intel_engine_breadcrumbs_irq(dev_priv->engine[BCS0]);
1444
1445         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1446                       GT_BSD_CS_ERROR_INTERRUPT |
1447                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1448                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1449
1450         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1451                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1452 }
1453
1454 static void
1455 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
1456 {
1457         bool tasklet = false;
1458
1459         if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
1460                 tasklet = true;
1461
1462         if (iir & GT_RENDER_USER_INTERRUPT) {
1463                 intel_engine_breadcrumbs_irq(engine);
1464                 tasklet |= USES_GUC_SUBMISSION(engine->i915);
1465         }
1466
1467         if (tasklet)
1468                 tasklet_hi_schedule(&engine->execlists.tasklet);
1469 }
1470
1471 static void gen8_gt_irq_ack(struct drm_i915_private *i915,
1472                             u32 master_ctl, u32 gt_iir[4])
1473 {
1474         void __iomem * const regs = i915->regs;
1475
1476 #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \
1477                       GEN8_GT_BCS_IRQ | \
1478                       GEN8_GT_VCS0_IRQ | \
1479                       GEN8_GT_VCS1_IRQ | \
1480                       GEN8_GT_VECS_IRQ | \
1481                       GEN8_GT_PM_IRQ | \
1482                       GEN8_GT_GUC_IRQ)
1483
1484         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1485                 gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
1486                 if (likely(gt_iir[0]))
1487                         raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
1488         }
1489
1490         if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1491                 gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
1492                 if (likely(gt_iir[1]))
1493                         raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
1494         }
1495
1496         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1497                 gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
1498                 if (likely(gt_iir[2]))
1499                         raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
1500         }
1501
1502         if (master_ctl & GEN8_GT_VECS_IRQ) {
1503                 gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
1504                 if (likely(gt_iir[3]))
1505                         raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
1506         }
1507 }
1508
1509 static void gen8_gt_irq_handler(struct drm_i915_private *i915,
1510                                 u32 master_ctl, u32 gt_iir[4])
1511 {
1512         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1513                 gen8_cs_irq_handler(i915->engine[RCS0],
1514                                     gt_iir[0] >> GEN8_RCS_IRQ_SHIFT);
1515                 gen8_cs_irq_handler(i915->engine[BCS0],
1516                                     gt_iir[0] >> GEN8_BCS_IRQ_SHIFT);
1517         }
1518
1519         if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
1520                 gen8_cs_irq_handler(i915->engine[VCS0],
1521                                     gt_iir[1] >> GEN8_VCS0_IRQ_SHIFT);
1522                 gen8_cs_irq_handler(i915->engine[VCS1],
1523                                     gt_iir[1] >> GEN8_VCS1_IRQ_SHIFT);
1524         }
1525
1526         if (master_ctl & GEN8_GT_VECS_IRQ) {
1527                 gen8_cs_irq_handler(i915->engine[VECS0],
1528                                     gt_iir[3] >> GEN8_VECS_IRQ_SHIFT);
1529         }
1530
1531         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1532                 gen6_rps_irq_handler(i915, gt_iir[2]);
1533                 gen9_guc_irq_handler(i915, gt_iir[2]);
1534         }
1535 }
1536
1537 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1538 {
1539         switch (pin) {
1540         case HPD_PORT_C:
1541                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1542         case HPD_PORT_D:
1543                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1544         case HPD_PORT_E:
1545                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1546         case HPD_PORT_F:
1547                 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1548         default:
1549                 return false;
1550         }
1551 }
1552
1553 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1554 {
1555         switch (pin) {
1556         case HPD_PORT_A:
1557                 return val & PORTA_HOTPLUG_LONG_DETECT;
1558         case HPD_PORT_B:
1559                 return val & PORTB_HOTPLUG_LONG_DETECT;
1560         case HPD_PORT_C:
1561                 return val & PORTC_HOTPLUG_LONG_DETECT;
1562         default:
1563                 return false;
1564         }
1565 }
1566
1567 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1568 {
1569         switch (pin) {
1570         case HPD_PORT_A:
1571                 return val & ICP_DDIA_HPD_LONG_DETECT;
1572         case HPD_PORT_B:
1573                 return val & ICP_DDIB_HPD_LONG_DETECT;
1574         default:
1575                 return false;
1576         }
1577 }
1578
1579 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1580 {
1581         switch (pin) {
1582         case HPD_PORT_C:
1583                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1584         case HPD_PORT_D:
1585                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1586         case HPD_PORT_E:
1587                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1588         case HPD_PORT_F:
1589                 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1590         default:
1591                 return false;
1592         }
1593 }
1594
1595 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1596 {
1597         switch (pin) {
1598         case HPD_PORT_E:
1599                 return val & PORTE_HOTPLUG_LONG_DETECT;
1600         default:
1601                 return false;
1602         }
1603 }
1604
1605 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1606 {
1607         switch (pin) {
1608         case HPD_PORT_A:
1609                 return val & PORTA_HOTPLUG_LONG_DETECT;
1610         case HPD_PORT_B:
1611                 return val & PORTB_HOTPLUG_LONG_DETECT;
1612         case HPD_PORT_C:
1613                 return val & PORTC_HOTPLUG_LONG_DETECT;
1614         case HPD_PORT_D:
1615                 return val & PORTD_HOTPLUG_LONG_DETECT;
1616         default:
1617                 return false;
1618         }
1619 }
1620
1621 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1622 {
1623         switch (pin) {
1624         case HPD_PORT_A:
1625                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1626         default:
1627                 return false;
1628         }
1629 }
1630
1631 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1632 {
1633         switch (pin) {
1634         case HPD_PORT_B:
1635                 return val & PORTB_HOTPLUG_LONG_DETECT;
1636         case HPD_PORT_C:
1637                 return val & PORTC_HOTPLUG_LONG_DETECT;
1638         case HPD_PORT_D:
1639                 return val & PORTD_HOTPLUG_LONG_DETECT;
1640         default:
1641                 return false;
1642         }
1643 }
1644
1645 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1646 {
1647         switch (pin) {
1648         case HPD_PORT_B:
1649                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1650         case HPD_PORT_C:
1651                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1652         case HPD_PORT_D:
1653                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1654         default:
1655                 return false;
1656         }
1657 }
1658
1659 /*
1660  * Get a bit mask of pins that have triggered, and which ones may be long.
1661  * This can be called multiple times with the same masks to accumulate
1662  * hotplug detection results from several registers.
1663  *
1664  * Note that the caller is expected to zero out the masks initially.
1665  */
1666 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1667                                u32 *pin_mask, u32 *long_mask,
1668                                u32 hotplug_trigger, u32 dig_hotplug_reg,
1669                                const u32 hpd[HPD_NUM_PINS],
1670                                bool long_pulse_detect(enum hpd_pin pin, u32 val))
1671 {
1672         enum hpd_pin pin;
1673
1674         for_each_hpd_pin(pin) {
1675                 if ((hpd[pin] & hotplug_trigger) == 0)
1676                         continue;
1677
1678                 *pin_mask |= BIT(pin);
1679
1680                 if (long_pulse_detect(pin, dig_hotplug_reg))
1681                         *long_mask |= BIT(pin);
1682         }
1683
1684         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1685                          hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1686
1687 }
1688
1689 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1690 {
1691         wake_up_all(&dev_priv->gmbus_wait_queue);
1692 }
1693
1694 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1695 {
1696         wake_up_all(&dev_priv->gmbus_wait_queue);
1697 }
1698
1699 #if defined(CONFIG_DEBUG_FS)
1700 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1701                                          enum pipe pipe,
1702                                          u32 crc0, u32 crc1,
1703                                          u32 crc2, u32 crc3,
1704                                          u32 crc4)
1705 {
1706         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1707         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1708         u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1709
1710         trace_intel_pipe_crc(crtc, crcs);
1711
1712         spin_lock(&pipe_crc->lock);
1713         /*
1714          * For some not yet identified reason, the first CRC is
1715          * bonkers. So let's just wait for the next vblank and read
1716          * out the buggy result.
1717          *
1718          * On GEN8+ sometimes the second CRC is bonkers as well, so
1719          * don't trust that one either.
1720          */
1721         if (pipe_crc->skipped <= 0 ||
1722             (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1723                 pipe_crc->skipped++;
1724                 spin_unlock(&pipe_crc->lock);
1725                 return;
1726         }
1727         spin_unlock(&pipe_crc->lock);
1728
1729         drm_crtc_add_crc_entry(&crtc->base, true,
1730                                 drm_crtc_accurate_vblank_count(&crtc->base),
1731                                 crcs);
1732 }
1733 #else
1734 static inline void
1735 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1736                              enum pipe pipe,
1737                              u32 crc0, u32 crc1,
1738                              u32 crc2, u32 crc3,
1739                              u32 crc4) {}
1740 #endif
1741
1742
1743 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1744                                      enum pipe pipe)
1745 {
1746         display_pipe_crc_irq_handler(dev_priv, pipe,
1747                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1748                                      0, 0, 0, 0);
1749 }
1750
1751 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1752                                      enum pipe pipe)
1753 {
1754         display_pipe_crc_irq_handler(dev_priv, pipe,
1755                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1756                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1757                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1758                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1759                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1760 }
1761
1762 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1763                                       enum pipe pipe)
1764 {
1765         u32 res1, res2;
1766
1767         if (INTEL_GEN(dev_priv) >= 3)
1768                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1769         else
1770                 res1 = 0;
1771
1772         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1773                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1774         else
1775                 res2 = 0;
1776
1777         display_pipe_crc_irq_handler(dev_priv, pipe,
1778                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1779                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1780                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1781                                      res1, res2);
1782 }
1783
1784 /* The RPS events need forcewake, so we add them to a work queue and mask their
1785  * IMR bits until the work is done. Other interrupts can be processed without
1786  * the work queue. */
1787 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1788 {
1789         struct intel_rps *rps = &dev_priv->gt_pm.rps;
1790
1791         if (pm_iir & dev_priv->pm_rps_events) {
1792                 spin_lock(&dev_priv->irq_lock);
1793                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1794                 if (rps->interrupts_enabled) {
1795                         rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1796                         schedule_work(&rps->work);
1797                 }
1798                 spin_unlock(&dev_priv->irq_lock);
1799         }
1800
1801         if (INTEL_GEN(dev_priv) >= 8)
1802                 return;
1803
1804         if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1805                 intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
1806
1807         if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1808                 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1809 }
1810
1811 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1812 {
1813         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
1814                 intel_guc_to_host_event_handler(&dev_priv->guc);
1815 }
1816
1817 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1818 {
1819         enum pipe pipe;
1820
1821         for_each_pipe(dev_priv, pipe) {
1822                 I915_WRITE(PIPESTAT(pipe),
1823                            PIPESTAT_INT_STATUS_MASK |
1824                            PIPE_FIFO_UNDERRUN_STATUS);
1825
1826                 dev_priv->pipestat_irq_mask[pipe] = 0;
1827         }
1828 }
1829
1830 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1831                                   u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1832 {
1833         int pipe;
1834
1835         spin_lock(&dev_priv->irq_lock);
1836
1837         if (!dev_priv->display_irqs_enabled) {
1838                 spin_unlock(&dev_priv->irq_lock);
1839                 return;
1840         }
1841
1842         for_each_pipe(dev_priv, pipe) {
1843                 i915_reg_t reg;
1844                 u32 status_mask, enable_mask, iir_bit = 0;
1845
1846                 /*
1847                  * PIPESTAT bits get signalled even when the interrupt is
1848                  * disabled with the mask bits, and some of the status bits do
1849                  * not generate interrupts at all (like the underrun bit). Hence
1850                  * we need to be careful that we only handle what we want to
1851                  * handle.
1852                  */
1853
1854                 /* fifo underruns are filterered in the underrun handler. */
1855                 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1856
1857                 switch (pipe) {
1858                 case PIPE_A:
1859                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1860                         break;
1861                 case PIPE_B:
1862                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1863                         break;
1864                 case PIPE_C:
1865                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1866                         break;
1867                 }
1868                 if (iir & iir_bit)
1869                         status_mask |= dev_priv->pipestat_irq_mask[pipe];
1870
1871                 if (!status_mask)
1872                         continue;
1873
1874                 reg = PIPESTAT(pipe);
1875                 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1876                 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1877
1878                 /*
1879                  * Clear the PIPE*STAT regs before the IIR
1880                  *
1881                  * Toggle the enable bits to make sure we get an
1882                  * edge in the ISR pipe event bit if we don't clear
1883                  * all the enabled status bits. Otherwise the edge
1884                  * triggered IIR on i965/g4x wouldn't notice that
1885                  * an interrupt is still pending.
1886                  */
1887                 if (pipe_stats[pipe]) {
1888                         I915_WRITE(reg, pipe_stats[pipe]);
1889                         I915_WRITE(reg, enable_mask);
1890                 }
1891         }
1892         spin_unlock(&dev_priv->irq_lock);
1893 }
1894
1895 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1896                                       u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1897 {
1898         enum pipe pipe;
1899
1900         for_each_pipe(dev_priv, pipe) {
1901                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1902                         drm_handle_vblank(&dev_priv->drm, pipe);
1903
1904                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1905                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1906
1907                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1908                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1909         }
1910 }
1911
1912 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1913                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1914 {
1915         bool blc_event = false;
1916         enum pipe pipe;
1917
1918         for_each_pipe(dev_priv, pipe) {
1919                 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1920                         drm_handle_vblank(&dev_priv->drm, pipe);
1921
1922                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1923                         blc_event = true;
1924
1925                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1926                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1927
1928                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1929                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1930         }
1931
1932         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1933                 intel_opregion_asle_intr(dev_priv);
1934 }
1935
1936 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1937                                       u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1938 {
1939         bool blc_event = false;
1940         enum pipe pipe;
1941
1942         for_each_pipe(dev_priv, pipe) {
1943                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1944                         drm_handle_vblank(&dev_priv->drm, pipe);
1945
1946                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1947                         blc_event = true;
1948
1949                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1950                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1951
1952                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1953                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1954         }
1955
1956         if (blc_event || (iir & I915_ASLE_INTERRUPT))
1957                 intel_opregion_asle_intr(dev_priv);
1958
1959         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1960                 gmbus_irq_handler(dev_priv);
1961 }
1962
1963 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1964                                             u32 pipe_stats[I915_MAX_PIPES])
1965 {
1966         enum pipe pipe;
1967
1968         for_each_pipe(dev_priv, pipe) {
1969                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1970                         drm_handle_vblank(&dev_priv->drm, pipe);
1971
1972                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1973                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1974
1975                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1976                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1977         }
1978
1979         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1980                 gmbus_irq_handler(dev_priv);
1981 }
1982
1983 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1984 {
1985         u32 hotplug_status = 0, hotplug_status_mask;
1986         int i;
1987
1988         if (IS_G4X(dev_priv) ||
1989             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1990                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1991                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1992         else
1993                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1994
1995         /*
1996          * We absolutely have to clear all the pending interrupt
1997          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1998          * interrupt bit won't have an edge, and the i965/g4x
1999          * edge triggered IIR will not notice that an interrupt
2000          * is still pending. We can't use PORT_HOTPLUG_EN to
2001          * guarantee the edge as the act of toggling the enable
2002          * bits can itself generate a new hotplug interrupt :(
2003          */
2004         for (i = 0; i < 10; i++) {
2005                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
2006
2007                 if (tmp == 0)
2008                         return hotplug_status;
2009
2010                 hotplug_status |= tmp;
2011                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2012         }
2013
2014         WARN_ONCE(1,
2015                   "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
2016                   I915_READ(PORT_HOTPLUG_STAT));
2017
2018         return hotplug_status;
2019 }
2020
2021 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2022                                  u32 hotplug_status)
2023 {
2024         u32 pin_mask = 0, long_mask = 0;
2025
2026         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2027             IS_CHERRYVIEW(dev_priv)) {
2028                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2029
2030                 if (hotplug_trigger) {
2031                         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2032                                            hotplug_trigger, hotplug_trigger,
2033                                            hpd_status_g4x,
2034                                            i9xx_port_hotplug_long_detect);
2035
2036                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2037                 }
2038
2039                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2040                         dp_aux_irq_handler(dev_priv);
2041         } else {
2042                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2043
2044                 if (hotplug_trigger) {
2045                         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2046                                            hotplug_trigger, hotplug_trigger,
2047                                            hpd_status_i915,
2048                                            i9xx_port_hotplug_long_detect);
2049                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2050                 }
2051         }
2052 }
2053
2054 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2055 {
2056         struct drm_device *dev = arg;
2057         struct drm_i915_private *dev_priv = to_i915(dev);
2058         irqreturn_t ret = IRQ_NONE;
2059
2060         if (!intel_irqs_enabled(dev_priv))
2061                 return IRQ_NONE;
2062
2063         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2064         disable_rpm_wakeref_asserts(dev_priv);
2065
2066         do {
2067                 u32 iir, gt_iir, pm_iir;
2068                 u32 pipe_stats[I915_MAX_PIPES] = {};
2069                 u32 hotplug_status = 0;
2070                 u32 ier = 0;
2071
2072                 gt_iir = I915_READ(GTIIR);
2073                 pm_iir = I915_READ(GEN6_PMIIR);
2074                 iir = I915_READ(VLV_IIR);
2075
2076                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2077                         break;
2078
2079                 ret = IRQ_HANDLED;
2080
2081                 /*
2082                  * Theory on interrupt generation, based on empirical evidence:
2083                  *
2084                  * x = ((VLV_IIR & VLV_IER) ||
2085                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
2086                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
2087                  *
2088                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2089                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
2090                  * guarantee the CPU interrupt will be raised again even if we
2091                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
2092                  * bits this time around.
2093                  */
2094                 I915_WRITE(VLV_MASTER_IER, 0);
2095                 ier = I915_READ(VLV_IER);
2096                 I915_WRITE(VLV_IER, 0);
2097
2098                 if (gt_iir)
2099                         I915_WRITE(GTIIR, gt_iir);
2100                 if (pm_iir)
2101                         I915_WRITE(GEN6_PMIIR, pm_iir);
2102
2103                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2104                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2105
2106                 /* Call regardless, as some status bits might not be
2107                  * signalled in iir */
2108                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2109
2110                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2111                            I915_LPE_PIPE_B_INTERRUPT))
2112                         intel_lpe_audio_irq_handler(dev_priv);
2113
2114                 /*
2115                  * VLV_IIR is single buffered, and reflects the level
2116                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2117                  */
2118                 if (iir)
2119                         I915_WRITE(VLV_IIR, iir);
2120
2121                 I915_WRITE(VLV_IER, ier);
2122                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2123
2124                 if (gt_iir)
2125                         snb_gt_irq_handler(dev_priv, gt_iir);
2126                 if (pm_iir)
2127                         gen6_rps_irq_handler(dev_priv, pm_iir);
2128
2129                 if (hotplug_status)
2130                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2131
2132                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2133         } while (0);
2134
2135         enable_rpm_wakeref_asserts(dev_priv);
2136
2137         return ret;
2138 }
2139
2140 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2141 {
2142         struct drm_device *dev = arg;
2143         struct drm_i915_private *dev_priv = to_i915(dev);
2144         irqreturn_t ret = IRQ_NONE;
2145
2146         if (!intel_irqs_enabled(dev_priv))
2147                 return IRQ_NONE;
2148
2149         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2150         disable_rpm_wakeref_asserts(dev_priv);
2151
2152         do {
2153                 u32 master_ctl, iir;
2154                 u32 pipe_stats[I915_MAX_PIPES] = {};
2155                 u32 hotplug_status = 0;
2156                 u32 gt_iir[4];
2157                 u32 ier = 0;
2158
2159                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2160                 iir = I915_READ(VLV_IIR);
2161
2162                 if (master_ctl == 0 && iir == 0)
2163                         break;
2164
2165                 ret = IRQ_HANDLED;
2166
2167                 /*
2168                  * Theory on interrupt generation, based on empirical evidence:
2169                  *
2170                  * x = ((VLV_IIR & VLV_IER) ||
2171                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2172                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2173                  *
2174                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2175                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2176                  * guarantee the CPU interrupt will be raised again even if we
2177                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2178                  * bits this time around.
2179                  */
2180                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2181                 ier = I915_READ(VLV_IER);
2182                 I915_WRITE(VLV_IER, 0);
2183
2184                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2185
2186                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2187                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2188
2189                 /* Call regardless, as some status bits might not be
2190                  * signalled in iir */
2191                 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2192
2193                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2194                            I915_LPE_PIPE_B_INTERRUPT |
2195                            I915_LPE_PIPE_C_INTERRUPT))
2196                         intel_lpe_audio_irq_handler(dev_priv);
2197
2198                 /*
2199                  * VLV_IIR is single buffered, and reflects the level
2200                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2201                  */
2202                 if (iir)
2203                         I915_WRITE(VLV_IIR, iir);
2204
2205                 I915_WRITE(VLV_IER, ier);
2206                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2207
2208                 gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2209
2210                 if (hotplug_status)
2211                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2212
2213                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2214         } while (0);
2215
2216         enable_rpm_wakeref_asserts(dev_priv);
2217
2218         return ret;
2219 }
2220
2221 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2222                                 u32 hotplug_trigger,
2223                                 const u32 hpd[HPD_NUM_PINS])
2224 {
2225         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2226
2227         /*
2228          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2229          * unless we touch the hotplug register, even if hotplug_trigger is
2230          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2231          * errors.
2232          */
2233         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2234         if (!hotplug_trigger) {
2235                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2236                         PORTD_HOTPLUG_STATUS_MASK |
2237                         PORTC_HOTPLUG_STATUS_MASK |
2238                         PORTB_HOTPLUG_STATUS_MASK;
2239                 dig_hotplug_reg &= ~mask;
2240         }
2241
2242         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2243         if (!hotplug_trigger)
2244                 return;
2245
2246         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2247                            dig_hotplug_reg, hpd,
2248                            pch_port_hotplug_long_detect);
2249
2250         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2251 }
2252
2253 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2254 {
2255         int pipe;
2256         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2257
2258         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2259
2260         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2261                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2262                                SDE_AUDIO_POWER_SHIFT);
2263                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2264                                  port_name(port));
2265         }
2266
2267         if (pch_iir & SDE_AUX_MASK)
2268                 dp_aux_irq_handler(dev_priv);
2269
2270         if (pch_iir & SDE_GMBUS)
2271                 gmbus_irq_handler(dev_priv);
2272
2273         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2274                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2275
2276         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2277                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2278
2279         if (pch_iir & SDE_POISON)
2280                 DRM_ERROR("PCH poison interrupt\n");
2281
2282         if (pch_iir & SDE_FDI_MASK)
2283                 for_each_pipe(dev_priv, pipe)
2284                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2285                                          pipe_name(pipe),
2286                                          I915_READ(FDI_RX_IIR(pipe)));
2287
2288         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2289                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2290
2291         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2292                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2293
2294         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2295                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2296
2297         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2298                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2299 }
2300
2301 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2302 {
2303         u32 err_int = I915_READ(GEN7_ERR_INT);
2304         enum pipe pipe;
2305
2306         if (err_int & ERR_INT_POISON)
2307                 DRM_ERROR("Poison interrupt\n");
2308
2309         for_each_pipe(dev_priv, pipe) {
2310                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2311                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2312
2313                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2314                         if (IS_IVYBRIDGE(dev_priv))
2315                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2316                         else
2317                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2318                 }
2319         }
2320
2321         I915_WRITE(GEN7_ERR_INT, err_int);
2322 }
2323
2324 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2325 {
2326         u32 serr_int = I915_READ(SERR_INT);
2327         enum pipe pipe;
2328
2329         if (serr_int & SERR_INT_POISON)
2330                 DRM_ERROR("PCH poison interrupt\n");
2331
2332         for_each_pipe(dev_priv, pipe)
2333                 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2334                         intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2335
2336         I915_WRITE(SERR_INT, serr_int);
2337 }
2338
2339 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2340 {
2341         int pipe;
2342         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2343
2344         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2345
2346         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2347                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2348                                SDE_AUDIO_POWER_SHIFT_CPT);
2349                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2350                                  port_name(port));
2351         }
2352
2353         if (pch_iir & SDE_AUX_MASK_CPT)
2354                 dp_aux_irq_handler(dev_priv);
2355
2356         if (pch_iir & SDE_GMBUS_CPT)
2357                 gmbus_irq_handler(dev_priv);
2358
2359         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2360                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2361
2362         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2363                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2364
2365         if (pch_iir & SDE_FDI_MASK_CPT)
2366                 for_each_pipe(dev_priv, pipe)
2367                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2368                                          pipe_name(pipe),
2369                                          I915_READ(FDI_RX_IIR(pipe)));
2370
2371         if (pch_iir & SDE_ERROR_CPT)
2372                 cpt_serr_int_handler(dev_priv);
2373 }
2374
2375 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2376 {
2377         u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2378         u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2379         u32 pin_mask = 0, long_mask = 0;
2380
2381         if (ddi_hotplug_trigger) {
2382                 u32 dig_hotplug_reg;
2383
2384                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2385                 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2386
2387                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2388                                    ddi_hotplug_trigger,
2389                                    dig_hotplug_reg, hpd_icp,
2390                                    icp_ddi_port_hotplug_long_detect);
2391         }
2392
2393         if (tc_hotplug_trigger) {
2394                 u32 dig_hotplug_reg;
2395
2396                 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2397                 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2398
2399                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2400                                    tc_hotplug_trigger,
2401                                    dig_hotplug_reg, hpd_icp,
2402                                    icp_tc_port_hotplug_long_detect);
2403         }
2404
2405         if (pin_mask)
2406                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2407
2408         if (pch_iir & SDE_GMBUS_ICP)
2409                 gmbus_irq_handler(dev_priv);
2410 }
2411
2412 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2413 {
2414         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2415                 ~SDE_PORTE_HOTPLUG_SPT;
2416         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2417         u32 pin_mask = 0, long_mask = 0;
2418
2419         if (hotplug_trigger) {
2420                 u32 dig_hotplug_reg;
2421
2422                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2423                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2424
2425                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2426                                    hotplug_trigger, dig_hotplug_reg, hpd_spt,
2427                                    spt_port_hotplug_long_detect);
2428         }
2429
2430         if (hotplug2_trigger) {
2431                 u32 dig_hotplug_reg;
2432
2433                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2434                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2435
2436                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2437                                    hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2438                                    spt_port_hotplug2_long_detect);
2439         }
2440
2441         if (pin_mask)
2442                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2443
2444         if (pch_iir & SDE_GMBUS_CPT)
2445                 gmbus_irq_handler(dev_priv);
2446 }
2447
2448 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2449                                 u32 hotplug_trigger,
2450                                 const u32 hpd[HPD_NUM_PINS])
2451 {
2452         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2453
2454         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2455         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2456
2457         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2458                            dig_hotplug_reg, hpd,
2459                            ilk_port_hotplug_long_detect);
2460
2461         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2462 }
2463
2464 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2465                                     u32 de_iir)
2466 {
2467         enum pipe pipe;
2468         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2469
2470         if (hotplug_trigger)
2471                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2472
2473         if (de_iir & DE_AUX_CHANNEL_A)
2474                 dp_aux_irq_handler(dev_priv);
2475
2476         if (de_iir & DE_GSE)
2477                 intel_opregion_asle_intr(dev_priv);
2478
2479         if (de_iir & DE_POISON)
2480                 DRM_ERROR("Poison interrupt\n");
2481
2482         for_each_pipe(dev_priv, pipe) {
2483                 if (de_iir & DE_PIPE_VBLANK(pipe))
2484                         drm_handle_vblank(&dev_priv->drm, pipe);
2485
2486                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2487                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2488
2489                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2490                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2491         }
2492
2493         /* check event from PCH */
2494         if (de_iir & DE_PCH_EVENT) {
2495                 u32 pch_iir = I915_READ(SDEIIR);
2496
2497                 if (HAS_PCH_CPT(dev_priv))
2498                         cpt_irq_handler(dev_priv, pch_iir);
2499                 else
2500                         ibx_irq_handler(dev_priv, pch_iir);
2501
2502                 /* should clear PCH hotplug event before clear CPU irq */
2503                 I915_WRITE(SDEIIR, pch_iir);
2504         }
2505
2506         if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2507                 ironlake_rps_change_irq_handler(dev_priv);
2508 }
2509
2510 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2511                                     u32 de_iir)
2512 {
2513         enum pipe pipe;
2514         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2515
2516         if (hotplug_trigger)
2517                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2518
2519         if (de_iir & DE_ERR_INT_IVB)
2520                 ivb_err_int_handler(dev_priv);
2521
2522         if (de_iir & DE_EDP_PSR_INT_HSW) {
2523                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2524
2525                 intel_psr_irq_handler(dev_priv, psr_iir);
2526                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2527         }
2528
2529         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2530                 dp_aux_irq_handler(dev_priv);
2531
2532         if (de_iir & DE_GSE_IVB)
2533                 intel_opregion_asle_intr(dev_priv);
2534
2535         for_each_pipe(dev_priv, pipe) {
2536                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2537                         drm_handle_vblank(&dev_priv->drm, pipe);
2538         }
2539
2540         /* check event from PCH */
2541         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2542                 u32 pch_iir = I915_READ(SDEIIR);
2543
2544                 cpt_irq_handler(dev_priv, pch_iir);
2545
2546                 /* clear PCH hotplug event before clear CPU irq */
2547                 I915_WRITE(SDEIIR, pch_iir);
2548         }
2549 }
2550
2551 /*
2552  * To handle irqs with the minimum potential races with fresh interrupts, we:
2553  * 1 - Disable Master Interrupt Control.
2554  * 2 - Find the source(s) of the interrupt.
2555  * 3 - Clear the Interrupt Identity bits (IIR).
2556  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2557  * 5 - Re-enable Master Interrupt Control.
2558  */
2559 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2560 {
2561         struct drm_device *dev = arg;
2562         struct drm_i915_private *dev_priv = to_i915(dev);
2563         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2564         irqreturn_t ret = IRQ_NONE;
2565
2566         if (!intel_irqs_enabled(dev_priv))
2567                 return IRQ_NONE;
2568
2569         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2570         disable_rpm_wakeref_asserts(dev_priv);
2571
2572         /* disable master interrupt before clearing iir  */
2573         de_ier = I915_READ(DEIER);
2574         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2575
2576         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2577          * interrupts will will be stored on its back queue, and then we'll be
2578          * able to process them after we restore SDEIER (as soon as we restore
2579          * it, we'll get an interrupt if SDEIIR still has something to process
2580          * due to its back queue). */
2581         if (!HAS_PCH_NOP(dev_priv)) {
2582                 sde_ier = I915_READ(SDEIER);
2583                 I915_WRITE(SDEIER, 0);
2584         }
2585
2586         /* Find, clear, then process each source of interrupt */
2587
2588         gt_iir = I915_READ(GTIIR);
2589         if (gt_iir) {
2590                 I915_WRITE(GTIIR, gt_iir);
2591                 ret = IRQ_HANDLED;
2592                 if (INTEL_GEN(dev_priv) >= 6)
2593                         snb_gt_irq_handler(dev_priv, gt_iir);
2594                 else
2595                         ilk_gt_irq_handler(dev_priv, gt_iir);
2596         }
2597
2598         de_iir = I915_READ(DEIIR);
2599         if (de_iir) {
2600                 I915_WRITE(DEIIR, de_iir);
2601                 ret = IRQ_HANDLED;
2602                 if (INTEL_GEN(dev_priv) >= 7)
2603                         ivb_display_irq_handler(dev_priv, de_iir);
2604                 else
2605                         ilk_display_irq_handler(dev_priv, de_iir);
2606         }
2607
2608         if (INTEL_GEN(dev_priv) >= 6) {
2609                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2610                 if (pm_iir) {
2611                         I915_WRITE(GEN6_PMIIR, pm_iir);
2612                         ret = IRQ_HANDLED;
2613                         gen6_rps_irq_handler(dev_priv, pm_iir);
2614                 }
2615         }
2616
2617         I915_WRITE(DEIER, de_ier);
2618         if (!HAS_PCH_NOP(dev_priv))
2619                 I915_WRITE(SDEIER, sde_ier);
2620
2621         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2622         enable_rpm_wakeref_asserts(dev_priv);
2623
2624         return ret;
2625 }
2626
2627 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2628                                 u32 hotplug_trigger,
2629                                 const u32 hpd[HPD_NUM_PINS])
2630 {
2631         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2632
2633         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2634         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2635
2636         intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2637                            dig_hotplug_reg, hpd,
2638                            bxt_port_hotplug_long_detect);
2639
2640         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2641 }
2642
2643 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2644 {
2645         u32 pin_mask = 0, long_mask = 0;
2646         u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2647         u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2648
2649         if (trigger_tc) {
2650                 u32 dig_hotplug_reg;
2651
2652                 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2653                 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2654
2655                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2656                                    dig_hotplug_reg, hpd_gen11,
2657                                    gen11_port_hotplug_long_detect);
2658         }
2659
2660         if (trigger_tbt) {
2661                 u32 dig_hotplug_reg;
2662
2663                 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2664                 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2665
2666                 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2667                                    dig_hotplug_reg, hpd_gen11,
2668                                    gen11_port_hotplug_long_detect);
2669         }
2670
2671         if (pin_mask)
2672                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2673         else
2674                 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2675 }
2676
2677 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2678 {
2679         u32 mask = GEN8_AUX_CHANNEL_A;
2680
2681         if (INTEL_GEN(dev_priv) >= 9)
2682                 mask |= GEN9_AUX_CHANNEL_B |
2683                         GEN9_AUX_CHANNEL_C |
2684                         GEN9_AUX_CHANNEL_D;
2685
2686         if (IS_CNL_WITH_PORT_F(dev_priv))
2687                 mask |= CNL_AUX_CHANNEL_F;
2688
2689         if (INTEL_GEN(dev_priv) >= 11)
2690                 mask |= ICL_AUX_CHANNEL_E |
2691                         CNL_AUX_CHANNEL_F;
2692
2693         return mask;
2694 }
2695
2696 static irqreturn_t
2697 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2698 {
2699         irqreturn_t ret = IRQ_NONE;
2700         u32 iir;
2701         enum pipe pipe;
2702
2703         if (master_ctl & GEN8_DE_MISC_IRQ) {
2704                 iir = I915_READ(GEN8_DE_MISC_IIR);
2705                 if (iir) {
2706                         bool found = false;
2707
2708                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2709                         ret = IRQ_HANDLED;
2710
2711                         if (iir & GEN8_DE_MISC_GSE) {
2712                                 intel_opregion_asle_intr(dev_priv);
2713                                 found = true;
2714                         }
2715
2716                         if (iir & GEN8_DE_EDP_PSR) {
2717                                 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2718
2719                                 intel_psr_irq_handler(dev_priv, psr_iir);
2720                                 I915_WRITE(EDP_PSR_IIR, psr_iir);
2721                                 found = true;
2722                         }
2723
2724                         if (!found)
2725                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2726                 }
2727                 else
2728                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2729         }
2730
2731         if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2732                 iir = I915_READ(GEN11_DE_HPD_IIR);
2733                 if (iir) {
2734                         I915_WRITE(GEN11_DE_HPD_IIR, iir);
2735                         ret = IRQ_HANDLED;
2736                         gen11_hpd_irq_handler(dev_priv, iir);
2737                 } else {
2738                         DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2739                 }
2740         }
2741
2742         if (master_ctl & GEN8_DE_PORT_IRQ) {
2743                 iir = I915_READ(GEN8_DE_PORT_IIR);
2744                 if (iir) {
2745                         u32 tmp_mask;
2746                         bool found = false;
2747
2748                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2749                         ret = IRQ_HANDLED;
2750
2751                         if (iir & gen8_de_port_aux_mask(dev_priv)) {
2752                                 dp_aux_irq_handler(dev_priv);
2753                                 found = true;
2754                         }
2755
2756                         if (IS_GEN9_LP(dev_priv)) {
2757                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2758                                 if (tmp_mask) {
2759                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2760                                                             hpd_bxt);
2761                                         found = true;
2762                                 }
2763                         } else if (IS_BROADWELL(dev_priv)) {
2764                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2765                                 if (tmp_mask) {
2766                                         ilk_hpd_irq_handler(dev_priv,
2767                                                             tmp_mask, hpd_bdw);
2768                                         found = true;
2769                                 }
2770                         }
2771
2772                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2773                                 gmbus_irq_handler(dev_priv);
2774                                 found = true;
2775                         }
2776
2777                         if (!found)
2778                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2779                 }
2780                 else
2781                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2782         }
2783
2784         for_each_pipe(dev_priv, pipe) {
2785                 u32 fault_errors;
2786
2787                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2788                         continue;
2789
2790                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2791                 if (!iir) {
2792                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2793                         continue;
2794                 }
2795
2796                 ret = IRQ_HANDLED;
2797                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2798
2799                 if (iir & GEN8_PIPE_VBLANK)
2800                         drm_handle_vblank(&dev_priv->drm, pipe);
2801
2802                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2803                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2804
2805                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2806                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2807
2808                 fault_errors = iir;
2809                 if (INTEL_GEN(dev_priv) >= 9)
2810                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2811                 else
2812                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2813
2814                 if (fault_errors)
2815                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2816                                   pipe_name(pipe),
2817                                   fault_errors);
2818         }
2819
2820         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2821             master_ctl & GEN8_DE_PCH_IRQ) {
2822                 /*
2823                  * FIXME(BDW): Assume for now that the new interrupt handling
2824                  * scheme also closed the SDE interrupt handling race we've seen
2825                  * on older pch-split platforms. But this needs testing.
2826                  */
2827                 iir = I915_READ(SDEIIR);
2828                 if (iir) {
2829                         I915_WRITE(SDEIIR, iir);
2830                         ret = IRQ_HANDLED;
2831
2832                         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2833                                 icp_irq_handler(dev_priv, iir);
2834                         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2835                                 spt_irq_handler(dev_priv, iir);
2836                         else
2837                                 cpt_irq_handler(dev_priv, iir);
2838                 } else {
2839                         /*
2840                          * Like on previous PCH there seems to be something
2841                          * fishy going on with forwarding PCH interrupts.
2842                          */
2843                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2844                 }
2845         }
2846
2847         return ret;
2848 }
2849
2850 static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2851 {
2852         raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2853
2854         /*
2855          * Now with master disabled, get a sample of level indications
2856          * for this interrupt. Indications will be cleared on related acks.
2857          * New indications can and will light up during processing,
2858          * and will generate new interrupt after enabling master.
2859          */
2860         return raw_reg_read(regs, GEN8_MASTER_IRQ);
2861 }
2862
2863 static inline void gen8_master_intr_enable(void __iomem * const regs)
2864 {
2865         raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2866 }
2867
2868 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2869 {
2870         struct drm_i915_private *dev_priv = to_i915(arg);
2871         void __iomem * const regs = dev_priv->regs;
2872         u32 master_ctl;
2873         u32 gt_iir[4];
2874
2875         if (!intel_irqs_enabled(dev_priv))
2876                 return IRQ_NONE;
2877
2878         master_ctl = gen8_master_intr_disable(regs);
2879         if (!master_ctl) {
2880                 gen8_master_intr_enable(regs);
2881                 return IRQ_NONE;
2882         }
2883
2884         /* Find, clear, then process each source of interrupt */
2885         gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2886
2887         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2888         if (master_ctl & ~GEN8_GT_IRQS) {
2889                 disable_rpm_wakeref_asserts(dev_priv);
2890                 gen8_de_irq_handler(dev_priv, master_ctl);
2891                 enable_rpm_wakeref_asserts(dev_priv);
2892         }
2893
2894         gen8_master_intr_enable(regs);
2895
2896         gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
2897
2898         return IRQ_HANDLED;
2899 }
2900
2901 static u32
2902 gen11_gt_engine_identity(struct drm_i915_private * const i915,
2903                          const unsigned int bank, const unsigned int bit)
2904 {
2905         void __iomem * const regs = i915->regs;
2906         u32 timeout_ts;
2907         u32 ident;
2908
2909         lockdep_assert_held(&i915->irq_lock);
2910
2911         raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
2912
2913         /*
2914          * NB: Specs do not specify how long to spin wait,
2915          * so we do ~100us as an educated guess.
2916          */
2917         timeout_ts = (local_clock() >> 10) + 100;
2918         do {
2919                 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
2920         } while (!(ident & GEN11_INTR_DATA_VALID) &&
2921                  !time_after32(local_clock() >> 10, timeout_ts));
2922
2923         if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
2924                 DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
2925                           bank, bit, ident);
2926                 return 0;
2927         }
2928
2929         raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
2930                       GEN11_INTR_DATA_VALID);
2931
2932         return ident;
2933 }
2934
2935 static void
2936 gen11_other_irq_handler(struct drm_i915_private * const i915,
2937                         const u8 instance, const u16 iir)
2938 {
2939         if (instance == OTHER_GTPM_INSTANCE)
2940                 return gen6_rps_irq_handler(i915, iir);
2941
2942         WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
2943                   instance, iir);
2944 }
2945
2946 static void
2947 gen11_engine_irq_handler(struct drm_i915_private * const i915,
2948                          const u8 class, const u8 instance, const u16 iir)
2949 {
2950         struct intel_engine_cs *engine;
2951
2952         if (instance <= MAX_ENGINE_INSTANCE)
2953                 engine = i915->engine_class[class][instance];
2954         else
2955                 engine = NULL;
2956
2957         if (likely(engine))
2958                 return gen8_cs_irq_handler(engine, iir);
2959
2960         WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
2961                   class, instance);
2962 }
2963
2964 static void
2965 gen11_gt_identity_handler(struct drm_i915_private * const i915,
2966                           const u32 identity)
2967 {
2968         const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
2969         const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
2970         const u16 intr = GEN11_INTR_ENGINE_INTR(identity);
2971
2972         if (unlikely(!intr))
2973                 return;
2974
2975         if (class <= COPY_ENGINE_CLASS)
2976                 return gen11_engine_irq_handler(i915, class, instance, intr);
2977
2978         if (class == OTHER_CLASS)
2979                 return gen11_other_irq_handler(i915, instance, intr);
2980
2981         WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
2982                   class, instance, intr);
2983 }
2984
2985 static void
2986 gen11_gt_bank_handler(struct drm_i915_private * const i915,
2987                       const unsigned int bank)
2988 {
2989         void __iomem * const regs = i915->regs;
2990         unsigned long intr_dw;
2991         unsigned int bit;
2992
2993         lockdep_assert_held(&i915->irq_lock);
2994
2995         intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
2996
2997         if (unlikely(!intr_dw)) {
2998                 DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
2999                 return;
3000         }
3001
3002         for_each_set_bit(bit, &intr_dw, 32) {
3003                 const u32 ident = gen11_gt_engine_identity(i915,
3004                                                            bank, bit);
3005
3006                 gen11_gt_identity_handler(i915, ident);
3007         }
3008
3009         /* Clear must be after shared has been served for engine */
3010         raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
3011 }
3012
3013 static void
3014 gen11_gt_irq_handler(struct drm_i915_private * const i915,
3015                      const u32 master_ctl)
3016 {
3017         unsigned int bank;
3018
3019         spin_lock(&i915->irq_lock);
3020
3021         for (bank = 0; bank < 2; bank++) {
3022                 if (master_ctl & GEN11_GT_DW_IRQ(bank))
3023                         gen11_gt_bank_handler(i915, bank);
3024         }
3025
3026         spin_unlock(&i915->irq_lock);
3027 }
3028
3029 static u32
3030 gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
3031 {
3032         void __iomem * const regs = dev_priv->regs;
3033         u32 iir;
3034
3035         if (!(master_ctl & GEN11_GU_MISC_IRQ))
3036                 return 0;
3037
3038         iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
3039         if (likely(iir))
3040                 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
3041
3042         return iir;
3043 }
3044
3045 static void
3046 gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
3047 {
3048         if (iir & GEN11_GU_MISC_GSE)
3049                 intel_opregion_asle_intr(dev_priv);
3050 }
3051
3052 static inline u32 gen11_master_intr_disable(void __iomem * const regs)
3053 {
3054         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
3055
3056         /*
3057          * Now with master disabled, get a sample of level indications
3058          * for this interrupt. Indications will be cleared on related acks.
3059          * New indications can and will light up during processing,
3060          * and will generate new interrupt after enabling master.
3061          */
3062         return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
3063 }
3064
3065 static inline void gen11_master_intr_enable(void __iomem * const regs)
3066 {
3067         raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
3068 }
3069
3070 static irqreturn_t gen11_irq_handler(int irq, void *arg)
3071 {
3072         struct drm_i915_private * const i915 = to_i915(arg);
3073         void __iomem * const regs = i915->regs;
3074         u32 master_ctl;
3075         u32 gu_misc_iir;
3076
3077         if (!intel_irqs_enabled(i915))
3078                 return IRQ_NONE;
3079
3080         master_ctl = gen11_master_intr_disable(regs);
3081         if (!master_ctl) {
3082                 gen11_master_intr_enable(regs);
3083                 return IRQ_NONE;
3084         }
3085
3086         /* Find, clear, then process each source of interrupt. */
3087         gen11_gt_irq_handler(i915, master_ctl);
3088
3089         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3090         if (master_ctl & GEN11_DISPLAY_IRQ) {
3091                 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
3092
3093                 disable_rpm_wakeref_asserts(i915);
3094                 /*
3095                  * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
3096                  * for the display related bits.
3097                  */
3098                 gen8_de_irq_handler(i915, disp_ctl);
3099                 enable_rpm_wakeref_asserts(i915);
3100         }
3101
3102         gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
3103
3104         gen11_master_intr_enable(regs);
3105
3106         gen11_gu_misc_irq_handler(i915, gu_misc_iir);
3107
3108         return IRQ_HANDLED;
3109 }
3110
3111 /* Called from drm generic code, passed 'crtc' which
3112  * we use as a pipe index
3113  */
3114 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
3115 {
3116         struct drm_i915_private *dev_priv = to_i915(dev);
3117         unsigned long irqflags;
3118
3119         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3120         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3121         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3122
3123         return 0;
3124 }
3125
3126 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
3127 {
3128         struct drm_i915_private *dev_priv = to_i915(dev);
3129         unsigned long irqflags;
3130
3131         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3132         i915_enable_pipestat(dev_priv, pipe,
3133                              PIPE_START_VBLANK_INTERRUPT_STATUS);
3134         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3135
3136         return 0;
3137 }
3138
3139 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
3140 {
3141         struct drm_i915_private *dev_priv = to_i915(dev);
3142         unsigned long irqflags;
3143         u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3144                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3145
3146         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3147         ilk_enable_display_irq(dev_priv, bit);
3148         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3149
3150         /* Even though there is no DMC, frame counter can get stuck when
3151          * PSR is active as no frames are generated.
3152          */
3153         if (HAS_PSR(dev_priv))
3154                 drm_vblank_restore(dev, pipe);
3155
3156         return 0;
3157 }
3158
3159 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
3160 {
3161         struct drm_i915_private *dev_priv = to_i915(dev);
3162         unsigned long irqflags;
3163
3164         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3165         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3166         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3167
3168         /* Even if there is no DMC, frame counter can get stuck when
3169          * PSR is active as no frames are generated, so check only for PSR.
3170          */
3171         if (HAS_PSR(dev_priv))
3172                 drm_vblank_restore(dev, pipe);
3173
3174         return 0;
3175 }
3176