1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
145 u32 val = I915_READ(reg);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
154 I915_WRITE(reg, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
175 /* For display hotplug interrupt */
177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
183 assert_spin_locked(&dev_priv->irq_lock);
184 WARN_ON(bits & ~mask);
186 val = I915_READ(PORT_HOTPLUG_EN);
189 I915_WRITE(PORT_HOTPLUG_EN, val);
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
208 spin_lock_irq(&dev_priv->irq_lock);
209 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
210 spin_unlock_irq(&dev_priv->irq_lock);
214 * ilk_update_display_irq - update DEIMR
215 * @dev_priv: driver private
216 * @interrupt_mask: mask of interrupt bits to update
217 * @enabled_irq_mask: mask of interrupt bits to enable
219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
220 uint32_t interrupt_mask,
221 uint32_t enabled_irq_mask)
225 assert_spin_locked(&dev_priv->irq_lock);
227 WARN_ON(enabled_irq_mask & ~interrupt_mask);
229 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
232 new_val = dev_priv->irq_mask;
233 new_val &= ~interrupt_mask;
234 new_val |= (~enabled_irq_mask & interrupt_mask);
236 if (new_val != dev_priv->irq_mask) {
237 dev_priv->irq_mask = new_val;
238 I915_WRITE(DEIMR, dev_priv->irq_mask);
244 * ilk_update_gt_irq - update GTIMR
245 * @dev_priv: driver private
246 * @interrupt_mask: mask of interrupt bits to update
247 * @enabled_irq_mask: mask of interrupt bits to enable
249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
253 assert_spin_locked(&dev_priv->irq_lock);
255 WARN_ON(enabled_irq_mask & ~interrupt_mask);
257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
260 dev_priv->gt_irq_mask &= ~interrupt_mask;
261 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
262 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
267 ilk_update_gt_irq(dev_priv, mask, mask);
268 POSTING_READ_FW(GTIMR);
271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
273 ilk_update_gt_irq(dev_priv, mask, 0);
276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
278 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
283 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
288 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
292 * snb_update_pm_irq - update GEN6_PMIMR
293 * @dev_priv: driver private
294 * @interrupt_mask: mask of interrupt bits to update
295 * @enabled_irq_mask: mask of interrupt bits to enable
297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
298 uint32_t interrupt_mask,
299 uint32_t enabled_irq_mask)
303 WARN_ON(enabled_irq_mask & ~interrupt_mask);
305 assert_spin_locked(&dev_priv->irq_lock);
307 new_val = dev_priv->pm_imr;
308 new_val &= ~interrupt_mask;
309 new_val |= (~enabled_irq_mask & interrupt_mask);
311 if (new_val != dev_priv->pm_imr) {
312 dev_priv->pm_imr = new_val;
313 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
314 POSTING_READ(gen6_pm_imr(dev_priv));
318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
320 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
323 snb_update_pm_irq(dev_priv, mask, mask);
326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
328 snb_update_pm_irq(dev_priv, mask, 0);
331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
336 __gen6_mask_pm_irq(dev_priv, mask);
339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
343 assert_spin_locked(&dev_priv->irq_lock);
345 I915_WRITE(reg, reset_mask);
346 I915_WRITE(reg, reset_mask);
350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
352 assert_spin_locked(&dev_priv->irq_lock);
354 dev_priv->pm_ier |= enable_mask;
355 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
356 gen6_unmask_pm_irq(dev_priv, enable_mask);
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
362 assert_spin_locked(&dev_priv->irq_lock);
364 dev_priv->pm_ier &= ~disable_mask;
365 __gen6_mask_pm_irq(dev_priv, disable_mask);
366 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
367 /* though a barrier is missing here, but don't really need a one */
370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
372 spin_lock_irq(&dev_priv->irq_lock);
373 gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
374 dev_priv->rps.pm_iir = 0;
375 spin_unlock_irq(&dev_priv->irq_lock);
378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
380 if (READ_ONCE(dev_priv->rps.interrupts_enabled))
383 spin_lock_irq(&dev_priv->irq_lock);
384 WARN_ON_ONCE(dev_priv->rps.pm_iir);
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
386 dev_priv->rps.interrupts_enabled = true;
387 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
389 spin_unlock_irq(&dev_priv->irq_lock);
392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
394 return (mask & ~dev_priv->rps.pm_intr_keep);
397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
399 if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
402 spin_lock_irq(&dev_priv->irq_lock);
403 dev_priv->rps.interrupts_enabled = false;
405 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
407 gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
409 spin_unlock_irq(&dev_priv->irq_lock);
410 synchronize_irq(dev_priv->drm.irq);
412 /* Now that we will not be generating any more work, flush any
413 * outsanding tasks. As we are called on the RPS idle path,
414 * we will reset the GPU to minimum frequencies, so the current
415 * state of the worker can be discarded.
417 cancel_work_sync(&dev_priv->rps.work);
418 gen6_reset_rps_interrupts(dev_priv);
421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
423 spin_lock_irq(&dev_priv->irq_lock);
424 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
425 spin_unlock_irq(&dev_priv->irq_lock);
428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
430 spin_lock_irq(&dev_priv->irq_lock);
431 if (!dev_priv->guc.interrupts_enabled) {
432 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
433 dev_priv->pm_guc_events);
434 dev_priv->guc.interrupts_enabled = true;
435 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
437 spin_unlock_irq(&dev_priv->irq_lock);
440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
442 spin_lock_irq(&dev_priv->irq_lock);
443 dev_priv->guc.interrupts_enabled = false;
445 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
447 spin_unlock_irq(&dev_priv->irq_lock);
448 synchronize_irq(dev_priv->drm.irq);
450 gen9_reset_guc_interrupts(dev_priv);
454 * bdw_update_port_irq - update DE port interrupt
455 * @dev_priv: driver private
456 * @interrupt_mask: mask of interrupt bits to update
457 * @enabled_irq_mask: mask of interrupt bits to enable
459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
460 uint32_t interrupt_mask,
461 uint32_t enabled_irq_mask)
466 assert_spin_locked(&dev_priv->irq_lock);
468 WARN_ON(enabled_irq_mask & ~interrupt_mask);
470 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
473 old_val = I915_READ(GEN8_DE_PORT_IMR);
476 new_val &= ~interrupt_mask;
477 new_val |= (~enabled_irq_mask & interrupt_mask);
479 if (new_val != old_val) {
480 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
481 POSTING_READ(GEN8_DE_PORT_IMR);
486 * bdw_update_pipe_irq - update DE pipe interrupt
487 * @dev_priv: driver private
488 * @pipe: pipe whose interrupt to update
489 * @interrupt_mask: mask of interrupt bits to update
490 * @enabled_irq_mask: mask of interrupt bits to enable
492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
494 uint32_t interrupt_mask,
495 uint32_t enabled_irq_mask)
499 assert_spin_locked(&dev_priv->irq_lock);
501 WARN_ON(enabled_irq_mask & ~interrupt_mask);
503 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
506 new_val = dev_priv->de_irq_mask[pipe];
507 new_val &= ~interrupt_mask;
508 new_val |= (~enabled_irq_mask & interrupt_mask);
510 if (new_val != dev_priv->de_irq_mask[pipe]) {
511 dev_priv->de_irq_mask[pipe] = new_val;
512 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
513 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
518 * ibx_display_interrupt_update - update SDEIMR
519 * @dev_priv: driver private
520 * @interrupt_mask: mask of interrupt bits to update
521 * @enabled_irq_mask: mask of interrupt bits to enable
523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
524 uint32_t interrupt_mask,
525 uint32_t enabled_irq_mask)
527 uint32_t sdeimr = I915_READ(SDEIMR);
528 sdeimr &= ~interrupt_mask;
529 sdeimr |= (~enabled_irq_mask & interrupt_mask);
531 WARN_ON(enabled_irq_mask & ~interrupt_mask);
533 assert_spin_locked(&dev_priv->irq_lock);
535 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
538 I915_WRITE(SDEIMR, sdeimr);
539 POSTING_READ(SDEIMR);
543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
544 u32 enable_mask, u32 status_mask)
546 i915_reg_t reg = PIPESTAT(pipe);
547 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
549 assert_spin_locked(&dev_priv->irq_lock);
550 WARN_ON(!intel_irqs_enabled(dev_priv));
552 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
553 status_mask & ~PIPESTAT_INT_STATUS_MASK,
554 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
555 pipe_name(pipe), enable_mask, status_mask))
558 if ((pipestat & enable_mask) == enable_mask)
561 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
563 /* Enable the interrupt, clear any pending status */
564 pipestat |= enable_mask | status_mask;
565 I915_WRITE(reg, pipestat);
570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
571 u32 enable_mask, u32 status_mask)
573 i915_reg_t reg = PIPESTAT(pipe);
574 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
576 assert_spin_locked(&dev_priv->irq_lock);
577 WARN_ON(!intel_irqs_enabled(dev_priv));
579 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
580 status_mask & ~PIPESTAT_INT_STATUS_MASK,
581 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
582 pipe_name(pipe), enable_mask, status_mask))
585 if ((pipestat & enable_mask) == 0)
588 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
590 pipestat &= ~enable_mask;
591 I915_WRITE(reg, pipestat);
595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
597 u32 enable_mask = status_mask << 16;
600 * On pipe A we don't support the PSR interrupt yet,
601 * on pipe B and C the same bit MBZ.
603 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
606 * On pipe B and C we don't support the PSR interrupt yet, on pipe
607 * A the same bit is for perf counters which we don't use either.
609 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
612 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
613 SPRITE0_FLIP_DONE_INT_EN_VLV |
614 SPRITE1_FLIP_DONE_INT_EN_VLV);
615 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
616 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
617 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
618 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
629 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
630 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
633 enable_mask = status_mask << 16;
634 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
643 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
644 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
647 enable_mask = status_mask << 16;
648 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
652 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
653 * @dev_priv: i915 device private
655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
657 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
660 spin_lock_irq(&dev_priv->irq_lock);
662 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
663 if (INTEL_GEN(dev_priv) >= 4)
664 i915_enable_pipestat(dev_priv, PIPE_A,
665 PIPE_LEGACY_BLC_EVENT_STATUS);
667 spin_unlock_irq(&dev_priv->irq_lock);
671 * This timing diagram depicts the video signal in and
672 * around the vertical blanking period.
674 * Assumptions about the fictitious mode used in this example:
676 * vsync_start = vblank_start + 1
677 * vsync_end = vblank_start + 2
678 * vtotal = vblank_start + 3
681 * latch double buffered registers
682 * increment frame counter (ctg+)
683 * generate start of vblank interrupt (gen4+)
686 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
687 * | may be shifted forward 1-3 extra lines via PIPECONF
689 * | | start of vsync:
690 * | | generate vsync interrupt
692 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
693 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
694 * ----va---> <-----------------vb--------------------> <--------va-------------
695 * | | <----vs-----> |
696 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
697 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
698 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
700 * last visible pixel first visible pixel
701 * | increment frame counter (gen3/4)
702 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
704 * x = horizontal active
705 * _ = horizontal blanking
706 * hs = horizontal sync
707 * va = vertical active
708 * vb = vertical blanking
710 * vbs = vblank_start (number)
713 * - most events happen at the start of horizontal sync
714 * - frame start happens at the start of horizontal blank, 1-4 lines
715 * (depending on PIPECONF settings) after the start of vblank
716 * - gen3/4 pixel and frame counter are synchronized with the start
717 * of horizontal active on the first line of vertical active
720 /* Called from drm generic code, passed a 'crtc', which
721 * we use as a pipe index
723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
725 struct drm_i915_private *dev_priv = to_i915(dev);
726 i915_reg_t high_frame, low_frame;
727 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
728 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
730 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
732 htotal = mode->crtc_htotal;
733 hsync_start = mode->crtc_hsync_start;
734 vbl_start = mode->crtc_vblank_start;
735 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
736 vbl_start = DIV_ROUND_UP(vbl_start, 2);
738 /* Convert to pixel count */
741 /* Start of vblank event occurs at start of hsync */
742 vbl_start -= htotal - hsync_start;
744 high_frame = PIPEFRAME(pipe);
745 low_frame = PIPEFRAMEPIXEL(pipe);
748 * High & low register fields aren't synchronized, so make sure
749 * we get a low value that's stable across two reads of the high
753 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
754 low = I915_READ(low_frame);
755 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
756 } while (high1 != high2);
758 high1 >>= PIPE_FRAME_HIGH_SHIFT;
759 pixel = low & PIPE_PIXEL_MASK;
760 low >>= PIPE_FRAME_LOW_SHIFT;
763 * The frame counter increments at beginning of active.
764 * Cook up a vblank counter by also checking the pixel
765 * counter against vblank start.
767 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
772 struct drm_i915_private *dev_priv = to_i915(dev);
774 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
780 struct drm_device *dev = crtc->base.dev;
781 struct drm_i915_private *dev_priv = to_i915(dev);
782 const struct drm_display_mode *mode = &crtc->base.hwmode;
783 enum pipe pipe = crtc->pipe;
784 int position, vtotal;
786 vtotal = mode->crtc_vtotal;
787 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
790 if (IS_GEN2(dev_priv))
791 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
793 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
796 * On HSW, the DSL reg (0x70000) appears to return 0 if we
797 * read it just before the start of vblank. So try it again
798 * so we don't accidentally end up spanning a vblank frame
799 * increment, causing the pipe_update_end() code to squak at us.
801 * The nature of this problem means we can't simply check the ISR
802 * bit and return the vblank start value; nor can we use the scanline
803 * debug register in the transcoder as it appears to have the same
804 * problem. We may need to extend this to include other platforms,
805 * but so far testing only shows the problem on HSW.
807 if (HAS_DDI(dev_priv) && !position) {
810 for (i = 0; i < 100; i++) {
812 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
814 if (temp != position) {
822 * See update_scanline_offset() for the details on the
823 * scanline_offset adjustment.
825 return (position + crtc->scanline_offset) % vtotal;
828 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
829 unsigned int flags, int *vpos, int *hpos,
830 ktime_t *stime, ktime_t *etime,
831 const struct drm_display_mode *mode)
833 struct drm_i915_private *dev_priv = to_i915(dev);
834 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
837 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
840 unsigned long irqflags;
842 if (WARN_ON(!mode->crtc_clock)) {
843 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
844 "pipe %c\n", pipe_name(pipe));
848 htotal = mode->crtc_htotal;
849 hsync_start = mode->crtc_hsync_start;
850 vtotal = mode->crtc_vtotal;
851 vbl_start = mode->crtc_vblank_start;
852 vbl_end = mode->crtc_vblank_end;
854 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
855 vbl_start = DIV_ROUND_UP(vbl_start, 2);
860 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
863 * Lock uncore.lock, as we will do multiple timing critical raw
864 * register reads, potentially with preemption disabled, so the
865 * following code must not block on uncore.lock.
867 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
869 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
871 /* Get optional system timestamp before query. */
873 *stime = ktime_get();
875 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
876 /* No obvious pixelcount register. Only query vertical
877 * scanout position from Display scan line register.
879 position = __intel_get_crtc_scanline(intel_crtc);
881 /* Have access to pixelcount since start of frame.
882 * We can split this into vertical and horizontal
885 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
887 /* convert to pixel counts */
893 * In interlaced modes, the pixel counter counts all pixels,
894 * so one field will have htotal more pixels. In order to avoid
895 * the reported position from jumping backwards when the pixel
896 * counter is beyond the length of the shorter field, just
897 * clamp the position the length of the shorter field. This
898 * matches how the scanline counter based position works since
899 * the scanline counter doesn't count the two half lines.
901 if (position >= vtotal)
902 position = vtotal - 1;
905 * Start of vblank interrupt is triggered at start of hsync,
906 * just prior to the first active line of vblank. However we
907 * consider lines to start at the leading edge of horizontal
908 * active. So, should we get here before we've crossed into
909 * the horizontal active of the first line in vblank, we would
910 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
911 * always add htotal-hsync_start to the current pixel position.
913 position = (position + htotal - hsync_start) % vtotal;
916 /* Get optional system timestamp after query. */
918 *etime = ktime_get();
920 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
922 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924 in_vbl = position >= vbl_start && position < vbl_end;
927 * While in vblank, position will be negative
928 * counting up towards 0 at vbl_end. And outside
929 * vblank, position will be positive counting
932 if (position >= vbl_start)
935 position += vtotal - vbl_end;
937 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
941 *vpos = position / htotal;
942 *hpos = position - (*vpos * htotal);
947 ret |= DRM_SCANOUTPOS_IN_VBLANK;
952 int intel_get_crtc_scanline(struct intel_crtc *crtc)
954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
955 unsigned long irqflags;
958 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
959 position = __intel_get_crtc_scanline(crtc);
960 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
965 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
967 struct timeval *vblank_time,
970 struct drm_i915_private *dev_priv = to_i915(dev);
971 struct intel_crtc *crtc;
973 if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
974 DRM_ERROR("Invalid crtc %u\n", pipe);
978 /* Get drm_crtc to timestamp: */
979 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
981 DRM_ERROR("Invalid crtc %u\n", pipe);
985 if (!crtc->base.hwmode.crtc_clock) {
986 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
990 /* Helper routine in DRM core does all the work: */
991 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
996 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
998 u32 busy_up, busy_down, max_avg, min_avg;
1001 spin_lock(&mchdev_lock);
1003 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1005 new_delay = dev_priv->ips.cur_delay;
1007 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1008 busy_up = I915_READ(RCPREVBSYTUPAVG);
1009 busy_down = I915_READ(RCPREVBSYTDNAVG);
1010 max_avg = I915_READ(RCBMAXAVG);
1011 min_avg = I915_READ(RCBMINAVG);
1013 /* Handle RCS change request from hw */
1014 if (busy_up > max_avg) {
1015 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1016 new_delay = dev_priv->ips.cur_delay - 1;
1017 if (new_delay < dev_priv->ips.max_delay)
1018 new_delay = dev_priv->ips.max_delay;
1019 } else if (busy_down < min_avg) {
1020 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1021 new_delay = dev_priv->ips.cur_delay + 1;
1022 if (new_delay > dev_priv->ips.min_delay)
1023 new_delay = dev_priv->ips.min_delay;
1026 if (ironlake_set_drps(dev_priv, new_delay))
1027 dev_priv->ips.cur_delay = new_delay;
1029 spin_unlock(&mchdev_lock);
1034 static void notify_ring(struct intel_engine_cs *engine)
1036 set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1037 if (intel_engine_wakeup(engine))
1038 trace_i915_gem_request_notify(engine);
1041 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1042 struct intel_rps_ei *ei)
1044 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1045 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1046 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1049 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1050 const struct intel_rps_ei *old,
1051 const struct intel_rps_ei *now,
1055 unsigned int mul = 100;
1057 if (old->cz_clock == 0)
1060 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1063 time = now->cz_clock - old->cz_clock;
1064 time *= threshold * dev_priv->czclk_freq;
1066 /* Workload can be split between render + media, e.g. SwapBuffers
1067 * being blitted in X after being rendered in mesa. To account for
1068 * this we need to combine both engines into our activity counter.
1070 c0 = now->render_c0 - old->render_c0;
1071 c0 += now->media_c0 - old->media_c0;
1072 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1077 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1079 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1080 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1083 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1085 struct intel_rps_ei now;
1088 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1091 vlv_c0_read(dev_priv, &now);
1092 if (now.cz_clock == 0)
1095 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1096 if (!vlv_c0_above(dev_priv,
1097 &dev_priv->rps.down_ei, &now,
1098 dev_priv->rps.down_threshold))
1099 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1100 dev_priv->rps.down_ei = now;
1103 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1104 if (vlv_c0_above(dev_priv,
1105 &dev_priv->rps.up_ei, &now,
1106 dev_priv->rps.up_threshold))
1107 events |= GEN6_PM_RP_UP_THRESHOLD;
1108 dev_priv->rps.up_ei = now;
1114 static bool any_waiters(struct drm_i915_private *dev_priv)
1116 struct intel_engine_cs *engine;
1117 enum intel_engine_id id;
1119 for_each_engine(engine, dev_priv, id)
1120 if (intel_engine_has_waiter(engine))
1126 static void gen6_pm_rps_work(struct work_struct *work)
1128 struct drm_i915_private *dev_priv =
1129 container_of(work, struct drm_i915_private, rps.work);
1131 int new_delay, adj, min, max;
1134 spin_lock_irq(&dev_priv->irq_lock);
1135 /* Speed up work cancelation during disabling rps interrupts. */
1136 if (!dev_priv->rps.interrupts_enabled) {
1137 spin_unlock_irq(&dev_priv->irq_lock);
1141 pm_iir = dev_priv->rps.pm_iir;
1142 dev_priv->rps.pm_iir = 0;
1143 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1144 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1145 client_boost = dev_priv->rps.client_boost;
1146 dev_priv->rps.client_boost = false;
1147 spin_unlock_irq(&dev_priv->irq_lock);
1149 /* Make sure we didn't queue anything we're not going to process. */
1150 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1152 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1155 mutex_lock(&dev_priv->rps.hw_lock);
1157 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1159 adj = dev_priv->rps.last_adj;
1160 new_delay = dev_priv->rps.cur_freq;
1161 min = dev_priv->rps.min_freq_softlimit;
1162 max = dev_priv->rps.max_freq_softlimit;
1163 if (client_boost || any_waiters(dev_priv))
1164 max = dev_priv->rps.max_freq;
1165 if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1166 new_delay = dev_priv->rps.boost_freq;
1168 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1171 else /* CHV needs even encode values */
1172 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1174 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1177 * For better performance, jump directly
1178 * to RPe if we're below it.
1180 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1181 new_delay = dev_priv->rps.efficient_freq;
1184 } else if (client_boost || any_waiters(dev_priv)) {
1186 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1187 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1188 new_delay = dev_priv->rps.efficient_freq;
1190 new_delay = dev_priv->rps.min_freq_softlimit;
1192 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1195 else /* CHV needs even encode values */
1196 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1198 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1200 } else { /* unknown event */
1204 dev_priv->rps.last_adj = adj;
1206 /* sysfs frequency interfaces may have snuck in while servicing the
1210 new_delay = clamp_t(int, new_delay, min, max);
1212 if (intel_set_rps(dev_priv, new_delay)) {
1213 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1214 dev_priv->rps.last_adj = 0;
1217 mutex_unlock(&dev_priv->rps.hw_lock);
1222 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1224 * @work: workqueue struct
1226 * Doesn't actually do anything except notify userspace. As a consequence of
1227 * this event, userspace should try to remap the bad rows since statistically
1228 * it is likely the same row is more likely to go bad again.
1230 static void ivybridge_parity_work(struct work_struct *work)
1232 struct drm_i915_private *dev_priv =
1233 container_of(work, struct drm_i915_private, l3_parity.error_work);
1234 u32 error_status, row, bank, subbank;
1235 char *parity_event[6];
1239 /* We must turn off DOP level clock gating to access the L3 registers.
1240 * In order to prevent a get/put style interface, acquire struct mutex
1241 * any time we access those registers.
1243 mutex_lock(&dev_priv->drm.struct_mutex);
1245 /* If we've screwed up tracking, just let the interrupt fire again */
1246 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1249 misccpctl = I915_READ(GEN7_MISCCPCTL);
1250 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1251 POSTING_READ(GEN7_MISCCPCTL);
1253 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1257 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1260 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1262 reg = GEN7_L3CDERRST1(slice);
1264 error_status = I915_READ(reg);
1265 row = GEN7_PARITY_ERROR_ROW(error_status);
1266 bank = GEN7_PARITY_ERROR_BANK(error_status);
1267 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1269 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1272 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1273 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1274 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1275 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1276 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1277 parity_event[5] = NULL;
1279 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1280 KOBJ_CHANGE, parity_event);
1282 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1283 slice, row, bank, subbank);
1285 kfree(parity_event[4]);
1286 kfree(parity_event[3]);
1287 kfree(parity_event[2]);
1288 kfree(parity_event[1]);
1291 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1294 WARN_ON(dev_priv->l3_parity.which_slice);
1295 spin_lock_irq(&dev_priv->irq_lock);
1296 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1297 spin_unlock_irq(&dev_priv->irq_lock);
1299 mutex_unlock(&dev_priv->drm.struct_mutex);
1302 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1305 if (!HAS_L3_DPF(dev_priv))
1308 spin_lock(&dev_priv->irq_lock);
1309 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1310 spin_unlock(&dev_priv->irq_lock);
1312 iir &= GT_PARITY_ERROR(dev_priv);
1313 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1314 dev_priv->l3_parity.which_slice |= 1 << 1;
1316 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1317 dev_priv->l3_parity.which_slice |= 1 << 0;
1319 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1322 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1325 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1326 notify_ring(dev_priv->engine[RCS]);
1327 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1328 notify_ring(dev_priv->engine[VCS]);
1331 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1334 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1335 notify_ring(dev_priv->engine[RCS]);
1336 if (gt_iir & GT_BSD_USER_INTERRUPT)
1337 notify_ring(dev_priv->engine[VCS]);
1338 if (gt_iir & GT_BLT_USER_INTERRUPT)
1339 notify_ring(dev_priv->engine[BCS]);
1341 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1342 GT_BSD_CS_ERROR_INTERRUPT |
1343 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1344 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1346 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1347 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1350 static __always_inline void
1351 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1353 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1354 notify_ring(engine);
1356 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1357 set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1358 tasklet_hi_schedule(&engine->irq_tasklet);
1362 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1366 irqreturn_t ret = IRQ_NONE;
1368 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1369 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1371 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1374 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1377 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1378 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1380 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1383 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1386 if (master_ctl & GEN8_GT_VECS_IRQ) {
1387 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1389 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1392 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1395 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1396 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1397 if (gt_iir[2] & (dev_priv->pm_rps_events |
1398 dev_priv->pm_guc_events)) {
1399 I915_WRITE_FW(GEN8_GT_IIR(2),
1400 gt_iir[2] & (dev_priv->pm_rps_events |
1401 dev_priv->pm_guc_events));
1404 DRM_ERROR("The master control interrupt lied (PM)!\n");
1410 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1414 gen8_cs_irq_handler(dev_priv->engine[RCS],
1415 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1416 gen8_cs_irq_handler(dev_priv->engine[BCS],
1417 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1421 gen8_cs_irq_handler(dev_priv->engine[VCS],
1422 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1423 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1424 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1428 gen8_cs_irq_handler(dev_priv->engine[VECS],
1429 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1431 if (gt_iir[2] & dev_priv->pm_rps_events)
1432 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1434 if (gt_iir[2] & dev_priv->pm_guc_events)
1435 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1438 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1442 return val & PORTA_HOTPLUG_LONG_DETECT;
1444 return val & PORTB_HOTPLUG_LONG_DETECT;
1446 return val & PORTC_HOTPLUG_LONG_DETECT;
1452 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1456 return val & PORTE_HOTPLUG_LONG_DETECT;
1462 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1466 return val & PORTA_HOTPLUG_LONG_DETECT;
1468 return val & PORTB_HOTPLUG_LONG_DETECT;
1470 return val & PORTC_HOTPLUG_LONG_DETECT;
1472 return val & PORTD_HOTPLUG_LONG_DETECT;
1478 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1482 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1488 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1492 return val & PORTB_HOTPLUG_LONG_DETECT;
1494 return val & PORTC_HOTPLUG_LONG_DETECT;
1496 return val & PORTD_HOTPLUG_LONG_DETECT;
1502 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1506 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1508 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1510 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1517 * Get a bit mask of pins that have triggered, and which ones may be long.
1518 * This can be called multiple times with the same masks to accumulate
1519 * hotplug detection results from several registers.
1521 * Note that the caller is expected to zero out the masks initially.
1523 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1524 u32 hotplug_trigger, u32 dig_hotplug_reg,
1525 const u32 hpd[HPD_NUM_PINS],
1526 bool long_pulse_detect(enum port port, u32 val))
1531 for_each_hpd_pin(i) {
1532 if ((hpd[i] & hotplug_trigger) == 0)
1535 *pin_mask |= BIT(i);
1537 if (!intel_hpd_pin_to_port(i, &port))
1540 if (long_pulse_detect(port, dig_hotplug_reg))
1541 *long_mask |= BIT(i);
1544 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1545 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1549 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1551 wake_up_all(&dev_priv->gmbus_wait_queue);
1554 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1556 wake_up_all(&dev_priv->gmbus_wait_queue);
1559 #if defined(CONFIG_DEBUG_FS)
1560 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1562 uint32_t crc0, uint32_t crc1,
1563 uint32_t crc2, uint32_t crc3,
1566 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1567 struct intel_pipe_crc_entry *entry;
1568 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1569 struct drm_driver *driver = dev_priv->drm.driver;
1573 spin_lock(&pipe_crc->lock);
1574 if (pipe_crc->source) {
1575 if (!pipe_crc->entries) {
1576 spin_unlock(&pipe_crc->lock);
1577 DRM_DEBUG_KMS("spurious interrupt\n");
1581 head = pipe_crc->head;
1582 tail = pipe_crc->tail;
1584 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1585 spin_unlock(&pipe_crc->lock);
1586 DRM_ERROR("CRC buffer overflowing\n");
1590 entry = &pipe_crc->entries[head];
1592 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1593 entry->crc[0] = crc0;
1594 entry->crc[1] = crc1;
1595 entry->crc[2] = crc2;
1596 entry->crc[3] = crc3;
1597 entry->crc[4] = crc4;
1599 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1600 pipe_crc->head = head;
1602 spin_unlock(&pipe_crc->lock);
1604 wake_up_interruptible(&pipe_crc->wq);
1607 * For some not yet identified reason, the first CRC is
1608 * bonkers. So let's just wait for the next vblank and read
1609 * out the buggy result.
1611 * On CHV sometimes the second CRC is bonkers as well, so
1612 * don't trust that one either.
1614 if (pipe_crc->skipped == 0 ||
1615 (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1616 pipe_crc->skipped++;
1617 spin_unlock(&pipe_crc->lock);
1620 spin_unlock(&pipe_crc->lock);
1626 drm_crtc_add_crc_entry(&crtc->base, true,
1627 drm_accurate_vblank_count(&crtc->base),
1633 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1635 uint32_t crc0, uint32_t crc1,
1636 uint32_t crc2, uint32_t crc3,
1641 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1644 display_pipe_crc_irq_handler(dev_priv, pipe,
1645 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1649 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1652 display_pipe_crc_irq_handler(dev_priv, pipe,
1653 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1654 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1655 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1656 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1657 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1660 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1663 uint32_t res1, res2;
1665 if (INTEL_GEN(dev_priv) >= 3)
1666 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1670 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1671 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1675 display_pipe_crc_irq_handler(dev_priv, pipe,
1676 I915_READ(PIPE_CRC_RES_RED(pipe)),
1677 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1678 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1682 /* The RPS events need forcewake, so we add them to a work queue and mask their
1683 * IMR bits until the work is done. Other interrupts can be processed without
1684 * the work queue. */
1685 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1687 if (pm_iir & dev_priv->pm_rps_events) {
1688 spin_lock(&dev_priv->irq_lock);
1689 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1690 if (dev_priv->rps.interrupts_enabled) {
1691 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1692 schedule_work(&dev_priv->rps.work);
1694 spin_unlock(&dev_priv->irq_lock);
1697 if (INTEL_INFO(dev_priv)->gen >= 8)
1700 if (HAS_VEBOX(dev_priv)) {
1701 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1702 notify_ring(dev_priv->engine[VECS]);
1704 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1705 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1709 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1711 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1712 /* Sample the log buffer flush related bits & clear them out now
1713 * itself from the message identity register to minimize the
1714 * probability of losing a flush interrupt, when there are back
1715 * to back flush interrupts.
1716 * There can be a new flush interrupt, for different log buffer
1717 * type (like for ISR), whilst Host is handling one (for DPC).
1718 * Since same bit is used in message register for ISR & DPC, it
1719 * could happen that GuC sets the bit for 2nd interrupt but Host
1720 * clears out the bit on handling the 1st interrupt.
1724 msg = I915_READ(SOFT_SCRATCH(15));
1725 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1726 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1728 /* Clear the message bits that are handled */
1729 I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1731 /* Handle flush interrupt in bottom half */
1732 queue_work(dev_priv->guc.log.flush_wq,
1733 &dev_priv->guc.log.flush_work);
1735 dev_priv->guc.log.flush_interrupt_count++;
1737 /* Not clearing of unhandled event bits won't result in
1738 * re-triggering of the interrupt.
1744 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1749 ret = drm_handle_vblank(&dev_priv->drm, pipe);
1751 intel_finish_page_flip_mmio(dev_priv, pipe);
1756 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1757 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1761 spin_lock(&dev_priv->irq_lock);
1763 if (!dev_priv->display_irqs_enabled) {
1764 spin_unlock(&dev_priv->irq_lock);
1768 for_each_pipe(dev_priv, pipe) {
1770 u32 mask, iir_bit = 0;
1773 * PIPESTAT bits get signalled even when the interrupt is
1774 * disabled with the mask bits, and some of the status bits do
1775 * not generate interrupts at all (like the underrun bit). Hence
1776 * we need to be careful that we only handle what we want to
1780 /* fifo underruns are filterered in the underrun handler. */
1781 mask = PIPE_FIFO_UNDERRUN_STATUS;
1785 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1788 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1791 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1795 mask |= dev_priv->pipestat_irq_mask[pipe];
1800 reg = PIPESTAT(pipe);
1801 mask |= PIPESTAT_INT_ENABLE_MASK;
1802 pipe_stats[pipe] = I915_READ(reg) & mask;
1805 * Clear the PIPE*STAT regs before the IIR
1807 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1808 PIPESTAT_INT_STATUS_MASK))
1809 I915_WRITE(reg, pipe_stats[pipe]);
1811 spin_unlock(&dev_priv->irq_lock);
1814 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1815 u32 pipe_stats[I915_MAX_PIPES])
1819 for_each_pipe(dev_priv, pipe) {
1820 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1821 intel_pipe_handle_vblank(dev_priv, pipe))
1822 intel_check_page_flip(dev_priv, pipe);
1824 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1825 intel_finish_page_flip_cs(dev_priv, pipe);
1827 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1828 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1830 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1831 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1834 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1835 gmbus_irq_handler(dev_priv);
1838 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1840 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1843 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1845 return hotplug_status;
1848 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1851 u32 pin_mask = 0, long_mask = 0;
1853 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1854 IS_CHERRYVIEW(dev_priv)) {
1855 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1857 if (hotplug_trigger) {
1858 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1859 hotplug_trigger, hpd_status_g4x,
1860 i9xx_port_hotplug_long_detect);
1862 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1865 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1866 dp_aux_irq_handler(dev_priv);
1868 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1870 if (hotplug_trigger) {
1871 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1872 hotplug_trigger, hpd_status_i915,
1873 i9xx_port_hotplug_long_detect);
1874 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1879 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1881 struct drm_device *dev = arg;
1882 struct drm_i915_private *dev_priv = to_i915(dev);
1883 irqreturn_t ret = IRQ_NONE;
1885 if (!intel_irqs_enabled(dev_priv))
1888 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1889 disable_rpm_wakeref_asserts(dev_priv);
1892 u32 iir, gt_iir, pm_iir;
1893 u32 pipe_stats[I915_MAX_PIPES] = {};
1894 u32 hotplug_status = 0;
1897 gt_iir = I915_READ(GTIIR);
1898 pm_iir = I915_READ(GEN6_PMIIR);
1899 iir = I915_READ(VLV_IIR);
1901 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1907 * Theory on interrupt generation, based on empirical evidence:
1909 * x = ((VLV_IIR & VLV_IER) ||
1910 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1911 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1913 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1914 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1915 * guarantee the CPU interrupt will be raised again even if we
1916 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1917 * bits this time around.
1919 I915_WRITE(VLV_MASTER_IER, 0);
1920 ier = I915_READ(VLV_IER);
1921 I915_WRITE(VLV_IER, 0);
1924 I915_WRITE(GTIIR, gt_iir);
1926 I915_WRITE(GEN6_PMIIR, pm_iir);
1928 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1929 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1931 /* Call regardless, as some status bits might not be
1932 * signalled in iir */
1933 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1936 * VLV_IIR is single buffered, and reflects the level
1937 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1940 I915_WRITE(VLV_IIR, iir);
1942 I915_WRITE(VLV_IER, ier);
1943 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1944 POSTING_READ(VLV_MASTER_IER);
1947 snb_gt_irq_handler(dev_priv, gt_iir);
1949 gen6_rps_irq_handler(dev_priv, pm_iir);
1952 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1954 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1957 enable_rpm_wakeref_asserts(dev_priv);
1962 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1964 struct drm_device *dev = arg;
1965 struct drm_i915_private *dev_priv = to_i915(dev);
1966 irqreturn_t ret = IRQ_NONE;
1968 if (!intel_irqs_enabled(dev_priv))
1971 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1972 disable_rpm_wakeref_asserts(dev_priv);
1975 u32 master_ctl, iir;
1977 u32 pipe_stats[I915_MAX_PIPES] = {};
1978 u32 hotplug_status = 0;
1981 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1982 iir = I915_READ(VLV_IIR);
1984 if (master_ctl == 0 && iir == 0)
1990 * Theory on interrupt generation, based on empirical evidence:
1992 * x = ((VLV_IIR & VLV_IER) ||
1993 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1994 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1996 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1997 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1998 * guarantee the CPU interrupt will be raised again even if we
1999 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2000 * bits this time around.
2002 I915_WRITE(GEN8_MASTER_IRQ, 0);
2003 ier = I915_READ(VLV_IER);
2004 I915_WRITE(VLV_IER, 0);
2006 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2008 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2009 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2011 /* Call regardless, as some status bits might not be
2012 * signalled in iir */
2013 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2016 * VLV_IIR is single buffered, and reflects the level
2017 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2020 I915_WRITE(VLV_IIR, iir);
2022 I915_WRITE(VLV_IER, ier);
2023 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2024 POSTING_READ(GEN8_MASTER_IRQ);
2026 gen8_gt_irq_handler(dev_priv, gt_iir);
2029 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2031 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2034 enable_rpm_wakeref_asserts(dev_priv);
2039 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2040 u32 hotplug_trigger,
2041 const u32 hpd[HPD_NUM_PINS])
2043 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2046 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2047 * unless we touch the hotplug register, even if hotplug_trigger is
2048 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2051 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2052 if (!hotplug_trigger) {
2053 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2054 PORTD_HOTPLUG_STATUS_MASK |
2055 PORTC_HOTPLUG_STATUS_MASK |
2056 PORTB_HOTPLUG_STATUS_MASK;
2057 dig_hotplug_reg &= ~mask;
2060 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2061 if (!hotplug_trigger)
2064 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2065 dig_hotplug_reg, hpd,
2066 pch_port_hotplug_long_detect);
2068 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2071 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2074 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2076 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2078 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2079 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2080 SDE_AUDIO_POWER_SHIFT);
2081 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2085 if (pch_iir & SDE_AUX_MASK)
2086 dp_aux_irq_handler(dev_priv);
2088 if (pch_iir & SDE_GMBUS)
2089 gmbus_irq_handler(dev_priv);
2091 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2092 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2094 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2095 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2097 if (pch_iir & SDE_POISON)
2098 DRM_ERROR("PCH poison interrupt\n");
2100 if (pch_iir & SDE_FDI_MASK)
2101 for_each_pipe(dev_priv, pipe)
2102 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2104 I915_READ(FDI_RX_IIR(pipe)));
2106 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2107 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2109 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2110 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2112 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2113 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2115 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2116 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2119 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2121 u32 err_int = I915_READ(GEN7_ERR_INT);
2124 if (err_int & ERR_INT_POISON)
2125 DRM_ERROR("Poison interrupt\n");
2127 for_each_pipe(dev_priv, pipe) {
2128 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2129 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2131 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2132 if (IS_IVYBRIDGE(dev_priv))
2133 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2135 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2139 I915_WRITE(GEN7_ERR_INT, err_int);
2142 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2144 u32 serr_int = I915_READ(SERR_INT);
2146 if (serr_int & SERR_INT_POISON)
2147 DRM_ERROR("PCH poison interrupt\n");
2149 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2150 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2152 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2153 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2155 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2156 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2158 I915_WRITE(SERR_INT, serr_int);
2161 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2164 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2166 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2168 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2169 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2170 SDE_AUDIO_POWER_SHIFT_CPT);
2171 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2175 if (pch_iir & SDE_AUX_MASK_CPT)
2176 dp_aux_irq_handler(dev_priv);
2178 if (pch_iir & SDE_GMBUS_CPT)
2179 gmbus_irq_handler(dev_priv);
2181 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2182 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2184 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2185 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2187 if (pch_iir & SDE_FDI_MASK_CPT)
2188 for_each_pipe(dev_priv, pipe)
2189 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2191 I915_READ(FDI_RX_IIR(pipe)));
2193 if (pch_iir & SDE_ERROR_CPT)
2194 cpt_serr_int_handler(dev_priv);
2197 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2199 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2200 ~SDE_PORTE_HOTPLUG_SPT;
2201 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2202 u32 pin_mask = 0, long_mask = 0;
2204 if (hotplug_trigger) {
2205 u32 dig_hotplug_reg;
2207 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2208 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2210 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2211 dig_hotplug_reg, hpd_spt,
2212 spt_port_hotplug_long_detect);
2215 if (hotplug2_trigger) {
2216 u32 dig_hotplug_reg;
2218 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2219 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2221 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2222 dig_hotplug_reg, hpd_spt,
2223 spt_port_hotplug2_long_detect);
2227 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2229 if (pch_iir & SDE_GMBUS_CPT)
2230 gmbus_irq_handler(dev_priv);
2233 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2234 u32 hotplug_trigger,
2235 const u32 hpd[HPD_NUM_PINS])
2237 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2239 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2240 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2242 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2243 dig_hotplug_reg, hpd,
2244 ilk_port_hotplug_long_detect);
2246 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2249 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2253 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2255 if (hotplug_trigger)
2256 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2258 if (de_iir & DE_AUX_CHANNEL_A)
2259 dp_aux_irq_handler(dev_priv);
2261 if (de_iir & DE_GSE)
2262 intel_opregion_asle_intr(dev_priv);
2264 if (de_iir & DE_POISON)
2265 DRM_ERROR("Poison interrupt\n");
2267 for_each_pipe(dev_priv, pipe) {
2268 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2269 intel_pipe_handle_vblank(dev_priv, pipe))
2270 intel_check_page_flip(dev_priv, pipe);
2272 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2273 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2275 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2276 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2278 /* plane/pipes map 1:1 on ilk+ */
2279 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2280 intel_finish_page_flip_cs(dev_priv, pipe);
2283 /* check event from PCH */
2284 if (de_iir & DE_PCH_EVENT) {
2285 u32 pch_iir = I915_READ(SDEIIR);
2287 if (HAS_PCH_CPT(dev_priv))
2288 cpt_irq_handler(dev_priv, pch_iir);
2290 ibx_irq_handler(dev_priv, pch_iir);
2292 /* should clear PCH hotplug event before clear CPU irq */
2293 I915_WRITE(SDEIIR, pch_iir);
2296 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2297 ironlake_rps_change_irq_handler(dev_priv);
2300 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2304 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2306 if (hotplug_trigger)
2307 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2309 if (de_iir & DE_ERR_INT_IVB)
2310 ivb_err_int_handler(dev_priv);
2312 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2313 dp_aux_irq_handler(dev_priv);
2315 if (de_iir & DE_GSE_IVB)
2316 intel_opregion_asle_intr(dev_priv);
2318 for_each_pipe(dev_priv, pipe) {
2319 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2320 intel_pipe_handle_vblank(dev_priv, pipe))
2321 intel_check_page_flip(dev_priv, pipe);
2323 /* plane/pipes map 1:1 on ilk+ */
2324 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2325 intel_finish_page_flip_cs(dev_priv, pipe);
2328 /* check event from PCH */
2329 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2330 u32 pch_iir = I915_READ(SDEIIR);
2332 cpt_irq_handler(dev_priv, pch_iir);
2334 /* clear PCH hotplug event before clear CPU irq */
2335 I915_WRITE(SDEIIR, pch_iir);
2340 * To handle irqs with the minimum potential races with fresh interrupts, we:
2341 * 1 - Disable Master Interrupt Control.
2342 * 2 - Find the source(s) of the interrupt.
2343 * 3 - Clear the Interrupt Identity bits (IIR).
2344 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2345 * 5 - Re-enable Master Interrupt Control.
2347 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2349 struct drm_device *dev = arg;
2350 struct drm_i915_private *dev_priv = to_i915(dev);
2351 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2352 irqreturn_t ret = IRQ_NONE;
2354 if (!intel_irqs_enabled(dev_priv))
2357 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2358 disable_rpm_wakeref_asserts(dev_priv);
2360 /* disable master interrupt before clearing iir */
2361 de_ier = I915_READ(DEIER);
2362 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2363 POSTING_READ(DEIER);
2365 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2366 * interrupts will will be stored on its back queue, and then we'll be
2367 * able to process them after we restore SDEIER (as soon as we restore
2368 * it, we'll get an interrupt if SDEIIR still has something to process
2369 * due to its back queue). */
2370 if (!HAS_PCH_NOP(dev_priv)) {
2371 sde_ier = I915_READ(SDEIER);
2372 I915_WRITE(SDEIER, 0);
2373 POSTING_READ(SDEIER);
2376 /* Find, clear, then process each source of interrupt */
2378 gt_iir = I915_READ(GTIIR);
2380 I915_WRITE(GTIIR, gt_iir);
2382 if (INTEL_GEN(dev_priv) >= 6)
2383 snb_gt_irq_handler(dev_priv, gt_iir);
2385 ilk_gt_irq_handler(dev_priv, gt_iir);
2388 de_iir = I915_READ(DEIIR);
2390 I915_WRITE(DEIIR, de_iir);
2392 if (INTEL_GEN(dev_priv) >= 7)
2393 ivb_display_irq_handler(dev_priv, de_iir);
2395 ilk_display_irq_handler(dev_priv, de_iir);
2398 if (INTEL_GEN(dev_priv) >= 6) {
2399 u32 pm_iir = I915_READ(GEN6_PMIIR);
2401 I915_WRITE(GEN6_PMIIR, pm_iir);
2403 gen6_rps_irq_handler(dev_priv, pm_iir);
2407 I915_WRITE(DEIER, de_ier);
2408 POSTING_READ(DEIER);
2409 if (!HAS_PCH_NOP(dev_priv)) {
2410 I915_WRITE(SDEIER, sde_ier);
2411 POSTING_READ(SDEIER);
2414 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2415 enable_rpm_wakeref_asserts(dev_priv);
2420 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2421 u32 hotplug_trigger,
2422 const u32 hpd[HPD_NUM_PINS])
2424 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2426 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2427 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2429 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2430 dig_hotplug_reg, hpd,
2431 bxt_port_hotplug_long_detect);
2433 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2437 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2439 irqreturn_t ret = IRQ_NONE;
2443 if (master_ctl & GEN8_DE_MISC_IRQ) {
2444 iir = I915_READ(GEN8_DE_MISC_IIR);
2446 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2448 if (iir & GEN8_DE_MISC_GSE)
2449 intel_opregion_asle_intr(dev_priv);
2451 DRM_ERROR("Unexpected DE Misc interrupt\n");
2454 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2457 if (master_ctl & GEN8_DE_PORT_IRQ) {
2458 iir = I915_READ(GEN8_DE_PORT_IIR);
2463 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2466 tmp_mask = GEN8_AUX_CHANNEL_A;
2467 if (INTEL_INFO(dev_priv)->gen >= 9)
2468 tmp_mask |= GEN9_AUX_CHANNEL_B |
2469 GEN9_AUX_CHANNEL_C |
2472 if (iir & tmp_mask) {
2473 dp_aux_irq_handler(dev_priv);
2477 if (IS_GEN9_LP(dev_priv)) {
2478 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2480 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2484 } else if (IS_BROADWELL(dev_priv)) {
2485 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2487 ilk_hpd_irq_handler(dev_priv,
2493 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2494 gmbus_irq_handler(dev_priv);
2499 DRM_ERROR("Unexpected DE Port interrupt\n");
2502 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2505 for_each_pipe(dev_priv, pipe) {
2506 u32 flip_done, fault_errors;
2508 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2511 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2513 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2518 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2520 if (iir & GEN8_PIPE_VBLANK &&
2521 intel_pipe_handle_vblank(dev_priv, pipe))
2522 intel_check_page_flip(dev_priv, pipe);
2525 if (INTEL_INFO(dev_priv)->gen >= 9)
2526 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2528 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2531 intel_finish_page_flip_cs(dev_priv, pipe);
2533 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2534 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2536 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2537 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2540 if (INTEL_INFO(dev_priv)->gen >= 9)
2541 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2543 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2546 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2551 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2552 master_ctl & GEN8_DE_PCH_IRQ) {
2554 * FIXME(BDW): Assume for now that the new interrupt handling
2555 * scheme also closed the SDE interrupt handling race we've seen
2556 * on older pch-split platforms. But this needs testing.
2558 iir = I915_READ(SDEIIR);
2560 I915_WRITE(SDEIIR, iir);
2563 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2564 spt_irq_handler(dev_priv, iir);
2566 cpt_irq_handler(dev_priv, iir);
2569 * Like on previous PCH there seems to be something
2570 * fishy going on with forwarding PCH interrupts.
2572 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2579 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2581 struct drm_device *dev = arg;
2582 struct drm_i915_private *dev_priv = to_i915(dev);
2587 if (!intel_irqs_enabled(dev_priv))
2590 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2591 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2595 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2597 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2598 disable_rpm_wakeref_asserts(dev_priv);
2600 /* Find, clear, then process each source of interrupt */
2601 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2602 gen8_gt_irq_handler(dev_priv, gt_iir);
2603 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2605 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2606 POSTING_READ_FW(GEN8_MASTER_IRQ);
2608 enable_rpm_wakeref_asserts(dev_priv);
2613 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2616 * Notify all waiters for GPU completion events that reset state has
2617 * been changed, and that they need to restart their wait after
2618 * checking for potential errors (and bail out to drop locks if there is
2619 * a gpu reset pending so that i915_error_work_func can acquire them).
2622 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2623 wake_up_all(&dev_priv->gpu_error.wait_queue);
2625 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2626 wake_up_all(&dev_priv->pending_flip_queue);
2630 * i915_reset_and_wakeup - do process context error handling work
2631 * @dev_priv: i915 device private
2633 * Fire an error uevent so userspace can see that a hang or error
2636 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2638 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2639 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2640 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2641 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2643 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2645 DRM_DEBUG_DRIVER("resetting chip\n");
2646 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2649 * In most cases it's guaranteed that we get here with an RPM
2650 * reference held, for example because there is a pending GPU
2651 * request that won't finish until the reset is done. This
2652 * isn't the case at least when we get here by doing a
2653 * simulated reset via debugs, so get an RPM reference.
2655 intel_runtime_pm_get(dev_priv);
2656 intel_prepare_reset(dev_priv);
2660 * All state reset _must_ be completed before we update the
2661 * reset counter, for otherwise waiters might miss the reset
2662 * pending state and not properly drop locks, resulting in
2663 * deadlocks with the reset work.
2665 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2666 i915_reset(dev_priv);
2667 mutex_unlock(&dev_priv->drm.struct_mutex);
2670 /* We need to wait for anyone holding the lock to wakeup */
2671 } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2672 I915_RESET_IN_PROGRESS,
2673 TASK_UNINTERRUPTIBLE,
2676 intel_finish_reset(dev_priv);
2677 intel_runtime_pm_put(dev_priv);
2679 if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2680 kobject_uevent_env(kobj,
2681 KOBJ_CHANGE, reset_done_event);
2684 * Note: The wake_up also serves as a memory barrier so that
2685 * waiters see the updated value of the dev_priv->gpu_error.
2687 wake_up_all(&dev_priv->gpu_error.reset_queue);
2691 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2692 struct intel_instdone *instdone)
2697 pr_err(" INSTDONE: 0x%08x\n", instdone->instdone);
2699 if (INTEL_GEN(dev_priv) <= 3)
2702 pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2704 if (INTEL_GEN(dev_priv) <= 6)
2707 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2708 pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2709 slice, subslice, instdone->sampler[slice][subslice]);
2711 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2712 pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n",
2713 slice, subslice, instdone->row[slice][subslice]);
2716 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2720 if (!IS_GEN2(dev_priv))
2721 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2723 if (INTEL_GEN(dev_priv) < 4)
2724 I915_WRITE(IPEIR, I915_READ(IPEIR));
2726 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2728 I915_WRITE(EIR, I915_READ(EIR));
2729 eir = I915_READ(EIR);
2732 * some errors might have become stuck,
2735 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2736 I915_WRITE(EMR, I915_READ(EMR) | eir);
2737 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2742 * i915_handle_error - handle a gpu error
2743 * @dev_priv: i915 device private
2744 * @engine_mask: mask representing engines that are hung
2745 * @fmt: Error message format string
2747 * Do some basic checking of register state at error time and
2748 * dump it to the syslog. Also call i915_capture_error_state() to make
2749 * sure we get a record and make it available in debugfs. Fire a uevent
2750 * so userspace knows something bad happened (should trigger collection
2751 * of a ring dump etc.).
2753 void i915_handle_error(struct drm_i915_private *dev_priv,
2755 const char *fmt, ...)
2760 va_start(args, fmt);
2761 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2764 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2765 i915_clear_error_registers(dev_priv);
2770 if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2771 &dev_priv->gpu_error.flags))
2775 * Wakeup waiting processes so that the reset function
2776 * i915_reset_and_wakeup doesn't deadlock trying to grab
2777 * various locks. By bumping the reset counter first, the woken
2778 * processes will see a reset in progress and back off,
2779 * releasing their locks and then wait for the reset completion.
2780 * We must do this for _all_ gpu waiters that might hold locks
2781 * that the reset work needs to acquire.
2783 * Note: The wake_up also provides a memory barrier to ensure that the
2784 * waiters see the updated value of the reset flags.
2786 i915_error_wake_up(dev_priv);
2788 i915_reset_and_wakeup(dev_priv);
2791 /* Called from drm generic code, passed 'crtc' which
2792 * we use as a pipe index
2794 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2796 struct drm_i915_private *dev_priv = to_i915(dev);
2797 unsigned long irqflags;
2799 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2800 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2801 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2806 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2808 struct drm_i915_private *dev_priv = to_i915(dev);
2809 unsigned long irqflags;
2811 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2812 i915_enable_pipestat(dev_priv, pipe,
2813 PIPE_START_VBLANK_INTERRUPT_STATUS);
2814 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2819 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2821 struct drm_i915_private *dev_priv = to_i915(dev);
2822 unsigned long irqflags;
2823 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2824 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2826 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2827 ilk_enable_display_irq(dev_priv, bit);
2828 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2833 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2835 struct drm_i915_private *dev_priv = to_i915(dev);
2836 unsigned long irqflags;
2838 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2839 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2840 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2845 /* Called from drm generic code, passed 'crtc' which
2846 * we use as a pipe index
2848 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2850 struct drm_i915_private *dev_priv = to_i915(dev);
2851 unsigned long irqflags;
2853 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2854 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2855 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2858 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2860 struct drm_i915_private *dev_priv = to_i915(dev);
2861 unsigned long irqflags;
2863 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2864 i915_disable_pipestat(dev_priv, pipe,
2865 PIPE_START_VBLANK_INTERRUPT_STATUS);
2866 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2869 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2871 struct drm_i915_private *dev_priv = to_i915(dev);
2872 unsigned long irqflags;
2873 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2874 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2876 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2877 ilk_disable_display_irq(dev_priv, bit);
2878 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2881 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2883 struct drm_i915_private *dev_priv = to_i915(dev);
2884 unsigned long irqflags;
2886 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2887 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2888 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2891 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2893 if (HAS_PCH_NOP(dev_priv))
2896 GEN5_IRQ_RESET(SDE);
2898 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2899 I915_WRITE(SERR_INT, 0xffffffff);
2903 * SDEIER is also touched by the interrupt handler to work around missed PCH
2904 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2905 * instead we unconditionally enable all PCH interrupt sources here, but then
2906 * only unmask them as needed with SDEIMR.
2908 * This function needs to be called before interrupts are enabled.
2910 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2912 struct drm_i915_private *dev_priv = to_i915(dev);
2914 if (HAS_PCH_NOP(dev_priv))
2917 WARN_ON(I915_READ(SDEIER) != 0);
2918 I915_WRITE(SDEIER, 0xffffffff);
2919 POSTING_READ(SDEIER);
2922 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2925 if (INTEL_GEN(dev_priv) >= 6)
2926 GEN5_IRQ_RESET(GEN6_PM);
2929 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2933 if (IS_CHERRYVIEW(dev_priv))
2934 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2936 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2938 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2939 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2941 for_each_pipe(dev_priv, pipe) {
2942 I915_WRITE(PIPESTAT(pipe),
2943 PIPE_FIFO_UNDERRUN_STATUS |
2944 PIPESTAT_INT_STATUS_MASK);
2945 dev_priv->pipestat_irq_mask[pipe] = 0;
2948 GEN5_IRQ_RESET(VLV_);
2949 dev_priv->irq_mask = ~0;
2952 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2958 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2959 PIPE_CRC_DONE_INTERRUPT_STATUS;
2961 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2962 for_each_pipe(dev_priv, pipe)
2963 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2965 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2966 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2967 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2968 if (IS_CHERRYVIEW(dev_priv))
2969 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2971 WARN_ON(dev_priv->irq_mask != ~0);
2973 dev_priv->irq_mask = ~enable_mask;
2975 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
2980 static void ironlake_irq_reset(struct drm_device *dev)
2982 struct drm_i915_private *dev_priv = to_i915(dev);
2984 I915_WRITE(HWSTAM, 0xffffffff);
2987 if (IS_GEN7(dev_priv))
2988 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2990 gen5_gt_irq_reset(dev_priv);
2992 ibx_irq_reset(dev_priv);
2995 static void valleyview_irq_preinstall(struct drm_device *dev)
2997 struct drm_i915_private *dev_priv = to_i915(dev);
2999 I915_WRITE(VLV_MASTER_IER, 0);
3000 POSTING_READ(VLV_MASTER_IER);
3002 gen5_gt_irq_reset(dev_priv);
3004 spin_lock_irq(&dev_priv->irq_lock);
3005 if (dev_priv->display_irqs_enabled)
3006 vlv_display_irq_reset(dev_priv);
3007 spin_unlock_irq(&dev_priv->irq_lock);
3010 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3012 GEN8_IRQ_RESET_NDX(GT, 0);
3013 GEN8_IRQ_RESET_NDX(GT, 1);
3014 GEN8_IRQ_RESET_NDX(GT, 2);
3015 GEN8_IRQ_RESET_NDX(GT, 3);
3018 static void gen8_irq_reset(struct drm_device *dev)
3020 struct drm_i915_private *dev_priv = to_i915(dev);
3023 I915_WRITE(GEN8_MASTER_IRQ, 0);
3024 POSTING_READ(GEN8_MASTER_IRQ);
3026 gen8_gt_irq_reset(dev_priv);
3028 for_each_pipe(dev_priv, pipe)
3029 if (intel_display_power_is_enabled(dev_priv,
3030 POWER_DOMAIN_PIPE(pipe)))
3031 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3033 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3034 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3035 GEN5_IRQ_RESET(GEN8_PCU_);
3037 if (HAS_PCH_SPLIT(dev_priv))
3038 ibx_irq_reset(dev_priv);
3041 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3042 unsigned int pipe_mask)
3044 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3047 spin_lock_irq(&dev_priv->irq_lock);
3048 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3049 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3050 dev_priv->de_irq_mask[pipe],
3051 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3052 spin_unlock_irq(&dev_priv->irq_lock);
3055 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3056 unsigned int pipe_mask)
3060 spin_lock_irq(&dev_priv->irq_lock);
3061 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3062 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3063 spin_unlock_irq(&dev_priv->irq_lock);
3065 /* make sure we're done processing display irqs */
3066 synchronize_irq(dev_priv->drm.irq);
3069 static void cherryview_irq_preinstall(struct drm_device *dev)
3071 struct drm_i915_private *dev_priv = to_i915(dev);
3073 I915_WRITE(GEN8_MASTER_IRQ, 0);
3074 POSTING_READ(GEN8_MASTER_IRQ);
3076 gen8_gt_irq_reset(dev_priv);
3078 GEN5_IRQ_RESET(GEN8_PCU_);
3080 spin_lock_irq(&dev_priv->irq_lock);
3081 if (dev_priv->display_irqs_enabled)
3082 vlv_display_irq_reset(dev_priv);
3083 spin_unlock_irq(&dev_priv->irq_lock);
3086 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3087 const u32 hpd[HPD_NUM_PINS])
3089 struct intel_encoder *encoder;
3090 u32 enabled_irqs = 0;
3092 for_each_intel_encoder(&dev_priv->drm, encoder)
3093 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3094 enabled_irqs |= hpd[encoder->hpd_pin];
3096 return enabled_irqs;
3099 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3104 * Enable digital hotplug on the PCH, and configure the DP short pulse
3105 * duration to 2ms (which is the minimum in the Display Port spec).
3106 * The pulse duration bits are reserved on LPT+.
3108 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3109 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3110 PORTC_PULSE_DURATION_MASK |
3111 PORTD_PULSE_DURATION_MASK);
3112 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3113 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3114 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3116 * When CPU and PCH are on the same package, port A
3117 * HPD must be enabled in both north and south.
3119 if (HAS_PCH_LPT_LP(dev_priv))
3120 hotplug |= PORTA_HOTPLUG_ENABLE;
3121 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3124 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3126 u32 hotplug_irqs, enabled_irqs;
3128 if (HAS_PCH_IBX(dev_priv)) {
3129 hotplug_irqs = SDE_HOTPLUG_MASK;
3130 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3132 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3133 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3136 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3138 ibx_hpd_detection_setup(dev_priv);
3141 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3145 /* Enable digital hotplug on the PCH */
3146 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3147 hotplug |= PORTA_HOTPLUG_ENABLE |
3148 PORTB_HOTPLUG_ENABLE |
3149 PORTC_HOTPLUG_ENABLE |
3150 PORTD_HOTPLUG_ENABLE;
3151 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3153 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3154 hotplug |= PORTE_HOTPLUG_ENABLE;
3155 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3158 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3160 u32 hotplug_irqs, enabled_irqs;
3162 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3163 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3165 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3167 spt_hpd_detection_setup(dev_priv);
3170 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3175 * Enable digital hotplug on the CPU, and configure the DP short pulse
3176 * duration to 2ms (which is the minimum in the Display Port spec)
3177 * The pulse duration bits are reserved on HSW+.
3179 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3180 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3181 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3182 DIGITAL_PORTA_PULSE_DURATION_2ms;
3183 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3186 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3188 u32 hotplug_irqs, enabled_irqs;
3190 if (INTEL_GEN(dev_priv) >= 8) {
3191 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3192 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3194 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3195 } else if (INTEL_GEN(dev_priv) >= 7) {
3196 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3197 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3199 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3201 hotplug_irqs = DE_DP_A_HOTPLUG;
3202 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3204 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3207 ilk_hpd_detection_setup(dev_priv);
3209 ibx_hpd_irq_setup(dev_priv);
3212 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3217 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3218 hotplug |= PORTA_HOTPLUG_ENABLE |
3219 PORTB_HOTPLUG_ENABLE |
3220 PORTC_HOTPLUG_ENABLE;
3222 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3223 hotplug, enabled_irqs);
3224 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3227 * For BXT invert bit has to be set based on AOB design
3228 * for HPD detection logic, update it based on VBT fields.
3230 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3231 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3232 hotplug |= BXT_DDIA_HPD_INVERT;
3233 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3234 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3235 hotplug |= BXT_DDIB_HPD_INVERT;
3236 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3237 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3238 hotplug |= BXT_DDIC_HPD_INVERT;
3240 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3243 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3245 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3248 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3250 u32 hotplug_irqs, enabled_irqs;
3252 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3253 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3255 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3257 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3260 static void ibx_irq_postinstall(struct drm_device *dev)
3262 struct drm_i915_private *dev_priv = to_i915(dev);
3265 if (HAS_PCH_NOP(dev_priv))
3268 if (HAS_PCH_IBX(dev_priv))
3269 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3271 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3273 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3274 I915_WRITE(SDEIMR, ~mask);
3276 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3277 HAS_PCH_LPT(dev_priv))
3278 ibx_hpd_detection_setup(dev_priv);
3280 spt_hpd_detection_setup(dev_priv);
3283 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3285 struct drm_i915_private *dev_priv = to_i915(dev);
3286 u32 pm_irqs, gt_irqs;
3288 pm_irqs = gt_irqs = 0;
3290 dev_priv->gt_irq_mask = ~0;
3291 if (HAS_L3_DPF(dev_priv)) {
3292 /* L3 parity interrupt is always unmasked. */
3293 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3294 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3297 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3298 if (IS_GEN5(dev_priv)) {
3299 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3301 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3304 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3306 if (INTEL_GEN(dev_priv) >= 6) {
3308 * RPS interrupts will get enabled/disabled on demand when RPS
3309 * itself is enabled/disabled.
3311 if (HAS_VEBOX(dev_priv)) {
3312 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3313 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3316 dev_priv->pm_imr = 0xffffffff;
3317 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3321 static int ironlake_irq_postinstall(struct drm_device *dev)
3323 struct drm_i915_private *dev_priv = to_i915(dev);
3324 u32 display_mask, extra_mask;
3326 if (INTEL_GEN(dev_priv) >= 7) {
3327 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3328 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3329 DE_PLANEB_FLIP_DONE_IVB |
3330 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3331 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3332 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3333 DE_DP_A_HOTPLUG_IVB);
3335 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3336 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3338 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3340 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3341 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3345 dev_priv->irq_mask = ~display_mask;
3347 I915_WRITE(HWSTAM, 0xeffe);
3349 ibx_irq_pre_postinstall(dev);
3351 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3353 gen5_gt_irq_postinstall(dev);
3355 ilk_hpd_detection_setup(dev_priv);
3357 ibx_irq_postinstall(dev);
3359 if (IS_IRONLAKE_M(dev_priv)) {
3360 /* Enable PCU event interrupts
3362 * spinlocking not required here for correctness since interrupt
3363 * setup is guaranteed to run in single-threaded context. But we
3364 * need it to make the assert_spin_locked happy. */
3365 spin_lock_irq(&dev_priv->irq_lock);
3366 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3367 spin_unlock_irq(&dev_priv->irq_lock);
3373 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3375 assert_spin_locked(&dev_priv->irq_lock);
3377 if (dev_priv->display_irqs_enabled)
3380 dev_priv->display_irqs_enabled = true;
3382 if (intel_irqs_enabled(dev_priv)) {
3383 vlv_display_irq_reset(dev_priv);
3384 vlv_display_irq_postinstall(dev_priv);
3388 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3390 assert_spin_locked(&dev_priv->irq_lock);
3392 if (!dev_priv->display_irqs_enabled)
3395 dev_priv->display_irqs_enabled = false;
3397 if (intel_irqs_enabled(dev_priv))
3398 vlv_display_irq_reset(dev_priv);
3402 static int valleyview_irq_postinstall(struct drm_device *dev)
3404 struct drm_i915_private *dev_priv = to_i915(dev);
3406 gen5_gt_irq_postinstall(dev);
3408 spin_lock_irq(&dev_priv->irq_lock);
3409 if (dev_priv->display_irqs_enabled)
3410 vlv_display_irq_postinstall(dev_priv);
3411 spin_unlock_irq(&dev_priv->irq_lock);
3413 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3414 POSTING_READ(VLV_MASTER_IER);
3419 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3421 /* These are interrupts we'll toggle with the ring mask register */
3422 uint32_t gt_interrupts[] = {
3423 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3424 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3425 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3426 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3427 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3428 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3429 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3430 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3432 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3433 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3436 if (HAS_L3_DPF(dev_priv))
3437 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3439 dev_priv->pm_ier = 0x0;
3440 dev_priv->pm_imr = ~dev_priv->pm_ier;
3441 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3442 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3444 * RPS interrupts will get enabled/disabled on demand when RPS itself
3445 * is enabled/disabled. Same wil be the case for GuC interrupts.
3447 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3448 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3451 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3453 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3454 uint32_t de_pipe_enables;
3455 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3456 u32 de_port_enables;
3457 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3460 if (INTEL_INFO(dev_priv)->gen >= 9) {
3461 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3462 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3463 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3465 if (IS_GEN9_LP(dev_priv))
3466 de_port_masked |= BXT_DE_PORT_GMBUS;
3468 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3469 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3472 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3473 GEN8_PIPE_FIFO_UNDERRUN;
3475 de_port_enables = de_port_masked;
3476 if (IS_GEN9_LP(dev_priv))
3477 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3478 else if (IS_BROADWELL(dev_priv))
3479 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3481 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3482 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3483 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3485 for_each_pipe(dev_priv, pipe)
3486 if (intel_display_power_is_enabled(dev_priv,
3487 POWER_DOMAIN_PIPE(pipe)))
3488 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3489 dev_priv->de_irq_mask[pipe],
3492 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3493 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3495 if (IS_GEN9_LP(dev_priv))
3496 bxt_hpd_detection_setup(dev_priv);
3497 else if (IS_BROADWELL(dev_priv))
3498 ilk_hpd_detection_setup(dev_priv);
3501 static int gen8_irq_postinstall(struct drm_device *dev)
3503 struct drm_i915_private *dev_priv = to_i915(dev);
3505 if (HAS_PCH_SPLIT(dev_priv))
3506 ibx_irq_pre_postinstall(dev);
3508 gen8_gt_irq_postinstall(dev_priv);
3509 gen8_de_irq_postinstall(dev_priv);
3511 if (HAS_PCH_SPLIT(dev_priv))
3512 ibx_irq_postinstall(dev);
3514 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3515 POSTING_READ(GEN8_MASTER_IRQ);
3520 static int cherryview_irq_postinstall(struct drm_device *dev)
3522 struct drm_i915_private *dev_priv = to_i915(dev);
3524 gen8_gt_irq_postinstall(dev_priv);
3526 spin_lock_irq(&dev_priv->irq_lock);
3527 if (dev_priv->display_irqs_enabled)
3528 vlv_display_irq_postinstall(dev_priv);
3529 spin_unlock_irq(&dev_priv->irq_lock);
3531 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3532 POSTING_READ(GEN8_MASTER_IRQ);
3537 static void gen8_irq_uninstall(struct drm_device *dev)
3539 struct drm_i915_private *dev_priv = to_i915(dev);
3544 gen8_irq_reset(dev);
3547 static void valleyview_irq_uninstall(struct drm_device *dev)
3549 struct drm_i915_private *dev_priv = to_i915(dev);
3554 I915_WRITE(VLV_MASTER_IER, 0);
3555 POSTING_READ(VLV_MASTER_IER);
3557 gen5_gt_irq_reset(dev_priv);
3559 I915_WRITE(HWSTAM, 0xffffffff);
3561 spin_lock_irq(&dev_priv->irq_lock);
3562 if (dev_priv->display_irqs_enabled)
3563 vlv_display_irq_reset(dev_priv);
3564 spin_unlock_irq(&dev_priv->irq_lock);
3567 static void cherryview_irq_uninstall(struct drm_device *dev)
3569 struct drm_i915_private *dev_priv = to_i915(dev);
3574 I915_WRITE(GEN8_MASTER_IRQ, 0);
3575 POSTING_READ(GEN8_MASTER_IRQ);
3577 gen8_gt_irq_reset(dev_priv);
3579 GEN5_IRQ_RESET(GEN8_PCU_);
3581 spin_lock_irq(&dev_priv->irq_lock);
3582 if (dev_priv->display_irqs_enabled)
3583 vlv_display_irq_reset(dev_priv);
3584 spin_unlock_irq(&dev_priv->irq_lock);
3587 static void ironlake_irq_uninstall(struct drm_device *dev)
3589 struct drm_i915_private *dev_priv = to_i915(dev);
3594 ironlake_irq_reset(dev);
3597 static void i8xx_irq_preinstall(struct drm_device * dev)
3599 struct drm_i915_private *dev_priv = to_i915(dev);
3602 for_each_pipe(dev_priv, pipe)
3603 I915_WRITE(PIPESTAT(pipe), 0);
3604 I915_WRITE16(IMR, 0xffff);
3605 I915_WRITE16(IER, 0x0);
3606 POSTING_READ16(IER);
3609 static int i8xx_irq_postinstall(struct drm_device *dev)
3611 struct drm_i915_private *dev_priv = to_i915(dev);
3614 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3616 /* Unmask the interrupts that we always want on. */
3617 dev_priv->irq_mask =
3618 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3619 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3620 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3621 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3622 I915_WRITE16(IMR, dev_priv->irq_mask);
3625 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3626 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3627 I915_USER_INTERRUPT);
3628 POSTING_READ16(IER);
3630 /* Interrupt setup is already guaranteed to be single-threaded, this is
3631 * just to make the assert_spin_locked check happy. */
3632 spin_lock_irq(&dev_priv->irq_lock);
3633 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3634 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3635 spin_unlock_irq(&dev_priv->irq_lock);
3641 * Returns true when a page flip has completed.
3643 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3644 int plane, int pipe, u32 iir)
3646 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3648 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3651 if ((iir & flip_pending) == 0)
3652 goto check_page_flip;
3654 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3655 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3656 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3657 * the flip is completed (no longer pending). Since this doesn't raise
3658 * an interrupt per se, we watch for the change at vblank.
3660 if (I915_READ16(ISR) & flip_pending)
3661 goto check_page_flip;
3663 intel_finish_page_flip_cs(dev_priv, pipe);
3667 intel_check_page_flip(dev_priv, pipe);
3671 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3673 struct drm_device *dev = arg;
3674 struct drm_i915_private *dev_priv = to_i915(dev);
3679 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3680 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3683 if (!intel_irqs_enabled(dev_priv))
3686 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3687 disable_rpm_wakeref_asserts(dev_priv);
3690 iir = I915_READ16(IIR);
3694 while (iir & ~flip_mask) {
3695 /* Can't rely on pipestat interrupt bit in iir as it might
3696 * have been cleared after the pipestat interrupt was received.
3697 * It doesn't set the bit in iir again, but it still produces
3698 * interrupts (for non-MSI).
3700 spin_lock(&dev_priv->irq_lock);
3701 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3702 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3704 for_each_pipe(dev_priv, pipe) {
3705 i915_reg_t reg = PIPESTAT(pipe);
3706 pipe_stats[pipe] = I915_READ(reg);
3709 * Clear the PIPE*STAT regs before the IIR
3711 if (pipe_stats[pipe] & 0x8000ffff)
3712 I915_WRITE(reg, pipe_stats[pipe]);
3714 spin_unlock(&dev_priv->irq_lock);
3716 I915_WRITE16(IIR, iir & ~flip_mask);
3717 new_iir = I915_READ16(IIR); /* Flush posted writes */
3719 if (iir & I915_USER_INTERRUPT)
3720 notify_ring(dev_priv->engine[RCS]);
3722 for_each_pipe(dev_priv, pipe) {
3724 if (HAS_FBC(dev_priv))
3727 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3728 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3729 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3731 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3732 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3734 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3735 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3744 enable_rpm_wakeref_asserts(dev_priv);
3749 static void i8xx_irq_uninstall(struct drm_device * dev)
3751 struct drm_i915_private *dev_priv = to_i915(dev);
3754 for_each_pipe(dev_priv, pipe) {
3755 /* Clear enable bits; then clear status bits */
3756 I915_WRITE(PIPESTAT(pipe), 0);
3757 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3759 I915_WRITE16(IMR, 0xffff);
3760 I915_WRITE16(IER, 0x0);
3761 I915_WRITE16(IIR, I915_READ16(IIR));
3764 static void i915_irq_preinstall(struct drm_device * dev)
3766 struct drm_i915_private *dev_priv = to_i915(dev);
3769 if (I915_HAS_HOTPLUG(dev_priv)) {
3770 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3771 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3774 I915_WRITE16(HWSTAM, 0xeffe);
3775 for_each_pipe(dev_priv, pipe)
3776 I915_WRITE(PIPESTAT(pipe), 0);
3777 I915_WRITE(IMR, 0xffffffff);
3778 I915_WRITE(IER, 0x0);
3782 static int i915_irq_postinstall(struct drm_device *dev)
3784 struct drm_i915_private *dev_priv = to_i915(dev);
3787 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3789 /* Unmask the interrupts that we always want on. */
3790 dev_priv->irq_mask =
3791 ~(I915_ASLE_INTERRUPT |
3792 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3793 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3794 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3795 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3798 I915_ASLE_INTERRUPT |
3799 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3800 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3801 I915_USER_INTERRUPT;
3803 if (I915_HAS_HOTPLUG(dev_priv)) {
3804 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3805 POSTING_READ(PORT_HOTPLUG_EN);
3807 /* Enable in IER... */
3808 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3809 /* and unmask in IMR */
3810 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3813 I915_WRITE(IMR, dev_priv->irq_mask);
3814 I915_WRITE(IER, enable_mask);
3817 i915_enable_asle_pipestat(dev_priv);
3819 /* Interrupt setup is already guaranteed to be single-threaded, this is
3820 * just to make the assert_spin_locked check happy. */
3821 spin_lock_irq(&dev_priv->irq_lock);
3822 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3823 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3824 spin_unlock_irq(&dev_priv->irq_lock);
3830 * Returns true when a page flip has completed.
3832 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3833 int plane, int pipe, u32 iir)
3835 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3837 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3840 if ((iir & flip_pending) == 0)
3841 goto check_page_flip;
3843 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3844 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3845 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3846 * the flip is completed (no longer pending). Since this doesn't raise
3847 * an interrupt per se, we watch for the change at vblank.
3849 if (I915_READ(ISR) & flip_pending)
3850 goto check_page_flip;
3852 intel_finish_page_flip_cs(dev_priv, pipe);
3856 intel_check_page_flip(dev_priv, pipe);
3860 static irqreturn_t i915_irq_handler(int irq, void *arg)
3862 struct drm_device *dev = arg;
3863 struct drm_i915_private *dev_priv = to_i915(dev);
3864 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3866 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3867 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3868 int pipe, ret = IRQ_NONE;
3870 if (!intel_irqs_enabled(dev_priv))
3873 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3874 disable_rpm_wakeref_asserts(dev_priv);
3876 iir = I915_READ(IIR);
3878 bool irq_received = (iir & ~flip_mask) != 0;
3879 bool blc_event = false;
3881 /* Can't rely on pipestat interrupt bit in iir as it might
3882 * have been cleared after the pipestat interrupt was received.
3883 * It doesn't set the bit in iir again, but it still produces
3884 * interrupts (for non-MSI).
3886 spin_lock(&dev_priv->irq_lock);
3887 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3888 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3890 for_each_pipe(dev_priv, pipe) {
3891 i915_reg_t reg = PIPESTAT(pipe);
3892 pipe_stats[pipe] = I915_READ(reg);
3894 /* Clear the PIPE*STAT regs before the IIR */
3895 if (pipe_stats[pipe] & 0x8000ffff) {
3896 I915_WRITE(reg, pipe_stats[pipe]);
3897 irq_received = true;
3900 spin_unlock(&dev_priv->irq_lock);
3905 /* Consume port. Then clear IIR or we'll miss events */
3906 if (I915_HAS_HOTPLUG(dev_priv) &&
3907 iir & I915_DISPLAY_PORT_INTERRUPT) {
3908 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3910 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3913 I915_WRITE(IIR, iir & ~flip_mask);
3914 new_iir = I915_READ(IIR); /* Flush posted writes */
3916 if (iir & I915_USER_INTERRUPT)
3917 notify_ring(dev_priv->engine[RCS]);
3919 for_each_pipe(dev_priv, pipe) {
3921 if (HAS_FBC(dev_priv))
3924 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3925 i915_handle_vblank(dev_priv, plane, pipe, iir))
3926 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3928 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3931 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3932 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3934 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3935 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3939 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3940 intel_opregion_asle_intr(dev_priv);
3942 /* With MSI, interrupts are only generated when iir
3943 * transitions from zero to nonzero. If another bit got
3944 * set while we were handling the existing iir bits, then
3945 * we would never get another interrupt.
3947 * This is fine on non-MSI as well, as if we hit this path
3948 * we avoid exiting the interrupt handler only to generate
3951 * Note that for MSI this could cause a stray interrupt report
3952 * if an interrupt landed in the time between writing IIR and
3953 * the posting read. This should be rare enough to never
3954 * trigger the 99% of 100,000 interrupts test for disabling
3959 } while (iir & ~flip_mask);
3961 enable_rpm_wakeref_asserts(dev_priv);
3966 static void i915_irq_uninstall(struct drm_device * dev)
3968 struct drm_i915_private *dev_priv = to_i915(dev);
3971 if (I915_HAS_HOTPLUG(dev_priv)) {
3972 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3973 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3976 I915_WRITE16(HWSTAM, 0xffff);
3977 for_each_pipe(dev_priv, pipe) {
3978 /* Clear enable bits; then clear status bits */
3979 I915_WRITE(PIPESTAT(pipe), 0);
3980 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3982 I915_WRITE(IMR, 0xffffffff);
3983 I915_WRITE(IER, 0x0);
3985 I915_WRITE(IIR, I915_READ(IIR));
3988 static void i965_irq_preinstall(struct drm_device * dev)
3990 struct drm_i915_private *dev_priv = to_i915(dev);
3993 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3994 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3996 I915_WRITE(HWSTAM, 0xeffe);
3997 for_each_pipe(dev_priv, pipe)
3998 I915_WRITE(PIPESTAT(pipe), 0);
3999 I915_WRITE(IMR, 0xffffffff);
4000 I915_WRITE(IER, 0x0);
4004 static int i965_irq_postinstall(struct drm_device *dev)
4006 struct drm_i915_private *dev_priv = to_i915(dev);
4010 /* Unmask the interrupts that we always want on. */
4011 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4012 I915_DISPLAY_PORT_INTERRUPT |
4013 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4014 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4015 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4016 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4017 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4019 enable_mask = ~dev_priv->irq_mask;
4020 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4021 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4022 enable_mask |= I915_USER_INTERRUPT;
4024 if (IS_G4X(dev_priv))
4025 enable_mask |= I915_BSD_USER_INTERRUPT;
4027 /* Interrupt setup is already guaranteed to be single-threaded, this is
4028 * just to make the assert_spin_locked check happy. */
4029 spin_lock_irq(&dev_priv->irq_lock);
4030 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4031 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4032 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4033 spin_unlock_irq(&dev_priv->irq_lock);
4036 * Enable some error detection, note the instruction error mask
4037 * bit is reserved, so we leave it masked.
4039 if (IS_G4X(dev_priv)) {
4040 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4041 GM45_ERROR_MEM_PRIV |
4042 GM45_ERROR_CP_PRIV |
4043 I915_ERROR_MEMORY_REFRESH);
4045 error_mask = ~(I915_ERROR_PAGE_TABLE |
4046 I915_ERROR_MEMORY_REFRESH);
4048 I915_WRITE(EMR, error_mask);
4050 I915_WRITE(IMR, dev_priv->irq_mask);
4051 I915_WRITE(IER, enable_mask);
4054 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4055 POSTING_READ(PORT_HOTPLUG_EN);
4057 i915_enable_asle_pipestat(dev_priv);
4062 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4066 assert_spin_locked(&dev_priv->irq_lock);
4068 /* Note HDMI and DP share hotplug bits */
4069 /* enable bits are the same for all generations */
4070 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4071 /* Programming the CRT detection parameters tends
4072 to generate a spurious hotplug event about three
4073 seconds later. So just do it once.
4075 if (IS_G4X(dev_priv))
4076 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4077 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4079 /* Ignore TV since it's buggy */
4080 i915_hotplug_interrupt_update_locked(dev_priv,
4081 HOTPLUG_INT_EN_MASK |
4082 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4083 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4087 static irqreturn_t i965_irq_handler(int irq, void *arg)
4089 struct drm_device *dev = arg;
4090 struct drm_i915_private *dev_priv = to_i915(dev);
4092 u32 pipe_stats[I915_MAX_PIPES];
4093 int ret = IRQ_NONE, pipe;
4095 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4096 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4098 if (!intel_irqs_enabled(dev_priv))
4101 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4102 disable_rpm_wakeref_asserts(dev_priv);
4104 iir = I915_READ(IIR);
4107 bool irq_received = (iir & ~flip_mask) != 0;
4108 bool blc_event = false;
4110 /* Can't rely on pipestat interrupt bit in iir as it might
4111 * have been cleared after the pipestat interrupt was received.
4112 * It doesn't set the bit in iir again, but it still produces
4113 * interrupts (for non-MSI).
4115 spin_lock(&dev_priv->irq_lock);
4116 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4117 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4119 for_each_pipe(dev_priv, pipe) {
4120 i915_reg_t reg = PIPESTAT(pipe);
4121 pipe_stats[pipe] = I915_READ(reg);
4124 * Clear the PIPE*STAT regs before the IIR
4126 if (pipe_stats[pipe] & 0x8000ffff) {
4127 I915_WRITE(reg, pipe_stats[pipe]);
4128 irq_received = true;
4131 spin_unlock(&dev_priv->irq_lock);
4138 /* Consume port. Then clear IIR or we'll miss events */
4139 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4140 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4142 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4145 I915_WRITE(IIR, iir & ~flip_mask);
4146 new_iir = I915_READ(IIR); /* Flush posted writes */
4148 if (iir & I915_USER_INTERRUPT)
4149 notify_ring(dev_priv->engine[RCS]);
4150 if (iir & I915_BSD_USER_INTERRUPT)
4151 notify_ring(dev_priv->engine[VCS]);
4153 for_each_pipe(dev_priv, pipe) {
4154 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4155 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4156 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4158 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4161 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4162 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4164 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4165 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4168 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4169 intel_opregion_asle_intr(dev_priv);
4171 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4172 gmbus_irq_handler(dev_priv);
4174 /* With MSI, interrupts are only generated when iir
4175 * transitions from zero to nonzero. If another bit got
4176 * set while we were handling the existing iir bits, then
4177 * we would never get another interrupt.
4179 * This is fine on non-MSI as well, as if we hit this path
4180 * we avoid exiting the interrupt handler only to generate
4183 * Note that for MSI this could cause a stray interrupt report
4184 * if an interrupt landed in the time between writing IIR and
4185 * the posting read. This should be rare enough to never
4186 * trigger the 99% of 100,000 interrupts test for disabling
4192 enable_rpm_wakeref_asserts(dev_priv);
4197 static void i965_irq_uninstall(struct drm_device * dev)
4199 struct drm_i915_private *dev_priv = to_i915(dev);
4205 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4206 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4208 I915_WRITE(HWSTAM, 0xffffffff);
4209 for_each_pipe(dev_priv, pipe)
4210 I915_WRITE(PIPESTAT(pipe), 0);
4211 I915_WRITE(IMR, 0xffffffff);
4212 I915_WRITE(IER, 0x0);
4214 for_each_pipe(dev_priv, pipe)
4215 I915_WRITE(PIPESTAT(pipe),
4216 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4217 I915_WRITE(IIR, I915_READ(IIR));
4221 * intel_irq_init - initializes irq support
4222 * @dev_priv: i915 device instance
4224 * This function initializes all the irq support including work items, timers
4225 * and all the vtables. It does not setup the interrupt itself though.
4227 void intel_irq_init(struct drm_i915_private *dev_priv)
4229 struct drm_device *dev = &dev_priv->drm;
4231 intel_hpd_init_work(dev_priv);
4233 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4234 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4236 if (HAS_GUC_SCHED(dev_priv))
4237 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4239 /* Let's track the enabled rps events */
4240 if (IS_VALLEYVIEW(dev_priv))
4241 /* WaGsvRC0ResidencyMethod:vlv */
4242 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4244 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4246 dev_priv->rps.pm_intr_keep = 0;
4249 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4250 * if GEN6_PM_UP_EI_EXPIRED is masked.
4252 * TODO: verify if this can be reproduced on VLV,CHV.
4254 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4255 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4257 if (INTEL_INFO(dev_priv)->gen >= 8)
4258 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4260 if (IS_GEN2(dev_priv)) {
4261 /* Gen2 doesn't have a hardware frame counter */
4262 dev->max_vblank_count = 0;
4263 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4264 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4265 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4266 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4268 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4269 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4273 * Opt out of the vblank disable timer on everything except gen2.
4274 * Gen2 doesn't have a hardware frame counter and so depends on
4275 * vblank interrupts to produce sane vblank seuquence numbers.
4277 if (!IS_GEN2(dev_priv))
4278 dev->vblank_disable_immediate = true;
4280 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4282 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4283 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4285 if (IS_CHERRYVIEW(dev_priv)) {
4286 dev->driver->irq_handler = cherryview_irq_handler;
4287 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4288 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4289 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4290 dev->driver->enable_vblank = i965_enable_vblank;
4291 dev->driver->disable_vblank = i965_disable_vblank;
4292 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4293 } else if (IS_VALLEYVIEW(dev_priv)) {
4294 dev->driver->irq_handler = valleyview_irq_handler;
4295 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4296 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4297 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4298 dev->driver->enable_vblank = i965_enable_vblank;
4299 dev->driver->disable_vblank = i965_disable_vblank;
4300 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4301 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4302 dev->driver->irq_handler = gen8_irq_handler;
4303 dev->driver->irq_preinstall = gen8_irq_reset;
4304 dev->driver->irq_postinstall = gen8_irq_postinstall;
4305 dev->driver->irq_uninstall = gen8_irq_uninstall;
4306 dev->driver->enable_vblank = gen8_enable_vblank;
4307 dev->driver->disable_vblank = gen8_disable_vblank;
4308 if (IS_GEN9_LP(dev_priv))
4309 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4310 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4311 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4313 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4314 } else if (HAS_PCH_SPLIT(dev_priv)) {
4315 dev->driver->irq_handler = ironlake_irq_handler;
4316 dev->driver->irq_preinstall = ironlake_irq_reset;
4317 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4318 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4319 dev->driver->enable_vblank = ironlake_enable_vblank;
4320 dev->driver->disable_vblank = ironlake_disable_vblank;
4321 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4323 if (IS_GEN2(dev_priv)) {
4324 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4325 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4326 dev->driver->irq_handler = i8xx_irq_handler;
4327 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4328 dev->driver->enable_vblank = i8xx_enable_vblank;
4329 dev->driver->disable_vblank = i8xx_disable_vblank;
4330 } else if (IS_GEN3(dev_priv)) {
4331 dev->driver->irq_preinstall = i915_irq_preinstall;
4332 dev->driver->irq_postinstall = i915_irq_postinstall;
4333 dev->driver->irq_uninstall = i915_irq_uninstall;
4334 dev->driver->irq_handler = i915_irq_handler;
4335 dev->driver->enable_vblank = i8xx_enable_vblank;
4336 dev->driver->disable_vblank = i8xx_disable_vblank;
4338 dev->driver->irq_preinstall = i965_irq_preinstall;
4339 dev->driver->irq_postinstall = i965_irq_postinstall;
4340 dev->driver->irq_uninstall = i965_irq_uninstall;
4341 dev->driver->irq_handler = i965_irq_handler;
4342 dev->driver->enable_vblank = i965_enable_vblank;
4343 dev->driver->disable_vblank = i965_disable_vblank;
4345 if (I915_HAS_HOTPLUG(dev_priv))
4346 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4351 * intel_irq_install - enables the hardware interrupt
4352 * @dev_priv: i915 device instance
4354 * This function enables the hardware interrupt handling, but leaves the hotplug
4355 * handling still disabled. It is called after intel_irq_init().
4357 * In the driver load and resume code we need working interrupts in a few places
4358 * but don't want to deal with the hassle of concurrent probe and hotplug
4359 * workers. Hence the split into this two-stage approach.
4361 int intel_irq_install(struct drm_i915_private *dev_priv)
4364 * We enable some interrupt sources in our postinstall hooks, so mark
4365 * interrupts as enabled _before_ actually enabling them to avoid
4366 * special cases in our ordering checks.
4368 dev_priv->pm.irqs_enabled = true;
4370 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4374 * intel_irq_uninstall - finilizes all irq handling
4375 * @dev_priv: i915 device instance
4377 * This stops interrupt and hotplug handling and unregisters and frees all
4378 * resources acquired in the init functions.
4380 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4382 drm_irq_uninstall(&dev_priv->drm);
4383 intel_hpd_cancel_work(dev_priv);
4384 dev_priv->pm.irqs_enabled = false;
4388 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4389 * @dev_priv: i915 device instance
4391 * This function is used to disable interrupts at runtime, both in the runtime
4392 * pm and the system suspend/resume code.
4394 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4396 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4397 dev_priv->pm.irqs_enabled = false;
4398 synchronize_irq(dev_priv->drm.irq);
4402 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4403 * @dev_priv: i915 device instance
4405 * This function is used to enable interrupts at runtime, both in the runtime
4406 * pm and the system suspend/resume code.
4408 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4410 dev_priv->pm.irqs_enabled = true;
4411 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4412 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);