Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2  * Copyright (c) 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Keith Packard <keithp@keithp.com>
26  *    Mika Kuoppala <mika.kuoppala@intel.com>
27  *
28  */
29
30 #include <linux/ascii85.h>
31 #include <linux/nmi.h>
32 #include <linux/scatterlist.h>
33 #include <linux/stop_machine.h>
34 #include <linux/utsname.h>
35 #include <linux/zlib.h>
36
37 #include <drm/drm_print.h>
38
39 #include "i915_gpu_error.h"
40 #include "i915_drv.h"
41
42 static inline const struct intel_engine_cs *
43 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
44 {
45         if (id >= I915_NUM_ENGINES)
46                 return NULL;
47
48         return i915->engine[id];
49 }
50
51 static inline const char *
52 __engine_name(const struct intel_engine_cs *engine)
53 {
54         return engine ? engine->name : "";
55 }
56
57 static const char *
58 engine_name(const struct drm_i915_private *i915, unsigned int id)
59 {
60         return __engine_name(engine_lookup(i915, id));
61 }
62
63 static const char *tiling_flag(int tiling)
64 {
65         switch (tiling) {
66         default:
67         case I915_TILING_NONE: return "";
68         case I915_TILING_X: return " X";
69         case I915_TILING_Y: return " Y";
70         }
71 }
72
73 static const char *dirty_flag(int dirty)
74 {
75         return dirty ? " dirty" : "";
76 }
77
78 static const char *purgeable_flag(int purgeable)
79 {
80         return purgeable ? " purgeable" : "";
81 }
82
83 static void __sg_set_buf(struct scatterlist *sg,
84                          void *addr, unsigned int len, loff_t it)
85 {
86         sg->page_link = (unsigned long)virt_to_page(addr);
87         sg->offset = offset_in_page(addr);
88         sg->length = len;
89         sg->dma_address = it;
90 }
91
92 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
93 {
94         if (!len)
95                 return false;
96
97         if (e->bytes + len + 1 <= e->size)
98                 return true;
99
100         if (e->bytes) {
101                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
102                 e->iter += e->bytes;
103                 e->buf = NULL;
104                 e->bytes = 0;
105         }
106
107         if (e->cur == e->end) {
108                 struct scatterlist *sgl;
109
110                 sgl = (typeof(sgl))__get_free_page(GFP_KERNEL);
111                 if (!sgl) {
112                         e->err = -ENOMEM;
113                         return false;
114                 }
115
116                 if (e->cur) {
117                         e->cur->offset = 0;
118                         e->cur->length = 0;
119                         e->cur->page_link =
120                                 (unsigned long)sgl | SG_CHAIN;
121                 } else {
122                         e->sgl = sgl;
123                 }
124
125                 e->cur = sgl;
126                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
127         }
128
129         e->size = ALIGN(len + 1, SZ_64K);
130         e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
131         if (!e->buf) {
132                 e->size = PAGE_ALIGN(len + 1);
133                 e->buf = kmalloc(e->size, GFP_KERNEL);
134         }
135         if (!e->buf) {
136                 e->err = -ENOMEM;
137                 return false;
138         }
139
140         return true;
141 }
142
143 __printf(2, 0)
144 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
145                                const char *fmt, va_list args)
146 {
147         va_list ap;
148         int len;
149
150         if (e->err)
151                 return;
152
153         va_copy(ap, args);
154         len = vsnprintf(NULL, 0, fmt, ap);
155         va_end(ap);
156         if (len <= 0) {
157                 e->err = len;
158                 return;
159         }
160
161         if (!__i915_error_grow(e, len))
162                 return;
163
164         GEM_BUG_ON(e->bytes >= e->size);
165         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
166         if (len < 0) {
167                 e->err = len;
168                 return;
169         }
170         e->bytes += len;
171 }
172
173 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
174 {
175         unsigned len;
176
177         if (e->err || !str)
178                 return;
179
180         len = strlen(str);
181         if (!__i915_error_grow(e, len))
182                 return;
183
184         GEM_BUG_ON(e->bytes + len > e->size);
185         memcpy(e->buf + e->bytes, str, len);
186         e->bytes += len;
187 }
188
189 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
190 #define err_puts(e, s) i915_error_puts(e, s)
191
192 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
193 {
194         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
195 }
196
197 static inline struct drm_printer
198 i915_error_printer(struct drm_i915_error_state_buf *e)
199 {
200         struct drm_printer p = {
201                 .printfn = __i915_printfn_error,
202                 .arg = e,
203         };
204         return p;
205 }
206
207 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
208
209 struct compress {
210         struct z_stream_s zstream;
211         void *tmp;
212 };
213
214 static bool compress_init(struct compress *c)
215 {
216         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
217
218         zstream->workspace =
219                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
220                         GFP_ATOMIC | __GFP_NOWARN);
221         if (!zstream->workspace)
222                 return false;
223
224         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
225                 kfree(zstream->workspace);
226                 return false;
227         }
228
229         c->tmp = NULL;
230         if (i915_has_memcpy_from_wc())
231                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
232
233         return true;
234 }
235
236 static void *compress_next_page(struct drm_i915_error_object *dst)
237 {
238         unsigned long page;
239
240         if (dst->page_count >= dst->num_pages)
241                 return ERR_PTR(-ENOSPC);
242
243         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
244         if (!page)
245                 return ERR_PTR(-ENOMEM);
246
247         return dst->pages[dst->page_count++] = (void *)page;
248 }
249
250 static int compress_page(struct compress *c,
251                          void *src,
252                          struct drm_i915_error_object *dst)
253 {
254         struct z_stream_s *zstream = &c->zstream;
255
256         zstream->next_in = src;
257         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
258                 zstream->next_in = c->tmp;
259         zstream->avail_in = PAGE_SIZE;
260
261         do {
262                 if (zstream->avail_out == 0) {
263                         zstream->next_out = compress_next_page(dst);
264                         if (IS_ERR(zstream->next_out))
265                                 return PTR_ERR(zstream->next_out);
266
267                         zstream->avail_out = PAGE_SIZE;
268                 }
269
270                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
271                         return -EIO;
272
273                 touch_nmi_watchdog();
274         } while (zstream->avail_in);
275
276         /* Fallback to uncompressed if we increase size? */
277         if (0 && zstream->total_out > zstream->total_in)
278                 return -E2BIG;
279
280         return 0;
281 }
282
283 static int compress_flush(struct compress *c,
284                           struct drm_i915_error_object *dst)
285 {
286         struct z_stream_s *zstream = &c->zstream;
287
288         do {
289                 switch (zlib_deflate(zstream, Z_FINISH)) {
290                 case Z_OK: /* more space requested */
291                         zstream->next_out = compress_next_page(dst);
292                         if (IS_ERR(zstream->next_out))
293                                 return PTR_ERR(zstream->next_out);
294
295                         zstream->avail_out = PAGE_SIZE;
296                         break;
297
298                 case Z_STREAM_END:
299                         goto end;
300
301                 default: /* any error */
302                         return -EIO;
303                 }
304         } while (1);
305
306 end:
307         memset(zstream->next_out, 0, zstream->avail_out);
308         dst->unused = zstream->avail_out;
309         return 0;
310 }
311
312 static void compress_fini(struct compress *c,
313                           struct drm_i915_error_object *dst)
314 {
315         struct z_stream_s *zstream = &c->zstream;
316
317         zlib_deflateEnd(zstream);
318         kfree(zstream->workspace);
319         if (c->tmp)
320                 free_page((unsigned long)c->tmp);
321 }
322
323 static void err_compression_marker(struct drm_i915_error_state_buf *m)
324 {
325         err_puts(m, ":");
326 }
327
328 #else
329
330 struct compress {
331 };
332
333 static bool compress_init(struct compress *c)
334 {
335         return true;
336 }
337
338 static int compress_page(struct compress *c,
339                          void *src,
340                          struct drm_i915_error_object *dst)
341 {
342         unsigned long page;
343         void *ptr;
344
345         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
346         if (!page)
347                 return -ENOMEM;
348
349         ptr = (void *)page;
350         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
351                 memcpy(ptr, src, PAGE_SIZE);
352         dst->pages[dst->page_count++] = ptr;
353
354         return 0;
355 }
356
357 static int compress_flush(struct compress *c,
358                           struct drm_i915_error_object *dst)
359 {
360         return 0;
361 }
362
363 static void compress_fini(struct compress *c,
364                           struct drm_i915_error_object *dst)
365 {
366 }
367
368 static void err_compression_marker(struct drm_i915_error_state_buf *m)
369 {
370         err_puts(m, "~");
371 }
372
373 #endif
374
375 static void print_error_buffers(struct drm_i915_error_state_buf *m,
376                                 const char *name,
377                                 struct drm_i915_error_buffer *err,
378                                 int count)
379 {
380         err_printf(m, "%s [%d]:\n", name, count);
381
382         while (count--) {
383                 err_printf(m, "    %08x_%08x %8u %02x %02x",
384                            upper_32_bits(err->gtt_offset),
385                            lower_32_bits(err->gtt_offset),
386                            err->size,
387                            err->read_domains,
388                            err->write_domain);
389                 err_puts(m, tiling_flag(err->tiling));
390                 err_puts(m, dirty_flag(err->dirty));
391                 err_puts(m, purgeable_flag(err->purgeable));
392                 err_puts(m, err->userptr ? " userptr" : "");
393                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
394
395                 if (err->name)
396                         err_printf(m, " (name: %d)", err->name);
397                 if (err->fence_reg != I915_FENCE_REG_NONE)
398                         err_printf(m, " (fence: %d)", err->fence_reg);
399
400                 err_puts(m, "\n");
401                 err++;
402         }
403 }
404
405 static void error_print_instdone(struct drm_i915_error_state_buf *m,
406                                  const struct drm_i915_error_engine *ee)
407 {
408         int slice;
409         int subslice;
410
411         err_printf(m, "  INSTDONE: 0x%08x\n",
412                    ee->instdone.instdone);
413
414         if (ee->engine_id != RCS0 || INTEL_GEN(m->i915) <= 3)
415                 return;
416
417         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
418                    ee->instdone.slice_common);
419
420         if (INTEL_GEN(m->i915) <= 6)
421                 return;
422
423         for_each_instdone_slice_subslice(m->i915, slice, subslice)
424                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
425                            slice, subslice,
426                            ee->instdone.sampler[slice][subslice]);
427
428         for_each_instdone_slice_subslice(m->i915, slice, subslice)
429                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
430                            slice, subslice,
431                            ee->instdone.row[slice][subslice]);
432 }
433
434 static void error_print_request(struct drm_i915_error_state_buf *m,
435                                 const char *prefix,
436                                 const struct drm_i915_error_request *erq,
437                                 const unsigned long epoch)
438 {
439         if (!erq->seqno)
440                 return;
441
442         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
443                    prefix, erq->pid, erq->context, erq->seqno,
444                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
445                             &erq->flags) ? "!" : "",
446                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
447                             &erq->flags) ? "+" : "",
448                    erq->sched_attr.priority,
449                    jiffies_to_msecs(erq->jiffies - epoch),
450                    erq->start, erq->head, erq->tail);
451 }
452
453 static void error_print_context(struct drm_i915_error_state_buf *m,
454                                 const char *header,
455                                 const struct drm_i915_error_context *ctx)
456 {
457         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, guilty %d active %d\n",
458                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
459                    ctx->sched_attr.priority, ctx->guilty, ctx->active);
460 }
461
462 static void error_print_engine(struct drm_i915_error_state_buf *m,
463                                const struct drm_i915_error_engine *ee,
464                                const unsigned long epoch)
465 {
466         int n;
467
468         err_printf(m, "%s command stream:\n",
469                    engine_name(m->i915, ee->engine_id));
470         err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
471         err_printf(m, "  START: 0x%08x\n", ee->start);
472         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
473         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
474                    ee->tail, ee->rq_post, ee->rq_tail);
475         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
476         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
477         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
478         err_printf(m, "  ACTHD: 0x%08x %08x\n",
479                    (u32)(ee->acthd>>32), (u32)ee->acthd);
480         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
481         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
482
483         error_print_instdone(m, ee);
484
485         if (ee->batchbuffer) {
486                 u64 start = ee->batchbuffer->gtt_offset;
487                 u64 end = start + ee->batchbuffer->gtt_size;
488
489                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
490                            upper_32_bits(start), lower_32_bits(start),
491                            upper_32_bits(end), lower_32_bits(end));
492         }
493         if (INTEL_GEN(m->i915) >= 4) {
494                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
495                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
496                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
497                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
498         }
499         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
500         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
501                    lower_32_bits(ee->faddr));
502         if (INTEL_GEN(m->i915) >= 6) {
503                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
504                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
505         }
506         if (HAS_PPGTT(m->i915)) {
507                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
508
509                 if (INTEL_GEN(m->i915) >= 8) {
510                         int i;
511                         for (i = 0; i < 4; i++)
512                                 err_printf(m, "  PDP%d: 0x%016llx\n",
513                                            i, ee->vm_info.pdp[i]);
514                 } else {
515                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
516                                    ee->vm_info.pp_dir_base);
517                 }
518         }
519         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
520         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
521         err_printf(m, "  hangcheck timestamp: %dms (%lu%s)\n",
522                    jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
523                    ee->hangcheck_timestamp,
524                    ee->hangcheck_timestamp == epoch ? "; epoch" : "");
525         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
526
527         for (n = 0; n < ee->num_ports; n++) {
528                 err_printf(m, "  ELSP[%d]:", n);
529                 error_print_request(m, " ", &ee->execlist[n], epoch);
530         }
531
532         error_print_context(m, "  Active context: ", &ee->context);
533 }
534
535 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
536 {
537         va_list args;
538
539         va_start(args, f);
540         i915_error_vprintf(e, f, args);
541         va_end(args);
542 }
543
544 static void print_error_obj(struct drm_i915_error_state_buf *m,
545                             struct intel_engine_cs *engine,
546                             const char *name,
547                             struct drm_i915_error_object *obj)
548 {
549         char out[ASCII85_BUFSZ];
550         int page;
551
552         if (!obj)
553                 return;
554
555         if (name) {
556                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
557                            engine ? engine->name : "global", name,
558                            upper_32_bits(obj->gtt_offset),
559                            lower_32_bits(obj->gtt_offset));
560         }
561
562         err_compression_marker(m);
563         for (page = 0; page < obj->page_count; page++) {
564                 int i, len;
565
566                 len = PAGE_SIZE;
567                 if (page == obj->page_count - 1)
568                         len -= obj->unused;
569                 len = ascii85_encode_len(len);
570
571                 for (i = 0; i < len; i++)
572                         err_puts(m, ascii85_encode(obj->pages[page][i], out));
573         }
574         err_puts(m, "\n");
575 }
576
577 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
578                                    const struct intel_device_info *info,
579                                    const struct intel_runtime_info *runtime,
580                                    const struct intel_driver_caps *caps)
581 {
582         struct drm_printer p = i915_error_printer(m);
583
584         intel_device_info_dump_flags(info, &p);
585         intel_driver_caps_print(caps, &p);
586         intel_device_info_dump_topology(&runtime->sseu, &p);
587 }
588
589 static void err_print_params(struct drm_i915_error_state_buf *m,
590                              const struct i915_params *params)
591 {
592         struct drm_printer p = i915_error_printer(m);
593
594         i915_params_dump(params, &p);
595 }
596
597 static void err_print_pciid(struct drm_i915_error_state_buf *m,
598                             struct drm_i915_private *i915)
599 {
600         struct pci_dev *pdev = i915->drm.pdev;
601
602         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
603         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
604         err_printf(m, "PCI Subsystem: %04x:%04x\n",
605                    pdev->subsystem_vendor,
606                    pdev->subsystem_device);
607 }
608
609 static void err_print_uc(struct drm_i915_error_state_buf *m,
610                          const struct i915_error_uc *error_uc)
611 {
612         struct drm_printer p = i915_error_printer(m);
613         const struct i915_gpu_state *error =
614                 container_of(error_uc, typeof(*error), uc);
615
616         if (!error->device_info.has_guc)
617                 return;
618
619         intel_uc_fw_dump(&error_uc->guc_fw, &p);
620         intel_uc_fw_dump(&error_uc->huc_fw, &p);
621         print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
622 }
623
624 static void err_free_sgl(struct scatterlist *sgl)
625 {
626         while (sgl) {
627                 struct scatterlist *sg;
628
629                 for (sg = sgl; !sg_is_chain(sg); sg++) {
630                         kfree(sg_virt(sg));
631                         if (sg_is_last(sg))
632                                 break;
633                 }
634
635                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
636                 free_page((unsigned long)sgl);
637                 sgl = sg;
638         }
639 }
640
641 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
642                                struct i915_gpu_state *error)
643 {
644         struct drm_i915_error_object *obj;
645         struct timespec64 ts;
646         int i, j;
647
648         if (*error->error_msg)
649                 err_printf(m, "%s\n", error->error_msg);
650         err_printf(m, "Kernel: %s %s\n",
651                    init_utsname()->release,
652                    init_utsname()->machine);
653         ts = ktime_to_timespec64(error->time);
654         err_printf(m, "Time: %lld s %ld us\n",
655                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
656         ts = ktime_to_timespec64(error->boottime);
657         err_printf(m, "Boottime: %lld s %ld us\n",
658                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
659         ts = ktime_to_timespec64(error->uptime);
660         err_printf(m, "Uptime: %lld s %ld us\n",
661                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
662         err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
663         err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
664                    error->capture,
665                    jiffies_to_msecs(jiffies - error->capture),
666                    jiffies_to_msecs(error->capture - error->epoch));
667
668         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
669                 if (!error->engine[i].context.pid)
670                         continue;
671
672                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
673                            engine_name(m->i915, i),
674                            error->engine[i].context.comm,
675                            error->engine[i].context.pid);
676         }
677         err_printf(m, "Reset count: %u\n", error->reset_count);
678         err_printf(m, "Suspend count: %u\n", error->suspend_count);
679         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
680         err_print_pciid(m, m->i915);
681
682         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
683
684         if (HAS_CSR(m->i915)) {
685                 struct intel_csr *csr = &m->i915->csr;
686
687                 err_printf(m, "DMC loaded: %s\n",
688                            yesno(csr->dmc_payload != NULL));
689                 err_printf(m, "DMC fw version: %d.%d\n",
690                            CSR_VERSION_MAJOR(csr->version),
691                            CSR_VERSION_MINOR(csr->version));
692         }
693
694         err_printf(m, "GT awake: %s\n", yesno(error->awake));
695         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
696         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
697         err_printf(m, "EIR: 0x%08x\n", error->eir);
698         err_printf(m, "IER: 0x%08x\n", error->ier);
699         for (i = 0; i < error->ngtier; i++)
700                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
701         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
702         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
703         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
704         err_printf(m, "CCID: 0x%08x\n", error->ccid);
705
706         for (i = 0; i < error->nfence; i++)
707                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
708
709         if (INTEL_GEN(m->i915) >= 6) {
710                 err_printf(m, "ERROR: 0x%08x\n", error->error);
711
712                 if (INTEL_GEN(m->i915) >= 8)
713                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
714                                    error->fault_data1, error->fault_data0);
715
716                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
717         }
718
719         if (IS_GEN(m->i915, 7))
720                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
721
722         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
723                 if (error->engine[i].engine_id != -1)
724                         error_print_engine(m, &error->engine[i], error->epoch);
725         }
726
727         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
728                 char buf[128];
729                 int len, first = 1;
730
731                 if (!error->active_vm[i])
732                         break;
733
734                 len = scnprintf(buf, sizeof(buf), "Active (");
735                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
736                         if (error->engine[j].vm != error->active_vm[i])
737                                 continue;
738
739                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
740                                          first ? "" : ", ",
741                                          m->i915->engine[j]->name);
742                         first = 0;
743                 }
744                 scnprintf(buf + len, sizeof(buf), ")");
745                 print_error_buffers(m, buf,
746                                     error->active_bo[i],
747                                     error->active_bo_count[i]);
748         }
749
750         print_error_buffers(m, "Pinned (global)",
751                             error->pinned_bo,
752                             error->pinned_bo_count);
753
754         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
755                 const struct drm_i915_error_engine *ee = &error->engine[i];
756
757                 obj = ee->batchbuffer;
758                 if (obj) {
759                         err_puts(m, m->i915->engine[i]->name);
760                         if (ee->context.pid)
761                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d])",
762                                            ee->context.comm,
763                                            ee->context.pid,
764                                            ee->context.handle,
765                                            ee->context.hw_id);
766                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
767                                    upper_32_bits(obj->gtt_offset),
768                                    lower_32_bits(obj->gtt_offset));
769                         print_error_obj(m, m->i915->engine[i], NULL, obj);
770                 }
771
772                 for (j = 0; j < ee->user_bo_count; j++)
773                         print_error_obj(m, m->i915->engine[i],
774                                         "user", ee->user_bo[j]);
775
776                 if (ee->num_requests) {
777                         err_printf(m, "%s --- %d requests\n",
778                                    m->i915->engine[i]->name,
779                                    ee->num_requests);
780                         for (j = 0; j < ee->num_requests; j++)
781                                 error_print_request(m, " ",
782                                                     &ee->requests[j],
783                                                     error->epoch);
784                 }
785
786                 print_error_obj(m, m->i915->engine[i],
787                                 "ringbuffer", ee->ringbuffer);
788
789                 print_error_obj(m, m->i915->engine[i],
790                                 "HW Status", ee->hws_page);
791
792                 print_error_obj(m, m->i915->engine[i],
793                                 "HW context", ee->ctx);
794
795                 print_error_obj(m, m->i915->engine[i],
796                                 "WA context", ee->wa_ctx);
797
798                 print_error_obj(m, m->i915->engine[i],
799                                 "WA batchbuffer", ee->wa_batchbuffer);
800
801                 print_error_obj(m, m->i915->engine[i],
802                                 "NULL context", ee->default_state);
803         }
804
805         if (error->overlay)
806                 intel_overlay_print_error_state(m, error->overlay);
807
808         if (error->display)
809                 intel_display_print_error_state(m, error->display);
810
811         err_print_capabilities(m, &error->device_info, &error->runtime_info,
812                                &error->driver_caps);
813         err_print_params(m, &error->params);
814         err_print_uc(m, &error->uc);
815 }
816
817 static int err_print_to_sgl(struct i915_gpu_state *error)
818 {
819         struct drm_i915_error_state_buf m;
820
821         if (IS_ERR(error))
822                 return PTR_ERR(error);
823
824         if (READ_ONCE(error->sgl))
825                 return 0;
826
827         memset(&m, 0, sizeof(m));
828         m.i915 = error->i915;
829
830         __err_print_to_sgl(&m, error);
831
832         if (m.buf) {
833                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
834                 m.bytes = 0;
835                 m.buf = NULL;
836         }
837         if (m.cur) {
838                 GEM_BUG_ON(m.end < m.cur);
839                 sg_mark_end(m.cur - 1);
840         }
841         GEM_BUG_ON(m.sgl && !m.cur);
842
843         if (m.err) {
844                 err_free_sgl(m.sgl);
845                 return m.err;
846         }
847
848         if (cmpxchg(&error->sgl, NULL, m.sgl))
849                 err_free_sgl(m.sgl);
850
851         return 0;
852 }
853
854 ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
855                                       char *buf, loff_t off, size_t rem)
856 {
857         struct scatterlist *sg;
858         size_t count;
859         loff_t pos;
860         int err;
861
862         if (!error || !rem)
863                 return 0;
864
865         err = err_print_to_sgl(error);
866         if (err)
867                 return err;
868
869         sg = READ_ONCE(error->fit);
870         if (!sg || off < sg->dma_address)
871                 sg = error->sgl;
872         if (!sg)
873                 return 0;
874
875         pos = sg->dma_address;
876         count = 0;
877         do {
878                 size_t len, start;
879
880                 if (sg_is_chain(sg)) {
881                         sg = sg_chain_ptr(sg);
882                         GEM_BUG_ON(sg_is_chain(sg));
883                 }
884
885                 len = sg->length;
886                 if (pos + len <= off) {
887                         pos += len;
888                         continue;
889                 }
890
891                 start = sg->offset;
892                 if (pos < off) {
893                         GEM_BUG_ON(off - pos > len);
894                         len -= off - pos;
895                         start += off - pos;
896                         pos = off;
897                 }
898
899                 len = min(len, rem);
900                 GEM_BUG_ON(!len || len > sg->length);
901
902                 memcpy(buf, page_address(sg_page(sg)) + start, len);
903
904                 count += len;
905                 pos += len;
906
907                 buf += len;
908                 rem -= len;
909                 if (!rem) {
910                         WRITE_ONCE(error->fit, sg);
911                         break;
912                 }
913         } while (!sg_is_last(sg++));
914
915         return count;
916 }
917
918 static void i915_error_object_free(struct drm_i915_error_object *obj)
919 {
920         int page;
921
922         if (obj == NULL)
923                 return;
924
925         for (page = 0; page < obj->page_count; page++)
926                 free_page((unsigned long)obj->pages[page]);
927
928         kfree(obj);
929 }
930
931
932 static void cleanup_params(struct i915_gpu_state *error)
933 {
934         i915_params_free(&error->params);
935 }
936
937 static void cleanup_uc_state(struct i915_gpu_state *error)
938 {
939         struct i915_error_uc *error_uc = &error->uc;
940
941         kfree(error_uc->guc_fw.path);
942         kfree(error_uc->huc_fw.path);
943         i915_error_object_free(error_uc->guc_log);
944 }
945
946 void __i915_gpu_state_free(struct kref *error_ref)
947 {
948         struct i915_gpu_state *error =
949                 container_of(error_ref, typeof(*error), ref);
950         long i, j;
951
952         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
953                 struct drm_i915_error_engine *ee = &error->engine[i];
954
955                 for (j = 0; j < ee->user_bo_count; j++)
956                         i915_error_object_free(ee->user_bo[j]);
957                 kfree(ee->user_bo);
958
959                 i915_error_object_free(ee->batchbuffer);
960                 i915_error_object_free(ee->wa_batchbuffer);
961                 i915_error_object_free(ee->ringbuffer);
962                 i915_error_object_free(ee->hws_page);
963                 i915_error_object_free(ee->ctx);
964                 i915_error_object_free(ee->wa_ctx);
965
966                 kfree(ee->requests);
967         }
968
969         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
970                 kfree(error->active_bo[i]);
971         kfree(error->pinned_bo);
972
973         kfree(error->overlay);
974         kfree(error->display);
975
976         cleanup_params(error);
977         cleanup_uc_state(error);
978
979         err_free_sgl(error->sgl);
980         kfree(error);
981 }
982
983 static struct drm_i915_error_object *
984 i915_error_object_create(struct drm_i915_private *i915,
985                          struct i915_vma *vma)
986 {
987         struct i915_ggtt *ggtt = &i915->ggtt;
988         const u64 slot = ggtt->error_capture.start;
989         struct drm_i915_error_object *dst;
990         struct compress compress;
991         unsigned long num_pages;
992         struct sgt_iter iter;
993         dma_addr_t dma;
994         int ret;
995
996         if (!vma || !vma->pages)
997                 return NULL;
998
999         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1000         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1001         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
1002                       GFP_ATOMIC | __GFP_NOWARN);
1003         if (!dst)
1004                 return NULL;
1005
1006         dst->gtt_offset = vma->node.start;
1007         dst->gtt_size = vma->node.size;
1008         dst->num_pages = num_pages;
1009         dst->page_count = 0;
1010         dst->unused = 0;
1011
1012         if (!compress_init(&compress)) {
1013                 kfree(dst);
1014                 return NULL;
1015         }
1016
1017         ret = -EINVAL;
1018         for_each_sgt_dma(dma, iter, vma->pages) {
1019                 void __iomem *s;
1020
1021                 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
1022
1023                 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
1024                 ret = compress_page(&compress, (void  __force *)s, dst);
1025                 io_mapping_unmap_atomic(s);
1026                 if (ret)
1027                         break;
1028         }
1029
1030         if (ret || compress_flush(&compress, dst)) {
1031                 while (dst->page_count--)
1032                         free_page((unsigned long)dst->pages[dst->page_count]);
1033                 kfree(dst);
1034                 dst = NULL;
1035         }
1036
1037         compress_fini(&compress, dst);
1038         return dst;
1039 }
1040
1041 static void capture_bo(struct drm_i915_error_buffer *err,
1042                        struct i915_vma *vma)
1043 {
1044         struct drm_i915_gem_object *obj = vma->obj;
1045
1046         err->size = obj->base.size;
1047         err->name = obj->base.name;
1048
1049         err->gtt_offset = vma->node.start;
1050         err->read_domains = obj->read_domains;
1051         err->write_domain = obj->write_domain;
1052         err->fence_reg = vma->fence ? vma->fence->id : -1;
1053         err->tiling = i915_gem_object_get_tiling(obj);
1054         err->dirty = obj->mm.dirty;
1055         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1056         err->userptr = obj->userptr.mm != NULL;
1057         err->cache_level = obj->cache_level;
1058 }
1059
1060 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1061                             int count, struct list_head *head,
1062                             unsigned int flags)
1063 #define ACTIVE_ONLY BIT(0)
1064 #define PINNED_ONLY BIT(1)
1065 {
1066         struct i915_vma *vma;
1067         int i = 0;
1068
1069         list_for_each_entry(vma, head, vm_link) {
1070                 if (!vma->obj)
1071                         continue;
1072
1073                 if (flags & ACTIVE_ONLY && !i915_vma_is_active(vma))
1074                         continue;
1075
1076                 if (flags & PINNED_ONLY && !i915_vma_is_pinned(vma))
1077                         continue;
1078
1079                 capture_bo(err++, vma);
1080                 if (++i == count)
1081                         break;
1082         }
1083
1084         return i;
1085 }
1086
1087 /*
1088  * Generate a semi-unique error code. The code is not meant to have meaning, The
1089  * code's only purpose is to try to prevent false duplicated bug reports by
1090  * grossly estimating a GPU error state.
1091  *
1092  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1093  * the hang if we could strip the GTT offset information from it.
1094  *
1095  * It's only a small step better than a random number in its current form.
1096  */
1097 static u32 i915_error_generate_code(struct i915_gpu_state *error,
1098                                     unsigned long engine_mask)
1099 {
1100         /*
1101          * IPEHR would be an ideal way to detect errors, as it's the gross
1102          * measure of "the command that hung." However, has some very common
1103          * synchronization commands which almost always appear in the case
1104          * strictly a client bug. Use instdone to differentiate those some.
1105          */
1106         if (engine_mask) {
1107                 struct drm_i915_error_engine *ee =
1108                         &error->engine[ffs(engine_mask)];
1109
1110                 return ee->ipehr ^ ee->instdone.instdone;
1111         }
1112
1113         return 0;
1114 }
1115
1116 static void gem_record_fences(struct i915_gpu_state *error)
1117 {
1118         struct drm_i915_private *dev_priv = error->i915;
1119         int i;
1120
1121         if (INTEL_GEN(dev_priv) >= 6) {
1122                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1123                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1124         } else if (INTEL_GEN(dev_priv) >= 4) {
1125                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1126                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1127         } else {
1128                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1129                         error->fence[i] = I915_READ(FENCE_REG(i));
1130         }
1131         error->nfence = i;
1132 }
1133
1134 static void error_record_engine_registers(struct i915_gpu_state *error,
1135                                           struct intel_engine_cs *engine,
1136                                           struct drm_i915_error_engine *ee)
1137 {
1138         struct drm_i915_private *dev_priv = engine->i915;
1139
1140         if (INTEL_GEN(dev_priv) >= 6) {
1141                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1142                 if (INTEL_GEN(dev_priv) >= 8)
1143                         ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1144                 else
1145                         ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1146         }
1147
1148         if (INTEL_GEN(dev_priv) >= 4) {
1149                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1150                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1151                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1152                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1153                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1154                 if (INTEL_GEN(dev_priv) >= 8) {
1155                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1156                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1157                 }
1158                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1159         } else {
1160                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1161                 ee->ipeir = I915_READ(IPEIR);
1162                 ee->ipehr = I915_READ(IPEHR);
1163         }
1164
1165         intel_engine_get_instdone(engine, &ee->instdone);
1166
1167         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1168         ee->acthd = intel_engine_get_active_head(engine);
1169         ee->start = I915_READ_START(engine);
1170         ee->head = I915_READ_HEAD(engine);
1171         ee->tail = I915_READ_TAIL(engine);
1172         ee->ctl = I915_READ_CTL(engine);
1173         if (INTEL_GEN(dev_priv) > 2)
1174                 ee->mode = I915_READ_MODE(engine);
1175
1176         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1177                 i915_reg_t mmio;
1178
1179                 if (IS_GEN(dev_priv, 7)) {
1180                         switch (engine->id) {
1181                         default:
1182                                 MISSING_CASE(engine->id);
1183                         case RCS0:
1184                                 mmio = RENDER_HWS_PGA_GEN7;
1185                                 break;
1186                         case BCS0:
1187                                 mmio = BLT_HWS_PGA_GEN7;
1188                                 break;
1189                         case VCS0:
1190                                 mmio = BSD_HWS_PGA_GEN7;
1191                                 break;
1192                         case VECS0:
1193                                 mmio = VEBOX_HWS_PGA_GEN7;
1194                                 break;
1195                         }
1196                 } else if (IS_GEN(engine->i915, 6)) {
1197                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1198                 } else {
1199                         /* XXX: gen8 returns to sanity */
1200                         mmio = RING_HWS_PGA(engine->mmio_base);
1201                 }
1202
1203                 ee->hws = I915_READ(mmio);
1204         }
1205
1206         ee->idle = intel_engine_is_idle(engine);
1207         if (!ee->idle)
1208                 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1209         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1210                                                   engine);
1211
1212         if (HAS_PPGTT(dev_priv)) {
1213                 int i;
1214
1215                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1216
1217                 if (IS_GEN(dev_priv, 6))
1218                         ee->vm_info.pp_dir_base =
1219                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1220                 else if (IS_GEN(dev_priv, 7))
1221                         ee->vm_info.pp_dir_base =
1222                                 I915_READ(RING_PP_DIR_BASE(engine));
1223                 else if (INTEL_GEN(dev_priv) >= 8)
1224                         for (i = 0; i < 4; i++) {
1225                                 ee->vm_info.pdp[i] =
1226                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1227                                 ee->vm_info.pdp[i] <<= 32;
1228                                 ee->vm_info.pdp[i] |=
1229                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1230                         }
1231         }
1232 }
1233
1234 static void record_request(struct i915_request *request,
1235                            struct drm_i915_error_request *erq)
1236 {
1237         struct i915_gem_context *ctx = request->gem_context;
1238
1239         erq->flags = request->fence.flags;
1240         erq->context = request->fence.context;
1241         erq->seqno = request->fence.seqno;
1242         erq->sched_attr = request->sched.attr;
1243         erq->jiffies = request->emitted_jiffies;
1244         erq->start = i915_ggtt_offset(request->ring->vma);
1245         erq->head = request->head;
1246         erq->tail = request->tail;
1247
1248         rcu_read_lock();
1249         erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1250         rcu_read_unlock();
1251 }
1252
1253 static void engine_record_requests(struct intel_engine_cs *engine,
1254                                    struct i915_request *first,
1255                                    struct drm_i915_error_engine *ee)
1256 {
1257         struct i915_request *request;
1258         int count;
1259
1260         count = 0;
1261         request = first;
1262         list_for_each_entry_from(request, &engine->timeline.requests, link)
1263                 count++;
1264         if (!count)
1265                 return;
1266
1267         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1268         if (!ee->requests)
1269                 return;
1270
1271         ee->num_requests = count;
1272
1273         count = 0;
1274         request = first;
1275         list_for_each_entry_from(request, &engine->timeline.requests, link) {
1276                 if (count >= ee->num_requests) {
1277                         /*
1278                          * If the ring request list was changed in
1279                          * between the point where the error request
1280                          * list was created and dimensioned and this
1281                          * point then just exit early to avoid crashes.
1282                          *
1283                          * We don't need to communicate that the
1284                          * request list changed state during error
1285                          * state capture and that the error state is
1286                          * slightly incorrect as a consequence since we
1287                          * are typically only interested in the request
1288                          * list state at the point of error state
1289                          * capture, not in any changes happening during
1290                          * the capture.
1291                          */
1292                         break;
1293                 }
1294
1295                 record_request(request, &ee->requests[count++]);
1296         }
1297         ee->num_requests = count;
1298 }
1299
1300 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1301                                           struct drm_i915_error_engine *ee)
1302 {
1303         const struct intel_engine_execlists * const execlists = &engine->execlists;
1304         unsigned int n;
1305
1306         for (n = 0; n < execlists_num_ports(execlists); n++) {
1307                 struct i915_request *rq = port_request(&execlists->port[n]);
1308
1309                 if (!rq)
1310                         break;
1311
1312                 record_request(rq, &ee->execlist[n]);
1313         }
1314
1315         ee->num_ports = n;
1316 }
1317
1318 static void record_context(struct drm_i915_error_context *e,
1319                            struct i915_gem_context *ctx)
1320 {
1321         if (ctx->pid) {
1322                 struct task_struct *task;
1323
1324                 rcu_read_lock();
1325                 task = pid_task(ctx->pid, PIDTYPE_PID);
1326                 if (task) {
1327                         strcpy(e->comm, task->comm);
1328                         e->pid = task->pid;
1329                 }
1330                 rcu_read_unlock();
1331         }
1332
1333         e->handle = ctx->user_handle;
1334         e->hw_id = ctx->hw_id;
1335         e->sched_attr = ctx->sched;
1336         e->guilty = atomic_read(&ctx->guilty_count);
1337         e->active = atomic_read(&ctx->active_count);
1338 }
1339
1340 static void request_record_user_bo(struct i915_request *request,
1341                                    struct drm_i915_error_engine *ee)
1342 {
1343         struct i915_capture_list *c;
1344         struct drm_i915_error_object **bo;
1345         long count, max;
1346
1347         max = 0;
1348         for (c = request->capture_list; c; c = c->next)
1349                 max++;
1350         if (!max)
1351                 return;
1352
1353         bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1354         if (!bo) {
1355                 /* If we can't capture everything, try to capture something. */
1356                 max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
1357                 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1358         }
1359         if (!bo)
1360                 return;
1361
1362         count = 0;
1363         for (c = request->capture_list; c; c = c->next) {
1364                 bo[count] = i915_error_object_create(request->i915, c->vma);
1365                 if (!bo[count])
1366                         break;
1367                 if (++count == max)
1368                         break;
1369         }
1370
1371         ee->user_bo = bo;
1372         ee->user_bo_count = count;
1373 }
1374
1375 static struct drm_i915_error_object *
1376 capture_object(struct drm_i915_private *dev_priv,
1377                struct drm_i915_gem_object *obj)
1378 {
1379         if (obj && i915_gem_object_has_pages(obj)) {
1380                 struct i915_vma fake = {
1381                         .node = { .start = U64_MAX, .size = obj->base.size },
1382                         .size = obj->base.size,
1383                         .pages = obj->mm.pages,
1384                         .obj = obj,
1385                 };
1386
1387                 return i915_error_object_create(dev_priv, &fake);
1388         } else {
1389                 return NULL;
1390         }
1391 }
1392
1393 static void gem_record_rings(struct i915_gpu_state *error)
1394 {
1395         struct drm_i915_private *i915 = error->i915;
1396         struct i915_ggtt *ggtt = &i915->ggtt;
1397         int i;
1398
1399         for (i = 0; i < I915_NUM_ENGINES; i++) {
1400                 struct intel_engine_cs *engine = i915->engine[i];
1401                 struct drm_i915_error_engine *ee = &error->engine[i];
1402                 struct i915_request *request;
1403
1404                 ee->engine_id = -1;
1405
1406                 if (!engine)
1407                         continue;
1408
1409                 ee->engine_id = i;
1410
1411                 error_record_engine_registers(error, engine, ee);
1412                 error_record_engine_execlists(engine, ee);
1413
1414                 request = intel_engine_find_active_request(engine);
1415                 if (request) {
1416                         struct i915_gem_context *ctx = request->gem_context;
1417                         struct intel_ring *ring;
1418
1419                         ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm;
1420
1421                         record_context(&ee->context, ctx);
1422
1423                         /* We need to copy these to an anonymous buffer
1424                          * as the simplest method to avoid being overwritten
1425                          * by userspace.
1426                          */
1427                         ee->batchbuffer =
1428                                 i915_error_object_create(i915, request->batch);
1429
1430                         if (HAS_BROKEN_CS_TLB(i915))
1431                                 ee->wa_batchbuffer =
1432                                         i915_error_object_create(i915,
1433                                                                  i915->gt.scratch);
1434                         request_record_user_bo(request, ee);
1435
1436                         ee->ctx =
1437                                 i915_error_object_create(i915,
1438                                                          request->hw_context->state);
1439
1440                         error->simulated |=
1441                                 i915_gem_context_no_error_capture(ctx);
1442
1443                         ee->rq_head = request->head;
1444                         ee->rq_post = request->postfix;
1445                         ee->rq_tail = request->tail;
1446
1447                         ring = request->ring;
1448                         ee->cpu_ring_head = ring->head;
1449                         ee->cpu_ring_tail = ring->tail;
1450                         ee->ringbuffer =
1451                                 i915_error_object_create(i915, ring->vma);
1452
1453                         engine_record_requests(engine, request, ee);
1454                 }
1455
1456                 ee->hws_page =
1457                         i915_error_object_create(i915,
1458                                                  engine->status_page.vma);
1459
1460                 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1461
1462                 ee->default_state = capture_object(i915, engine->default_state);
1463         }
1464 }
1465
1466 static void gem_capture_vm(struct i915_gpu_state *error,
1467                            struct i915_address_space *vm,
1468                            int idx)
1469 {
1470         struct drm_i915_error_buffer *active_bo;
1471         struct i915_vma *vma;
1472         int count;
1473
1474         count = 0;
1475         list_for_each_entry(vma, &vm->bound_list, vm_link)
1476                 if (i915_vma_is_active(vma))
1477                         count++;
1478
1479         active_bo = NULL;
1480         if (count)
1481                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1482         if (active_bo)
1483                 count = capture_error_bo(active_bo,
1484                                          count, &vm->bound_list,
1485                                          ACTIVE_ONLY);
1486         else
1487                 count = 0;
1488
1489         error->active_vm[idx] = vm;
1490         error->active_bo[idx] = active_bo;
1491         error->active_bo_count[idx] = count;
1492 }
1493
1494 static void capture_active_buffers(struct i915_gpu_state *error)
1495 {
1496         int cnt = 0, i, j;
1497
1498         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1499         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1500         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1501
1502         /* Scan each engine looking for unique active contexts/vm */
1503         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1504                 struct drm_i915_error_engine *ee = &error->engine[i];
1505                 bool found;
1506
1507                 if (!ee->vm)
1508                         continue;
1509
1510                 found = false;
1511                 for (j = 0; j < i && !found; j++)
1512                         found = error->engine[j].vm == ee->vm;
1513                 if (!found)
1514                         gem_capture_vm(error, ee->vm, cnt++);
1515         }
1516 }
1517
1518 static void capture_pinned_buffers(struct i915_gpu_state *error)
1519 {
1520         struct i915_address_space *vm = &error->i915->ggtt.vm;
1521         struct drm_i915_error_buffer *bo;
1522         struct i915_vma *vma;
1523         int count;
1524
1525         count = 0;
1526         list_for_each_entry(vma, &vm->bound_list, vm_link)
1527                 count++;
1528
1529         bo = NULL;
1530         if (count)
1531                 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1532         if (!bo)
1533                 return;
1534
1535         error->pinned_bo_count =
1536                 capture_error_bo(bo, count, &vm->bound_list, PINNED_ONLY);
1537         error->pinned_bo = bo;
1538 }
1539
1540 static void capture_uc_state(struct i915_gpu_state *error)
1541 {
1542         struct drm_i915_private *i915 = error->i915;
1543         struct i915_error_uc *error_uc = &error->uc;
1544
1545         /* Capturing uC state won't be useful if there is no GuC */
1546         if (!error->device_info.has_guc)
1547                 return;
1548
1549         error_uc->guc_fw = i915->guc.fw;
1550         error_uc->huc_fw = i915->huc.fw;
1551
1552         /* Non-default firmware paths will be specified by the modparam.
1553          * As modparams are generally accesible from the userspace make
1554          * explicit copies of the firmware paths.
1555          */
1556         error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1557         error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1558         error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1559 }
1560
1561 /* Capture all registers which don't fit into another category. */
1562 static void capture_reg_state(struct i915_gpu_state *error)
1563 {
1564         struct drm_i915_private *dev_priv = error->i915;
1565         int i;
1566
1567         /* General organization
1568          * 1. Registers specific to a single generation
1569          * 2. Registers which belong to multiple generations
1570          * 3. Feature specific registers.
1571          * 4. Everything else
1572          * Please try to follow the order.
1573          */
1574
1575         /* 1: Registers specific to a single generation */
1576         if (IS_VALLEYVIEW(dev_priv)) {
1577                 error->gtier[0] = I915_READ(GTIER);
1578                 error->ier = I915_READ(VLV_IER);
1579                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1580         }
1581
1582         if (IS_GEN(dev_priv, 7))
1583                 error->err_int = I915_READ(GEN7_ERR_INT);
1584
1585         if (INTEL_GEN(dev_priv) >= 8) {
1586                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1587                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1588         }
1589
1590         if (IS_GEN(dev_priv, 6)) {
1591                 error->forcewake = I915_READ_FW(FORCEWAKE);
1592                 error->gab_ctl = I915_READ(GAB_CTL);
1593                 error->gfx_mode = I915_READ(GFX_MODE);
1594         }
1595
1596         /* 2: Registers which belong to multiple generations */
1597         if (INTEL_GEN(dev_priv) >= 7)
1598                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1599
1600         if (INTEL_GEN(dev_priv) >= 6) {
1601                 error->derrmr = I915_READ(DERRMR);
1602                 error->error = I915_READ(ERROR_GEN6);
1603                 error->done_reg = I915_READ(DONE_REG);
1604         }
1605
1606         if (INTEL_GEN(dev_priv) >= 5)
1607                 error->ccid = I915_READ(CCID);
1608
1609         /* 3: Feature specific registers */
1610         if (IS_GEN_RANGE(dev_priv, 6, 7)) {
1611                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1612                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1613         }
1614
1615         /* 4: Everything else */
1616         if (INTEL_GEN(dev_priv) >= 11) {
1617                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1618                 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
1619                 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
1620                 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
1621                 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1622                 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
1623                 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
1624                 error->ngtier = 6;
1625         } else if (INTEL_GEN(dev_priv) >= 8) {
1626                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1627                 for (i = 0; i < 4; i++)
1628                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1629                 error->ngtier = 4;
1630         } else if (HAS_PCH_SPLIT(dev_priv)) {
1631                 error->ier = I915_READ(DEIER);
1632                 error->gtier[0] = I915_READ(GTIER);
1633                 error->ngtier = 1;
1634         } else if (IS_GEN(dev_priv, 2)) {
1635                 error->ier = I915_READ16(IER);
1636         } else if (!IS_VALLEYVIEW(dev_priv)) {
1637                 error->ier = I915_READ(IER);
1638         }
1639         error->eir = I915_READ(EIR);
1640         error->pgtbl_er = I915_READ(PGTBL_ER);
1641 }
1642
1643 static const char *
1644 error_msg(struct i915_gpu_state *error, unsigned long engines, const char *msg)
1645 {
1646         int len;
1647         int i;
1648
1649         for (i = 0; i < ARRAY_SIZE(error->engine); i++)
1650                 if (!error->engine[i].context.pid)
1651                         engines &= ~BIT(i);
1652
1653         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1654                         "GPU HANG: ecode %d:%lx:0x%08x",
1655                         INTEL_GEN(error->i915), engines,
1656                         i915_error_generate_code(error, engines));
1657         if (engines) {
1658                 /* Just show the first executing process, more is confusing */
1659                 i = __ffs(engines);
1660                 len += scnprintf(error->error_msg + len,
1661                                  sizeof(error->error_msg) - len,
1662                                  ", in %s [%d]",
1663                                  error->engine[i].context.comm,
1664                                  error->engine[i].context.pid);
1665         }
1666         if (msg)
1667                 len += scnprintf(error->error_msg + len,
1668                                  sizeof(error->error_msg) - len,
1669                                  ", %s", msg);
1670
1671         return error->error_msg;
1672 }
1673
1674 static void capture_gen_state(struct i915_gpu_state *error)
1675 {
1676         struct drm_i915_private *i915 = error->i915;
1677
1678         error->awake = i915->gt.awake;
1679         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1680         error->suspended = i915->runtime_pm.suspended;
1681
1682         error->iommu = -1;
1683 #ifdef CONFIG_INTEL_IOMMU
1684         error->iommu = intel_iommu_gfx_mapped;
1685 #endif
1686         error->reset_count = i915_reset_count(&i915->gpu_error);
1687         error->suspend_count = i915->suspend_count;
1688
1689         memcpy(&error->device_info,
1690                INTEL_INFO(i915),
1691                sizeof(error->device_info));
1692         memcpy(&error->runtime_info,
1693                RUNTIME_INFO(i915),
1694                sizeof(error->runtime_info));
1695         error->driver_caps = i915->caps;
1696 }
1697
1698 static void capture_params(struct i915_gpu_state *error)
1699 {
1700         i915_params_copy(&error->params, &i915_modparams);
1701 }
1702
1703 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1704 {
1705         unsigned long epoch = error->capture;
1706         int i;
1707
1708         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1709                 const struct drm_i915_error_engine *ee = &error->engine[i];
1710
1711                 if (ee->hangcheck_timestamp &&
1712                     time_before(ee->hangcheck_timestamp, epoch))
1713                         epoch = ee->hangcheck_timestamp;
1714         }
1715
1716         return epoch;
1717 }
1718
1719 static void capture_finish(struct i915_gpu_state *error)
1720 {
1721         struct i915_ggtt *ggtt = &error->i915->ggtt;
1722         const u64 slot = ggtt->error_capture.start;
1723
1724         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1725 }
1726
1727 static int capture(void *data)
1728 {
1729         struct i915_gpu_state *error = data;
1730
1731         error->time = ktime_get_real();
1732         error->boottime = ktime_get_boottime();
1733         error->uptime = ktime_sub(ktime_get(),
1734                                   error->i915->gt.last_init_time);
1735         error->capture = jiffies;
1736
1737         capture_params(error);
1738         capture_gen_state(error);
1739         capture_uc_state(error);
1740         capture_reg_state(error);
1741         gem_record_fences(error);
1742         gem_record_rings(error);
1743         capture_active_buffers(error);
1744         capture_pinned_buffers(error);
1745
1746         error->overlay = intel_overlay_capture_error_state(error->i915);
1747         error->display = intel_display_capture_error_state(error->i915);
1748
1749         error->epoch = capture_find_epoch(error);
1750
1751         capture_finish(error);
1752         return 0;
1753 }
1754
1755 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1756
1757 struct i915_gpu_state *
1758 i915_capture_gpu_state(struct drm_i915_private *i915)
1759 {
1760         struct i915_gpu_state *error;
1761
1762         /* Check if GPU capture has been disabled */
1763         error = READ_ONCE(i915->gpu_error.first_error);
1764         if (IS_ERR(error))
1765                 return error;
1766
1767         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1768         if (!error) {
1769                 i915_disable_error_state(i915, -ENOMEM);
1770                 return ERR_PTR(-ENOMEM);
1771         }
1772
1773         kref_init(&error->ref);
1774         error->i915 = i915;
1775
1776         stop_machine(capture, error, NULL);
1777
1778         return error;
1779 }
1780
1781 /**
1782  * i915_capture_error_state - capture an error record for later analysis
1783  * @i915: i915 device
1784  * @engine_mask: the mask of engines triggering the hang
1785  * @msg: a message to insert into the error capture header
1786  *
1787  * Should be called when an error is detected (either a hang or an error
1788  * interrupt) to capture error state from the time of the error.  Fills
1789  * out a structure which becomes available in debugfs for user level tools
1790  * to pick up.
1791  */
1792 void i915_capture_error_state(struct drm_i915_private *i915,
1793                               unsigned long engine_mask,
1794                               const char *msg)
1795 {
1796         static bool warned;
1797         struct i915_gpu_state *error;
1798         unsigned long flags;
1799
1800         if (!i915_modparams.error_capture)
1801                 return;
1802
1803         if (READ_ONCE(i915->gpu_error.first_error))
1804                 return;
1805
1806         error = i915_capture_gpu_state(i915);
1807         if (IS_ERR(error))
1808                 return;
1809
1810         dev_info(i915->drm.dev, "%s\n", error_msg(error, engine_mask, msg));
1811
1812         if (!error->simulated) {
1813                 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1814                 if (!i915->gpu_error.first_error) {
1815                         i915->gpu_error.first_error = error;
1816                         error = NULL;
1817                 }
1818                 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1819         }
1820
1821         if (error) {
1822                 __i915_gpu_state_free(&error->ref);
1823                 return;
1824         }
1825
1826         if (!warned &&
1827             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1828                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1829                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1830                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1831                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1832                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1833                          i915->drm.primary->index);
1834                 warned = true;
1835         }
1836 }
1837
1838 struct i915_gpu_state *
1839 i915_first_error_state(struct drm_i915_private *i915)
1840 {
1841         struct i915_gpu_state *error;
1842
1843         spin_lock_irq(&i915->gpu_error.lock);
1844         error = i915->gpu_error.first_error;
1845         if (!IS_ERR_OR_NULL(error))
1846                 i915_gpu_state_get(error);
1847         spin_unlock_irq(&i915->gpu_error.lock);
1848
1849         return error;
1850 }
1851
1852 void i915_reset_error_state(struct drm_i915_private *i915)
1853 {
1854         struct i915_gpu_state *error;
1855
1856         spin_lock_irq(&i915->gpu_error.lock);
1857         error = i915->gpu_error.first_error;
1858         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1859                 i915->gpu_error.first_error = NULL;
1860         spin_unlock_irq(&i915->gpu_error.lock);
1861
1862         if (!IS_ERR_OR_NULL(error))
1863                 i915_gpu_state_put(error);
1864 }
1865
1866 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1867 {
1868         spin_lock_irq(&i915->gpu_error.lock);
1869         if (!i915->gpu_error.first_error)
1870                 i915->gpu_error.first_error = ERR_PTR(err);
1871         spin_unlock_irq(&i915->gpu_error.lock);
1872 }