2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/string.h>
29 #include <linux/bitops.h>
31 #include <drm/i915_drm.h>
35 * DOC: buffer object tiling
37 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
38 * declare fence register requirements.
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
61 /* Check pitch constriants for all chips & tiling formats */
63 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
65 struct drm_i915_private *dev_priv = to_i915(dev);
68 /* Linear is always fine */
69 if (tiling_mode == I915_TILING_NONE)
72 if (tiling_mode > I915_TILING_LAST)
75 if (IS_GEN2(dev_priv) ||
76 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
81 /* check maximum stride & object size */
82 /* i965+ stores the end address of the gtt mapping in the fence
83 * reg, so dont bother to check the size */
84 if (INTEL_INFO(dev)->gen >= 7) {
85 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
87 } else if (INTEL_INFO(dev)->gen >= 4) {
88 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
94 if (IS_GEN3(dev_priv)) {
95 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
98 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
103 if (stride < tile_width)
106 /* 965+ just needs multiples of tile width */
107 if (INTEL_INFO(dev)->gen >= 4) {
108 if (stride & (tile_width - 1))
113 /* Pre-965 needs power of two tile widths */
114 if (stride & (stride - 1))
120 static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
122 struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
125 if (!i915_vma_is_map_and_fenceable(vma))
128 if (INTEL_GEN(dev_priv) == 3) {
129 if (vma->node.start & ~I915_FENCE_START_MASK)
132 if (vma->node.start & ~I830_FENCE_START_MASK)
136 size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
137 if (vma->node.size < size)
140 if (vma->node.start & (size - 1))
146 /* Make the current GTT allocation valid for the change in tiling. */
148 i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
150 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
151 struct i915_vma *vma;
154 if (tiling_mode == I915_TILING_NONE)
157 if (INTEL_GEN(dev_priv) >= 4)
160 list_for_each_entry(vma, &obj->vma_list, obj_link) {
161 if (i915_vma_fence_prepare(vma, tiling_mode))
164 ret = i915_vma_unbind(vma);
173 * i915_gem_set_tiling - IOCTL handler to set tiling mode
175 * @data: data pointer for the ioctl
176 * @file: DRM file for the ioctl call
178 * Sets the tiling mode of an object, returning the required swizzling of
179 * bit 6 of addresses in the object.
181 * Called by the user via ioctl.
184 * Zero on success, negative errno on failure.
187 i915_gem_set_tiling(struct drm_device *dev, void *data,
188 struct drm_file *file)
190 struct drm_i915_gem_set_tiling *args = data;
191 struct drm_i915_private *dev_priv = to_i915(dev);
192 struct drm_i915_gem_object *obj;
195 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
196 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
198 obj = i915_gem_object_lookup(file, args->handle);
202 if (!i915_tiling_ok(dev,
203 args->stride, obj->base.size, args->tiling_mode)) {
204 i915_gem_object_put_unlocked(obj);
208 intel_runtime_pm_get(dev_priv);
210 mutex_lock(&dev->struct_mutex);
211 if (obj->pin_display || obj->framebuffer_references) {
216 if (args->tiling_mode == I915_TILING_NONE) {
217 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
220 if (args->tiling_mode == I915_TILING_X)
221 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
223 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
225 /* Hide bit 17 swizzling from the user. This prevents old Mesa
226 * from aborting the application on sw fallbacks to bit 17,
227 * and we use the pread/pwrite bit17 paths to swizzle for it.
228 * If there was a user that was relying on the swizzle
229 * information for drm_intel_bo_map()ed reads/writes this would
230 * break it, but we don't have any of those.
232 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
233 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
234 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
235 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
237 /* If we can't handle the swizzling, make it untiled. */
238 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
239 args->tiling_mode = I915_TILING_NONE;
240 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
245 if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
246 args->stride != i915_gem_object_get_stride(obj)) {
247 /* We need to rebind the object if its current allocation
248 * no longer meets the alignment restrictions for its new
249 * tiling mode. Otherwise we can just leave it alone, but
250 * need to ensure that any fence register is updated before
251 * the next fenced (either through the GTT or by the BLT unit
252 * on older GPUs) access.
254 * After updating the tiling parameters, we then flag whether
255 * we need to update an associated fence register. Note this
256 * has to also include the unfenced register the GPU uses
257 * whilst executing a fenced command for an untiled object.
260 err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
262 struct i915_vma *vma;
265 obj->madv == I915_MADV_WILLNEED &&
266 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
267 if (args->tiling_mode == I915_TILING_NONE)
268 i915_gem_object_unpin_pages(obj);
269 if (!i915_gem_object_is_tiled(obj))
270 i915_gem_object_pin_pages(obj);
273 list_for_each_entry(vma, &obj->vma_list, obj_link) {
277 vma->fence->dirty = true;
279 obj->tiling_and_stride =
280 args->stride | args->tiling_mode;
282 /* Force the fence to be reacquired for GTT access */
283 i915_gem_release_mmap(obj);
286 /* we have to maintain this existing ABI... */
287 args->stride = i915_gem_object_get_stride(obj);
288 args->tiling_mode = i915_gem_object_get_tiling(obj);
290 /* Try to preallocate memory required to save swizzling on put-pages */
291 if (i915_gem_object_needs_bit17_swizzle(obj)) {
292 if (obj->bit_17 == NULL) {
293 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
294 sizeof(long), GFP_KERNEL);
302 i915_gem_object_put(obj);
303 mutex_unlock(&dev->struct_mutex);
305 intel_runtime_pm_put(dev_priv);
311 * i915_gem_get_tiling - IOCTL handler to get tiling mode
313 * @data: data pointer for the ioctl
314 * @file: DRM file for the ioctl call
316 * Returns the current tiling mode and required bit 6 swizzling for the object.
318 * Called by the user via ioctl.
321 * Zero on success, negative errno on failure.
324 i915_gem_get_tiling(struct drm_device *dev, void *data,
325 struct drm_file *file)
327 struct drm_i915_gem_get_tiling *args = data;
328 struct drm_i915_private *dev_priv = to_i915(dev);
329 struct drm_i915_gem_object *obj;
331 obj = i915_gem_object_lookup(file, args->handle);
335 args->tiling_mode = READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
336 switch (args->tiling_mode) {
338 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
341 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
343 case I915_TILING_NONE:
344 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
347 DRM_ERROR("unknown tiling mode\n");
350 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
351 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
352 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
354 args->phys_swizzle_mode = args->swizzle_mode;
355 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
356 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
357 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
358 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
360 i915_gem_object_put_unlocked(obj);