Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
1 /*
2  * Copyright © 2010 Daniel Vetter
3  * Copyright © 2011-2014 Intel Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22  * IN THE SOFTWARE.
23  *
24  */
25
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
27
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
33
34 #include <asm/set_memory.h>
35
36 #include <drm/i915_drm.h>
37
38 #include "i915_drv.h"
39 #include "i915_vgpu.h"
40 #include "i915_reset.h"
41 #include "i915_trace.h"
42 #include "intel_drv.h"
43 #include "intel_frontbuffer.h"
44
45 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
46
47 /**
48  * DOC: Global GTT views
49  *
50  * Background and previous state
51  *
52  * Historically objects could exists (be bound) in global GTT space only as
53  * singular instances with a view representing all of the object's backing pages
54  * in a linear fashion. This view will be called a normal view.
55  *
56  * To support multiple views of the same object, where the number of mapped
57  * pages is not equal to the backing store, or where the layout of the pages
58  * is not linear, concept of a GGTT view was added.
59  *
60  * One example of an alternative view is a stereo display driven by a single
61  * image. In this case we would have a framebuffer looking like this
62  * (2x2 pages):
63  *
64  *    12
65  *    34
66  *
67  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
68  * rendering. In contrast, fed to the display engine would be an alternative
69  * view which could look something like this:
70  *
71  *   1212
72  *   3434
73  *
74  * In this example both the size and layout of pages in the alternative view is
75  * different from the normal view.
76  *
77  * Implementation and usage
78  *
79  * GGTT views are implemented using VMAs and are distinguished via enum
80  * i915_ggtt_view_type and struct i915_ggtt_view.
81  *
82  * A new flavour of core GEM functions which work with GGTT bound objects were
83  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
84  * renaming  in large amounts of code. They take the struct i915_ggtt_view
85  * parameter encapsulating all metadata required to implement a view.
86  *
87  * As a helper for callers which are only interested in the normal view,
88  * globally const i915_ggtt_view_normal singleton instance exists. All old core
89  * GEM API functions, the ones not taking the view parameter, are operating on,
90  * or with the normal GGTT view.
91  *
92  * Code wanting to add or use a new GGTT view needs to:
93  *
94  * 1. Add a new enum with a suitable name.
95  * 2. Extend the metadata in the i915_ggtt_view structure if required.
96  * 3. Add support to i915_get_vma_pages().
97  *
98  * New views are required to build a scatter-gather table from within the
99  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
100  * exists for the lifetime of an VMA.
101  *
102  * Core API is designed to have copy semantics which means that passed in
103  * struct i915_ggtt_view does not need to be persistent (left around after
104  * calling the core API functions).
105  *
106  */
107
108 static int
109 i915_get_ggtt_vma_pages(struct i915_vma *vma);
110
111 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
112 {
113         /*
114          * Note that as an uncached mmio write, this will flush the
115          * WCB of the writes into the GGTT before it triggers the invalidate.
116          */
117         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
118 }
119
120 static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv)
121 {
122         gen6_ggtt_invalidate(dev_priv);
123         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
124 }
125
126 static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv)
127 {
128         intel_gtt_chipset_flush();
129 }
130
131 static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
132 {
133         i915->ggtt.invalidate(i915);
134 }
135
136 static int ppgtt_bind_vma(struct i915_vma *vma,
137                           enum i915_cache_level cache_level,
138                           u32 unused)
139 {
140         u32 pte_flags;
141         int err;
142
143         if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
144                 err = vma->vm->allocate_va_range(vma->vm,
145                                                  vma->node.start, vma->size);
146                 if (err)
147                         return err;
148         }
149
150         /* Applicable to VLV, and gen8+ */
151         pte_flags = 0;
152         if (i915_gem_object_is_readonly(vma->obj))
153                 pte_flags |= PTE_READ_ONLY;
154
155         vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
156
157         return 0;
158 }
159
160 static void ppgtt_unbind_vma(struct i915_vma *vma)
161 {
162         vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
163 }
164
165 static int ppgtt_set_pages(struct i915_vma *vma)
166 {
167         GEM_BUG_ON(vma->pages);
168
169         vma->pages = vma->obj->mm.pages;
170
171         vma->page_sizes = vma->obj->mm.page_sizes;
172
173         return 0;
174 }
175
176 static void clear_pages(struct i915_vma *vma)
177 {
178         GEM_BUG_ON(!vma->pages);
179
180         if (vma->pages != vma->obj->mm.pages) {
181                 sg_free_table(vma->pages);
182                 kfree(vma->pages);
183         }
184         vma->pages = NULL;
185
186         memset(&vma->page_sizes, 0, sizeof(vma->page_sizes));
187 }
188
189 static u64 gen8_pte_encode(dma_addr_t addr,
190                            enum i915_cache_level level,
191                            u32 flags)
192 {
193         gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
194
195         if (unlikely(flags & PTE_READ_ONLY))
196                 pte &= ~_PAGE_RW;
197
198         switch (level) {
199         case I915_CACHE_NONE:
200                 pte |= PPAT_UNCACHED;
201                 break;
202         case I915_CACHE_WT:
203                 pte |= PPAT_DISPLAY_ELLC;
204                 break;
205         default:
206                 pte |= PPAT_CACHED;
207                 break;
208         }
209
210         return pte;
211 }
212
213 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
214                                   const enum i915_cache_level level)
215 {
216         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
217         pde |= addr;
218         if (level != I915_CACHE_NONE)
219                 pde |= PPAT_CACHED_PDE;
220         else
221                 pde |= PPAT_UNCACHED;
222         return pde;
223 }
224
225 #define gen8_pdpe_encode gen8_pde_encode
226 #define gen8_pml4e_encode gen8_pde_encode
227
228 static u64 snb_pte_encode(dma_addr_t addr,
229                           enum i915_cache_level level,
230                           u32 flags)
231 {
232         gen6_pte_t pte = GEN6_PTE_VALID;
233         pte |= GEN6_PTE_ADDR_ENCODE(addr);
234
235         switch (level) {
236         case I915_CACHE_L3_LLC:
237         case I915_CACHE_LLC:
238                 pte |= GEN6_PTE_CACHE_LLC;
239                 break;
240         case I915_CACHE_NONE:
241                 pte |= GEN6_PTE_UNCACHED;
242                 break;
243         default:
244                 MISSING_CASE(level);
245         }
246
247         return pte;
248 }
249
250 static u64 ivb_pte_encode(dma_addr_t addr,
251                           enum i915_cache_level level,
252                           u32 flags)
253 {
254         gen6_pte_t pte = GEN6_PTE_VALID;
255         pte |= GEN6_PTE_ADDR_ENCODE(addr);
256
257         switch (level) {
258         case I915_CACHE_L3_LLC:
259                 pte |= GEN7_PTE_CACHE_L3_LLC;
260                 break;
261         case I915_CACHE_LLC:
262                 pte |= GEN6_PTE_CACHE_LLC;
263                 break;
264         case I915_CACHE_NONE:
265                 pte |= GEN6_PTE_UNCACHED;
266                 break;
267         default:
268                 MISSING_CASE(level);
269         }
270
271         return pte;
272 }
273
274 static u64 byt_pte_encode(dma_addr_t addr,
275                           enum i915_cache_level level,
276                           u32 flags)
277 {
278         gen6_pte_t pte = GEN6_PTE_VALID;
279         pte |= GEN6_PTE_ADDR_ENCODE(addr);
280
281         if (!(flags & PTE_READ_ONLY))
282                 pte |= BYT_PTE_WRITEABLE;
283
284         if (level != I915_CACHE_NONE)
285                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
286
287         return pte;
288 }
289
290 static u64 hsw_pte_encode(dma_addr_t addr,
291                           enum i915_cache_level level,
292                           u32 flags)
293 {
294         gen6_pte_t pte = GEN6_PTE_VALID;
295         pte |= HSW_PTE_ADDR_ENCODE(addr);
296
297         if (level != I915_CACHE_NONE)
298                 pte |= HSW_WB_LLC_AGE3;
299
300         return pte;
301 }
302
303 static u64 iris_pte_encode(dma_addr_t addr,
304                            enum i915_cache_level level,
305                            u32 flags)
306 {
307         gen6_pte_t pte = GEN6_PTE_VALID;
308         pte |= HSW_PTE_ADDR_ENCODE(addr);
309
310         switch (level) {
311         case I915_CACHE_NONE:
312                 break;
313         case I915_CACHE_WT:
314                 pte |= HSW_WT_ELLC_LLC_AGE3;
315                 break;
316         default:
317                 pte |= HSW_WB_ELLC_LLC_AGE3;
318                 break;
319         }
320
321         return pte;
322 }
323
324 static void stash_init(struct pagestash *stash)
325 {
326         pagevec_init(&stash->pvec);
327         spin_lock_init(&stash->lock);
328 }
329
330 static struct page *stash_pop_page(struct pagestash *stash)
331 {
332         struct page *page = NULL;
333
334         spin_lock(&stash->lock);
335         if (likely(stash->pvec.nr))
336                 page = stash->pvec.pages[--stash->pvec.nr];
337         spin_unlock(&stash->lock);
338
339         return page;
340 }
341
342 static void stash_push_pagevec(struct pagestash *stash, struct pagevec *pvec)
343 {
344         int nr;
345
346         spin_lock_nested(&stash->lock, SINGLE_DEPTH_NESTING);
347
348         nr = min_t(int, pvec->nr, pagevec_space(&stash->pvec));
349         memcpy(stash->pvec.pages + stash->pvec.nr,
350                pvec->pages + pvec->nr - nr,
351                sizeof(pvec->pages[0]) * nr);
352         stash->pvec.nr += nr;
353
354         spin_unlock(&stash->lock);
355
356         pvec->nr -= nr;
357 }
358
359 static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
360 {
361         struct pagevec stack;
362         struct page *page;
363
364         if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
365                 i915_gem_shrink_all(vm->i915);
366
367         page = stash_pop_page(&vm->free_pages);
368         if (page)
369                 return page;
370
371         if (!vm->pt_kmap_wc)
372                 return alloc_page(gfp);
373
374         /* Look in our global stash of WC pages... */
375         page = stash_pop_page(&vm->i915->mm.wc_stash);
376         if (page)
377                 return page;
378
379         /*
380          * Otherwise batch allocate pages to amortize cost of set_pages_wc.
381          *
382          * We have to be careful as page allocation may trigger the shrinker
383          * (via direct reclaim) which will fill up the WC stash underneath us.
384          * So we add our WB pages into a temporary pvec on the stack and merge
385          * them into the WC stash after all the allocations are complete.
386          */
387         pagevec_init(&stack);
388         do {
389                 struct page *page;
390
391                 page = alloc_page(gfp);
392                 if (unlikely(!page))
393                         break;
394
395                 stack.pages[stack.nr++] = page;
396         } while (pagevec_space(&stack));
397
398         if (stack.nr && !set_pages_array_wc(stack.pages, stack.nr)) {
399                 page = stack.pages[--stack.nr];
400
401                 /* Merge spare WC pages to the global stash */
402                 stash_push_pagevec(&vm->i915->mm.wc_stash, &stack);
403
404                 /* Push any surplus WC pages onto the local VM stash */
405                 if (stack.nr)
406                         stash_push_pagevec(&vm->free_pages, &stack);
407         }
408
409         /* Return unwanted leftovers */
410         if (unlikely(stack.nr)) {
411                 WARN_ON_ONCE(set_pages_array_wb(stack.pages, stack.nr));
412                 __pagevec_release(&stack);
413         }
414
415         return page;
416 }
417
418 static void vm_free_pages_release(struct i915_address_space *vm,
419                                   bool immediate)
420 {
421         struct pagevec *pvec = &vm->free_pages.pvec;
422         struct pagevec stack;
423
424         lockdep_assert_held(&vm->free_pages.lock);
425         GEM_BUG_ON(!pagevec_count(pvec));
426
427         if (vm->pt_kmap_wc) {
428                 /*
429                  * When we use WC, first fill up the global stash and then
430                  * only if full immediately free the overflow.
431                  */
432                 stash_push_pagevec(&vm->i915->mm.wc_stash, pvec);
433
434                 /*
435                  * As we have made some room in the VM's free_pages,
436                  * we can wait for it to fill again. Unless we are
437                  * inside i915_address_space_fini() and must
438                  * immediately release the pages!
439                  */
440                 if (pvec->nr <= (immediate ? 0 : PAGEVEC_SIZE - 1))
441                         return;
442
443                 /*
444                  * We have to drop the lock to allow ourselves to sleep,
445                  * so take a copy of the pvec and clear the stash for
446                  * others to use it as we sleep.
447                  */
448                 stack = *pvec;
449                 pagevec_reinit(pvec);
450                 spin_unlock(&vm->free_pages.lock);
451
452                 pvec = &stack;
453                 set_pages_array_wb(pvec->pages, pvec->nr);
454
455                 spin_lock(&vm->free_pages.lock);
456         }
457
458         __pagevec_release(pvec);
459 }
460
461 static void vm_free_page(struct i915_address_space *vm, struct page *page)
462 {
463         /*
464          * On !llc, we need to change the pages back to WB. We only do so
465          * in bulk, so we rarely need to change the page attributes here,
466          * but doing so requires a stop_machine() from deep inside arch/x86/mm.
467          * To make detection of the possible sleep more likely, use an
468          * unconditional might_sleep() for everybody.
469          */
470         might_sleep();
471         spin_lock(&vm->free_pages.lock);
472         if (!pagevec_add(&vm->free_pages.pvec, page))
473                 vm_free_pages_release(vm, false);
474         spin_unlock(&vm->free_pages.lock);
475 }
476
477 static void i915_address_space_init(struct i915_address_space *vm, int subclass)
478 {
479         /*
480          * The vm->mutex must be reclaim safe (for use in the shrinker).
481          * Do a dummy acquire now under fs_reclaim so that any allocation
482          * attempt holding the lock is immediately reported by lockdep.
483          */
484         mutex_init(&vm->mutex);
485         lockdep_set_subclass(&vm->mutex, subclass);
486         i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex);
487
488         GEM_BUG_ON(!vm->total);
489         drm_mm_init(&vm->mm, 0, vm->total);
490         vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
491
492         stash_init(&vm->free_pages);
493
494         INIT_LIST_HEAD(&vm->unbound_list);
495         INIT_LIST_HEAD(&vm->bound_list);
496 }
497
498 static void i915_address_space_fini(struct i915_address_space *vm)
499 {
500         spin_lock(&vm->free_pages.lock);
501         if (pagevec_count(&vm->free_pages.pvec))
502                 vm_free_pages_release(vm, true);
503         GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec));
504         spin_unlock(&vm->free_pages.lock);
505
506         drm_mm_takedown(&vm->mm);
507
508         mutex_destroy(&vm->mutex);
509 }
510
511 static int __setup_page_dma(struct i915_address_space *vm,
512                             struct i915_page_dma *p,
513                             gfp_t gfp)
514 {
515         p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL);
516         if (unlikely(!p->page))
517                 return -ENOMEM;
518
519         p->daddr = dma_map_page_attrs(vm->dma,
520                                       p->page, 0, PAGE_SIZE,
521                                       PCI_DMA_BIDIRECTIONAL,
522                                       DMA_ATTR_SKIP_CPU_SYNC |
523                                       DMA_ATTR_NO_WARN);
524         if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
525                 vm_free_page(vm, p->page);
526                 return -ENOMEM;
527         }
528
529         return 0;
530 }
531
532 static int setup_page_dma(struct i915_address_space *vm,
533                           struct i915_page_dma *p)
534 {
535         return __setup_page_dma(vm, p, __GFP_HIGHMEM);
536 }
537
538 static void cleanup_page_dma(struct i915_address_space *vm,
539                              struct i915_page_dma *p)
540 {
541         dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
542         vm_free_page(vm, p->page);
543 }
544
545 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
546
547 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
548 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
549 #define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
550 #define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
551
552 static void fill_page_dma(struct i915_address_space *vm,
553                           struct i915_page_dma *p,
554                           const u64 val)
555 {
556         u64 * const vaddr = kmap_atomic(p->page);
557
558         memset64(vaddr, val, PAGE_SIZE / sizeof(val));
559
560         kunmap_atomic(vaddr);
561 }
562
563 static void fill_page_dma_32(struct i915_address_space *vm,
564                              struct i915_page_dma *p,
565                              const u32 v)
566 {
567         fill_page_dma(vm, p, (u64)v << 32 | v);
568 }
569
570 static int
571 setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
572 {
573         unsigned long size;
574
575         /*
576          * In order to utilize 64K pages for an object with a size < 2M, we will
577          * need to support a 64K scratch page, given that every 16th entry for a
578          * page-table operating in 64K mode must point to a properly aligned 64K
579          * region, including any PTEs which happen to point to scratch.
580          *
581          * This is only relevant for the 48b PPGTT where we support
582          * huge-gtt-pages, see also i915_vma_insert(). However, as we share the
583          * scratch (read-only) between all vm, we create one 64k scratch page
584          * for all.
585          */
586         size = I915_GTT_PAGE_SIZE_4K;
587         if (i915_vm_is_4lvl(vm) &&
588             HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) {
589                 size = I915_GTT_PAGE_SIZE_64K;
590                 gfp |= __GFP_NOWARN;
591         }
592         gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL;
593
594         do {
595                 int order = get_order(size);
596                 struct page *page;
597                 dma_addr_t addr;
598
599                 page = alloc_pages(gfp, order);
600                 if (unlikely(!page))
601                         goto skip;
602
603                 addr = dma_map_page_attrs(vm->dma,
604                                           page, 0, size,
605                                           PCI_DMA_BIDIRECTIONAL,
606                                           DMA_ATTR_SKIP_CPU_SYNC |
607                                           DMA_ATTR_NO_WARN);
608                 if (unlikely(dma_mapping_error(vm->dma, addr)))
609                         goto free_page;
610
611                 if (unlikely(!IS_ALIGNED(addr, size)))
612                         goto unmap_page;
613
614                 vm->scratch_page.page = page;
615                 vm->scratch_page.daddr = addr;
616                 vm->scratch_order = order;
617                 return 0;
618
619 unmap_page:
620                 dma_unmap_page(vm->dma, addr, size, PCI_DMA_BIDIRECTIONAL);
621 free_page:
622                 __free_pages(page, order);
623 skip:
624                 if (size == I915_GTT_PAGE_SIZE_4K)
625                         return -ENOMEM;
626
627                 size = I915_GTT_PAGE_SIZE_4K;
628                 gfp &= ~__GFP_NOWARN;
629         } while (1);
630 }
631
632 static void cleanup_scratch_page(struct i915_address_space *vm)
633 {
634         struct i915_page_dma *p = &vm->scratch_page;
635         int order = vm->scratch_order;
636
637         dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT,
638                        PCI_DMA_BIDIRECTIONAL);
639         __free_pages(p->page, order);
640 }
641
642 static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
643 {
644         struct i915_page_table *pt;
645
646         pt = kmalloc(sizeof(*pt), I915_GFP_ALLOW_FAIL);
647         if (unlikely(!pt))
648                 return ERR_PTR(-ENOMEM);
649
650         if (unlikely(setup_px(vm, pt))) {
651                 kfree(pt);
652                 return ERR_PTR(-ENOMEM);
653         }
654
655         pt->used_ptes = 0;
656         return pt;
657 }
658
659 static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
660 {
661         cleanup_px(vm, pt);
662         kfree(pt);
663 }
664
665 static void gen8_initialize_pt(struct i915_address_space *vm,
666                                struct i915_page_table *pt)
667 {
668         fill_px(vm, pt, vm->scratch_pte);
669 }
670
671 static void gen6_initialize_pt(struct i915_address_space *vm,
672                                struct i915_page_table *pt)
673 {
674         fill32_px(vm, pt, vm->scratch_pte);
675 }
676
677 static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
678 {
679         struct i915_page_directory *pd;
680
681         pd = kzalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
682         if (unlikely(!pd))
683                 return ERR_PTR(-ENOMEM);
684
685         if (unlikely(setup_px(vm, pd))) {
686                 kfree(pd);
687                 return ERR_PTR(-ENOMEM);
688         }
689
690         pd->used_pdes = 0;
691         return pd;
692 }
693
694 static void free_pd(struct i915_address_space *vm,
695                     struct i915_page_directory *pd)
696 {
697         cleanup_px(vm, pd);
698         kfree(pd);
699 }
700
701 static void gen8_initialize_pd(struct i915_address_space *vm,
702                                struct i915_page_directory *pd)
703 {
704         fill_px(vm, pd,
705                 gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC));
706         memset_p((void **)pd->page_table, vm->scratch_pt, I915_PDES);
707 }
708
709 static int __pdp_init(struct i915_address_space *vm,
710                       struct i915_page_directory_pointer *pdp)
711 {
712         const unsigned int pdpes = i915_pdpes_per_pdp(vm);
713
714         pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
715                                             I915_GFP_ALLOW_FAIL);
716         if (unlikely(!pdp->page_directory))
717                 return -ENOMEM;
718
719         memset_p((void **)pdp->page_directory, vm->scratch_pd, pdpes);
720
721         return 0;
722 }
723
724 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
725 {
726         kfree(pdp->page_directory);
727         pdp->page_directory = NULL;
728 }
729
730 static struct i915_page_directory_pointer *
731 alloc_pdp(struct i915_address_space *vm)
732 {
733         struct i915_page_directory_pointer *pdp;
734         int ret = -ENOMEM;
735
736         GEM_BUG_ON(!i915_vm_is_4lvl(vm));
737
738         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
739         if (!pdp)
740                 return ERR_PTR(-ENOMEM);
741
742         ret = __pdp_init(vm, pdp);
743         if (ret)
744                 goto fail_bitmap;
745
746         ret = setup_px(vm, pdp);
747         if (ret)
748                 goto fail_page_m;
749
750         return pdp;
751
752 fail_page_m:
753         __pdp_fini(pdp);
754 fail_bitmap:
755         kfree(pdp);
756
757         return ERR_PTR(ret);
758 }
759
760 static void free_pdp(struct i915_address_space *vm,
761                      struct i915_page_directory_pointer *pdp)
762 {
763         __pdp_fini(pdp);
764
765         if (!i915_vm_is_4lvl(vm))
766                 return;
767
768         cleanup_px(vm, pdp);
769         kfree(pdp);
770 }
771
772 static void gen8_initialize_pdp(struct i915_address_space *vm,
773                                 struct i915_page_directory_pointer *pdp)
774 {
775         gen8_ppgtt_pdpe_t scratch_pdpe;
776
777         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
778
779         fill_px(vm, pdp, scratch_pdpe);
780 }
781
782 static void gen8_initialize_pml4(struct i915_address_space *vm,
783                                  struct i915_pml4 *pml4)
784 {
785         fill_px(vm, pml4,
786                 gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC));
787         memset_p((void **)pml4->pdps, vm->scratch_pdp, GEN8_PML4ES_PER_PML4);
788 }
789
790 /*
791  * PDE TLBs are a pain to invalidate on GEN8+. When we modify
792  * the page table structures, we mark them dirty so that
793  * context switching/execlist queuing code takes extra steps
794  * to ensure that tlbs are flushed.
795  */
796 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
797 {
798         ppgtt->pd_dirty_engines = ALL_ENGINES;
799 }
800
801 /* Removes entries from a single page table, releasing it if it's empty.
802  * Caller can use the return value to update higher-level entries.
803  */
804 static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
805                                 struct i915_page_table *pt,
806                                 u64 start, u64 length)
807 {
808         unsigned int num_entries = gen8_pte_count(start, length);
809         gen8_pte_t *vaddr;
810
811         GEM_BUG_ON(num_entries > pt->used_ptes);
812
813         pt->used_ptes -= num_entries;
814         if (!pt->used_ptes)
815                 return true;
816
817         vaddr = kmap_atomic_px(pt);
818         memset64(vaddr + gen8_pte_index(start), vm->scratch_pte, num_entries);
819         kunmap_atomic(vaddr);
820
821         return false;
822 }
823
824 static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
825                                struct i915_page_directory *pd,
826                                struct i915_page_table *pt,
827                                unsigned int pde)
828 {
829         gen8_pde_t *vaddr;
830
831         pd->page_table[pde] = pt;
832
833         vaddr = kmap_atomic_px(pd);
834         vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
835         kunmap_atomic(vaddr);
836 }
837
838 static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
839                                 struct i915_page_directory *pd,
840                                 u64 start, u64 length)
841 {
842         struct i915_page_table *pt;
843         u32 pde;
844
845         gen8_for_each_pde(pt, pd, start, length, pde) {
846                 GEM_BUG_ON(pt == vm->scratch_pt);
847
848                 if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
849                         continue;
850
851                 gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde);
852                 GEM_BUG_ON(!pd->used_pdes);
853                 pd->used_pdes--;
854
855                 free_pt(vm, pt);
856         }
857
858         return !pd->used_pdes;
859 }
860
861 static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
862                                 struct i915_page_directory_pointer *pdp,
863                                 struct i915_page_directory *pd,
864                                 unsigned int pdpe)
865 {
866         gen8_ppgtt_pdpe_t *vaddr;
867
868         pdp->page_directory[pdpe] = pd;
869         if (!i915_vm_is_4lvl(vm))
870                 return;
871
872         vaddr = kmap_atomic_px(pdp);
873         vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
874         kunmap_atomic(vaddr);
875 }
876
877 /* Removes entries from a single page dir pointer, releasing it if it's empty.
878  * Caller can use the return value to update higher-level entries
879  */
880 static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
881                                  struct i915_page_directory_pointer *pdp,
882                                  u64 start, u64 length)
883 {
884         struct i915_page_directory *pd;
885         unsigned int pdpe;
886
887         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
888                 GEM_BUG_ON(pd == vm->scratch_pd);
889
890                 if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
891                         continue;
892
893                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
894                 GEM_BUG_ON(!pdp->used_pdpes);
895                 pdp->used_pdpes--;
896
897                 free_pd(vm, pd);
898         }
899
900         return !pdp->used_pdpes;
901 }
902
903 static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
904                                   u64 start, u64 length)
905 {
906         gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length);
907 }
908
909 static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
910                                  struct i915_page_directory_pointer *pdp,
911                                  unsigned int pml4e)
912 {
913         gen8_ppgtt_pml4e_t *vaddr;
914
915         pml4->pdps[pml4e] = pdp;
916
917         vaddr = kmap_atomic_px(pml4);
918         vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
919         kunmap_atomic(vaddr);
920 }
921
922 /* Removes entries from a single pml4.
923  * This is the top-level structure in 4-level page tables used on gen8+.
924  * Empty entries are always scratch pml4e.
925  */
926 static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
927                                   u64 start, u64 length)
928 {
929         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
930         struct i915_pml4 *pml4 = &ppgtt->pml4;
931         struct i915_page_directory_pointer *pdp;
932         unsigned int pml4e;
933
934         GEM_BUG_ON(!i915_vm_is_4lvl(vm));
935
936         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
937                 GEM_BUG_ON(pdp == vm->scratch_pdp);
938
939                 if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length))
940                         continue;
941
942                 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
943
944                 free_pdp(vm, pdp);
945         }
946 }
947
948 static inline struct sgt_dma {
949         struct scatterlist *sg;
950         dma_addr_t dma, max;
951 } sgt_dma(struct i915_vma *vma) {
952         struct scatterlist *sg = vma->pages->sgl;
953         dma_addr_t addr = sg_dma_address(sg);
954         return (struct sgt_dma) { sg, addr, addr + sg->length };
955 }
956
957 struct gen8_insert_pte {
958         u16 pml4e;
959         u16 pdpe;
960         u16 pde;
961         u16 pte;
962 };
963
964 static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
965 {
966         return (struct gen8_insert_pte) {
967                  gen8_pml4e_index(start),
968                  gen8_pdpe_index(start),
969                  gen8_pde_index(start),
970                  gen8_pte_index(start),
971         };
972 }
973
974 static __always_inline bool
975 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
976                               struct i915_page_directory_pointer *pdp,
977                               struct sgt_dma *iter,
978                               struct gen8_insert_pte *idx,
979                               enum i915_cache_level cache_level,
980                               u32 flags)
981 {
982         struct i915_page_directory *pd;
983         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
984         gen8_pte_t *vaddr;
985         bool ret;
986
987         GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
988         pd = pdp->page_directory[idx->pdpe];
989         vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
990         do {
991                 vaddr[idx->pte] = pte_encode | iter->dma;
992
993                 iter->dma += I915_GTT_PAGE_SIZE;
994                 if (iter->dma >= iter->max) {
995                         iter->sg = __sg_next(iter->sg);
996                         if (!iter->sg) {
997                                 ret = false;
998                                 break;
999                         }
1000
1001                         iter->dma = sg_dma_address(iter->sg);
1002                         iter->max = iter->dma + iter->sg->length;
1003                 }
1004
1005                 if (++idx->pte == GEN8_PTES) {
1006                         idx->pte = 0;
1007
1008                         if (++idx->pde == I915_PDES) {
1009                                 idx->pde = 0;
1010
1011                                 /* Limited by sg length for 3lvl */
1012                                 if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
1013                                         idx->pdpe = 0;
1014                                         ret = true;
1015                                         break;
1016                                 }
1017
1018                                 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
1019                                 pd = pdp->page_directory[idx->pdpe];
1020                         }
1021
1022                         kunmap_atomic(vaddr);
1023                         vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
1024                 }
1025         } while (1);
1026         kunmap_atomic(vaddr);
1027
1028         return ret;
1029 }
1030
1031 static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
1032                                    struct i915_vma *vma,
1033                                    enum i915_cache_level cache_level,
1034                                    u32 flags)
1035 {
1036         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1037         struct sgt_dma iter = sgt_dma(vma);
1038         struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
1039
1040         gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
1041                                       cache_level, flags);
1042
1043         vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1044 }
1045
1046 static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
1047                                            struct i915_page_directory_pointer **pdps,
1048                                            struct sgt_dma *iter,
1049                                            enum i915_cache_level cache_level,
1050                                            u32 flags)
1051 {
1052         const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
1053         u64 start = vma->node.start;
1054         dma_addr_t rem = iter->sg->length;
1055
1056         do {
1057                 struct gen8_insert_pte idx = gen8_insert_pte(start);
1058                 struct i915_page_directory_pointer *pdp = pdps[idx.pml4e];
1059                 struct i915_page_directory *pd = pdp->page_directory[idx.pdpe];
1060                 unsigned int page_size;
1061                 bool maybe_64K = false;
1062                 gen8_pte_t encode = pte_encode;
1063                 gen8_pte_t *vaddr;
1064                 u16 index, max;
1065
1066                 if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
1067                     IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
1068                     rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
1069                         index = idx.pde;
1070                         max = I915_PDES;
1071                         page_size = I915_GTT_PAGE_SIZE_2M;
1072
1073                         encode |= GEN8_PDE_PS_2M;
1074
1075                         vaddr = kmap_atomic_px(pd);
1076                 } else {
1077                         struct i915_page_table *pt = pd->page_table[idx.pde];
1078
1079                         index = idx.pte;
1080                         max = GEN8_PTES;
1081                         page_size = I915_GTT_PAGE_SIZE;
1082
1083                         if (!index &&
1084                             vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
1085                             IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
1086                             (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
1087                              rem >= (max - index) * I915_GTT_PAGE_SIZE))
1088                                 maybe_64K = true;
1089
1090                         vaddr = kmap_atomic_px(pt);
1091                 }
1092
1093                 do {
1094                         GEM_BUG_ON(iter->sg->length < page_size);
1095                         vaddr[index++] = encode | iter->dma;
1096
1097                         start += page_size;
1098                         iter->dma += page_size;
1099                         rem -= page_size;
1100                         if (iter->dma >= iter->max) {
1101                                 iter->sg = __sg_next(iter->sg);
1102                                 if (!iter->sg)
1103                                         break;
1104
1105                                 rem = iter->sg->length;
1106                                 iter->dma = sg_dma_address(iter->sg);
1107                                 iter->max = iter->dma + rem;
1108
1109                                 if (maybe_64K && index < max &&
1110                                     !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
1111                                       (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
1112                                        rem >= (max - index) * I915_GTT_PAGE_SIZE)))
1113                                         maybe_64K = false;
1114
1115                                 if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
1116                                         break;
1117                         }
1118                 } while (rem >= page_size && index < max);
1119
1120                 kunmap_atomic(vaddr);
1121
1122                 /*
1123                  * Is it safe to mark the 2M block as 64K? -- Either we have
1124                  * filled whole page-table with 64K entries, or filled part of
1125                  * it and have reached the end of the sg table and we have
1126                  * enough padding.
1127                  */
1128                 if (maybe_64K &&
1129                     (index == max ||
1130                      (i915_vm_has_scratch_64K(vma->vm) &&
1131                       !iter->sg && IS_ALIGNED(vma->node.start +
1132                                               vma->node.size,
1133                                               I915_GTT_PAGE_SIZE_2M)))) {
1134                         vaddr = kmap_atomic_px(pd);
1135                         vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
1136                         kunmap_atomic(vaddr);
1137                         page_size = I915_GTT_PAGE_SIZE_64K;
1138
1139                         /*
1140                          * We write all 4K page entries, even when using 64K
1141                          * pages. In order to verify that the HW isn't cheating
1142                          * by using the 4K PTE instead of the 64K PTE, we want
1143                          * to remove all the surplus entries. If the HW skipped
1144                          * the 64K PTE, it will read/write into the scratch page
1145                          * instead - which we detect as missing results during
1146                          * selftests.
1147                          */
1148                         if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
1149                                 u16 i;
1150
1151                                 encode = vma->vm->scratch_pte;
1152                                 vaddr = kmap_atomic_px(pd->page_table[idx.pde]);
1153
1154                                 for (i = 1; i < index; i += 16)
1155                                         memset64(vaddr + i, encode, 15);
1156
1157                                 kunmap_atomic(vaddr);
1158                         }
1159                 }
1160
1161                 vma->page_sizes.gtt |= page_size;
1162         } while (iter->sg);
1163 }
1164
1165 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
1166                                    struct i915_vma *vma,
1167                                    enum i915_cache_level cache_level,
1168                                    u32 flags)
1169 {
1170         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1171         struct sgt_dma iter = sgt_dma(vma);
1172         struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
1173
1174         if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
1175                 gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level,
1176                                                flags);
1177         } else {
1178                 struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
1179
1180                 while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
1181                                                      &iter, &idx, cache_level,
1182                                                      flags))
1183                         GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
1184
1185                 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1186         }
1187 }
1188
1189 static void gen8_free_page_tables(struct i915_address_space *vm,
1190                                   struct i915_page_directory *pd)
1191 {
1192         int i;
1193
1194         for (i = 0; i < I915_PDES; i++) {
1195                 if (pd->page_table[i] != vm->scratch_pt)
1196                         free_pt(vm, pd->page_table[i]);
1197         }
1198 }
1199
1200 static int gen8_init_scratch(struct i915_address_space *vm)
1201 {
1202         int ret;
1203
1204         /*
1205          * If everybody agrees to not to write into the scratch page,
1206          * we can reuse it for all vm, keeping contexts and processes separate.
1207          */
1208         if (vm->has_read_only &&
1209             vm->i915->kernel_context &&
1210             vm->i915->kernel_context->ppgtt) {
1211                 struct i915_address_space *clone =
1212                         &vm->i915->kernel_context->ppgtt->vm;
1213
1214                 GEM_BUG_ON(!clone->has_read_only);
1215
1216                 vm->scratch_order = clone->scratch_order;
1217                 vm->scratch_pte = clone->scratch_pte;
1218                 vm->scratch_pt  = clone->scratch_pt;
1219                 vm->scratch_pd  = clone->scratch_pd;
1220                 vm->scratch_pdp = clone->scratch_pdp;
1221                 return 0;
1222         }
1223
1224         ret = setup_scratch_page(vm, __GFP_HIGHMEM);
1225         if (ret)
1226                 return ret;
1227
1228         vm->scratch_pte =
1229                 gen8_pte_encode(vm->scratch_page.daddr,
1230                                 I915_CACHE_LLC,
1231                                 PTE_READ_ONLY);
1232
1233         vm->scratch_pt = alloc_pt(vm);
1234         if (IS_ERR(vm->scratch_pt)) {
1235                 ret = PTR_ERR(vm->scratch_pt);
1236                 goto free_scratch_page;
1237         }
1238
1239         vm->scratch_pd = alloc_pd(vm);
1240         if (IS_ERR(vm->scratch_pd)) {
1241                 ret = PTR_ERR(vm->scratch_pd);
1242                 goto free_pt;
1243         }
1244
1245         if (i915_vm_is_4lvl(vm)) {
1246                 vm->scratch_pdp = alloc_pdp(vm);
1247                 if (IS_ERR(vm->scratch_pdp)) {
1248                         ret = PTR_ERR(vm->scratch_pdp);
1249                         goto free_pd;
1250                 }
1251         }
1252
1253         gen8_initialize_pt(vm, vm->scratch_pt);
1254         gen8_initialize_pd(vm, vm->scratch_pd);
1255         if (i915_vm_is_4lvl(vm))
1256                 gen8_initialize_pdp(vm, vm->scratch_pdp);
1257
1258         return 0;
1259
1260 free_pd:
1261         free_pd(vm, vm->scratch_pd);
1262 free_pt:
1263         free_pt(vm, vm->scratch_pt);
1264 free_scratch_page:
1265         cleanup_scratch_page(vm);
1266
1267         return ret;
1268 }
1269
1270 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
1271 {
1272         struct i915_address_space *vm = &ppgtt->vm;
1273         struct drm_i915_private *dev_priv = vm->i915;
1274         enum vgt_g2v_type msg;
1275         int i;
1276
1277         if (i915_vm_is_4lvl(vm)) {
1278                 const u64 daddr = px_dma(&ppgtt->pml4);
1279
1280                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
1281                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
1282
1283                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
1284                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
1285         } else {
1286                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1287                         const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
1288
1289                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
1290                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
1291                 }
1292
1293                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
1294                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
1295         }
1296
1297         I915_WRITE(vgtif_reg(g2v_notify), msg);
1298
1299         return 0;
1300 }
1301
1302 static void gen8_free_scratch(struct i915_address_space *vm)
1303 {
1304         if (!vm->scratch_page.daddr)
1305                 return;
1306
1307         if (i915_vm_is_4lvl(vm))
1308                 free_pdp(vm, vm->scratch_pdp);
1309         free_pd(vm, vm->scratch_pd);
1310         free_pt(vm, vm->scratch_pt);
1311         cleanup_scratch_page(vm);
1312 }
1313
1314 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
1315                                     struct i915_page_directory_pointer *pdp)
1316 {
1317         const unsigned int pdpes = i915_pdpes_per_pdp(vm);
1318         int i;
1319
1320         for (i = 0; i < pdpes; i++) {
1321                 if (pdp->page_directory[i] == vm->scratch_pd)
1322                         continue;
1323
1324                 gen8_free_page_tables(vm, pdp->page_directory[i]);
1325                 free_pd(vm, pdp->page_directory[i]);
1326         }
1327
1328         free_pdp(vm, pdp);
1329 }
1330
1331 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
1332 {
1333         int i;
1334
1335         for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
1336                 if (ppgtt->pml4.pdps[i] == ppgtt->vm.scratch_pdp)
1337                         continue;
1338
1339                 gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, ppgtt->pml4.pdps[i]);
1340         }
1341
1342         cleanup_px(&ppgtt->vm, &ppgtt->pml4);
1343 }
1344
1345 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
1346 {
1347         struct drm_i915_private *dev_priv = vm->i915;
1348         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1349
1350         if (intel_vgpu_active(dev_priv))
1351                 gen8_ppgtt_notify_vgt(ppgtt, false);
1352
1353         if (i915_vm_is_4lvl(vm))
1354                 gen8_ppgtt_cleanup_4lvl(ppgtt);
1355         else
1356                 gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, &ppgtt->pdp);
1357
1358         gen8_free_scratch(vm);
1359 }
1360
1361 static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
1362                                struct i915_page_directory *pd,
1363                                u64 start, u64 length)
1364 {
1365         struct i915_page_table *pt;
1366         u64 from = start;
1367         unsigned int pde;
1368
1369         gen8_for_each_pde(pt, pd, start, length, pde) {
1370                 int count = gen8_pte_count(start, length);
1371
1372                 if (pt == vm->scratch_pt) {
1373                         pd->used_pdes++;
1374
1375                         pt = alloc_pt(vm);
1376                         if (IS_ERR(pt)) {
1377                                 pd->used_pdes--;
1378                                 goto unwind;
1379                         }
1380
1381                         if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
1382                                 gen8_initialize_pt(vm, pt);
1383
1384                         gen8_ppgtt_set_pde(vm, pd, pt, pde);
1385                         GEM_BUG_ON(pd->used_pdes > I915_PDES);
1386                 }
1387
1388                 pt->used_ptes += count;
1389         }
1390         return 0;
1391
1392 unwind:
1393         gen8_ppgtt_clear_pd(vm, pd, from, start - from);
1394         return -ENOMEM;
1395 }
1396
1397 static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
1398                                 struct i915_page_directory_pointer *pdp,
1399                                 u64 start, u64 length)
1400 {
1401         struct i915_page_directory *pd;
1402         u64 from = start;
1403         unsigned int pdpe;
1404         int ret;
1405
1406         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1407                 if (pd == vm->scratch_pd) {
1408                         pdp->used_pdpes++;
1409
1410                         pd = alloc_pd(vm);
1411                         if (IS_ERR(pd)) {
1412                                 pdp->used_pdpes--;
1413                                 goto unwind;
1414                         }
1415
1416                         gen8_initialize_pd(vm, pd);
1417                         gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1418                         GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
1419                 }
1420
1421                 ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
1422                 if (unlikely(ret))
1423                         goto unwind_pd;
1424         }
1425
1426         return 0;
1427
1428 unwind_pd:
1429         if (!pd->used_pdes) {
1430                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1431                 GEM_BUG_ON(!pdp->used_pdpes);
1432                 pdp->used_pdpes--;
1433                 free_pd(vm, pd);
1434         }
1435 unwind:
1436         gen8_ppgtt_clear_pdp(vm, pdp, from, start - from);
1437         return -ENOMEM;
1438 }
1439
1440 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
1441                                  u64 start, u64 length)
1442 {
1443         return gen8_ppgtt_alloc_pdp(vm,
1444                                     &i915_vm_to_ppgtt(vm)->pdp, start, length);
1445 }
1446
1447 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
1448                                  u64 start, u64 length)
1449 {
1450         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1451         struct i915_pml4 *pml4 = &ppgtt->pml4;
1452         struct i915_page_directory_pointer *pdp;
1453         u64 from = start;
1454         u32 pml4e;
1455         int ret;
1456
1457         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1458                 if (pml4->pdps[pml4e] == vm->scratch_pdp) {
1459                         pdp = alloc_pdp(vm);
1460                         if (IS_ERR(pdp))
1461                                 goto unwind;
1462
1463                         gen8_initialize_pdp(vm, pdp);
1464                         gen8_ppgtt_set_pml4e(pml4, pdp, pml4e);
1465                 }
1466
1467                 ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length);
1468                 if (unlikely(ret))
1469                         goto unwind_pdp;
1470         }
1471
1472         return 0;
1473
1474 unwind_pdp:
1475         if (!pdp->used_pdpes) {
1476                 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
1477                 free_pdp(vm, pdp);
1478         }
1479 unwind:
1480         gen8_ppgtt_clear_4lvl(vm, from, start - from);
1481         return -ENOMEM;
1482 }
1483
1484 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
1485 {
1486         struct i915_address_space *vm = &ppgtt->vm;
1487         struct i915_page_directory_pointer *pdp = &ppgtt->pdp;
1488         struct i915_page_directory *pd;
1489         u64 start = 0, length = ppgtt->vm.total;
1490         u64 from = start;
1491         unsigned int pdpe;
1492
1493         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1494                 pd = alloc_pd(vm);
1495                 if (IS_ERR(pd))
1496                         goto unwind;
1497
1498                 gen8_initialize_pd(vm, pd);
1499                 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1500                 pdp->used_pdpes++;
1501         }
1502
1503         pdp->used_pdpes++; /* never remove */
1504         return 0;
1505
1506 unwind:
1507         start -= from;
1508         gen8_for_each_pdpe(pd, pdp, from, start, pdpe) {
1509                 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1510                 free_pd(vm, pd);
1511         }
1512         pdp->used_pdpes = 0;
1513         return -ENOMEM;
1514 }
1515
1516 static void ppgtt_init(struct drm_i915_private *i915,
1517                        struct i915_hw_ppgtt *ppgtt)
1518 {
1519         kref_init(&ppgtt->ref);
1520
1521         ppgtt->vm.i915 = i915;
1522         ppgtt->vm.dma = &i915->drm.pdev->dev;
1523         ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
1524
1525         i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
1526
1527         ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
1528         ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
1529         ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
1530         ppgtt->vm.vma_ops.clear_pages = clear_pages;
1531 }
1532
1533 /*
1534  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1535  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1536  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1537  * space.
1538  *
1539  */
1540 static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
1541 {
1542         struct i915_hw_ppgtt *ppgtt;
1543         int err;
1544
1545         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1546         if (!ppgtt)
1547                 return ERR_PTR(-ENOMEM);
1548
1549         ppgtt_init(i915, ppgtt);
1550
1551         /* From bdw, there is support for read-only pages in the PPGTT. */
1552         ppgtt->vm.has_read_only = true;
1553
1554         /* There are only few exceptions for gen >=6. chv and bxt.
1555          * And we are not sure about the latter so play safe for now.
1556          */
1557         if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915))
1558                 ppgtt->vm.pt_kmap_wc = true;
1559
1560         err = gen8_init_scratch(&ppgtt->vm);
1561         if (err)
1562                 goto err_free;
1563
1564         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1565                 err = setup_px(&ppgtt->vm, &ppgtt->pml4);
1566                 if (err)
1567                         goto err_scratch;
1568
1569                 gen8_initialize_pml4(&ppgtt->vm, &ppgtt->pml4);
1570
1571                 ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
1572                 ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
1573                 ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
1574         } else {
1575                 err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
1576                 if (err)
1577                         goto err_scratch;
1578
1579                 if (intel_vgpu_active(i915)) {
1580                         err = gen8_preallocate_top_level_pdp(ppgtt);
1581                         if (err) {
1582                                 __pdp_fini(&ppgtt->pdp);
1583                                 goto err_scratch;
1584                         }
1585                 }
1586
1587                 ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
1588                 ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
1589                 ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
1590         }
1591
1592         if (intel_vgpu_active(i915))
1593                 gen8_ppgtt_notify_vgt(ppgtt, true);
1594
1595         ppgtt->vm.cleanup = gen8_ppgtt_cleanup;
1596
1597         return ppgtt;
1598
1599 err_scratch:
1600         gen8_free_scratch(&ppgtt->vm);
1601 err_free:
1602         kfree(ppgtt);
1603         return ERR_PTR(err);
1604 }
1605
1606 /* Write pde (index) from the page directory @pd to the page table @pt */
1607 static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
1608                                   const unsigned int pde,
1609                                   const struct i915_page_table *pt)
1610 {
1611         /* Caller needs to make sure the write completes if necessary */
1612         iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
1613                   ppgtt->pd_addr + pde);
1614 }
1615
1616 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
1617 {
1618         struct intel_engine_cs *engine;
1619         u32 ecochk, ecobits;
1620         enum intel_engine_id id;
1621
1622         ecobits = I915_READ(GAC_ECO_BITS);
1623         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1624
1625         ecochk = I915_READ(GAM_ECOCHK);
1626         if (IS_HASWELL(dev_priv)) {
1627                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1628         } else {
1629                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1630                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1631         }
1632         I915_WRITE(GAM_ECOCHK, ecochk);
1633
1634         for_each_engine(engine, dev_priv, id) {
1635                 /* GFX_MODE is per-ring on gen7+ */
1636                 I915_WRITE(RING_MODE_GEN7(engine),
1637                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1638         }
1639 }
1640
1641 static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
1642 {
1643         u32 ecochk, gab_ctl, ecobits;
1644
1645         ecobits = I915_READ(GAC_ECO_BITS);
1646         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1647                    ECOBITS_PPGTT_CACHE64B);
1648
1649         gab_ctl = I915_READ(GAB_CTL);
1650         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1651
1652         ecochk = I915_READ(GAM_ECOCHK);
1653         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1654
1655         if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
1656                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1657 }
1658
1659 /* PPGTT support for Sandybdrige/Gen6 and later */
1660 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1661                                    u64 start, u64 length)
1662 {
1663         struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1664         unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
1665         unsigned int pde = first_entry / GEN6_PTES;
1666         unsigned int pte = first_entry % GEN6_PTES;
1667         unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
1668         const gen6_pte_t scratch_pte = vm->scratch_pte;
1669
1670         while (num_entries) {
1671                 struct i915_page_table *pt = ppgtt->base.pd.page_table[pde++];
1672                 const unsigned int count = min(num_entries, GEN6_PTES - pte);
1673                 gen6_pte_t *vaddr;
1674
1675                 GEM_BUG_ON(pt == vm->scratch_pt);
1676
1677                 num_entries -= count;
1678
1679                 GEM_BUG_ON(count > pt->used_ptes);
1680                 pt->used_ptes -= count;
1681                 if (!pt->used_ptes)
1682                         ppgtt->scan_for_unused_pt = true;
1683
1684                 /*
1685                  * Note that the hw doesn't support removing PDE on the fly
1686                  * (they are cached inside the context with no means to
1687                  * invalidate the cache), so we can only reset the PTE
1688                  * entries back to scratch.
1689                  */
1690
1691                 vaddr = kmap_atomic_px(pt);
1692                 memset32(vaddr + pte, scratch_pte, count);
1693                 kunmap_atomic(vaddr);
1694
1695                 pte = 0;
1696         }
1697 }
1698
1699 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1700                                       struct i915_vma *vma,
1701                                       enum i915_cache_level cache_level,
1702                                       u32 flags)
1703 {
1704         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1705         unsigned first_entry = vma->node.start / I915_GTT_PAGE_SIZE;
1706         unsigned act_pt = first_entry / GEN6_PTES;
1707         unsigned act_pte = first_entry % GEN6_PTES;
1708         const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
1709         struct sgt_dma iter = sgt_dma(vma);
1710         gen6_pte_t *vaddr;
1711
1712         GEM_BUG_ON(ppgtt->pd.page_table[act_pt] == vm->scratch_pt);
1713
1714         vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
1715         do {
1716                 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
1717
1718                 iter.dma += I915_GTT_PAGE_SIZE;
1719                 if (iter.dma == iter.max) {
1720                         iter.sg = __sg_next(iter.sg);
1721                         if (!iter.sg)
1722                                 break;
1723
1724                         iter.dma = sg_dma_address(iter.sg);
1725                         iter.max = iter.dma + iter.sg->length;
1726                 }
1727
1728                 if (++act_pte == GEN6_PTES) {
1729                         kunmap_atomic(vaddr);
1730                         vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]);
1731                         act_pte = 0;
1732                 }
1733         } while (1);
1734         kunmap_atomic(vaddr);
1735
1736         vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
1737 }
1738
1739 static int gen6_alloc_va_range(struct i915_address_space *vm,
1740                                u64 start, u64 length)
1741 {
1742         struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1743         struct i915_page_table *pt;
1744         u64 from = start;
1745         unsigned int pde;
1746         bool flush = false;
1747
1748         gen6_for_each_pde(pt, &ppgtt->base.pd, start, length, pde) {
1749                 const unsigned int count = gen6_pte_count(start, length);
1750
1751                 if (pt == vm->scratch_pt) {
1752                         pt = alloc_pt(vm);
1753                         if (IS_ERR(pt))
1754                                 goto unwind_out;
1755
1756                         gen6_initialize_pt(vm, pt);
1757                         ppgtt->base.pd.page_table[pde] = pt;
1758
1759                         if (i915_vma_is_bound(ppgtt->vma,
1760                                               I915_VMA_GLOBAL_BIND)) {
1761                                 gen6_write_pde(ppgtt, pde, pt);
1762                                 flush = true;
1763                         }
1764
1765                         GEM_BUG_ON(pt->used_ptes);
1766                 }
1767
1768                 pt->used_ptes += count;
1769         }
1770
1771         if (flush) {
1772                 mark_tlbs_dirty(&ppgtt->base);
1773                 gen6_ggtt_invalidate(ppgtt->base.vm.i915);
1774         }
1775
1776         return 0;
1777
1778 unwind_out:
1779         gen6_ppgtt_clear_range(vm, from, start - from);
1780         return -ENOMEM;
1781 }
1782
1783 static int gen6_ppgtt_init_scratch(struct gen6_hw_ppgtt *ppgtt)
1784 {
1785         struct i915_address_space * const vm = &ppgtt->base.vm;
1786         struct i915_page_table *unused;
1787         u32 pde;
1788         int ret;
1789
1790         ret = setup_scratch_page(vm, __GFP_HIGHMEM);
1791         if (ret)
1792                 return ret;
1793
1794         vm->scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1795                                          I915_CACHE_NONE,
1796                                          PTE_READ_ONLY);
1797
1798         vm->scratch_pt = alloc_pt(vm);
1799         if (IS_ERR(vm->scratch_pt)) {
1800                 cleanup_scratch_page(vm);
1801                 return PTR_ERR(vm->scratch_pt);
1802         }
1803
1804         gen6_initialize_pt(vm, vm->scratch_pt);
1805         gen6_for_all_pdes(unused, &ppgtt->base.pd, pde)
1806                 ppgtt->base.pd.page_table[pde] = vm->scratch_pt;
1807
1808         return 0;
1809 }
1810
1811 static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
1812 {
1813         free_pt(vm, vm->scratch_pt);
1814         cleanup_scratch_page(vm);
1815 }
1816
1817 static void gen6_ppgtt_free_pd(struct gen6_hw_ppgtt *ppgtt)
1818 {
1819         struct i915_page_table *pt;
1820         u32 pde;
1821
1822         gen6_for_all_pdes(pt, &ppgtt->base.pd, pde)
1823                 if (pt != ppgtt->base.vm.scratch_pt)
1824                         free_pt(&ppgtt->base.vm, pt);
1825 }
1826
1827 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1828 {
1829         struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
1830
1831         i915_vma_destroy(ppgtt->vma);
1832
1833         gen6_ppgtt_free_pd(ppgtt);
1834         gen6_ppgtt_free_scratch(vm);
1835 }
1836
1837 static int pd_vma_set_pages(struct i915_vma *vma)
1838 {
1839         vma->pages = ERR_PTR(-ENODEV);
1840         return 0;
1841 }
1842
1843 static void pd_vma_clear_pages(struct i915_vma *vma)
1844 {
1845         GEM_BUG_ON(!vma->pages);
1846
1847         vma->pages = NULL;
1848 }
1849
1850 static int pd_vma_bind(struct i915_vma *vma,
1851                        enum i915_cache_level cache_level,
1852                        u32 unused)
1853 {
1854         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
1855         struct gen6_hw_ppgtt *ppgtt = vma->private;
1856         u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE;
1857         struct i915_page_table *pt;
1858         unsigned int pde;
1859
1860         ppgtt->base.pd.base.ggtt_offset = ggtt_offset * sizeof(gen6_pte_t);
1861         ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset;
1862
1863         gen6_for_all_pdes(pt, &ppgtt->base.pd, pde)
1864                 gen6_write_pde(ppgtt, pde, pt);
1865
1866         mark_tlbs_dirty(&ppgtt->base);
1867         gen6_ggtt_invalidate(ppgtt->base.vm.i915);
1868
1869         return 0;
1870 }
1871
1872 static void pd_vma_unbind(struct i915_vma *vma)
1873 {
1874         struct gen6_hw_ppgtt *ppgtt = vma->private;
1875         struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt;
1876         struct i915_page_table *pt;
1877         unsigned int pde;
1878
1879         if (!ppgtt->scan_for_unused_pt)
1880                 return;
1881
1882         /* Free all no longer used page tables */
1883         gen6_for_all_pdes(pt, &ppgtt->base.pd, pde) {
1884                 if (pt->used_ptes || pt == scratch_pt)
1885                         continue;
1886
1887                 free_pt(&ppgtt->base.vm, pt);
1888                 ppgtt->base.pd.page_table[pde] = scratch_pt;
1889         }
1890
1891         ppgtt->scan_for_unused_pt = false;
1892 }
1893
1894 static const struct i915_vma_ops pd_vma_ops = {
1895         .set_pages = pd_vma_set_pages,
1896         .clear_pages = pd_vma_clear_pages,
1897         .bind_vma = pd_vma_bind,
1898         .unbind_vma = pd_vma_unbind,
1899 };
1900
1901 static struct i915_vma *pd_vma_create(struct gen6_hw_ppgtt *ppgtt, int size)
1902 {
1903         struct drm_i915_private *i915 = ppgtt->base.vm.i915;
1904         struct i915_ggtt *ggtt = &i915->ggtt;
1905         struct i915_vma *vma;
1906
1907         GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
1908         GEM_BUG_ON(size > ggtt->vm.total);
1909
1910         vma = i915_vma_alloc();
1911         if (!vma)
1912                 return ERR_PTR(-ENOMEM);
1913
1914         i915_active_init(i915, &vma->active, NULL);
1915         INIT_ACTIVE_REQUEST(&vma->last_fence);
1916
1917         vma->vm = &ggtt->vm;
1918         vma->ops = &pd_vma_ops;
1919         vma->private = ppgtt;
1920
1921         vma->size = size;
1922         vma->fence_size = size;
1923         vma->flags = I915_VMA_GGTT;
1924         vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */
1925
1926         INIT_LIST_HEAD(&vma->obj_link);
1927
1928         mutex_lock(&vma->vm->mutex);
1929         list_add(&vma->vm_link, &vma->vm->unbound_list);
1930         mutex_unlock(&vma->vm->mutex);
1931
1932         return vma;
1933 }
1934
1935 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
1936 {
1937         struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
1938         int err;
1939
1940         /*
1941          * Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
1942          * which will be pinned into every active context.
1943          * (When vma->pin_count becomes atomic, I expect we will naturally
1944          * need a larger, unpacked, type and kill this redundancy.)
1945          */
1946         if (ppgtt->pin_count++)
1947                 return 0;
1948
1949         /*
1950          * PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1951          * allocator works in address space sizes, so it's multiplied by page
1952          * size. We allocate at the top of the GTT to avoid fragmentation.
1953          */
1954         err = i915_vma_pin(ppgtt->vma,
1955                            0, GEN6_PD_ALIGN,
1956                            PIN_GLOBAL | PIN_HIGH);
1957         if (err)
1958                 goto unpin;
1959
1960         return 0;
1961
1962 unpin:
1963         ppgtt->pin_count = 0;
1964         return err;
1965 }
1966
1967 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
1968 {
1969         struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
1970
1971         GEM_BUG_ON(!ppgtt->pin_count);
1972         if (--ppgtt->pin_count)
1973                 return;
1974
1975         i915_vma_unpin(ppgtt->vma);
1976 }
1977
1978 static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
1979 {
1980         struct i915_ggtt * const ggtt = &i915->ggtt;
1981         struct gen6_hw_ppgtt *ppgtt;
1982         int err;
1983
1984         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1985         if (!ppgtt)
1986                 return ERR_PTR(-ENOMEM);
1987
1988         ppgtt_init(i915, &ppgtt->base);
1989
1990         ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
1991         ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
1992         ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries;
1993         ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;
1994
1995         ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
1996
1997         err = gen6_ppgtt_init_scratch(ppgtt);
1998         if (err)
1999                 goto err_free;
2000
2001         ppgtt->vma = pd_vma_create(ppgtt, GEN6_PD_SIZE);
2002         if (IS_ERR(ppgtt->vma)) {
2003                 err = PTR_ERR(ppgtt->vma);
2004                 goto err_scratch;
2005         }
2006
2007         return &ppgtt->base;
2008
2009 err_scratch:
2010         gen6_ppgtt_free_scratch(&ppgtt->base.vm);
2011 err_free:
2012         kfree(ppgtt);
2013         return ERR_PTR(err);
2014 }
2015
2016 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
2017 {
2018         /* This function is for gtt related workarounds. This function is
2019          * called on driver load and after a GPU reset, so you can place
2020          * workarounds here even if they get overwritten by GPU reset.
2021          */
2022         /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
2023         if (IS_BROADWELL(dev_priv))
2024                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2025         else if (IS_CHERRYVIEW(dev_priv))
2026                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2027         else if (IS_GEN9_LP(dev_priv))
2028                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2029         else if (INTEL_GEN(dev_priv) >= 9)
2030                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2031
2032         /*
2033          * To support 64K PTEs we need to first enable the use of the
2034          * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
2035          * mmio, otherwise the page-walker will simply ignore the IPS bit. This
2036          * shouldn't be needed after GEN10.
2037          *
2038          * 64K pages were first introduced from BDW+, although technically they
2039          * only *work* from gen9+. For pre-BDW we instead have the option for
2040          * 32K pages, but we don't currently have any support for it in our
2041          * driver.
2042          */
2043         if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
2044             INTEL_GEN(dev_priv) <= 10)
2045                 I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
2046                            I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
2047                            GAMW_ECO_ENABLE_64K_IPS_FIELD);
2048 }
2049
2050 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
2051 {
2052         gtt_write_workarounds(dev_priv);
2053
2054         if (IS_GEN(dev_priv, 6))
2055                 gen6_ppgtt_enable(dev_priv);
2056         else if (IS_GEN(dev_priv, 7))
2057                 gen7_ppgtt_enable(dev_priv);
2058
2059         return 0;
2060 }
2061
2062 static struct i915_hw_ppgtt *
2063 __hw_ppgtt_create(struct drm_i915_private *i915)
2064 {
2065         if (INTEL_GEN(i915) < 8)
2066                 return gen6_ppgtt_create(i915);
2067         else
2068                 return gen8_ppgtt_create(i915);
2069 }
2070
2071 struct i915_hw_ppgtt *
2072 i915_ppgtt_create(struct drm_i915_private *i915,
2073                   struct drm_i915_file_private *fpriv)
2074 {
2075         struct i915_hw_ppgtt *ppgtt;
2076
2077         ppgtt = __hw_ppgtt_create(i915);
2078         if (IS_ERR(ppgtt))
2079                 return ppgtt;
2080
2081         ppgtt->vm.file = fpriv;
2082
2083         trace_i915_ppgtt_create(&ppgtt->vm);
2084
2085         return ppgtt;
2086 }
2087
2088 void i915_ppgtt_close(struct i915_address_space *vm)
2089 {
2090         GEM_BUG_ON(vm->closed);
2091         vm->closed = true;
2092 }
2093
2094 static void ppgtt_destroy_vma(struct i915_address_space *vm)
2095 {
2096         struct list_head *phases[] = {
2097                 &vm->bound_list,
2098                 &vm->unbound_list,
2099                 NULL,
2100         }, **phase;
2101
2102         vm->closed = true;
2103         for (phase = phases; *phase; phase++) {
2104                 struct i915_vma *vma, *vn;
2105
2106                 list_for_each_entry_safe(vma, vn, *phase, vm_link)
2107                         i915_vma_destroy(vma);
2108         }
2109 }
2110
2111 void i915_ppgtt_release(struct kref *kref)
2112 {
2113         struct i915_hw_ppgtt *ppgtt =
2114                 container_of(kref, struct i915_hw_ppgtt, ref);
2115
2116         trace_i915_ppgtt_release(&ppgtt->vm);
2117
2118         ppgtt_destroy_vma(&ppgtt->vm);
2119
2120         GEM_BUG_ON(!list_empty(&ppgtt->vm.bound_list));
2121         GEM_BUG_ON(!list_empty(&ppgtt->vm.unbound_list));
2122
2123         ppgtt->vm.cleanup(&ppgtt->vm);
2124         i915_address_space_fini(&ppgtt->vm);
2125         kfree(ppgtt);
2126 }
2127
2128 /* Certain Gen5 chipsets require require idling the GPU before
2129  * unmapping anything from the GTT when VT-d is enabled.
2130  */
2131 static bool needs_idle_maps(struct drm_i915_private *dev_priv)
2132 {
2133         /* Query intel_iommu to see if we need the workaround. Presumably that
2134          * was loaded first.
2135          */
2136         return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
2137 }
2138
2139 static void gen6_check_faults(struct drm_i915_private *dev_priv)
2140 {
2141         struct intel_engine_cs *engine;
2142         enum intel_engine_id id;
2143         u32 fault;
2144
2145         for_each_engine(engine, dev_priv, id) {
2146                 fault = I915_READ(RING_FAULT_REG(engine));
2147                 if (fault & RING_FAULT_VALID) {
2148                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2149                                          "\tAddr: 0x%08lx\n"
2150                                          "\tAddress space: %s\n"
2151                                          "\tSource ID: %d\n"
2152                                          "\tType: %d\n",
2153                                          fault & PAGE_MASK,
2154                                          fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2155                                          RING_FAULT_SRCID(fault),
2156                                          RING_FAULT_FAULT_TYPE(fault));
2157                 }
2158         }
2159 }
2160
2161 static void gen8_check_faults(struct drm_i915_private *dev_priv)
2162 {
2163         u32 fault = I915_READ(GEN8_RING_FAULT_REG);
2164
2165         if (fault & RING_FAULT_VALID) {
2166                 u32 fault_data0, fault_data1;
2167                 u64 fault_addr;
2168
2169                 fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
2170                 fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
2171                 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
2172                              ((u64)fault_data0 << 12);
2173
2174                 DRM_DEBUG_DRIVER("Unexpected fault\n"
2175                                  "\tAddr: 0x%08x_%08x\n"
2176                                  "\tAddress space: %s\n"
2177                                  "\tEngine ID: %d\n"
2178                                  "\tSource ID: %d\n"
2179                                  "\tType: %d\n",
2180                                  upper_32_bits(fault_addr),
2181                                  lower_32_bits(fault_addr),
2182                                  fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
2183                                  GEN8_RING_FAULT_ENGINE_ID(fault),
2184                                  RING_FAULT_SRCID(fault),
2185                                  RING_FAULT_FAULT_TYPE(fault));
2186         }
2187 }
2188
2189 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
2190 {
2191         /* From GEN8 onwards we only have one 'All Engine Fault Register' */
2192         if (INTEL_GEN(dev_priv) >= 8)
2193                 gen8_check_faults(dev_priv);
2194         else if (INTEL_GEN(dev_priv) >= 6)
2195                 gen6_check_faults(dev_priv);
2196         else
2197                 return;
2198
2199         i915_clear_error_registers(dev_priv);
2200 }
2201
2202 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
2203 {
2204         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2205
2206         /* Don't bother messing with faults pre GEN6 as we have little
2207          * documentation supporting that it's a good idea.
2208          */
2209         if (INTEL_GEN(dev_priv) < 6)
2210                 return;
2211
2212         i915_check_and_clear_faults(dev_priv);
2213
2214         ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
2215
2216         i915_ggtt_invalidate(dev_priv);
2217 }
2218
2219 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
2220                                struct sg_table *pages)
2221 {
2222         do {
2223                 if (dma_map_sg_attrs(&obj->base.dev->pdev->dev,
2224                                      pages->sgl, pages->nents,
2225                                      PCI_DMA_BIDIRECTIONAL,
2226                                      DMA_ATTR_NO_WARN))
2227                         return 0;
2228
2229                 /*
2230                  * If the DMA remap fails, one cause can be that we have
2231                  * too many objects pinned in a small remapping table,
2232                  * such as swiotlb. Incrementally purge all other objects and
2233                  * try again - if there are no more pages to remove from
2234                  * the DMA remapper, i915_gem_shrink will return 0.
2235                  */
2236                 GEM_BUG_ON(obj->mm.pages == pages);
2237         } while (i915_gem_shrink(to_i915(obj->base.dev),
2238                                  obj->base.size >> PAGE_SHIFT, NULL,
2239                                  I915_SHRINK_BOUND |
2240                                  I915_SHRINK_UNBOUND));
2241
2242         return -ENOSPC;
2243 }
2244
2245 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2246 {
2247         writeq(pte, addr);
2248 }
2249
2250 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2251                                   dma_addr_t addr,
2252                                   u64 offset,
2253                                   enum i915_cache_level level,
2254                                   u32 unused)
2255 {
2256         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2257         gen8_pte_t __iomem *pte =
2258                 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
2259
2260         gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
2261
2262         ggtt->invalidate(vm->i915);
2263 }
2264
2265 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2266                                      struct i915_vma *vma,
2267                                      enum i915_cache_level level,
2268                                      u32 flags)
2269 {
2270         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2271         struct sgt_iter sgt_iter;
2272         gen8_pte_t __iomem *gtt_entries;
2273         const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
2274         dma_addr_t addr;
2275
2276         /*
2277          * Note that we ignore PTE_READ_ONLY here. The caller must be careful
2278          * not to allow the user to override access to a read only page.
2279          */
2280
2281         gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
2282         gtt_entries += vma->node.start / I915_GTT_PAGE_SIZE;
2283         for_each_sgt_dma(addr, sgt_iter, vma->pages)
2284                 gen8_set_pte(gtt_entries++, pte_encode | addr);
2285
2286         /*
2287          * We want to flush the TLBs only after we're certain all the PTE
2288          * updates have finished.
2289          */
2290         ggtt->invalidate(vm->i915);
2291 }
2292
2293 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2294                                   dma_addr_t addr,
2295                                   u64 offset,
2296                                   enum i915_cache_level level,
2297                                   u32 flags)
2298 {
2299         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2300         gen6_pte_t __iomem *pte =
2301                 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
2302
2303         iowrite32(vm->pte_encode(addr, level, flags), pte);
2304
2305         ggtt->invalidate(vm->i915);
2306 }
2307
2308 /*
2309  * Binds an object into the global gtt with the specified cache level. The object
2310  * will be accessible to the GPU via commands whose operands reference offsets
2311  * within the global GTT as well as accessible by the GPU through the GMADR
2312  * mapped BAR (dev_priv->mm.gtt->gtt).
2313  */
2314 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2315                                      struct i915_vma *vma,
2316                                      enum i915_cache_level level,
2317                                      u32 flags)
2318 {
2319         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2320         gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
2321         unsigned int i = vma->node.start / I915_GTT_PAGE_SIZE;
2322         struct sgt_iter iter;
2323         dma_addr_t addr;
2324         for_each_sgt_dma(addr, iter, vma->pages)
2325                 iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]);
2326
2327         /*
2328          * We want to flush the TLBs only after we're certain all the PTE
2329          * updates have finished.
2330          */
2331         ggtt->invalidate(vm->i915);
2332 }
2333
2334 static void nop_clear_range(struct i915_address_space *vm,
2335                             u64 start, u64 length)
2336 {
2337 }
2338
2339 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2340                                   u64 start, u64 length)
2341 {
2342         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2343         unsigned first_entry = start / I915_GTT_PAGE_SIZE;
2344         unsigned num_entries = length / I915_GTT_PAGE_SIZE;
2345         const gen8_pte_t scratch_pte = vm->scratch_pte;
2346         gen8_pte_t __iomem *gtt_base =
2347                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2348         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2349         int i;
2350
2351         if (WARN(num_entries > max_entries,
2352                  "First entry = %d; Num entries = %d (max=%d)\n",
2353                  first_entry, num_entries, max_entries))
2354                 num_entries = max_entries;
2355
2356         for (i = 0; i < num_entries; i++)
2357                 gen8_set_pte(&gtt_base[i], scratch_pte);
2358 }
2359
2360 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
2361 {
2362         struct drm_i915_private *dev_priv = vm->i915;
2363
2364         /*
2365          * Make sure the internal GAM fifo has been cleared of all GTT
2366          * writes before exiting stop_machine(). This guarantees that
2367          * any aperture accesses waiting to start in another process
2368          * cannot back up behind the GTT writes causing a hang.
2369          * The register can be any arbitrary GAM register.
2370          */
2371         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2372 }
2373
2374 struct insert_page {
2375         struct i915_address_space *vm;
2376         dma_addr_t addr;
2377         u64 offset;
2378         enum i915_cache_level level;
2379 };
2380
2381 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
2382 {
2383         struct insert_page *arg = _arg;
2384
2385         gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
2386         bxt_vtd_ggtt_wa(arg->vm);
2387
2388         return 0;
2389 }
2390
2391 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
2392                                           dma_addr_t addr,
2393                                           u64 offset,
2394                                           enum i915_cache_level level,
2395                                           u32 unused)
2396 {
2397         struct insert_page arg = { vm, addr, offset, level };
2398
2399         stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
2400 }
2401
2402 struct insert_entries {
2403         struct i915_address_space *vm;
2404         struct i915_vma *vma;
2405         enum i915_cache_level level;
2406         u32 flags;
2407 };
2408
2409 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
2410 {
2411         struct insert_entries *arg = _arg;
2412
2413         gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
2414         bxt_vtd_ggtt_wa(arg->vm);
2415
2416         return 0;
2417 }
2418
2419 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2420                                              struct i915_vma *vma,
2421                                              enum i915_cache_level level,
2422                                              u32 flags)
2423 {
2424         struct insert_entries arg = { vm, vma, level, flags };
2425
2426         stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
2427 }
2428
2429 struct clear_range {
2430         struct i915_address_space *vm;
2431         u64 start;
2432         u64 length;
2433 };
2434
2435 static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
2436 {
2437         struct clear_range *arg = _arg;
2438
2439         gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
2440         bxt_vtd_ggtt_wa(arg->vm);
2441
2442         return 0;
2443 }
2444
2445 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
2446                                           u64 start,
2447                                           u64 length)
2448 {
2449         struct clear_range arg = { vm, start, length };
2450
2451         stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
2452 }
2453
2454 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2455                                   u64 start, u64 length)
2456 {
2457         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2458         unsigned first_entry = start / I915_GTT_PAGE_SIZE;
2459         unsigned num_entries = length / I915_GTT_PAGE_SIZE;
2460         gen6_pte_t scratch_pte, __iomem *gtt_base =
2461                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2462         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2463         int i;
2464
2465         if (WARN(num_entries > max_entries,
2466                  "First entry = %d; Num entries = %d (max=%d)\n",
2467                  first_entry, num_entries, max_entries))
2468                 num_entries = max_entries;
2469
2470         scratch_pte = vm->scratch_pte;
2471
2472         for (i = 0; i < num_entries; i++)
2473                 iowrite32(scratch_pte, &gtt_base[i]);
2474 }
2475
2476 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2477                                   dma_addr_t addr,
2478                                   u64 offset,
2479                                   enum i915_cache_level cache_level,
2480                                   u32 unused)
2481 {
2482         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2483                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2484
2485         intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2486 }
2487
2488 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2489                                      struct i915_vma *vma,
2490                                      enum i915_cache_level cache_level,
2491                                      u32 unused)
2492 {
2493         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2494                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2495
2496         intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
2497                                     flags);
2498 }
2499
2500 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2501                                   u64 start, u64 length)
2502 {
2503         intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
2504 }
2505
2506 static int ggtt_bind_vma(struct i915_vma *vma,
2507                          enum i915_cache_level cache_level,
2508                          u32 flags)
2509 {
2510         struct drm_i915_private *i915 = vma->vm->i915;
2511         struct drm_i915_gem_object *obj = vma->obj;
2512         intel_wakeref_t wakeref;
2513         u32 pte_flags;
2514
2515         /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
2516         pte_flags = 0;
2517         if (i915_gem_object_is_readonly(obj))
2518                 pte_flags |= PTE_READ_ONLY;
2519
2520         with_intel_runtime_pm(i915, wakeref)
2521                 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2522
2523         vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
2524
2525         /*
2526          * Without aliasing PPGTT there's no difference between
2527          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2528          * upgrade to both bound if we bind either to avoid double-binding.
2529          */
2530         vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
2531
2532         return 0;
2533 }
2534
2535 static void ggtt_unbind_vma(struct i915_vma *vma)
2536 {
2537         struct drm_i915_private *i915 = vma->vm->i915;
2538         intel_wakeref_t wakeref;
2539
2540         with_intel_runtime_pm(i915, wakeref)
2541                 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2542 }
2543
2544 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2545                                  enum i915_cache_level cache_level,
2546                                  u32 flags)
2547 {
2548         struct drm_i915_private *i915 = vma->vm->i915;
2549         u32 pte_flags;
2550         int ret;
2551
2552         /* Currently applicable only to VLV */
2553         pte_flags = 0;
2554         if (i915_gem_object_is_readonly(vma->obj))
2555                 pte_flags |= PTE_READ_ONLY;
2556
2557         if (flags & I915_VMA_LOCAL_BIND) {
2558                 struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
2559
2560                 if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
2561                         ret = appgtt->vm.allocate_va_range(&appgtt->vm,
2562                                                            vma->node.start,
2563                                                            vma->size);
2564                         if (ret)
2565                                 return ret;
2566                 }
2567
2568                 appgtt->vm.insert_entries(&appgtt->vm, vma, cache_level,
2569                                           pte_flags);
2570         }
2571
2572         if (flags & I915_VMA_GLOBAL_BIND) {
2573                 intel_wakeref_t wakeref;
2574
2575                 with_intel_runtime_pm(i915, wakeref) {
2576                         vma->vm->insert_entries(vma->vm, vma,
2577                                                 cache_level, pte_flags);
2578                 }
2579         }
2580
2581         return 0;
2582 }
2583
2584 static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
2585 {
2586         struct drm_i915_private *i915 = vma->vm->i915;
2587
2588         if (vma->flags & I915_VMA_GLOBAL_BIND) {
2589                 struct i915_address_space *vm = vma->vm;
2590                 intel_wakeref_t wakeref;
2591
2592                 with_intel_runtime_pm(i915, wakeref)
2593                         vm->clear_range(vm, vma->node.start, vma->size);
2594         }
2595
2596         if (vma->flags & I915_VMA_LOCAL_BIND) {
2597                 struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->vm;
2598
2599                 vm->clear_range(vm, vma->node.start, vma->size);
2600         }
2601 }
2602
2603 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
2604                                struct sg_table *pages)
2605 {
2606         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2607         struct device *kdev = &dev_priv->drm.pdev->dev;
2608         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2609
2610         if (unlikely(ggtt->do_idle_maps)) {
2611                 if (i915_gem_wait_for_idle(dev_priv, 0, MAX_SCHEDULE_TIMEOUT)) {
2612                         DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2613                         /* Wait a bit, in hopes it avoids the hang */
2614                         udelay(10);
2615                 }
2616         }
2617
2618         dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
2619 }
2620
2621 static int ggtt_set_pages(struct i915_vma *vma)
2622 {
2623         int ret;
2624
2625         GEM_BUG_ON(vma->pages);
2626
2627         ret = i915_get_ggtt_vma_pages(vma);
2628         if (ret)
2629                 return ret;
2630
2631         vma->page_sizes = vma->obj->mm.page_sizes;
2632
2633         return 0;
2634 }
2635
2636 static void i915_gtt_color_adjust(const struct drm_mm_node *node,
2637                                   unsigned long color,
2638                                   u64 *start,
2639                                   u64 *end)
2640 {
2641         if (node->allocated && node->color != color)
2642                 *start += I915_GTT_PAGE_SIZE;
2643
2644         /* Also leave a space between the unallocated reserved node after the
2645          * GTT and any objects within the GTT, i.e. we use the color adjustment
2646          * to insert a guard page to prevent prefetches crossing over the
2647          * GTT boundary.
2648          */
2649         node = list_next_entry(node, node_list);
2650         if (node->color != color)
2651                 *end -= I915_GTT_PAGE_SIZE;
2652 }
2653
2654 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
2655 {
2656         struct i915_ggtt *ggtt = &i915->ggtt;
2657         struct i915_hw_ppgtt *ppgtt;
2658         int err;
2659
2660         ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM));
2661         if (IS_ERR(ppgtt))
2662                 return PTR_ERR(ppgtt);
2663
2664         if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
2665                 err = -ENODEV;
2666                 goto err_ppgtt;
2667         }
2668
2669         /*
2670          * Note we only pre-allocate as far as the end of the global
2671          * GTT. On 48b / 4-level page-tables, the difference is very,
2672          * very significant! We have to preallocate as GVT/vgpu does
2673          * not like the page directory disappearing.
2674          */
2675         err = ppgtt->vm.allocate_va_range(&ppgtt->vm, 0, ggtt->vm.total);
2676         if (err)
2677                 goto err_ppgtt;
2678
2679         i915->mm.aliasing_ppgtt = ppgtt;
2680
2681         GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
2682         ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
2683
2684         GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
2685         ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
2686
2687         return 0;
2688
2689 err_ppgtt:
2690         i915_ppgtt_put(ppgtt);
2691         return err;
2692 }
2693
2694 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
2695 {
2696         struct i915_ggtt *ggtt = &i915->ggtt;
2697         struct i915_hw_ppgtt *ppgtt;
2698
2699         ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
2700         if (!ppgtt)
2701                 return;
2702
2703         i915_ppgtt_put(ppgtt);
2704
2705         ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
2706         ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
2707 }
2708
2709 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
2710 {
2711         /* Let GEM Manage all of the aperture.
2712          *
2713          * However, leave one page at the end still bound to the scratch page.
2714          * There are a number of places where the hardware apparently prefetches
2715          * past the end of the object, and we've seen multiple hangs with the
2716          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2717          * aperture.  One page should be enough to keep any prefetching inside
2718          * of the aperture.
2719          */
2720         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2721         unsigned long hole_start, hole_end;
2722         struct drm_mm_node *entry;
2723         int ret;
2724
2725         /*
2726          * GuC requires all resources that we're sharing with it to be placed in
2727          * non-WOPCM memory. If GuC is not present or not in use we still need a
2728          * small bias as ring wraparound at offset 0 sometimes hangs. No idea
2729          * why.
2730          */
2731         ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
2732                                intel_guc_reserved_gtt_size(&dev_priv->guc));
2733
2734         ret = intel_vgt_balloon(dev_priv);
2735         if (ret)
2736                 return ret;
2737
2738         /* Reserve a mappable slot for our lockless error capture */
2739         ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
2740                                           PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
2741                                           0, ggtt->mappable_end,
2742                                           DRM_MM_INSERT_LOW);
2743         if (ret)
2744                 return ret;
2745
2746         /* Clear any non-preallocated blocks */
2747         drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
2748                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2749                               hole_start, hole_end);
2750                 ggtt->vm.clear_range(&ggtt->vm, hole_start,
2751                                      hole_end - hole_start);
2752         }
2753
2754         /* And finally clear the reserved guard page */
2755         ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
2756
2757         if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
2758                 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
2759                 if (ret)
2760                         goto err;
2761         }
2762
2763         return 0;
2764
2765 err:
2766         drm_mm_remove_node(&ggtt->error_capture);
2767         return ret;
2768 }
2769
2770 /**
2771  * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2772  * @dev_priv: i915 device
2773  */
2774 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2775 {
2776         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2777         struct i915_vma *vma, *vn;
2778         struct pagevec *pvec;
2779
2780         ggtt->vm.closed = true;
2781
2782         mutex_lock(&dev_priv->drm.struct_mutex);
2783         i915_gem_fini_aliasing_ppgtt(dev_priv);
2784
2785         list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
2786                 WARN_ON(i915_vma_unbind(vma));
2787
2788         if (drm_mm_node_allocated(&ggtt->error_capture))
2789                 drm_mm_remove_node(&ggtt->error_capture);
2790
2791         if (drm_mm_initialized(&ggtt->vm.mm)) {
2792                 intel_vgt_deballoon(dev_priv);
2793                 i915_address_space_fini(&ggtt->vm);
2794         }
2795
2796         ggtt->vm.cleanup(&ggtt->vm);
2797
2798         pvec = &dev_priv->mm.wc_stash.pvec;
2799         if (pvec->nr) {
2800                 set_pages_array_wb(pvec->pages, pvec->nr);
2801                 __pagevec_release(pvec);
2802         }
2803
2804         mutex_unlock(&dev_priv->drm.struct_mutex);
2805
2806         arch_phys_wc_del(ggtt->mtrr);
2807         io_mapping_fini(&ggtt->iomap);
2808
2809         i915_gem_cleanup_stolen(dev_priv);
2810 }
2811
2812 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2813 {
2814         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2815         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2816         return snb_gmch_ctl << 20;
2817 }
2818
2819 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2820 {
2821         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2822         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2823         if (bdw_gmch_ctl)
2824                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2825
2826 #ifdef CONFIG_X86_32
2827         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
2828         if (bdw_gmch_ctl > 4)
2829                 bdw_gmch_ctl = 4;
2830 #endif
2831
2832         return bdw_gmch_ctl << 20;
2833 }
2834
2835 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2836 {
2837         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2838         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2839
2840         if (gmch_ctrl)
2841                 return 1 << (20 + gmch_ctrl);
2842
2843         return 0;
2844 }
2845
2846 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2847 {
2848         struct drm_i915_private *dev_priv = ggtt->vm.i915;
2849         struct pci_dev *pdev = dev_priv->drm.pdev;
2850         phys_addr_t phys_addr;
2851         int ret;
2852
2853         /* For Modern GENs the PTEs and register space are split in the BAR */
2854         phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2855
2856         /*
2857          * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
2858          * will be dropped. For WC mappings in general we have 64 byte burst
2859          * writes when the WC buffer is flushed, so we can't use it, but have to
2860          * resort to an uncached mapping. The WC issue is easily caught by the
2861          * readback check when writing GTT PTE entries.
2862          */
2863         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
2864                 ggtt->gsm = ioremap_nocache(phys_addr, size);
2865         else
2866                 ggtt->gsm = ioremap_wc(phys_addr, size);
2867         if (!ggtt->gsm) {
2868                 DRM_ERROR("Failed to map the ggtt page table\n");
2869                 return -ENOMEM;
2870         }
2871
2872         ret = setup_scratch_page(&ggtt->vm, GFP_DMA32);
2873         if (ret) {
2874                 DRM_ERROR("Scratch setup failed\n");
2875                 /* iounmap will also get called at remove, but meh */
2876                 iounmap(ggtt->gsm);
2877                 return ret;
2878         }
2879
2880         ggtt->vm.scratch_pte =
2881                 ggtt->vm.pte_encode(ggtt->vm.scratch_page.daddr,
2882                                     I915_CACHE_NONE, 0);
2883
2884         return 0;
2885 }
2886
2887 static struct intel_ppat_entry *
2888 __alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
2889 {
2890         struct intel_ppat_entry *entry = &ppat->entries[index];
2891
2892         GEM_BUG_ON(index >= ppat->max_entries);
2893         GEM_BUG_ON(test_bit(index, ppat->used));
2894
2895         entry->ppat = ppat;
2896         entry->value = value;
2897         kref_init(&entry->ref);
2898         set_bit(index, ppat->used);
2899         set_bit(index, ppat->dirty);
2900
2901         return entry;
2902 }
2903
2904 static void __free_ppat_entry(struct intel_ppat_entry *entry)
2905 {
2906         struct intel_ppat *ppat = entry->ppat;
2907         unsigned int index = entry - ppat->entries;
2908
2909         GEM_BUG_ON(index >= ppat->max_entries);
2910         GEM_BUG_ON(!test_bit(index, ppat->used));
2911
2912         entry->value = ppat->clear_value;
2913         clear_bit(index, ppat->used);
2914         set_bit(index, ppat->dirty);
2915 }
2916
2917 /**
2918  * intel_ppat_get - get a usable PPAT entry
2919  * @i915: i915 device instance
2920  * @value: the PPAT value required by the caller
2921  *
2922  * The function tries to search if there is an existing PPAT entry which
2923  * matches with the required value. If perfectly matched, the existing PPAT
2924  * entry will be used. If only partially matched, it will try to check if
2925  * there is any available PPAT index. If yes, it will allocate a new PPAT
2926  * index for the required entry and update the HW. If not, the partially
2927  * matched entry will be used.
2928  */
2929 const struct intel_ppat_entry *
2930 intel_ppat_get(struct drm_i915_private *i915, u8 value)
2931 {
2932         struct intel_ppat *ppat = &i915->ppat;
2933         struct intel_ppat_entry *entry = NULL;
2934         unsigned int scanned, best_score;
2935         int i;
2936
2937         GEM_BUG_ON(!ppat->max_entries);
2938
2939         scanned = best_score = 0;
2940         for_each_set_bit(i, ppat->used, ppat->max_entries) {
2941                 unsigned int score;
2942
2943                 score = ppat->match(ppat->entries[i].value, value);
2944                 if (score > best_score) {
2945                         entry = &ppat->entries[i];
2946                         if (score == INTEL_PPAT_PERFECT_MATCH) {
2947                                 kref_get(&entry->ref);
2948                                 return entry;
2949                         }
2950                         best_score = score;
2951                 }
2952                 scanned++;
2953         }
2954
2955         if (scanned == ppat->max_entries) {
2956                 if (!entry)
2957                         return ERR_PTR(-ENOSPC);
2958
2959                 kref_get(&entry->ref);
2960                 return entry;
2961         }
2962
2963         i = find_first_zero_bit(ppat->used, ppat->max_entries);
2964         entry = __alloc_ppat_entry(ppat, i, value);
2965         ppat->update_hw(i915);
2966         return entry;
2967 }
2968
2969 static void release_ppat(struct kref *kref)
2970 {
2971         struct intel_ppat_entry *entry =
2972                 container_of(kref, struct intel_ppat_entry, ref);
2973         struct drm_i915_private *i915 = entry->ppat->i915;
2974
2975         __free_ppat_entry(entry);
2976         entry->ppat->update_hw(i915);
2977 }
2978
2979 /**
2980  * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
2981  * @entry: an intel PPAT entry
2982  *
2983  * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
2984  * entry is dynamically allocated, its reference count will be decreased. Once
2985  * the reference count becomes into zero, the PPAT index becomes free again.
2986  */
2987 void intel_ppat_put(const struct intel_ppat_entry *entry)
2988 {
2989         struct intel_ppat *ppat = entry->ppat;
2990         unsigned int index = entry - ppat->entries;
2991
2992         GEM_BUG_ON(!ppat->max_entries);
2993
2994         kref_put(&ppat->entries[index].ref, release_ppat);
2995 }
2996
2997 static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
2998 {
2999         struct intel_ppat *ppat = &dev_priv->ppat;
3000         int i;
3001
3002         for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
3003                 I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
3004                 clear_bit(i, ppat->dirty);
3005         }
3006 }
3007
3008 static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
3009 {
3010         struct intel_ppat *ppat = &dev_priv->ppat;
3011         u64 pat = 0;
3012         int i;
3013
3014         for (i = 0; i < ppat->max_entries; i++)
3015                 pat |= GEN8_PPAT(i, ppat->entries[i].value);
3016
3017         bitmap_clear(ppat->dirty, 0, ppat->max_entries);
3018
3019         I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
3020         I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
3021 }
3022
3023 static unsigned int bdw_private_pat_match(u8 src, u8 dst)
3024 {
3025         unsigned int score = 0;
3026         enum {
3027                 AGE_MATCH = BIT(0),
3028                 TC_MATCH = BIT(1),
3029                 CA_MATCH = BIT(2),
3030         };
3031
3032         /* Cache attribute has to be matched. */
3033         if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
3034                 return 0;
3035
3036         score |= CA_MATCH;
3037
3038         if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
3039                 score |= TC_MATCH;
3040
3041         if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
3042                 score |= AGE_MATCH;
3043
3044         if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
3045                 return INTEL_PPAT_PERFECT_MATCH;
3046
3047         return score;
3048 }
3049
3050 static unsigned int chv_private_pat_match(u8 src, u8 dst)
3051 {
3052         return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
3053                 INTEL_PPAT_PERFECT_MATCH : 0;
3054 }
3055
3056 static void cnl_setup_private_ppat(struct intel_ppat *ppat)
3057 {
3058         ppat->max_entries = 8;
3059         ppat->update_hw = cnl_private_pat_update_hw;
3060         ppat->match = bdw_private_pat_match;
3061         ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
3062
3063         __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
3064         __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
3065         __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
3066         __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
3067         __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
3068         __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
3069         __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
3070         __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3071 }
3072
3073 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3074  * bits. When using advanced contexts each context stores its own PAT, but
3075  * writing this data shouldn't be harmful even in those cases. */
3076 static void bdw_setup_private_ppat(struct intel_ppat *ppat)
3077 {
3078         ppat->max_entries = 8;
3079         ppat->update_hw = bdw_private_pat_update_hw;
3080         ppat->match = bdw_private_pat_match;
3081         ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
3082
3083         if (!HAS_PPGTT(ppat->i915)) {
3084                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3085                  * so RTL will always use the value corresponding to
3086                  * pat_sel = 000".
3087                  * So let's disable cache for GGTT to avoid screen corruptions.
3088                  * MOCS still can be used though.
3089                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3090                  * before this patch, i.e. the same uncached + snooping access
3091                  * like on gen6/7 seems to be in effect.
3092                  * - So this just fixes blitter/render access. Again it looks
3093                  * like it's not just uncached access, but uncached + snooping.
3094                  * So we can still hold onto all our assumptions wrt cpu
3095                  * clflushing on LLC machines.
3096                  */
3097                 __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
3098                 return;
3099         }
3100
3101         __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
3102         __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
3103         __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
3104         __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
3105         __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
3106         __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
3107         __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
3108         __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3109 }
3110
3111 static void chv_setup_private_ppat(struct intel_ppat *ppat)
3112 {
3113         ppat->max_entries = 8;
3114         ppat->update_hw = bdw_private_pat_update_hw;
3115         ppat->match = chv_private_pat_match;
3116         ppat->clear_value = CHV_PPAT_SNOOP;
3117
3118         /*
3119          * Map WB on BDW to snooped on CHV.
3120          *
3121          * Only the snoop bit has meaning for CHV, the rest is
3122          * ignored.
3123          *
3124          * The hardware will never snoop for certain types of accesses:
3125          * - CPU GTT (GMADR->GGTT->no snoop->memory)
3126          * - PPGTT page tables
3127          * - some other special cycles
3128          *
3129          * As with BDW, we also need to consider the following for GT accesses:
3130          * "For GGTT, there is NO pat_sel[2:0] from the entry,
3131          * so RTL will always use the value corresponding to
3132          * pat_sel = 000".
3133          * Which means we must set the snoop bit in PAT entry 0
3134          * in order to keep the global status page working.
3135          */
3136
3137         __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
3138         __alloc_ppat_entry(ppat, 1, 0);
3139         __alloc_ppat_entry(ppat, 2, 0);
3140         __alloc_ppat_entry(ppat, 3, 0);
3141         __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
3142         __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
3143         __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
3144         __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
3145 }
3146
3147 static void gen6_gmch_remove(struct i915_address_space *vm)
3148 {
3149         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
3150
3151         iounmap(ggtt->gsm);
3152         cleanup_scratch_page(vm);
3153 }
3154
3155 static void setup_private_pat(struct drm_i915_private *dev_priv)
3156 {
3157         struct intel_ppat *ppat = &dev_priv->ppat;
3158         int i;
3159
3160         ppat->i915 = dev_priv;
3161
3162         if (INTEL_GEN(dev_priv) >= 10)
3163                 cnl_setup_private_ppat(ppat);
3164         else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
3165                 chv_setup_private_ppat(ppat);
3166         else
3167                 bdw_setup_private_ppat(ppat);
3168
3169         GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
3170
3171         for_each_clear_bit(i, ppat->used, ppat->max_entries) {
3172                 ppat->entries[i].value = ppat->clear_value;
3173                 ppat->entries[i].ppat = ppat;
3174                 set_bit(i, ppat->dirty);
3175         }
3176