drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  43 static __must_check int
  44 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  45                                bool readonly);
  46 static void
  47 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  48
  49 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  50                                  struct drm_i915_gem_object *obj);
  51 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  52                                          struct drm_i915_fence_reg *fence,
  53                                          bool enable);
  54
  55 static bool cpu_cache_is_coherent(struct drm_device *dev,
  56                                   enum i915_cache_level level)
  57 {
  58         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  59 }
  60
  61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  62 {
  63         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  64                 return true;
  65
  66         return obj->pin_display;
  67 }
  68
  69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  70 {
  71         if (obj->tiling_mode)
  72                 i915_gem_release_mmap(obj);
  73
  74         /* As we do not have an associated fence register, we will force
  75          * a tiling change if we ever need to acquire one.
  76          */
  77         obj->fence_dirty = false;
  78         obj->fence_reg = I915_FENCE_REG_NONE;
  79 }
  80
  81 /* some bookkeeping */
  82 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  83                                   size_t size)
  84 {
  85         spin_lock(&dev_priv->mm.object_stat_lock);
  86         dev_priv->mm.object_count++;
  87         dev_priv->mm.object_memory += size;
  88         spin_unlock(&dev_priv->mm.object_stat_lock);
  89 }
  90
  91 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  92                                      size_t size)
  93 {
  94         spin_lock(&dev_priv->mm.object_stat_lock);
  95         dev_priv->mm.object_count--;
  96         dev_priv->mm.object_memory -= size;
  97         spin_unlock(&dev_priv->mm.object_stat_lock);
  98 }
  99
 100 static int
 101 i915_gem_wait_for_error(struct i915_gpu_error *error)
 102 {
 103         int ret;
 104
 105 #define EXIT_COND (!i915_reset_in_progress(error) || \
 106                    i915_terminally_wedged(error))
 107         if (EXIT_COND)
 108                 return 0;
 109
 110         /*
 111          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 112          * userspace. If it takes that long something really bad is going on and
 113          * we should simply try to bail out and fail as gracefully as possible.
 114          */
 115         ret = wait_event_interruptible_timeout(error->reset_queue,
 116                                                EXIT_COND,
 117                                                10*HZ);
 118         if (ret == 0) {
 119                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 120                 return -EIO;
 121         } else if (ret < 0) {
 122                 return ret;
 123         }
 124 #undef EXIT_COND
 125
 126         return 0;
 127 }
 128
 129 int i915_mutex_lock_interruptible(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132         int ret;
 133
 134         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 135         if (ret)
 136                 return ret;
 137
 138         ret = mutex_lock_interruptible(&dev->struct_mutex);
 139         if (ret)
 140                 return ret;
 141
 142         WARN_ON(i915_verify_lists(dev));
 143         return 0;
 144 }
 145
 146 int
 147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 148                             struct drm_file *file)
 149 {
 150         struct drm_i915_private *dev_priv = dev->dev_private;
 151         struct drm_i915_gem_get_aperture *args = data;
 152         struct drm_i915_gem_object *obj;
 153         size_t pinned;
 154
 155         pinned = 0;
 156         mutex_lock(&dev->struct_mutex);
 157         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 158                 if (i915_gem_obj_is_pinned(obj))
 159                         pinned += i915_gem_obj_ggtt_size(obj);
 160         mutex_unlock(&dev->struct_mutex);
 161
 162         args->aper_size = dev_priv->gtt.base.total;
 163         args->aper_available_size = args->aper_size - pinned;
 164
 165         return 0;
 166 }
 167
 168 static int
 169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 170 {
 171         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 172         char *vaddr = obj->phys_handle->vaddr;
 173         struct sg_table *st;
 174         struct scatterlist *sg;
 175         int i;
 176
 177         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 178                 return -EINVAL;
 179
 180         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 181                 struct page *page;
 182                 char *src;
 183
 184                 page = shmem_read_mapping_page(mapping, i);
 185                 if (IS_ERR(page))
 186                         return PTR_ERR(page);
 187
 188                 src = kmap_atomic(page);
 189                 memcpy(vaddr, src, PAGE_SIZE);
 190                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 191                 kunmap_atomic(src);
 192
 193                 page_cache_release(page);
 194                 vaddr += PAGE_SIZE;
 195         }
 196
 197         i915_gem_chipset_flush(obj->base.dev);
 198
 199         st = kmalloc(sizeof(*st), GFP_KERNEL);
 200         if (st == NULL)
 201                 return -ENOMEM;
 202
 203         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 204                 kfree(st);
 205                 return -ENOMEM;
 206         }
 207
 208         sg = st->sgl;
 209         sg->offset = 0;
 210         sg->length = obj->base.size;
 211
 212         sg_dma_address(sg) = obj->phys_handle->busaddr;
 213         sg_dma_len(sg) = obj->base.size;
 214
 215         obj->pages = st;
 216         obj->has_dma_mapping = true;
 217         return 0;
 218 }
 219
 220 static void
 221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 222 {
 223         int ret;
 224
 225         BUG_ON(obj->madv == __I915_MADV_PURGED);
 226
 227         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 228         if (ret) {
 229                 /* In the event of a disaster, abandon all caches and
 230                  * hope for the best.
 231                  */
 232                 WARN_ON(ret != -EIO);
 233                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 234         }
 235
 236         if (obj->madv == I915_MADV_DONTNEED)
 237                 obj->dirty = 0;
 238
 239         if (obj->dirty) {
 240                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 241                 char *vaddr = obj->phys_handle->vaddr;
 242                 int i;
 243
 244                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 245                         struct page *page;
 246                         char *dst;
 247
 248                         page = shmem_read_mapping_page(mapping, i);
 249                         if (IS_ERR(page))
 250                                 continue;
 251
 252                         dst = kmap_atomic(page);
 253                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 254                         memcpy(dst, vaddr, PAGE_SIZE);
 255                         kunmap_atomic(dst);
 256
 257                         set_page_dirty(page);
 258                         if (obj->madv == I915_MADV_WILLNEED)
 259                                 mark_page_accessed(page);
 260                         page_cache_release(page);
 261                         vaddr += PAGE_SIZE;
 262                 }
 263                 obj->dirty = 0;
 264         }
 265
 266         sg_free_table(obj->pages);
 267         kfree(obj->pages);
 268
 269         obj->has_dma_mapping = false;
 270 }
 271
 272 static void
 273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 274 {
 275         drm_pci_free(obj->base.dev, obj->phys_handle);
 276 }
 277
 278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 279         .get_pages = i915_gem_object_get_pages_phys,
 280         .put_pages = i915_gem_object_put_pages_phys,
 281         .release = i915_gem_object_release_phys,
 282 };
 283
 284 static int
 285 drop_pages(struct drm_i915_gem_object *obj)
 286 {
 287         struct i915_vma *vma, *next;
 288         int ret;
 289
 290         drm_gem_object_reference(&obj->base);
 291         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link)
 292                 if (i915_vma_unbind(vma))
 293                         break;
 294
 295         ret = i915_gem_object_put_pages(obj);
 296         drm_gem_object_unreference(&obj->base);
 297
 298         return ret;
 299 }
 300
 301 int
 302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 303                             int align)
 304 {
 305         drm_dma_handle_t *phys;
 306         int ret;
 307
 308         if (obj->phys_handle) {
 309                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 310                         return -EBUSY;
 311
 312                 return 0;
 313         }
 314
 315         if (obj->madv != I915_MADV_WILLNEED)
 316                 return -EFAULT;
 317
 318         if (obj->base.filp == NULL)
 319                 return -EINVAL;
 320
 321         ret = drop_pages(obj);
 322         if (ret)
 323                 return ret;
 324
 325         /* create a new object */
 326         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 327         if (!phys)
 328                 return -ENOMEM;
 329
 330         obj->phys_handle = phys;
 331         obj->ops = &i915_gem_phys_ops;
 332
 333         return i915_gem_object_get_pages(obj);
 334 }
 335
 336 static int
 337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 338                      struct drm_i915_gem_pwrite *args,
 339                      struct drm_file *file_priv)
 340 {
 341         struct drm_device *dev = obj->base.dev;
 342         void *vaddr = obj->phys_handle->vaddr + args->offset;
 343         char __user *user_data = to_user_ptr(args->data_ptr);
 344         int ret = 0;
 345
 346         /* We manually control the domain here and pretend that it
 347          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 348          */
 349         ret = i915_gem_object_wait_rendering(obj, false);
 350         if (ret)
 351                 return ret;
 352
 353         intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
 354         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 355                 unsigned long unwritten;
 356
 357                 /* The physical object once assigned is fixed for the lifetime
 358                  * of the obj, so we can safely drop the lock and continue
 359                  * to access vaddr.
 360                  */
 361                 mutex_unlock(&dev->struct_mutex);
 362                 unwritten = copy_from_user(vaddr, user_data, args->size);
 363                 mutex_lock(&dev->struct_mutex);
 364                 if (unwritten) {
 365                         ret = -EFAULT;
 366                         goto out;
 367                 }
 368         }
 369
 370         drm_clflush_virt_range(vaddr, args->size);
 371         i915_gem_chipset_flush(dev);
 372
 373 out:
 374         intel_fb_obj_flush(obj, false);
 375         return ret;
 376 }
 377
 378 void *i915_gem_object_alloc(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 382 }
 383
 384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 385 {
 386         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 387         kmem_cache_free(dev_priv->objects, obj);
 388 }
 389
 390 static int
 391 i915_gem_create(struct drm_file *file,
 392                 struct drm_device *dev,
 393                 uint64_t size,
 394                 uint32_t *handle_p)
 395 {
 396         struct drm_i915_gem_object *obj;
 397         int ret;
 398         u32 handle;
 399
 400         size = roundup(size, PAGE_SIZE);
 401         if (size == 0)
 402                 return -EINVAL;
 403
 404         /* Allocate the new object */
 405         obj = i915_gem_alloc_object(dev, size);
 406         if (obj == NULL)
 407                 return -ENOMEM;
 408
 409         ret = drm_gem_handle_create(file, &obj->base, &handle);
 410         /* drop reference from allocate - handle holds it now */
 411         drm_gem_object_unreference_unlocked(&obj->base);
 412         if (ret)
 413                 return ret;
 414
 415         *handle_p = handle;
 416         return 0;
 417 }
 418
 419 int
 420 i915_gem_dumb_create(struct drm_file *file,
 421                      struct drm_device *dev,
 422                      struct drm_mode_create_dumb *args)
 423 {
 424         /* have to work out size/pitch and return them */
 425         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 426         args->size = args->pitch * args->height;
 427         return i915_gem_create(file, dev,
 428                                args->size, &args->handle);
 429 }
 430
 431 /**
 432  * Creates a new mm object and returns a handle to it.
 433  */
 434 int
 435 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 436                       struct drm_file *file)
 437 {
 438         struct drm_i915_gem_create *args = data;
 439
 440         return i915_gem_create(file, dev,
 441                                args->size, &args->handle);
 442 }
 443
 444 static inline int
 445 __copy_to_user_swizzled(char __user *cpu_vaddr,
 446                         const char *gpu_vaddr, int gpu_offset,
 447                         int length)
 448 {
 449         int ret, cpu_offset = 0;
 450
 451         while (length > 0) {
 452                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 453                 int this_length = min(cacheline_end - gpu_offset, length);
 454                 int swizzled_gpu_offset = gpu_offset ^ 64;
 455
 456                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 457                                      gpu_vaddr + swizzled_gpu_offset,
 458                                      this_length);
 459                 if (ret)
 460                         return ret + length;
 461
 462                 cpu_offset += this_length;
 463                 gpu_offset += this_length;
 464                 length -= this_length;
 465         }
 466
 467         return 0;
 468 }
 469
 470 static inline int
 471 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 472                           const char __user *cpu_vaddr,
 473                           int length)
 474 {
 475         int ret, cpu_offset = 0;
 476
 477         while (length > 0) {
 478                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 479                 int this_length = min(cacheline_end - gpu_offset, length);
 480                 int swizzled_gpu_offset = gpu_offset ^ 64;
 481
 482                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 483                                        cpu_vaddr + cpu_offset,
 484                                        this_length);
 485                 if (ret)
 486                         return ret + length;
 487
 488                 cpu_offset += this_length;
 489                 gpu_offset += this_length;
 490                 length -= this_length;
 491         }
 492
 493         return 0;
 494 }
 495
 496 /*
 497  * Pins the specified object's pages and synchronizes the object with
 498  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 499  * flush the object from the CPU cache.
 500  */
 501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 502                                     int *needs_clflush)
 503 {
 504         int ret;
 505
 506         *needs_clflush = 0;
 507
 508         if (!obj->base.filp)
 509                 return -EINVAL;
 510
 511         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 512                 /* If we're not in the cpu read domain, set ourself into the gtt
 513                  * read domain and manually flush cachelines (if required). This
 514                  * optimizes for the case when the gpu will dirty the data
 515                  * anyway again before the next pread happens. */
 516                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 517                                                         obj->cache_level);
 518                 ret = i915_gem_object_wait_rendering(obj, true);
 519                 if (ret)
 520                         return ret;
 521
 522                 i915_gem_object_retire(obj);
 523         }
 524
 525         ret = i915_gem_object_get_pages(obj);
 526         if (ret)
 527                 return ret;
 528
 529         i915_gem_object_pin_pages(obj);
 530
 531         return ret;
 532 }
 533
 534 /* Per-page copy function for the shmem pread fastpath.
 535  * Flushes invalid cachelines before reading the target if
 536  * needs_clflush is set. */
 537 static int
 538 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 539                  char __user *user_data,
 540                  bool page_do_bit17_swizzling, bool needs_clflush)
 541 {
 542         char *vaddr;
 543         int ret;
 544
 545         if (unlikely(page_do_bit17_swizzling))
 546                 return -EINVAL;
 547
 548         vaddr = kmap_atomic(page);
 549         if (needs_clflush)
 550                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 551                                        page_length);
 552         ret = __copy_to_user_inatomic(user_data,
 553                                       vaddr + shmem_page_offset,
 554                                       page_length);
 555         kunmap_atomic(vaddr);
 556
 557         return ret ? -EFAULT : 0;
 558 }
 559
 560 static void
 561 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 562                              bool swizzled)
 563 {
 564         if (unlikely(swizzled)) {
 565                 unsigned long start = (unsigned long) addr;
 566                 unsigned long end = (unsigned long) addr + length;
 567
 568                 /* For swizzling simply ensure that we always flush both
 569                  * channels. Lame, but simple and it works. Swizzled
 570                  * pwrite/pread is far from a hotpath - current userspace
 571                  * doesn't use it at all. */
 572                 start = round_down(start, 128);
 573                 end = round_up(end, 128);
 574
 575                 drm_clflush_virt_range((void *)start, end - start);
 576         } else {
 577                 drm_clflush_virt_range(addr, length);
 578         }
 579
 580 }
 581
 582 /* Only difference to the fast-path function is that this can handle bit17
 583  * and uses non-atomic copy and kmap functions. */
 584 static int
 585 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 586                  char __user *user_data,
 587                  bool page_do_bit17_swizzling, bool needs_clflush)
 588 {
 589         char *vaddr;
 590         int ret;
 591
 592         vaddr = kmap(page);
 593         if (needs_clflush)
 594                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 595                                              page_length,
 596                                              page_do_bit17_swizzling);
 597
 598         if (page_do_bit17_swizzling)
 599                 ret = __copy_to_user_swizzled(user_data,
 600                                               vaddr, shmem_page_offset,
 601                                               page_length);
 602         else
 603                 ret = __copy_to_user(user_data,
 604                                      vaddr + shmem_page_offset,
 605                                      page_length);
 606         kunmap(page);
 607
 608         return ret ? - EFAULT : 0;
 609 }
 610
 611 static int
 612 i915_gem_shmem_pread(struct drm_device *dev,
 613                      struct drm_i915_gem_object *obj,
 614                      struct drm_i915_gem_pread *args,
 615                      struct drm_file *file)
 616 {
 617         char __user *user_data;
 618         ssize_t remain;
 619         loff_t offset;
 620         int shmem_page_offset, page_length, ret = 0;
 621         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 622         int prefaulted = 0;
 623         int needs_clflush = 0;
 624         struct sg_page_iter sg_iter;
 625
 626         user_data = to_user_ptr(args->data_ptr);
 627         remain = args->size;
 628
 629         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 630
 631         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 632         if (ret)
 633                 return ret;
 634
 635         offset = args->offset;
 636
 637         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 638                          offset >> PAGE_SHIFT) {
 639                 struct page *page = sg_page_iter_page(&sg_iter);
 640
 641                 if (remain <= 0)
 642                         break;
 643
 644                 /* Operation in this page
 645                  *
 646                  * shmem_page_offset = offset within page in shmem file
 647                  * page_length = bytes to copy for this page
 648                  */
 649                 shmem_page_offset = offset_in_page(offset);
 650                 page_length = remain;
 651                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 652                         page_length = PAGE_SIZE - shmem_page_offset;
 653
 654                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 655                         (page_to_phys(page) & (1 << 17)) != 0;
 656
 657                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 658                                        user_data, page_do_bit17_swizzling,
 659                                        needs_clflush);
 660                 if (ret == 0)
 661                         goto next_page;
 662
 663                 mutex_unlock(&dev->struct_mutex);
 664
 665                 if (likely(!i915.prefault_disable) && !prefaulted) {
 666                         ret = fault_in_multipages_writeable(user_data, remain);
 667                         /* Userspace is tricking us, but we've already clobbered
 668                          * its pages with the prefault and promised to write the
 669                          * data up to the first fault. Hence ignore any errors
 670                          * and just continue. */
 671                         (void)ret;
 672                         prefaulted = 1;
 673                 }
 674
 675                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 676                                        user_data, page_do_bit17_swizzling,
 677                                        needs_clflush);
 678
 679                 mutex_lock(&dev->struct_mutex);
 680
 681                 if (ret)
 682                         goto out;
 683
 684 next_page:
 685                 remain -= page_length;
 686                 user_data += page_length;
 687                 offset += page_length;
 688         }
 689
 690 out:
 691         i915_gem_object_unpin_pages(obj);
 692
 693         return ret;
 694 }
 695
 696 /**
 697  * Reads data from the object referenced by handle.
 698  *
 699  * On error, the contents of *data are undefined.
 700  */
 701 int
 702 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 703                      struct drm_file *file)
 704 {
 705         struct drm_i915_gem_pread *args = data;
 706         struct drm_i915_gem_object *obj;
 707         int ret = 0;
 708
 709         if (args->size == 0)
 710                 return 0;
 711
 712         if (!access_ok(VERIFY_WRITE,
 713                        to_user_ptr(args->data_ptr),
 714                        args->size))
 715                 return -EFAULT;
 716
 717         ret = i915_mutex_lock_interruptible(dev);
 718         if (ret)
 719                 return ret;
 720
 721         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 722         if (&obj->base == NULL) {
 723                 ret = -ENOENT;
 724                 goto unlock;
 725         }
 726
 727         /* Bounds check source.  */
 728         if (args->offset > obj->base.size ||
 729             args->size > obj->base.size - args->offset) {
 730                 ret = -EINVAL;
 731                 goto out;
 732         }
 733
 734         /* prime objects have no backing filp to GEM pread/pwrite
 735          * pages from.
 736          */
 737         if (!obj->base.filp) {
 738                 ret = -EINVAL;
 739                 goto out;
 740         }
 741
 742         trace_i915_gem_object_pread(obj, args->offset, args->size);
 743
 744         ret = i915_gem_shmem_pread(dev, obj, args, file);
 745
 746 out:
 747         drm_gem_object_unreference(&obj->base);
 748 unlock:
 749         mutex_unlock(&dev->struct_mutex);
 750         return ret;
 751 }
 752
 753 /* This is the fast write path which cannot handle
 754  * page faults in the source data
 755  */
 756
 757 static inline int
 758 fast_user_write(struct io_mapping *mapping,
 759                 loff_t page_base, int page_offset,
 760                 char __user *user_data,
 761                 int length)
 762 {
 763         void __iomem *vaddr_atomic;
 764         void *vaddr;
 765         unsigned long unwritten;
 766
 767         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 768         /* We can use the cpu mem copy function because this is X86. */
 769         vaddr = (void __force*)vaddr_atomic + page_offset;
 770         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 771                                                       user_data, length);
 772         io_mapping_unmap_atomic(vaddr_atomic);
 773         return unwritten;
 774 }
 775
 776 /**
 777  * This is the fast pwrite path, where we copy the data directly from the
 778  * user into the GTT, uncached.
 779  */
 780 static int
 781 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 782                          struct drm_i915_gem_object *obj,
 783                          struct drm_i915_gem_pwrite *args,
 784                          struct drm_file *file)
 785 {
 786         struct drm_i915_private *dev_priv = dev->dev_private;
 787         ssize_t remain;
 788         loff_t offset, page_base;
 789         char __user *user_data;
 790         int page_offset, page_length, ret;
 791
 792         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 793         if (ret)
 794                 goto out;
 795
 796         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 797         if (ret)
 798                 goto out_unpin;
 799
 800         ret = i915_gem_object_put_fence(obj);
 801         if (ret)
 802                 goto out_unpin;
 803
 804         user_data = to_user_ptr(args->data_ptr);
 805         remain = args->size;
 806
 807         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 808
 809         intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
 810
 811         while (remain > 0) {
 812                 /* Operation in this page
 813                  *
 814                  * page_base = page offset within aperture
 815                  * page_offset = offset within page
 816                  * page_length = bytes to copy for this page
 817                  */
 818                 page_base = offset & PAGE_MASK;
 819                 page_offset = offset_in_page(offset);
 820                 page_length = remain;
 821                 if ((page_offset + remain) > PAGE_SIZE)
 822                         page_length = PAGE_SIZE - page_offset;
 823
 824                 /* If we get a fault while copying data, then (presumably) our
 825                  * source page isn't available.  Return the error and we'll
 826                  * retry in the slow path.
 827                  */
 828                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 829                                     page_offset, user_data, page_length)) {
 830                         ret = -EFAULT;
 831                         goto out_flush;
 832                 }
 833
 834                 remain -= page_length;
 835                 user_data += page_length;
 836                 offset += page_length;
 837         }
 838
 839 out_flush:
 840         intel_fb_obj_flush(obj, false);
 841 out_unpin:
 842         i915_gem_object_ggtt_unpin(obj);
 843 out:
 844         return ret;
 845 }
 846
 847 /* Per-page copy function for the shmem pwrite fastpath.
 848  * Flushes invalid cachelines before writing to the target if
 849  * needs_clflush_before is set and flushes out any written cachelines after
 850  * writing if needs_clflush is set. */
 851 static int
 852 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 853                   char __user *user_data,
 854                   bool page_do_bit17_swizzling,
 855                   bool needs_clflush_before,
 856                   bool needs_clflush_after)
 857 {
 858         char *vaddr;
 859         int ret;
 860
 861         if (unlikely(page_do_bit17_swizzling))
 862                 return -EINVAL;
 863
 864         vaddr = kmap_atomic(page);
 865         if (needs_clflush_before)
 866                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 867                                        page_length);
 868         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 869                                         user_data, page_length);
 870         if (needs_clflush_after)
 871                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 872                                        page_length);
 873         kunmap_atomic(vaddr);
 874
 875         return ret ? -EFAULT : 0;
 876 }
 877
 878 /* Only difference to the fast-path function is that this can handle bit17
 879  * and uses non-atomic copy and kmap functions. */
 880 static int
 881 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 882                   char __user *user_data,
 883                   bool page_do_bit17_swizzling,
 884                   bool needs_clflush_before,
 885                   bool needs_clflush_after)
 886 {
 887         char *vaddr;
 888         int ret;
 889
 890         vaddr = kmap(page);
 891         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 892                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 893                                              page_length,
 894                                              page_do_bit17_swizzling);
 895         if (page_do_bit17_swizzling)
 896                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 897                                                 user_data,
 898                                                 page_length);
 899         else
 900                 ret = __copy_from_user(vaddr + shmem_page_offset,
 901                                        user_data,
 902                                        page_length);
 903         if (needs_clflush_after)
 904                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 905                                              page_length,
 906                                              page_do_bit17_swizzling);
 907         kunmap(page);
 908
 909         return ret ? -EFAULT : 0;
 910 }
 911
 912 static int
 913 i915_gem_shmem_pwrite(struct drm_device *dev,
 914                       struct drm_i915_gem_object *obj,
 915                       struct drm_i915_gem_pwrite *args,
 916                       struct drm_file *file)
 917 {
 918         ssize_t remain;
 919         loff_t offset;
 920         char __user *user_data;
 921         int shmem_page_offset, page_length, ret = 0;
 922         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 923         int hit_slowpath = 0;
 924         int needs_clflush_after = 0;
 925         int needs_clflush_before = 0;
 926         struct sg_page_iter sg_iter;
 927
 928         user_data = to_user_ptr(args->data_ptr);
 929         remain = args->size;
 930
 931         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 932
 933         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 934                 /* If we're not in the cpu write domain, set ourself into the gtt
 935                  * write domain and manually flush cachelines (if required). This
 936                  * optimizes for the case when the gpu will use the data
 937                  * right away and we therefore have to clflush anyway. */
 938                 needs_clflush_after = cpu_write_needs_clflush(obj);
 939                 ret = i915_gem_object_wait_rendering(obj, false);
 940                 if (ret)
 941                         return ret;
 942
 943                 i915_gem_object_retire(obj);
 944         }
 945         /* Same trick applies to invalidate partially written cachelines read
 946          * before writing. */
 947         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 948                 needs_clflush_before =
 949                         !cpu_cache_is_coherent(dev, obj->cache_level);
 950
 951         ret = i915_gem_object_get_pages(obj);
 952         if (ret)
 953                 return ret;
 954
 955         intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
 956
 957         i915_gem_object_pin_pages(obj);
 958
 959         offset = args->offset;
 960         obj->dirty = 1;
 961
 962         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 963                          offset >> PAGE_SHIFT) {
 964                 struct page *page = sg_page_iter_page(&sg_iter);
 965                 int partial_cacheline_write;
 966
 967                 if (remain <= 0)
 968                         break;
 969
 970                 /* Operation in this page
 971                  *
 972                  * shmem_page_offset = offset within page in shmem file
 973                  * page_length = bytes to copy for this page
 974                  */
 975                 shmem_page_offset = offset_in_page(offset);
 976
 977                 page_length = remain;
 978                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 979                         page_length = PAGE_SIZE - shmem_page_offset;
 980
 981                 /* If we don't overwrite a cacheline completely we need to be
 982                  * careful to have up-to-date data by first clflushing. Don't
 983                  * overcomplicate things and flush the entire patch. */
 984                 partial_cacheline_write = needs_clflush_before &&
 985                         ((shmem_page_offset | page_length)
 986                                 & (boot_cpu_data.x86_clflush_size - 1));
 987
 988                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 989                         (page_to_phys(page) & (1 << 17)) != 0;
 990
 991                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 992                                         user_data, page_do_bit17_swizzling,
 993                                         partial_cacheline_write,
 994                                         needs_clflush_after);
 995                 if (ret == 0)
 996                         goto next_page;
 997
 998                 hit_slowpath = 1;
 999                 mutex_unlock(&dev->struct_mutex);
1000                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1001                                         user_data, page_do_bit17_swizzling,
1002                                         partial_cacheline_write,
1003                                         needs_clflush_after);
1004
1005                 mutex_lock(&dev->struct_mutex);
1006
1007                 if (ret)
1008                         goto out;
1009
1010 next_page:
1011                 remain -= page_length;
1012                 user_data += page_length;
1013                 offset += page_length;
1014         }
1015
1016 out:
1017         i915_gem_object_unpin_pages(obj);
1018
1019         if (hit_slowpath) {
1020                 /*
1021                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1022                  * cachelines in-line while writing and the object moved
1023                  * out of the cpu write domain while we've dropped the lock.
1024                  */
1025                 if (!needs_clflush_after &&
1026                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1027                         if (i915_gem_clflush_object(obj, obj->pin_display))
1028                                 i915_gem_chipset_flush(dev);
1029                 }
1030         }
1031
1032         if (needs_clflush_after)
1033                 i915_gem_chipset_flush(dev);
1034
1035         intel_fb_obj_flush(obj, false);
1036         return ret;
1037 }
1038
1039 /**
1040  * Writes data to the object referenced by handle.
1041  *
1042  * On error, the contents of the buffer that were to be modified are undefined.
1043  */
1044 int
1045 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1046                       struct drm_file *file)
1047 {
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         struct drm_i915_gem_pwrite *args = data;
1050         struct drm_i915_gem_object *obj;
1051         int ret;
1052
1053         if (args->size == 0)
1054                 return 0;
1055
1056         if (!access_ok(VERIFY_READ,
1057                        to_user_ptr(args->data_ptr),
1058                        args->size))
1059                 return -EFAULT;
1060
1061         if (likely(!i915.prefault_disable)) {
1062                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1063                                                    args->size);
1064                 if (ret)
1065                         return -EFAULT;
1066         }
1067
1068         intel_runtime_pm_get(dev_priv);
1069
1070         ret = i915_mutex_lock_interruptible(dev);
1071         if (ret)
1072                 goto put_rpm;
1073
1074         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1075         if (&obj->base == NULL) {
1076                 ret = -ENOENT;
1077                 goto unlock;
1078         }
1079
1080         /* Bounds check destination. */
1081         if (args->offset > obj->base.size ||
1082             args->size > obj->base.size - args->offset) {
1083                 ret = -EINVAL;
1084                 goto out;
1085         }
1086
1087         /* prime objects have no backing filp to GEM pread/pwrite
1088          * pages from.
1089          */
1090         if (!obj->base.filp) {
1091                 ret = -EINVAL;
1092                 goto out;
1093         }
1094
1095         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1096
1097         ret = -EFAULT;
1098         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099          * it would end up going through the fenced access, and we'll get
1100          * different detiling behavior between reading and writing.
1101          * pread/pwrite currently are reading and writing from the CPU
1102          * perspective, requiring manual detiling by the client.
1103          */
1104         if (obj->tiling_mode == I915_TILING_NONE &&
1105             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1106             cpu_write_needs_clflush(obj)) {
1107                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1108                 /* Note that the gtt paths might fail with non-page-backed user
1109                  * pointers (e.g. gtt mappings when moving data between
1110                  * textures). Fallback to the shmem path in that case. */
1111         }
1112
1113         if (ret == -EFAULT || ret == -ENOSPC) {
1114                 if (obj->phys_handle)
1115                         ret = i915_gem_phys_pwrite(obj, args, file);
1116                 else
1117                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1118         }
1119
1120 out:
1121         drm_gem_object_unreference(&obj->base);
1122 unlock:
1123         mutex_unlock(&dev->struct_mutex);
1124 put_rpm:
1125         intel_runtime_pm_put(dev_priv);
1126
1127         return ret;
1128 }
1129
1130 int
1131 i915_gem_check_wedge(struct i915_gpu_error *error,
1132                      bool interruptible)
1133 {
1134         if (i915_reset_in_progress(error)) {
1135                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136                  * -EIO unconditionally for these. */
1137                 if (!interruptible)
1138                         return -EIO;
1139
1140                 /* Recovery complete, but the reset failed ... */
1141                 if (i915_terminally_wedged(error))
1142                         return -EIO;
1143
1144                 /*
1145                  * Check if GPU Reset is in progress - we need intel_ring_begin
1146                  * to work properly to reinit the hw state while the gpu is
1147                  * still marked as reset-in-progress. Handle this with a flag.
1148                  */
1149                 if (!error->reload_in_reset)
1150                         return -EAGAIN;
1151         }
1152
1153         return 0;
1154 }
1155
1156 /*
1157  * Compare arbitrary request against outstanding lazy request. Emit on match.
1158  */
1159 int
1160 i915_gem_check_olr(struct drm_i915_gem_request *req)
1161 {
1162         int ret;
1163
1164         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
1165
1166         ret = 0;
1167         if (req == req->ring->outstanding_lazy_request)
1168                 ret = i915_add_request(req->ring);
1169
1170         return ret;
1171 }
1172
1173 static void fake_irq(unsigned long data)
1174 {
1175         wake_up_process((struct task_struct *)data);
1176 }
1177
1178 static bool missed_irq(struct drm_i915_private *dev_priv,
1179                        struct intel_engine_cs *ring)
1180 {
1181         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1182 }
1183
1184 static int __i915_spin_request(struct drm_i915_gem_request *rq)
1185 {
1186         unsigned long timeout;
1187
1188         if (i915_gem_request_get_ring(rq)->irq_refcount)
1189                 return -EBUSY;
1190
1191         timeout = jiffies + 1;
1192         while (!need_resched()) {
1193                 if (i915_gem_request_completed(rq, true))
1194                         return 0;
1195
1196                 if (time_after_eq(jiffies, timeout))
1197                         break;
1198
1199                 cpu_relax_lowlatency();
1200         }
1201         if (i915_gem_request_completed(rq, false))
1202                 return 0;
1203
1204         return -EAGAIN;
1205 }
1206
1207 /**
1208  * __i915_wait_request - wait until execution of request has finished
1209  * @req: duh!
1210  * @reset_counter: reset sequence associated with the given request
1211  * @interruptible: do an interruptible wait (normally yes)
1212  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1213  *
1214  * Note: It is of utmost importance that the passed in seqno and reset_counter
1215  * values have been read by the caller in an smp safe manner. Where read-side
1216  * locks are involved, it is sufficient to read the reset_counter before
1217  * unlocking the lock that protects the seqno. For lockless tricks, the
1218  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1219  * inserted.
1220  *
1221  * Returns 0 if the request was found within the alloted time. Else returns the
1222  * errno with remaining time filled in timeout argument.
1223  */
1224 int __i915_wait_request(struct drm_i915_gem_request *req,
1225                         unsigned reset_counter,
1226                         bool interruptible,
1227                         s64 *timeout,
1228                         struct drm_i915_file_private *file_priv)
1229 {
1230         struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
1231         struct drm_device *dev = ring->dev;
1232         struct drm_i915_private *dev_priv = dev->dev_private;
1233         const bool irq_test_in_progress =
1234                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1235         DEFINE_WAIT(wait);
1236         unsigned long timeout_expire;
1237         s64 before, now;
1238         int ret;
1239
1240         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1241
1242         if (i915_gem_request_completed(req, true))
1243                 return 0;
1244
1245         timeout_expire = timeout ?
1246                 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
1247
1248         if (INTEL_INFO(dev)->gen >= 6)
1249                 gen6_rps_boost(dev_priv, file_priv);
1250
1251         /* Record current time in case interrupted by signal, or wedged */
1252         trace_i915_gem_request_wait_begin(req);
1253         before = ktime_get_raw_ns();
1254
1255         /* Optimistic spin for the next jiffie before touching IRQs */
1256         ret = __i915_spin_request(req);
1257         if (ret == 0)
1258                 goto out;
1259
1260         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
1261                 ret = -ENODEV;
1262                 goto out;
1263         }
1264
1265         for (;;) {
1266                 struct timer_list timer;
1267
1268                 prepare_to_wait(&ring->irq_queue, &wait,
1269                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1270
1271                 /* We need to check whether any gpu reset happened in between
1272                  * the caller grabbing the seqno and now ... */
1273                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1274                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1275                          * is truely gone. */
1276                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1277                         if (ret == 0)
1278                                 ret = -EAGAIN;
1279                         break;
1280                 }
1281
1282                 if (i915_gem_request_completed(req, false)) {
1283                         ret = 0;
1284                         break;
1285                 }
1286
1287                 if (interruptible && signal_pending(current)) {
1288                         ret = -ERESTARTSYS;
1289                         break;
1290                 }
1291
1292                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1293                         ret = -ETIME;
1294                         break;
1295                 }
1296
1297                 timer.function = NULL;
1298                 if (timeout || missed_irq(dev_priv, ring)) {
1299                         unsigned long expire;
1300
1301                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1302                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1303                         mod_timer(&timer, expire);
1304                 }
1305
1306                 io_schedule();
1307
1308                 if (timer.function) {
1309                         del_singleshot_timer_sync(&timer);
1310                         destroy_timer_on_stack(&timer);
1311                 }
1312         }
1313         if (!irq_test_in_progress)
1314                 ring->irq_put(ring);
1315
1316         finish_wait(&ring->irq_queue, &wait);
1317
1318 out:
1319         now = ktime_get_raw_ns();
1320         trace_i915_gem_request_wait_end(req);
1321
1322         if (timeout) {
1323                 s64 tres = *timeout - (now - before);
1324
1325                 *timeout = tres < 0 ? 0 : tres;
1326
1327                 /*
1328                  * Apparently ktime isn't accurate enough and occasionally has a
1329                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1330                  * things up to make the test happy. We allow up to 1 jiffy.
1331                  *
1332                  * This is a regrssion from the timespec->ktime conversion.
1333                  */
1334                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1335                         *timeout = 0;
1336         }
1337
1338         return ret;
1339 }
1340
1341 /**
1342  * Waits for a request to be signaled, and cleans up the
1343  * request and object lists appropriately for that event.
1344  */
1345 int
1346 i915_wait_request(struct drm_i915_gem_request *req)
1347 {
1348         struct drm_device *dev;
1349         struct drm_i915_private *dev_priv;
1350         bool interruptible;
1351         unsigned reset_counter;
1352         int ret;
1353
1354         BUG_ON(req == NULL);
1355
1356         dev = req->ring->dev;
1357         dev_priv = dev->dev_private;
1358         interruptible = dev_priv->mm.interruptible;
1359
1360         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1361
1362         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1363         if (ret)
1364                 return ret;
1365
1366         ret = i915_gem_check_olr(req);
1367         if (ret)
1368                 return ret;
1369
1370         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1371         i915_gem_request_reference(req);
1372         ret = __i915_wait_request(req, reset_counter,
1373                                   interruptible, NULL, NULL);
1374         i915_gem_request_unreference(req);
1375         return ret;
1376 }
1377
1378 static int
1379 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1380 {
1381         if (!obj->active)
1382                 return 0;
1383
1384         /* Manually manage the write flush as we may have not yet
1385          * retired the buffer.
1386          *
1387          * Note that the last_write_req is always the earlier of
1388          * the two (read/write) requests, so if we haved successfully waited,
1389          * we know we have passed the last write.
1390          */
1391         i915_gem_request_assign(&obj->last_write_req, NULL);
1392
1393         return 0;
1394 }
1395
1396 /**
1397  * Ensures that all rendering to the object has completed and the object is
1398  * safe to unbind from the GTT or access from the CPU.
1399  */
1400 static __must_check int
1401 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1402                                bool readonly)
1403 {
1404         struct drm_i915_gem_request *req;
1405         int ret;
1406
1407         req = readonly ? obj->last_write_req : obj->last_read_req;
1408         if (!req)
1409                 return 0;
1410
1411         ret = i915_wait_request(req);
1412         if (ret)
1413                 return ret;
1414
1415         return i915_gem_object_wait_rendering__tail(obj);
1416 }
1417
1418 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1419  * as the object state may change during this call.
1420  */
1421 static __must_check int
1422 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1423                                             struct drm_i915_file_private *file_priv,
1424                                             bool readonly)
1425 {
1426         struct drm_i915_gem_request *req;
1427         struct drm_device *dev = obj->base.dev;
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         unsigned reset_counter;
1430         int ret;
1431
1432         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1433         BUG_ON(!dev_priv->mm.interruptible);
1434
1435         req = readonly ? obj->last_write_req : obj->last_read_req;
1436         if (!req)
1437                 return 0;
1438
1439         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1440         if (ret)
1441                 return ret;
1442
1443         ret = i915_gem_check_olr(req);
1444         if (ret)
1445                 return ret;
1446
1447         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1448         i915_gem_request_reference(req);
1449         mutex_unlock(&dev->struct_mutex);
1450         ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv);
1451         mutex_lock(&dev->struct_mutex);
1452         i915_gem_request_unreference(req);
1453         if (ret)
1454                 return ret;
1455
1456         return i915_gem_object_wait_rendering__tail(obj);
1457 }
1458
1459 /**
1460  * Called when user space prepares to use an object with the CPU, either
1461  * through the mmap ioctl's mapping or a GTT mapping.
1462  */
1463 int
1464 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1465                           struct drm_file *file)
1466 {
1467         struct drm_i915_gem_set_domain *args = data;
1468         struct drm_i915_gem_object *obj;
1469         uint32_t read_domains = args->read_domains;
1470         uint32_t write_domain = args->write_domain;
1471         int ret;
1472
1473         /* Only handle setting domains to types used by the CPU. */
1474         if (write_domain & I915_GEM_GPU_DOMAINS)
1475                 return -EINVAL;
1476
1477         if (read_domains & I915_GEM_GPU_DOMAINS)
1478                 return -EINVAL;
1479
1480         /* Having something in the write domain implies it's in the read
1481          * domain, and only that read domain.  Enforce that in the request.
1482          */
1483         if (write_domain != 0 && read_domains != write_domain)
1484                 return -EINVAL;
1485
1486         ret = i915_mutex_lock_interruptible(dev);
1487         if (ret)
1488                 return ret;
1489
1490         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1491         if (&obj->base == NULL) {
1492                 ret = -ENOENT;
1493                 goto unlock;
1494         }
1495
1496         /* Try to flush the object off the GPU without holding the lock.
1497          * We will repeat the flush holding the lock in the normal manner
1498          * to catch cases where we are gazumped.
1499          */
1500         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1501                                                           file->driver_priv,
1502                                                           !write_domain);
1503         if (ret)
1504                 goto unref;
1505
1506         if (read_domains & I915_GEM_DOMAIN_GTT)
1507                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1508         else
1509                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1510
1511 unref:
1512         drm_gem_object_unreference(&obj->base);
1513 unlock:
1514         mutex_unlock(&dev->struct_mutex);
1515         return ret;
1516 }
1517
1518 /**
1519  * Called when user space has done writes to this buffer
1520  */
1521 int
1522 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1523                          struct drm_file *file)
1524 {
1525         struct drm_i915_gem_sw_finish *args = data;
1526         struct drm_i915_gem_object *obj;
1527         int ret = 0;
1528
1529         ret = i915_mutex_lock_interruptible(dev);
1530         if (ret)
1531                 return ret;
1532
1533         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1534         if (&obj->base == NULL) {
1535                 ret = -ENOENT;
1536                 goto unlock;
1537         }
1538
1539         /* Pinned buffers may be scanout, so flush the cache */
1540         if (obj->pin_display)
1541                 i915_gem_object_flush_cpu_write_domain(obj);
1542
1543         drm_gem_object_unreference(&obj->base);
1544 unlock:
1545         mutex_unlock(&dev->struct_mutex);
1546         return ret;
1547 }
1548
1549 /**
1550  * Maps the contents of an object, returning the address it is mapped
1551  * into.
1552  *
1553  * While the mapping holds a reference on the contents of the object, it doesn't
1554  * imply a ref on the object itself.
1555  *
1556  * IMPORTANT:
1557  *
1558  * DRM driver writers who look a this function as an example for how to do GEM
1559  * mmap support, please don't implement mmap support like here. The modern way
1560  * to implement DRM mmap support is with an mmap offset ioctl (like
1561  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1562  * That way debug tooling like valgrind will understand what's going on, hiding
1563  * the mmap call in a driver private ioctl will break that. The i915 driver only
1564  * does cpu mmaps this way because we didn't know better.
1565  */
1566 int
1567 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1568                     struct drm_file *file)
1569 {
1570         struct drm_i915_gem_mmap *args = data;
1571         struct drm_gem_object *obj;
1572         unsigned long addr;
1573
1574         if (args->flags & ~(I915_MMAP_WC))
1575                 return -EINVAL;
1576
1577         if (args->flags & I915_MMAP_WC && !cpu_has_pat)
1578                 return -ENODEV;
1579
1580         obj = drm_gem_object_lookup(dev, file, args->handle);
1581         if (obj == NULL)
1582                 return -ENOENT;
1583
1584         /* prime objects have no backing filp to GEM mmap
1585          * pages from.
1586          */
1587         if (!obj->filp) {
1588                 drm_gem_object_unreference_unlocked(obj);
1589                 return -EINVAL;
1590         }
1591
1592         addr = vm_mmap(obj->filp, 0, args->size,
1593                        PROT_READ | PROT_WRITE, MAP_SHARED,
1594                        args->offset);
1595         if (args->flags & I915_MMAP_WC) {
1596                 struct mm_struct *mm = current->mm;
1597                 struct vm_area_struct *vma;
1598
1599                 down_write(&mm->mmap_sem);
1600                 vma = find_vma(mm, addr);
1601                 if (vma)
1602                         vma->vm_page_prot =
1603                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1604                 else
1605                         addr = -ENOMEM;
1606                 up_write(&mm->mmap_sem);
1607         }
1608         drm_gem_object_unreference_unlocked(obj);
1609         if (IS_ERR((void *)addr))
1610                 return addr;
1611
1612         args->addr_ptr = (uint64_t) addr;
1613
1614         return 0;
1615 }
1616
1617 /**
1618  * i915_gem_fault - fault a page into the GTT
1619  * vma: VMA in question
1620  * vmf: fault info
1621  *
1622  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1623  * from userspace.  The fault handler takes care of binding the object to
1624  * the GTT (if needed), allocating and programming a fence register (again,
1625  * only if needed based on whether the old reg is still valid or the object
1626  * is tiled) and inserting a new PTE into the faulting process.
1627  *
1628  * Note that the faulting process may involve evicting existing objects
1629  * from the GTT and/or fence registers to make room.  So performance may
1630  * suffer if the GTT working set is large or there are few fence registers
1631  * left.
1632  */
1633 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1634 {
1635         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1636         struct drm_device *dev = obj->base.dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         pgoff_t page_offset;
1639         unsigned long pfn;
1640         int ret = 0;
1641         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1642
1643         intel_runtime_pm_get(dev_priv);
1644
1645         /* We don't use vmf->pgoff since that has the fake offset */
1646         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1647                 PAGE_SHIFT;
1648
1649         ret = i915_mutex_lock_interruptible(dev);
1650         if (ret)
1651                 goto out;
1652
1653         trace_i915_gem_object_fault(obj, page_offset, true, write);
1654
1655         /* Try to flush the object off the GPU first without holding the lock.
1656          * Upon reacquiring the lock, we will perform our sanity checks and then
1657          * repeat the flush holding the lock in the normal manner to catch cases
1658          * where we are gazumped.
1659          */
1660         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1661         if (ret)
1662                 goto unlock;
1663
1664         /* Access to snoopable pages through the GTT is incoherent. */
1665         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1666                 ret = -EFAULT;
1667                 goto unlock;
1668         }
1669
1670         /* Now bind it into the GTT if needed */
1671         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1672         if (ret)
1673                 goto unlock;
1674
1675         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1676         if (ret)
1677                 goto unpin;
1678
1679         ret = i915_gem_object_get_fence(obj);
1680         if (ret)
1681                 goto unpin;
1682
1683         /* Finally, remap it using the new GTT offset */
1684         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1685         pfn >>= PAGE_SHIFT;
1686
1687         if (!obj->fault_mappable) {
1688                 unsigned long size = min_t(unsigned long,
1689                                            vma->vm_end - vma->vm_start,
1690                                            obj->base.size);
1691                 int i;
1692
1693                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1694                         ret = vm_insert_pfn(vma,
1695                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1696                                             pfn + i);
1697                         if (ret)
1698                                 break;
1699                 }
1700
1701                 obj->fault_mappable = true;
1702         } else
1703                 ret = vm_insert_pfn(vma,
1704                                     (unsigned long)vmf->virtual_address,
1705                                     pfn + page_offset);
1706 unpin:
1707         i915_gem_object_ggtt_unpin(obj);
1708 unlock:
1709         mutex_unlock(&dev->struct_mutex);
1710 out:
1711         switch (ret) {
1712         case -EIO:
1713                 /*
1714                  * We eat errors when the gpu is terminally wedged to avoid
1715                  * userspace unduly crashing (gl has no provisions for mmaps to
1716                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1717                  * and so needs to be reported.
1718                  */
1719                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1720                         ret = VM_FAULT_SIGBUS;
1721                         break;
1722                 }
1723         case -EAGAIN:
1724                 /*
1725                  * EAGAIN means the gpu is hung and we'll wait for the error
1726                  * handler to reset everything when re-faulting in
1727                  * i915_mutex_lock_interruptible.
1728                  */
1729         case 0:
1730         case -ERESTARTSYS:
1731         case -EINTR:
1732         case -EBUSY:
1733                 /*
1734                  * EBUSY is ok: this just means that another thread
1735                  * already did the job.
1736                  */
1737                 ret = VM_FAULT_NOPAGE;
1738                 break;
1739         case -ENOMEM:
1740                 ret = VM_FAULT_OOM;
1741                 break;
1742         case -ENOSPC:
1743         case -EFAULT:
1744                 ret = VM_FAULT_SIGBUS;
1745                 break;
1746         default:
1747                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1748                 ret = VM_FAULT_SIGBUS;
1749                 break;
1750         }
1751
1752         intel_runtime_pm_put(dev_priv);
1753         return ret;
1754 }
1755
1756 /**
1757  * i915_gem_release_mmap - remove physical page mappings
1758  * @obj: obj in question
1759  *
1760  * Preserve the reservation of the mmapping with the DRM core code, but
1761  * relinquish ownership of the pages back to the system.
1762  *
1763  * It is vital that we remove the page mapping if we have mapped a tiled
1764  * object through the GTT and then lose the fence register due to
1765  * resource pressure. Similarly if the object has been moved out of the
1766  * aperture, than pages mapped into userspace must be revoked. Removing the
1767  * mapping will then trigger a page fault on the next user access, allowing
1768  * fixup by i915_gem_fault().
1769  */
1770 void
1771 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1772 {
1773         if (!obj->fault_mappable)
1774                 return;
1775
1776         drm_vma_node_unmap(&obj->base.vma_node,
1777                            obj->base.dev->anon_inode->i_mapping);
1778         obj->fault_mappable = false;
1779 }
1780
1781 void
1782 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1783 {
1784         struct drm_i915_gem_object *obj;
1785
1786         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1787                 i915_gem_release_mmap(obj);
1788 }
1789
1790 uint32_t
1791 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1792 {
1793         uint32_t gtt_size;
1794
1795         if (INTEL_INFO(dev)->gen >= 4 ||
1796             tiling_mode == I915_TILING_NONE)
1797                 return size;
1798
1799         /* Previous chips need a power-of-two fence region when tiling */
1800         if (INTEL_INFO(dev)->gen == 3)
1801                 gtt_size = 1024*1024;
1802         else
1803                 gtt_size = 512*1024;
1804
1805         while (gtt_size < size)
1806                 gtt_size <<= 1;
1807
1808         return gtt_size;
1809 }
1810
1811 /**
1812  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1813  * @obj: object to check
1814  *
1815  * Return the required GTT alignment for an object, taking into account
1816  * potential fence register mapping.
1817  */
1818 uint32_t
1819 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1820                            int tiling_mode, bool fenced)
1821 {
1822         /*
1823          * Minimum alignment is 4k (GTT page size), but might be greater
1824          * if a fence register is needed for the object.
1825          */
1826         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1827             tiling_mode == I915_TILING_NONE)
1828                 return 4096;
1829
1830         /*
1831          * Previous chips need to be aligned to the size of the smallest
1832          * fence register that can contain the object.
1833          */
1834         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1835 }
1836
1837 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1838 {
1839         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1840         int ret;
1841
1842         if (drm_vma_node_has_offset(&obj->base.vma_node))
1843                 return 0;
1844
1845         dev_priv->mm.shrinker_no_lock_stealing = true;
1846
1847         ret = drm_gem_create_mmap_offset(&obj->base);
1848         if (ret != -ENOSPC)
1849                 goto out;
1850
1851         /* Badly fragmented mmap space? The only way we can recover
1852          * space is by destroying unwanted objects. We can't randomly release
1853          * mmap_offsets as userspace expects them to be persistent for the
1854          * lifetime of the objects. The closest we can is to release the
1855          * offsets on purgeable objects by truncating it and marking it purged,
1856          * which prevents userspace from ever using that object again.
1857          */
1858         i915_gem_shrink(dev_priv,
1859                         obj->base.size >> PAGE_SHIFT,
1860                         I915_SHRINK_BOUND |
1861                         I915_SHRINK_UNBOUND |
1862                         I915_SHRINK_PURGEABLE);
1863         ret = drm_gem_create_mmap_offset(&obj->base);
1864         if (ret != -ENOSPC)
1865                 goto out;
1866
1867         i915_gem_shrink_all(dev_priv);
1868         ret = drm_gem_create_mmap_offset(&obj->base);
1869 out:
1870         dev_priv->mm.shrinker_no_lock_stealing = false;
1871
1872         return ret;
1873 }
1874
1875 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1876 {
1877         drm_gem_free_mmap_offset(&obj->base);
1878 }
1879
1880 int
1881 i915_gem_mmap_gtt(struct drm_file *file,
1882                   struct drm_device *dev,
1883                   uint32_t handle,
1884                   uint64_t *offset)
1885 {
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct drm_i915_gem_object *obj;
1888         int ret;
1889
1890         ret = i915_mutex_lock_interruptible(dev);
1891         if (ret)
1892                 return ret;
1893
1894         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1895         if (&obj->base == NULL) {
1896                 ret = -ENOENT;
1897                 goto unlock;
1898         }
1899
1900         if (obj->base.size > dev_priv->gtt.mappable_end) {
1901                 ret = -E2BIG;
1902                 goto out;
1903         }
1904
1905         if (obj->madv != I915_MADV_WILLNEED) {
1906                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1907                 ret = -EFAULT;
1908                 goto out;
1909         }
1910
1911         ret = i915_gem_object_create_mmap_offset(obj);
1912         if (ret)
1913                 goto out;
1914
1915         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1916
1917 out:
1918         drm_gem_object_unreference(&obj->base);
1919 unlock:
1920         mutex_unlock(&dev->struct_mutex);
1921         return ret;
1922 }
1923
1924 /**
1925  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1926  * @dev: DRM device
1927  * @data: GTT mapping ioctl data
1928  * @file: GEM object info
1929  *
1930  * Simply returns the fake offset to userspace so it can mmap it.
1931  * The mmap call will end up in drm_gem_mmap(), which will set things
1932  * up so we can get faults in the handler above.
1933  *
1934  * The fault handler will take care of binding the object into the GTT
1935  * (since it may have been evicted to make room for something), allocating
1936  * a fence register, and mapping the appropriate aperture address into
1937  * userspace.
1938  */
1939 int
1940 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1941                         struct drm_file *file)
1942 {
1943         struct drm_i915_gem_mmap_gtt *args = data;
1944
1945         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1946 }
1947
1948 /* Immediately discard the backing storage */
1949 static void
1950 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_free_mmap_offset(obj);
1953
1954         if (obj->base.filp == NULL)
1955                 return;
1956
1957         /* Our goal here is to return as much of the memory as
1958          * is possible back to the system as we are called from OOM.
1959          * To do this we must instruct the shmfs to drop all of its
1960          * backing pages, *now*.
1961          */
1962         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1963         obj->madv = __I915_MADV_PURGED;
1964 }
1965
1966 /* Try to discard unwanted pages */
1967 static void
1968 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1969 {
1970         struct address_space *mapping;
1971
1972         switch (obj->madv) {
1973         case I915_MADV_DONTNEED:
1974                 i915_gem_object_truncate(obj);
1975         case __I915_MADV_PURGED:
1976                 return;
1977         }
1978
1979         if (obj->base.filp == NULL)
1980                 return;
1981
1982         mapping = file_inode(obj->base.filp)->i_mapping,
1983         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1984 }
1985
1986 static void
1987 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1988 {
1989         struct sg_page_iter sg_iter;
1990         int ret;
1991
1992         BUG_ON(obj->madv == __I915_MADV_PURGED);
1993
1994         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1995         if (ret) {
1996                 /* In the event of a disaster, abandon all caches and
1997                  * hope for the best.
1998                  */
1999                 WARN_ON(ret != -EIO);
2000                 i915_gem_clflush_object(obj, true);
2001                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2002         }
2003
2004         if (i915_gem_object_needs_bit17_swizzle(obj))
2005                 i915_gem_object_save_bit_17_swizzle(obj);
2006
2007         if (obj->madv == I915_MADV_DONTNEED)
2008                 obj->dirty = 0;
2009
2010         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2011                 struct page *page = sg_page_iter_page(&sg_iter);
2012
2013                 if (obj->dirty)
2014                         set_page_dirty(page);
2015
2016                 if (obj->madv == I915_MADV_WILLNEED)
2017                         mark_page_accessed(page);
2018
2019                 page_cache_release(page);
2020         }
2021         obj->dirty = 0;
2022
2023         sg_free_table(obj->pages);
2024         kfree(obj->pages);
2025 }
2026
2027 int
2028 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2029 {
2030         const struct drm_i915_gem_object_ops *ops = obj->ops;
2031
2032         if (obj->pages == NULL)
2033                 return 0;
2034
2035         if (obj->pages_pin_count)
2036                 return -EBUSY;
2037
2038         BUG_ON(i915_gem_obj_bound_any(obj));
2039
2040         /* ->put_pages might need to allocate memory for the bit17 swizzle
2041          * array, hence protect them from being reaped by removing them from gtt
2042          * lists early. */
2043         list_del(&obj->global_list);
2044
2045         ops->put_pages(obj);
2046         obj->pages = NULL;
2047
2048         i915_gem_object_invalidate(obj);
2049
2050         return 0;
2051 }
2052
2053 static int
2054 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2055 {
2056         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2057         int page_count, i;
2058         struct address_space *mapping;
2059         struct sg_table *st;
2060         struct scatterlist *sg;
2061         struct sg_page_iter sg_iter;
2062         struct page *page;
2063         unsigned long last_pfn = 0;     /* suppress gcc warning */
2064         gfp_t gfp;
2065
2066         /* Assert that the object is not currently in any GPU domain. As it
2067          * wasn't in the GTT, there shouldn't be any way it could have been in
2068          * a GPU cache
2069          */
2070         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2071         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2072
2073         st = kmalloc(sizeof(*st), GFP_KERNEL);
2074         if (st == NULL)
2075                 return -ENOMEM;
2076
2077         page_count = obj->base.size / PAGE_SIZE;
2078         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2079                 kfree(st);
2080                 return -ENOMEM;
2081         }
2082
2083         /* Get the list of pages out of our struct file.  They'll be pinned
2084          * at this point until we release them.
2085          *
2086          * Fail silently without starting the shrinker
2087          */
2088         mapping = file_inode(obj->base.filp)->i_mapping;
2089         gfp = mapping_gfp_mask(mapping);
2090         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2091         gfp &= ~(__GFP_IO | __GFP_WAIT);
2092         sg = st->sgl;
2093         st->nents = 0;
2094         for (i = 0; i < page_count; i++) {
2095                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2096                 if (IS_ERR(page)) {
2097                         i915_gem_shrink(dev_priv,
2098                                         page_count,
2099                                         I915_SHRINK_BOUND |
2100                                         I915_SHRINK_UNBOUND |
2101                                         I915_SHRINK_PURGEABLE);
2102                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2103                 }
2104                 if (IS_ERR(page)) {
2105                         /* We've tried hard to allocate the memory by reaping
2106                          * our own buffer, now let the real VM do its job and
2107                          * go down in flames if truly OOM.
2108                          */
2109                         i915_gem_shrink_all(dev_priv);
2110                         page = shmem_read_mapping_page(mapping, i);
2111                         if (IS_ERR(page))
2112                                 goto err_pages;
2113                 }
2114 #ifdef CONFIG_SWIOTLB
2115                 if (swiotlb_nr_tbl()) {
2116                         st->nents++;
2117                         sg_set_page(sg, page, PAGE_SIZE, 0);
2118                         sg = sg_next(sg);
2119                         continue;
2120                 }
2121 #endif
2122                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2123                         if (i)
2124                                 sg = sg_next(sg);
2125                         st->nents++;
2126                         sg_set_page(sg, page, PAGE_SIZE, 0);
2127                 } else {
2128                         sg->length += PAGE_SIZE;
2129                 }
2130                 last_pfn = page_to_pfn(page);
2131
2132                 /* Check that the i965g/gm workaround works. */
2133                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2134         }
2135 #ifdef CONFIG_SWIOTLB
2136         if (!swiotlb_nr_tbl())
2137 #endif
2138                 sg_mark_end(sg);
2139         obj->pages = st;
2140
2141         if (i915_gem_object_needs_bit17_swizzle(obj))
2142                 i915_gem_object_do_bit_17_swizzle(obj);
2143
2144         if (obj->tiling_mode != I915_TILING_NONE &&
2145             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2146                 i915_gem_object_pin_pages(obj);
2147
2148         return 0;
2149
2150 err_pages:
2151         sg_mark_end(sg);
2152         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2153                 page_cache_release(sg_page_iter_page(&sg_iter));
2154         sg_free_table(st);
2155         kfree(st);
2156
2157         /* shmemfs first checks if there is enough memory to allocate the page
2158          * and reports ENOSPC should there be insufficient, along with the usual
2159          * ENOMEM for a genuine allocation failure.
2160          *
2161          * We use ENOSPC in our driver to mean that we have run out of aperture
2162          * space and so want to translate the error from shmemfs back to our
2163          * usual understanding of ENOMEM.
2164          */
2165         if (PTR_ERR(page) == -ENOSPC)
2166                 return -ENOMEM;
2167         else
2168                 return PTR_ERR(page);
2169 }
2170
2171 /* Ensure that the associated pages are gathered from the backing storage
2172  * and pinned into our object. i915_gem_object_get_pages() may be called
2173  * multiple times before they are released by a single call to
2174  * i915_gem_object_put_pages() - once the pages are no longer referenced
2175  * either as a result of memory pressure (reaping pages under the shrinker)
2176  * or as the object is itself released.
2177  */
2178 int
2179 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2180 {
2181         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182         const struct drm_i915_gem_object_ops *ops = obj->ops;
2183         int ret;
2184
2185         if (obj->pages)
2186                 return 0;
2187
2188         if (obj->madv != I915_MADV_WILLNEED) {
2189                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2190                 return -EFAULT;
2191         }
2192
2193         BUG_ON(obj->pages_pin_count);
2194
2195         ret = ops->get_pages(obj);
2196         if (ret)
2197                 return ret;
2198
2199         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2200
2201         obj->get_page.sg = obj->pages->sgl;
2202         obj->get_page.last = 0;
2203
2204         return 0;
2205 }
2206
2207 static void
2208 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2209                                struct intel_engine_cs *ring)
2210 {
2211         struct drm_i915_gem_request *req;
2212         struct intel_engine_cs *old_ring;
2213
2214         BUG_ON(ring == NULL);
2215
2216         req = intel_ring_get_request(ring);
2217         old_ring = i915_gem_request_get_ring(obj->last_read_req);
2218
2219         if (old_ring != ring && obj->last_write_req) {
2220                 /* Keep the request relative to the current ring */
2221                 i915_gem_request_assign(&obj->last_write_req, req);
2222         }
2223
2224         /* Add a reference if we're newly entering the active list. */
2225         if (!obj->active) {
2226                 drm_gem_object_reference(&obj->base);
2227                 obj->active = 1;
2228         }
2229
2230         list_move_tail(&obj->ring_list, &ring->active_list);
2231
2232         i915_gem_request_assign(&obj->last_read_req, req);
2233 }
2234
2235 void i915_vma_move_to_active(struct i915_vma *vma,
2236                              struct intel_engine_cs *ring)
2237 {
2238         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2239         return i915_gem_object_move_to_active(vma->obj, ring);
2240 }
2241
2242 static void
2243 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2244 {
2245         struct i915_vma *vma;
2246
2247         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2248         BUG_ON(!obj->active);
2249
2250         list_for_each_entry(vma, &obj->vma_list, vma_link) {
2251                 if (!list_empty(&vma->mm_list))
2252                         list_move_tail(&vma->mm_list, &vma->vm->inactive_list);
2253         }
2254
2255         intel_fb_obj_flush(obj, true);
2256
2257         list_del_init(&obj->ring_list);
2258
2259         i915_gem_request_assign(&obj->last_read_req, NULL);
2260         i915_gem_request_assign(&obj->last_write_req, NULL);
2261         obj->base.write_domain = 0;
2262
2263         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2264
2265         obj->active = 0;
2266         drm_gem_object_unreference(&obj->base);
2267
2268         WARN_ON(i915_verify_lists(dev));
2269 }
2270
2271 static void
2272 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2273 {
2274         if (obj->last_read_req == NULL)
2275                 return;
2276
2277         if (i915_gem_request_completed(obj->last_read_req, true))
2278                 i915_gem_object_move_to_inactive(obj);
2279 }
2280
2281 static int
2282 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2283 {
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         struct intel_engine_cs *ring;
2286         int ret, i, j;
2287
2288         /* Carefully retire all requests without writing to the rings */
2289         for_each_ring(ring, dev_priv, i) {
2290                 ret = intel_ring_idle(ring);
2291                 if (ret)
2292                         return ret;
2293         }
2294         i915_gem_retire_requests(dev);
2295
2296         /* Finally reset hw state */
2297         for_each_ring(ring, dev_priv, i) {
2298                 intel_ring_init_seqno(ring, seqno);
2299
2300                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2301                         ring->semaphore.sync_seqno[j] = 0;
2302         }
2303
2304         return 0;
2305 }
2306
2307 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2308 {
2309         struct drm_i915_private *dev_priv = dev->dev_private;
2310         int ret;
2311
2312         if (seqno == 0)
2313                 return -EINVAL;
2314
2315         /* HWS page needs to be set less than what we
2316          * will inject to ring
2317          */
2318         ret = i915_gem_init_seqno(dev, seqno - 1);
2319         if (ret)
2320                 return ret;
2321
2322         /* Carefully set the last_seqno value so that wrap
2323          * detection still works
2324          */
2325         dev_priv->next_seqno = seqno;
2326         dev_priv->last_seqno = seqno - 1;
2327         if (dev_priv->last_seqno == 0)
2328                 dev_priv->last_seqno--;
2329
2330         return 0;
2331 }
2332
2333 int
2334 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337
2338         /* reserve 0 for non-seqno */
2339         if (dev_priv->next_seqno == 0) {
2340                 int ret = i915_gem_init_seqno(dev, 0);
2341                 if (ret)
2342                         return ret;
2343
2344                 dev_priv->next_seqno = 1;
2345         }
2346
2347         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2348         return 0;
2349 }
2350
2351 int __i915_add_request(struct intel_engine_cs *ring,
2352                        struct drm_file *file,
2353                        struct drm_i915_gem_object *obj)
2354 {
2355         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2356         struct drm_i915_gem_request *request;
2357         struct intel_ringbuffer *ringbuf;
2358         u32 request_start;
2359         int ret;
2360
2361         request = ring->outstanding_lazy_request;
2362         if (WARN_ON(request == NULL))
2363                 return -ENOMEM;
2364
2365         if (i915.enable_execlists) {
2366                 ringbuf = request->ctx->engine[ring->id].ringbuf;
2367         } else
2368                 ringbuf = ring->buffer;
2369
2370         request_start = intel_ring_get_tail(ringbuf);
2371         /*
2372          * Emit any outstanding flushes - execbuf can fail to emit the flush
2373          * after having emitted the batchbuffer command. Hence we need to fix
2374          * things up similar to emitting the lazy request. The difference here
2375          * is that the flush _must_ happen before the next request, no matter
2376          * what.
2377          */
2378         if (i915.enable_execlists) {
2379                 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2380                 if (ret)
2381                         return ret;
2382         } else {
2383                 ret = intel_ring_flush_all_caches(ring);
2384                 if (ret)
2385                         return ret;
2386         }
2387
2388         /* Record the position of the start of the request so that
2389          * should we detect the updated seqno part-way through the
2390          * GPU processing the request, we never over-estimate the
2391          * position of the head.
2392          */
2393         request->postfix = intel_ring_get_tail(ringbuf);
2394
2395         if (i915.enable_execlists) {
2396                 ret = ring->emit_request(ringbuf, request);
2397                 if (ret)
2398                         return ret;
2399         } else {
2400                 ret = ring->add_request(ring);
2401                 if (ret)
2402                         return ret;
2403
2404                 request->tail = intel_ring_get_tail(ringbuf);
2405         }
2406
2407         request->head = request_start;
2408
2409         /* Whilst this request exists, batch_obj will be on the
2410          * active_list, and so will hold the active reference. Only when this
2411          * request is retired will the the batch_obj be moved onto the
2412          * inactive_list and lose its active reference. Hence we do not need
2413          * to explicitly hold another reference here.
2414          */
2415         request->batch_obj = obj;
2416
2417         if (!i915.enable_execlists) {
2418                 /* Hold a reference to the current context so that we can inspect
2419                  * it later in case a hangcheck error event fires.
2420                  */
2421                 request->ctx = ring->last_context;
2422                 if (request->ctx)
2423                         i915_gem_context_reference(request->ctx);
2424         }
2425
2426         request->emitted_jiffies = jiffies;
2427         list_add_tail(&request->list, &ring->request_list);
2428         request->file_priv = NULL;
2429
2430         if (file) {
2431                 struct drm_i915_file_private *file_priv = file->driver_priv;
2432
2433                 spin_lock(&file_priv->mm.lock);
2434                 request->file_priv = file_priv;
2435                 list_add_tail(&request->client_list,
2436                               &file_priv->mm.request_list);
2437                 spin_unlock(&file_priv->mm.lock);
2438
2439                 request->pid = get_pid(task_pid(current));
2440         }
2441
2442         trace_i915_gem_request_add(request);
2443         ring->outstanding_lazy_request = NULL;
2444
2445         i915_queue_hangcheck(ring->dev);
2446
2447         queue_delayed_work(dev_priv->wq,
2448                            &dev_priv->mm.retire_work,
2449                            round_jiffies_up_relative(HZ));
2450         intel_mark_busy(dev_priv->dev);
2451
2452         return 0;
2453 }
2454
2455 static inline void
2456 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2457 {
2458         struct drm_i915_file_private *file_priv = request->file_priv;
2459
2460         if (!file_priv)
2461                 return;
2462
2463         spin_lock(&file_priv->mm.lock);
2464         list_del(&request->client_list);
2465         request->file_priv = NULL;
2466         spin_unlock(&file_priv->mm.lock);
2467 }
2468
2469 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2470                                    const struct intel_context *ctx)
2471 {
2472         unsigned long elapsed;
2473
2474         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2475
2476         if (ctx->hang_stats.banned)
2477                 return true;
2478
2479         if (ctx->hang_stats.ban_period_seconds &&
2480             elapsed <= ctx->hang_stats.ban_period_seconds) {
2481                 if (!i915_gem_context_is_default(ctx)) {
2482                         DRM_DEBUG("context hanging too fast, banning!\n");
2483                         return true;
2484                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2485                         if (i915_stop_ring_allow_warn(dev_priv))
2486                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2487                         return true;
2488                 }
2489         }
2490
2491         return false;
2492 }
2493
2494 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2495                                   struct intel_context *ctx,
2496                                   const bool guilty)
2497 {
2498         struct i915_ctx_hang_stats *hs;
2499
2500         if (WARN_ON(!ctx))
2501                 return;
2502
2503         hs = &ctx->hang_stats;
2504
2505         if (guilty) {
2506                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2507                 hs->batch_active++;
2508                 hs->guilty_ts = get_seconds();
2509         } else {
2510                 hs->batch_pending++;
2511         }
2512 }
2513
2514 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2515 {
2516         list_del(&request->list);
2517         i915_gem_request_remove_from_client(request);
2518
2519         put_pid(request->pid);
2520
2521         i915_gem_request_unreference(request);
2522 }
2523
2524 void i915_gem_request_free(struct kref *req_ref)
2525 {
2526         struct drm_i915_gem_request *req = container_of(req_ref,
2527                                                  typeof(*req), ref);
2528         struct intel_context *ctx = req->ctx;
2529
2530         if (ctx) {
2531                 if (i915.enable_execlists) {
2532                         struct intel_engine_cs *ring = req->ring;
2533
2534                         if (ctx != ring->default_context)
2535                                 intel_lr_context_unpin(ring, ctx);
2536                 }
2537
2538                 i915_gem_context_unreference(ctx);
2539         }
2540
2541         kmem_cache_free(req->i915->requests, req);
2542 }
2543
2544 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2545                            struct intel_context *ctx)
2546 {
2547         struct drm_i915_private *dev_priv = to_i915(ring->dev);
2548         struct drm_i915_gem_request *rq;
2549         int ret;
2550
2551         if (ring->outstanding_lazy_request)
2552                 return 0;
2553
2554         rq = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2555         if (rq == NULL)
2556                 return -ENOMEM;
2557
2558         kref_init(&rq->ref);
2559         rq->i915 = dev_priv;
2560
2561         ret = i915_gem_get_seqno(ring->dev, &rq->seqno);
2562         if (ret) {
2563                 kfree(rq);
2564                 return ret;
2565         }
2566
2567         rq->ring = ring;
2568
2569         if (i915.enable_execlists)
2570                 ret = intel_logical_ring_alloc_request_extras(rq, ctx);
2571         else
2572                 ret = intel_ring_alloc_request_extras(rq);
2573         if (ret) {
2574                 kfree(rq);
2575                 return ret;
2576         }
2577
2578         ring->outstanding_lazy_request = rq;
2579         return 0;
2580 }
2581
2582 struct drm_i915_gem_request *
2583 i915_gem_find_active_request(struct intel_engine_cs *ring)
2584 {
2585         struct drm_i915_gem_request *request;
2586
2587         list_for_each_entry(request, &ring->request_list, list) {
2588                 if (i915_gem_request_completed(request, false))
2589                         continue;
2590
2591                 return request;
2592         }
2593
2594         return NULL;
2595 }
2596
2597 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2598                                        struct intel_engine_cs *ring)
2599 {
2600         struct drm_i915_gem_request *request;
2601         bool ring_hung;
2602
2603         request = i915_gem_find_active_request(ring);
2604
2605         if (request == NULL)
2606                 return;
2607
2608         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2609
2610         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2611
2612         list_for_each_entry_continue(request, &ring->request_list, list)
2613                 i915_set_reset_status(dev_priv, request->ctx, false);
2614 }
2615
2616 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2617                                         struct intel_engine_cs *ring)
2618 {
2619         while (!list_empty(&ring->active_list)) {
2620                 struct drm_i915_gem_object *obj;
2621
2622                 obj = list_first_entry(&ring->active_list,
2623                                        struct drm_i915_gem_object,
2624                                        ring_list);
2625
2626                 i915_gem_object_move_to_inactive(obj);
2627         }
2628
2629         /*
2630          * Clear the execlists queue up before freeing the requests, as those
2631          * are the ones that keep the context and ringbuffer backing objects
2632          * pinned in place.
2633          */
2634         while (!list_empty(&ring->execlist_queue)) {
2635                 struct drm_i915_gem_request *submit_req;
2636
2637                 submit_req = list_first_entry(&ring->execlist_queue,
2638                                 struct drm_i915_gem_request,
2639                                 execlist_link);
2640                 list_del(&submit_req->execlist_link);
2641
2642                 if (submit_req->ctx != ring->default_context)
2643                         intel_lr_context_unpin(ring, submit_req->ctx);
2644
2645                 i915_gem_request_unreference(submit_req);
2646         }
2647
2648         /*
2649          * We must free the requests after all the corresponding objects have
2650          * been moved off active lists. Which is the same order as the normal
2651          * retire_requests function does. This is important if object hold
2652          * implicit references on things like e.g. ppgtt address spaces through
2653          * the request.
2654          */
2655         while (!list_empty(&ring->request_list)) {
2656                 struct drm_i915_gem_request *request;
2657
2658                 request = list_first_entry(&ring->request_list,
2659                                            struct drm_i915_gem_request,
2660                                            list);
2661
2662                 i915_gem_free_request(request);
2663         }
2664
2665         /* This may not have been flushed before the reset, so clean it now */
2666         i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2667 }
2668
2669 void i915_gem_restore_fences(struct drm_device *dev)
2670 {
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         int i;
2673
2674         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2675                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2676
2677                 /*
2678                  * Commit delayed tiling changes if we have an object still
2679                  * attached to the fence, otherwise just clear the fence.
2680                  */
2681                 if (reg->obj) {
2682                         i915_gem_object_update_fence(reg->obj, reg,
2683                                                      reg->obj->tiling_mode);
2684                 } else {
2685                         i915_gem_write_fence(dev, i, NULL);
2686                 }
2687         }
2688 }
2689
2690 void i915_gem_reset(struct drm_device *dev)
2691 {
2692         struct drm_i915_private *dev_priv = dev->dev_private;
2693         struct intel_engine_cs *ring;
2694         int i;
2695
2696         /*
2697          * Before we free the objects from the requests, we need to inspect
2698          * them for finding the guilty party. As the requests only borrow
2699          * their reference to the objects, the inspection must be done first.
2700          */
2701         for_each_ring(ring, dev_priv, i)
2702                 i915_gem_reset_ring_status(dev_priv, ring);
2703
2704         for_each_ring(ring, dev_priv, i)
2705                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2706
2707         i915_gem_context_reset(dev);
2708
2709         i915_gem_restore_fences(dev);
2710 }
2711
2712 /**
2713  * This function clears the request list as sequence numbers are passed.
2714  */
2715 void
2716 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2717 {
2718         if (list_empty(&ring->request_list))
2719                 return;
2720
2721         WARN_ON(i915_verify_lists(ring->dev));
2722
2723         /* Retire requests first as we use it above for the early return.
2724          * If we retire requests last, we may use a later seqno and so clear
2725          * the requests lists without clearing the active list, leading to
2726          * confusion.
2727          */
2728         while (!list_empty(&ring->request_list)) {
2729                 struct drm_i915_gem_request *request;
2730
2731                 request = list_first_entry(&ring->request_list,
2732                                            struct drm_i915_gem_request,
2733                                            list);
2734
2735                 if (!i915_gem_request_completed(request, true))
2736                         break;
2737
2738                 trace_i915_gem_request_retire(request);
2739
2740                 /* We know the GPU must have read the request to have
2741                  * sent us the seqno + interrupt, so use the position
2742                  * of tail of the request to update the last known position
2743                  * of the GPU head.
2744                  */
2745                 request->ringbuf->last_retired_head = request->postfix;
2746
2747                 i915_gem_free_request(request);
2748         }
2749
2750         /* Move any buffers on the active list that are no longer referenced
2751          * by the ringbuffer to the flushing/inactive lists as appropriate,
2752          * before we free the context associated with the requests.
2753          */
2754         while (!list_empty(&ring->active_list)) {
2755                 struct drm_i915_gem_object *obj;
2756
2757                 obj = list_first_entry(&ring->active_list,
2758                                       struct drm_i915_gem_object,
2759                                       ring_list);
2760
2761                 if (!i915_gem_request_completed(obj->last_read_req, true))
2762                         break;
2763
2764                 i915_gem_object_move_to_inactive(obj);
2765         }
2766
2767         if (unlikely(ring->trace_irq_req &&
2768                      i915_gem_request_completed(ring->trace_irq_req, true))) {
2769                 ring->irq_put(ring);
2770                 i915_gem_request_assign(&ring->trace_irq_req, NULL);
2771         }
2772
2773         WARN_ON(i915_verify_lists(ring->dev));
2774 }
2775
2776 bool
2777 i915_gem_retire_requests(struct drm_device *dev)
2778 {
2779         struct drm_i915_private *dev_priv = dev->dev_private;
2780         struct intel_engine_cs *ring;
2781         bool idle = true;
2782         int i;
2783
2784         for_each_ring(ring, dev_priv, i) {
2785                 i915_gem_retire_requests_ring(ring);
2786                 idle &= list_empty(&ring->request_list);
2787                 if (i915.enable_execlists) {
2788                         unsigned long flags;
2789
2790                         spin_lock_irqsave(&ring->execlist_lock, flags);
2791                         idle &= list_empty(&ring->execlist_queue);
2792                         spin_unlock_irqrestore(&ring->execlist_lock, flags);
2793
2794                         intel_execlists_retire_requests(ring);
2795                 }
2796         }
2797
2798         if (idle)
2799                 mod_delayed_work(dev_priv->wq,
2800                                    &dev_priv->mm.idle_work,
2801                                    msecs_to_jiffies(100));
2802
2803         return idle;
2804 }
2805
2806 static void
2807 i915_gem_retire_work_handler(struct work_struct *work)
2808 {
2809         struct drm_i915_private *dev_priv =
2810                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2811         struct drm_device *dev = dev_priv->dev;
2812         bool idle;
2813
2814         /* Come back later if the device is busy... */
2815         idle = false;
2816         if (mutex_trylock(&dev->struct_mutex)) {
2817                 idle = i915_gem_retire_requests(dev);
2818                 mutex_unlock(&dev->struct_mutex);
2819         }
2820         if (!idle)
2821                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2822                                    round_jiffies_up_relative(HZ));
2823 }
2824
2825 static void
2826 i915_gem_idle_work_handler(struct work_struct *work)
2827 {
2828         struct drm_i915_private *dev_priv =
2829                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2830         struct drm_device *dev = dev_priv->dev;
2831         struct intel_engine_cs *ring;
2832         int i;
2833
2834         for_each_ring(ring, dev_priv, i)
2835                 if (!list_empty(&ring->request_list))
2836                         return;
2837
2838         intel_mark_idle(dev);
2839
2840         if (mutex_trylock(&dev->struct_mutex)) {
2841                 struct intel_engine_cs *ring;
2842                 int i;
2843
2844                 for_each_ring(ring, dev_priv, i)
2845                         i915_gem_batch_pool_fini(&ring->batch_pool);
2846
2847                 mutex_unlock(&dev->struct_mutex);
2848         }
2849 }
2850
2851 /**
2852  * Ensures that an object will eventually get non-busy by flushing any required
2853  * write domains, emitting any outstanding lazy request and retiring and
2854  * completed requests.
2855  */
2856 static int
2857 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2858 {
2859         struct intel_engine_cs *ring;
2860         int ret;
2861
2862         if (obj->active) {
2863                 ring = i915_gem_request_get_ring(obj->last_read_req);
2864
2865                 ret = i915_gem_check_olr(obj->last_read_req);
2866                 if (ret)
2867                         return ret;
2868
2869                 i915_gem_retire_requests_ring(ring);
2870         }
2871
2872         return 0;
2873 }
2874
2875 /**
2876  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2877  * @DRM_IOCTL_ARGS: standard ioctl arguments
2878  *
2879  * Returns 0 if successful, else an error is returned with the remaining time in
2880  * the timeout parameter.
2881  *  -ETIME: object is still busy after timeout
2882  *  -ERESTARTSYS: signal interrupted the wait
2883  *  -ENONENT: object doesn't exist
2884  * Also possible, but rare:
2885  *  -EAGAIN: GPU wedged
2886  *  -ENOMEM: damn
2887  *  -ENODEV: Internal IRQ fail
2888  *  -E?: The add request failed
2889  *
2890  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2891  * non-zero timeout parameter the wait ioctl will wait for the given number of
2892  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2893  * without holding struct_mutex the object may become re-busied before this
2894  * function completes. A similar but shorter * race condition exists in the busy
2895  * ioctl
2896  */
2897 int
2898 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2899 {
2900         struct drm_i915_private *dev_priv = dev->dev_private;
2901         struct drm_i915_gem_wait *args = data;
2902         struct drm_i915_gem_object *obj;
2903         struct drm_i915_gem_request *req;
2904         unsigned reset_counter;
2905         int ret = 0;
2906
2907         if (args->flags != 0)
2908                 return -EINVAL;
2909
2910         ret = i915_mutex_lock_interruptible(dev);
2911         if (ret)
2912                 return ret;
2913
2914         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2915         if (&obj->base == NULL) {
2916                 mutex_unlock(&dev->struct_mutex);
2917                 return -ENOENT;
2918         }
2919
2920         /* Need to make sure the object gets inactive eventually. */
2921         ret = i915_gem_object_flush_active(obj);
2922         if (ret)
2923                 goto out;
2924
2925         if (!obj->active || !obj->last_read_req)
2926                 goto out;
2927
2928         req = obj->last_read_req;
2929
2930         /* Do this after OLR check to make sure we make forward progress polling
2931          * on this IOCTL with a timeout == 0 (like busy ioctl)
2932          */
2933         if (args->timeout_ns == 0) {
2934                 ret = -ETIME;
2935                 goto out;
2936         }
2937
2938         drm_gem_object_unreference(&obj->base);
2939         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2940         i915_gem_request_reference(req);
2941         mutex_unlock(&dev->struct_mutex);
2942
2943         ret = __i915_wait_request(req, reset_counter, true,
2944                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
2945                                   file->driver_priv);
2946         i915_gem_request_unreference__unlocked(req);
2947         return ret;
2948
2949 out:
2950         drm_gem_object_unreference(&obj->base);
2951         mutex_unlock(&dev->struct_mutex);
2952         return ret;
2953 }
2954
2955 /**
2956  * i915_gem_object_sync - sync an object to a ring.
2957  *
2958  * @obj: object which may be in use on another ring.
2959  * @to: ring we wish to use the object on. May be NULL.
2960  *
2961  * This code is meant to abstract object synchronization with the GPU.
2962  * Calling with NULL implies synchronizing the object with the CPU
2963  * rather than a particular GPU ring.
2964  *
2965  * Returns 0 if successful, else propagates up the lower layer error.
2966  */
2967 int
2968 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2969                      struct intel_engine_cs *to)
2970 {
2971         struct intel_engine_cs *from;
2972         u32 seqno;
2973         int ret, idx;
2974
2975         from = i915_gem_request_get_ring(obj->last_read_req);
2976
2977         if (from == NULL || to == from)
2978                 return 0;
2979
2980         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2981                 return i915_gem_object_wait_rendering(obj, false);
2982
2983         idx = intel_ring_sync_index(from, to);
2984
2985         seqno = i915_gem_request_get_seqno(obj->last_read_req);
2986         /* Optimization: Avoid semaphore sync when we are sure we already
2987          * waited for an object with higher seqno */
2988         if (seqno <= from->semaphore.sync_seqno[idx])
2989                 return 0;
2990
2991         ret = i915_gem_check_olr(obj->last_read_req);
2992         if (ret)
2993                 return ret;
2994
2995         trace_i915_gem_ring_sync_to(from, to, obj->last_read_req);
2996         ret = to->semaphore.sync_to(to, from, seqno);
2997         if (!ret)
2998                 /* We use last_read_req because sync_to()
2999                  * might have just caused seqno wrap under
3000                  * the radar.
3001                  */
3002                 from->semaphore.sync_seqno[idx] =
3003                                 i915_gem_request_get_seqno(obj->last_read_req);
3004
3005         return ret;
3006 }
3007
3008 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3009 {
3010         u32 old_write_domain, old_read_domains;
3011
3012         /* Force a pagefault for domain tracking on next user access */
3013         i915_gem_release_mmap(obj);
3014
3015         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3016                 return;
3017
3018         /* Wait for any direct GTT access to complete */
3019         mb();
3020
3021         old_read_domains = obj->base.read_domains;
3022         old_write_domain = obj->base.write_domain;
3023
3024         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3025         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3026
3027         trace_i915_gem_object_change_domain(obj,
3028                                             old_read_domains,
3029                                             old_write_domain);
3030 }
3031
3032 int i915_vma_unbind(struct i915_vma *vma)
3033 {
3034         struct drm_i915_gem_object *obj = vma->obj;
3035         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3036         int ret;
3037
3038         if (list_empty(&vma->vma_link))
3039                 return 0;
3040
3041         if (!drm_mm_node_allocated(&vma->node)) {
3042                 i915_gem_vma_destroy(vma);
3043                 return 0;
3044         }
3045
3046         if (vma->pin_count)
3047                 return -EBUSY;
3048
3049         BUG_ON(obj->pages == NULL);
3050
3051         ret = i915_gem_object_finish_gpu(obj);
3052         if (ret)
3053                 return ret;
3054         /* Continue on if we fail due to EIO, the GPU is hung so we
3055          * should be safe and we need to cleanup or else we might
3056          * cause memory corruption through use-after-free.
3057          */
3058
3059         if (i915_is_ggtt(vma->vm) &&
3060             vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3061                 i915_gem_object_finish_gtt(obj);
3062
3063                 /* release the fence reg _after_ flushing */
3064                 ret = i915_gem_object_put_fence(obj);
3065                 if (ret)
3066                         return ret;
3067         }
3068
3069         trace_i915_vma_unbind(vma);
3070
3071         vma->vm->unbind_vma(vma);
3072
3073         list_del_init(&vma->mm_list);
3074         if (i915_is_ggtt(vma->vm)) {
3075                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3076                         obj->map_and_fenceable = false;
3077                 } else if (vma->ggtt_view.pages) {
3078                         sg_free_table(vma->ggtt_view.pages);
3079                         kfree(vma->ggtt_view.pages);
3080                         vma->ggtt_view.pages = NULL;
3081                 }
3082         }
3083
3084         drm_mm_remove_node(&vma->node);
3085         i915_gem_vma_destroy(vma);
3086
3087         /* Since the unbound list is global, only move to that list if
3088          * no more VMAs exist. */
3089         if (list_empty(&obj->vma_list)) {
3090                 /* Throw away the active reference before
3091                  * moving to the unbound list. */
3092                 i915_gem_object_retire(obj);
3093
3094                 i915_gem_gtt_finish_object(obj);
3095                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3096         }
3097
3098         /* And finally now the object is completely decoupled from this vma,
3099          * we can drop its hold on the backing storage and allow it to be
3100          * reaped by the shrinker.
3101          */
3102         i915_gem_object_unpin_pages(obj);
3103
3104         return 0;
3105 }
3106
3107 int i915_gpu_idle(struct drm_device *dev)
3108 {
3109         struct drm_i915_private *dev_priv = dev->dev_private;
3110         struct intel_engine_cs *ring;
3111         int ret, i;
3112
3113         /* Flush everything onto the inactive list. */
3114         for_each_ring(ring, dev_priv, i) {
3115                 if (!i915.enable_execlists) {
3116                         ret = i915_switch_context(ring, ring->default_context);
3117                         if (ret)
3118                                 return ret;
3119                 }
3120
3121                 ret = intel_ring_idle(ring);
3122                 if (ret)
3123                         return ret;
3124         }
3125
3126         return 0;
3127 }
3128
3129 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3130                                  struct drm_i915_gem_object *obj)
3131 {
3132         struct drm_i915_private *dev_priv = dev->dev_private;
3133         int fence_reg;
3134         int fence_pitch_shift;
3135
3136         if (INTEL_INFO(dev)->gen >= 6) {
3137                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3138                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3139         } else {
3140                 fence_reg = FENCE_REG_965_0;
3141                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3142         }
3143
3144         fence_reg += reg * 8;
3145
3146         /* To w/a incoherency with non-atomic 64-bit register updates,
3147          * we split the 64-bit update into two 32-bit writes. In order
3148          * for a partial fence not to be evaluated between writes, we
3149          * precede the update with write to turn off the fence register,
3150          * and only enable the fence as the last step.
3151          *
3152          * For extra levels of paranoia, we make sure each step lands
3153          * before applying the next step.
3154          */
3155         I915_WRITE(fence_reg, 0);
3156         POSTING_READ(fence_reg);
3157
3158         if (obj) {
3159                 u32 size = i915_gem_obj_ggtt_size(obj);
3160                 uint64_t val;
3161
3162                 /* Adjust fence size to match tiled area */
3163                 if (obj->tiling_mode != I915_TILING_NONE) {
3164                         uint32_t row_size = obj->stride *
3165                                 (obj->tiling_mode == I915_TILING_Y ? 32 : 8);
3166                         size = (size / row_size) * row_size;
3167                 }
3168
3169                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3170                                  0xfffff000) << 32;
3171                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3172                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3173                 if (obj->tiling_mode == I915_TILING_Y)
3174                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3175                 val |= I965_FENCE_REG_VALID;
3176
3177                 I915_WRITE(fence_reg + 4, val >> 32);
3178                 POSTING_READ(fence_reg + 4);
3179
3180                 I915_WRITE(fence_reg + 0, val);
3181                 POSTING_READ(fence_reg);
3182         } else {
3183                 I915_WRITE(fence_reg + 4, 0);
3184                 POSTING_READ(fence_reg + 4);
3185         }
3186 }
3187
3188 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3189                                  struct drm_i915_gem_object *obj)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         u32 val;
3193
3194         if (obj) {
3195                 u32 size = i915_gem_obj_ggtt_size(obj);
3196                 int pitch_val;
3197                 int tile_width;
3198
3199                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3200                      (size & -size) != size ||
3201                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3202                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3203                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3204
3205                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3206                         tile_width = 128;
3207                 else
3208                         tile_width = 512;
3209
3210                 /* Note: pitch better be a power of two tile widths */
3211                 pitch_val = obj->stride / tile_width;
3212                 pitch_val = ffs(pitch_val) - 1;
3213
3214                 val = i915_gem_obj_ggtt_offset(obj);
3215                 if (obj->tiling_mode == I915_TILING_Y)
3216                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3217                 val |= I915_FENCE_SIZE_BITS(size);
3218                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3219                 val |= I830_FENCE_REG_VALID;
3220         } else
3221                 val = 0;
3222
3223         if (reg < 8)
3224                 reg = FENCE_REG_830_0 + reg * 4;
3225         else
3226                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3227
3228         I915_WRITE(reg, val);
3229         POSTING_READ(reg);
3230 }
3231
3232 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3233                                 struct drm_i915_gem_object *obj)
3234 {
3235         struct drm_i915_private *dev_priv = dev->dev_private;
3236         uint32_t val;
3237
3238         if (obj) {
3239                 u32 size = i915_gem_obj_ggtt_size(obj);
3240                 uint32_t pitch_val;
3241
3242                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3243                      (size & -size) != size ||
3244                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3245                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3246                      i915_gem_obj_ggtt_offset(obj), size);
3247
3248                 pitch_val = obj->stride / 128;
3249                 pitch_val = ffs(pitch_val) - 1;
3250
3251                 val = i915_gem_obj_ggtt_offset(obj);
3252                 if (obj->tiling_mode == I915_TILING_Y)
3253                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3254                 val |= I830_FENCE_SIZE_BITS(size);
3255                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3256                 val |= I830_FENCE_REG_VALID;
3257         } else
3258                 val = 0;
3259
3260         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3261         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3262 }
3263
3264 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3265 {
3266         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3267 }
3268
3269 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3270                                  struct drm_i915_gem_object *obj)
3271 {
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274         /* Ensure that all CPU reads are completed before installing a fence
3275          * and all writes before removing the fence.
3276          */
3277         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3278                 mb();
3279
3280         WARN(obj && (!obj->stride || !obj->tiling_mode),
3281              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3282              obj->stride, obj->tiling_mode);
3283
3284         if (IS_GEN2(dev))
3285                 i830_write_fence_reg(dev, reg, obj);
3286         else if (IS_GEN3(dev))
3287                 i915_write_fence_reg(dev, reg, obj);
3288         else if (INTEL_INFO(dev)->gen >= 4)
3289                 i965_write_fence_reg(dev, reg, obj);
3290
3291         /* And similarly be paranoid that no direct access to this region
3292          * is reordered to before the fence is installed.
3293          */
3294         if (i915_gem_object_needs_mb(obj))
3295                 mb();
3296 }
3297
3298 static inline int fence_number(struct drm_i915_private *dev_priv,
3299                                struct drm_i915_fence_reg *fence)
3300 {
3301         return fence - dev_priv->fence_regs;
3302 }
3303
3304 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3305                                          struct drm_i915_fence_reg *fence,
3306                                          bool enable)
3307 {
3308         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3309         int reg = fence_number(dev_priv, fence);
3310
3311         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3312
3313         if (enable) {
3314                 obj->fence_reg = reg;
3315                 fence->obj = obj;
3316                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3317         } else {
3318                 obj->fence_reg = I915_FENCE_REG_NONE;
3319                 fence->obj = NULL;
3320                 list_del_init(&fence->lru_list);
3321         }
3322         obj->fence_dirty = false;
3323 }
3324
3325 static int
3326 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3327 {
3328         if (obj->last_fenced_req) {
3329                 int ret = i915_wait_request(obj->last_fenced_req);
3330                 if (ret)
3331                         return ret;
3332
3333                 i915_gem_request_assign(&obj->last_fenced_req, NULL);
3334         }
3335
3336         return 0;
3337 }
3338
3339 int
3340 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3341 {
3342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3343         struct drm_i915_fence_reg *fence;
3344         int ret;
3345
3346         ret = i915_gem_object_wait_fence(obj);
3347         if (ret)
3348                 return ret;
3349
3350         if (obj->fence_reg == I915_FENCE_REG_NONE)
3351                 return 0;
3352
3353         fence = &dev_priv->fence_regs[obj->fence_reg];
3354
3355         if (WARN_ON(fence->pin_count))
3356                 return -EBUSY;
3357
3358         i915_gem_object_fence_lost(obj);
3359         i915_gem_object_update_fence(obj, fence, false);
3360
3361         return 0;
3362 }
3363
3364 static struct drm_i915_fence_reg *
3365 i915_find_fence_reg(struct drm_device *dev)
3366 {
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         struct drm_i915_fence_reg *reg, *avail;
3369         int i;
3370
3371         /* First try to find a free reg */
3372         avail = NULL;
3373         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3374                 reg = &dev_priv->fence_regs[i];
3375                 if (!reg->obj)
3376                         return reg;
3377
3378                 if (!reg->pin_count)
3379                         avail = reg;
3380         }
3381
3382         if (avail == NULL)
3383                 goto deadlock;
3384
3385         /* None available, try to steal one or wait for a user to finish */
3386         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3387                 if (reg->pin_count)
3388                         continue;
3389
3390                 return reg;
3391         }
3392
3393 deadlock:
3394         /* Wait for completion of pending flips which consume fences */
3395         if (intel_has_pending_fb_unpin(dev))
3396                 return ERR_PTR(-EAGAIN);
3397
3398         return ERR_PTR(-EDEADLK);
3399 }
3400
3401 /**
3402  * i915_gem_object_get_fence - set up fencing for an object
3403  * @obj: object to map through a fence reg
3404  *
3405  * When mapping objects through the GTT, userspace wants to be able to write
3406  * to them without having to worry about swizzling if the object is tiled.
3407  * This function walks the fence regs looking for a free one for @obj,
3408  * stealing one if it can't find any.
3409  *
3410  * It then sets up the reg based on the object's properties: address, pitch
3411  * and tiling format.
3412  *
3413  * For an untiled surface, this removes any existing fence.
3414  */
3415 int
3416 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3417 {
3418         struct drm_device *dev = obj->base.dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         bool enable = obj->tiling_mode != I915_TILING_NONE;
3421         struct drm_i915_fence_reg *reg;
3422         int ret;
3423
3424         /* Have we updated the tiling parameters upon the object and so
3425          * will need to serialise the write to the associated fence register?
3426          */
3427         if (obj->fence_dirty) {
3428                 ret = i915_gem_object_wait_fence(obj);
3429                 if (ret)
3430                         return ret;
3431         }
3432
3433         /* Just update our place in the LRU if our fence is getting reused. */
3434         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3435                 reg = &dev_priv->fence_regs[obj->fence_reg];
3436                 if (!obj->fence_dirty) {
3437                         list_move_tail(&reg->lru_list,
3438                                        &dev_priv->mm.fence_list);
3439                         return 0;
3440                 }
3441         } else if (enable) {
3442                 if (WARN_ON(!obj->map_and_fenceable))
3443                         return -EINVAL;
3444
3445                 reg = i915_find_fence_reg(dev);
3446                 if (IS_ERR(reg))
3447                         return PTR_ERR(reg);
3448
3449                 if (reg->obj) {
3450                         struct drm_i915_gem_object *old = reg->obj;
3451
3452                         ret = i915_gem_object_wait_fence(old);
3453                         if (ret)
3454                                 return ret;
3455
3456                         i915_gem_object_fence_lost(old);
3457                 }
3458         } else
3459                 return 0;
3460
3461         i915_gem_object_update_fence(obj, reg, enable);
3462
3463         return 0;
3464 }
3465
3466 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3467                                      unsigned long cache_level)
3468 {
3469         struct drm_mm_node *gtt_space = &vma->node;
3470         struct drm_mm_node *other;
3471
3472         /*
3473          * On some machines we have to be careful when putting differing types
3474          * of snoopable memory together to avoid the prefetcher crossing memory
3475          * domains and dying. During vm initialisation, we decide whether or not
3476          * these constraints apply and set the drm_mm.color_adjust
3477          * appropriately.
3478          */
3479         if (vma->vm->mm.color_adjust == NULL)
3480                 return true;
3481
3482         if (!drm_mm_node_allocated(gtt_space))
3483                 return true;
3484
3485         if (list_empty(&gtt_space->node_list))
3486                 return true;
3487
3488         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3489         if (other->allocated && !other->hole_follows && other->color != cache_level)
3490                 return false;
3491
3492         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3493         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3494                 return false;
3495
3496         return true;
3497 }
3498
3499 /**
3500  * Finds free space in the GTT aperture and binds the object there.
3501  */
3502 static struct i915_vma *
3503 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3504                            struct i915_address_space *vm,
3505                            const struct i915_ggtt_view *ggtt_view,
3506                            unsigned alignment,
3507                            uint64_t flags)
3508 {
3509         struct drm_device *dev = obj->base.dev;
3510         struct drm_i915_private *dev_priv = dev->dev_private;
3511         u32 size, fence_size, fence_alignment, unfenced_alignment;
3512         unsigned long start =
3513                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3514         unsigned long end =
3515                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3516         struct i915_vma *vma;
3517         int ret;
3518
3519         if(WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3520                 return ERR_PTR(-EINVAL);
3521
3522         fence_size = i915_gem_get_gtt_size(dev,
3523                                            obj->base.size,
3524                                            obj->tiling_mode);
3525         fence_alignment = i915_gem_get_gtt_alignment(dev,
3526                                                      obj->base.size,
3527                                                      obj->tiling_mode, true);
3528         unfenced_alignment =
3529                 i915_gem_get_gtt_alignment(dev,
3530                                            obj->base.size,
3531                                            obj->tiling_mode, false);
3532
3533         if (alignment == 0)
3534                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3535                                                 unfenced_alignment;
3536         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3537                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3538                 return ERR_PTR(-EINVAL);
3539         }
3540
3541         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3542
3543         /* If the object is bigger than the entire aperture, reject it early
3544          * before evicting everything in a vain attempt to find space.
3545          */
3546         if (obj->base.size > end) {
3547                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3548                           obj->base.size,
3549                           flags & PIN_MAPPABLE ? "mappable" : "total",
3550                           end);
3551                 return ERR_PTR(-E2BIG);
3552         }
3553
3554         ret = i915_gem_object_get_pages(obj);
3555         if (ret)
3556                 return ERR_PTR(ret);
3557
3558         i915_gem_object_pin_pages(obj);
3559
3560         vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3561                           i915_gem_obj_lookup_or_create_vma(obj, vm);
3562
3563         if (IS_ERR(vma))
3564                 goto err_unpin;
3565
3566 search_free:
3567         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3568                                                   size, alignment,
3569                                                   obj->cache_level,
3570                                                   start, end,
3571                                                   DRM_MM_SEARCH_DEFAULT,
3572                                                   DRM_MM_CREATE_DEFAULT);
3573         if (ret) {
3574                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3575                                                obj->cache_level,
3576                                                start, end,
3577                                                flags);
3578                 if (ret == 0)
3579                         goto search_free;
3580
3581                 goto err_free_vma;
3582         }
3583         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3584                 ret = -EINVAL;
3585                 goto err_remove_node;
3586         }
3587
3588         ret = i915_gem_gtt_prepare_object(obj);
3589         if (ret)
3590                 goto err_remove_node;
3591
3592         trace_i915_vma_bind(vma, flags);
3593         ret = i915_vma_bind(vma, obj->cache_level, flags);
3594         if (ret)
3595                 goto err_finish_gtt;
3596
3597         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3598         list_add_tail(&vma->mm_list, &vm->inactive_list);
3599
3600         return vma;
3601
3602 err_finish_gtt:
3603         i915_gem_gtt_finish_object(obj);
3604 err_remove_node:
3605         drm_mm_remove_node(&vma->node);
3606 err_free_vma:
3607         i915_gem_vma_destroy(vma);
3608         vma = ERR_PTR(ret);
3609 err_unpin:
3610         i915_gem_object_unpin_pages(obj);
3611         return vma;
3612 }
3613
3614 bool
3615 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3616                         bool force)
3617 {
3618         /* If we don't have a page list set up, then we're not pinned
3619          * to GPU, and we can ignore the cache flush because it'll happen
3620          * again at bind time.
3621          */
3622         if (obj->pages == NULL)
3623                 return false;
3624
3625         /*
3626          * Stolen memory is always coherent with the GPU as it is explicitly
3627          * marked as wc by the system, or the system is cache-coherent.
3628          */
3629         if (obj->stolen || obj->phys_handle)
3630                 return false;
3631
3632         /* If the GPU is snooping the contents of the CPU cache,
3633          * we do not need to manually clear the CPU cache lines.  However,
3634          * the caches are only snooped when the render cache is
3635          * flushed/invalidated.  As we always have to emit invalidations
3636          * and flushes when moving into and out of the RENDER domain, correct
3637          * snooping behaviour occurs naturally as the result of our domain
3638          * tracking.
3639          */
3640         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3641                 obj->cache_dirty = true;
3642                 return false;
3643         }
3644
3645         trace_i915_gem_object_clflush(obj);
3646         drm_clflush_sg(obj->pages);
3647         obj->cache_dirty = false;
3648
3649         return true;
3650 }
3651
3652 /** Flushes the GTT write domain for the object if it's dirty. */
3653 static void
3654 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3655 {
3656         uint32_t old_write_domain;
3657
3658         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3659                 return;
3660
3661         /* No actual flushing is required for the GTT write domain.  Writes
3662          * to it immediately go to main memory as far as we know, so there's
3663          * no chipset flush.  It also doesn't land in render cache.
3664          *
3665          * However, we do have to enforce the order so that all writes through
3666          * the GTT land before any writes to the device, such as updates to
3667          * the GATT itself.
3668          */
3669         wmb();
3670
3671         old_write_domain = obj->base.write_domain;
3672         obj->base.write_domain = 0;
3673
3674         intel_fb_obj_flush(obj, false);
3675
3676         trace_i915_gem_object_change_domain(obj,
3677                                             obj->base.read_domains,
3678                                             old_write_domain);
3679 }
3680
3681 /** Flushes the CPU write domain for the object if it's dirty. */
3682 static void
3683 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3684 {
3685         uint32_t old_write_domain;
3686
3687         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3688                 return;
3689
3690         if (i915_gem_clflush_object(obj, obj->pin_display))
3691                 i915_gem_chipset_flush(obj->base.dev);
3692
3693         old_write_domain = obj->base.write_domain;
3694         obj->base.write_domain = 0;
3695
3696         intel_fb_obj_flush(obj, false);
3697
3698         trace_i915_gem_object_change_domain(obj,
3699                                             obj->base.read_domains,
3700                                             old_write_domain);
3701 }
3702
3703 /**
3704  * Moves a single object to the GTT read, and possibly write domain.
3705  *
3706  * This function returns when the move is complete, including waiting on
3707  * flushes to occur.
3708  */
3709 int
3710 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3711 {
3712         uint32_t old_write_domain, old_read_domains;
3713         struct i915_vma *vma;
3714         int ret;
3715
3716         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3717                 return 0;
3718
3719         ret = i915_gem_object_wait_rendering(obj, !write);
3720         if (ret)
3721                 return ret;
3722
3723         i915_gem_object_retire(obj);
3724
3725         /* Flush and acquire obj->pages so that we are coherent through
3726          * direct access in memory with previous cached writes through
3727          * shmemfs and that our cache domain tracking remains valid.
3728          * For example, if the obj->filp was moved to swap without us
3729          * being notified and releasing the pages, we would mistakenly
3730          * continue to assume that the obj remained out of the CPU cached
3731          * domain.
3732          */
3733         ret = i915_gem_object_get_pages(obj);
3734         if (ret)
3735                 return ret;
3736
3737         i915_gem_object_flush_cpu_write_domain(obj);
3738
3739         /* Serialise direct access to this object with the barriers for
3740          * coherent writes from the GPU, by effectively invalidating the
3741          * GTT domain upon first access.
3742          */
3743         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3744                 mb();
3745
3746         old_write_domain = obj->base.write_domain;
3747         old_read_domains = obj->base.read_domains;
3748
3749         /* It should now be out of any other write domains, and we can update
3750          * the domain values for our changes.
3751          */
3752         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3753         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3754         if (write) {
3755                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3756                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3757                 obj->dirty = 1;
3758         }
3759
3760         if (write)
3761                 intel_fb_obj_invalidate(obj, NULL, ORIGIN_GTT);
3762
3763         trace_i915_gem_object_change_domain(obj,
3764                                             old_read_domains,
3765                                             old_write_domain);
3766
3767         /* And bump the LRU for this access */
3768         vma = i915_gem_obj_to_ggtt(obj);
3769         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3770                 list_move_tail(&vma->mm_list,
3771                                &to_i915(obj->base.dev)->gtt.base.inactive_list);
3772
3773         return 0;
3774 }
3775
3776 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3777                                     enum i915_cache_level cache_level)
3778 {
3779         struct drm_device *dev = obj->base.dev;
3780         struct i915_vma *vma, *next;
3781         int ret;
3782
3783         if (obj->cache_level == cache_level)
3784                 return 0;
3785
3786         if (i915_gem_obj_is_pinned(obj)) {
3787                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3788                 return -EBUSY;
3789         }
3790
3791         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3792                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3793                         ret = i915_vma_unbind(vma);
3794                         if (ret)
3795                                 return ret;
3796                 }
3797         }
3798
3799         if (i915_gem_obj_bound_any(obj)) {
3800                 ret = i915_gem_object_finish_gpu(obj);
3801                 if (ret)
3802                         return ret;
3803
3804                 i915_gem_object_finish_gtt(obj);
3805
3806                 /* Before SandyBridge, you could not use tiling or fence
3807                  * registers with snooped memory, so relinquish any fences
3808                  * currently pointing to our region in the aperture.
3809                  */
3810                 if (INTEL_INFO(dev)->gen < 6) {
3811                         ret = i915_gem_object_put_fence(obj);
3812                         if (ret)
3813                                 return ret;
3814                 }
3815
3816                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3817                         if (drm_mm_node_allocated(&vma->node)) {
3818                                 ret = i915_vma_bind(vma, cache_level,
3819                                                     PIN_UPDATE);
3820                                 if (ret)
3821                                         return ret;
3822                         }
3823         }
3824
3825         list_for_each_entry(vma, &obj->vma_list, vma_link)
3826                 vma->node.color = cache_level;
3827         obj->cache_level = cache_level;
3828
3829         if (obj->cache_dirty &&
3830             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3831             cpu_write_needs_clflush(obj)) {
3832                 if (i915_gem_clflush_object(obj, true))
3833                         i915_gem_chipset_flush(obj->base.dev);
3834         }
3835
3836         return 0;
3837 }
3838
3839 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3840                                struct drm_file *file)
3841 {
3842         struct drm_i915_gem_caching *args = data;
3843         struct drm_i915_gem_object *obj;
3844         int ret;
3845
3846         ret = i915_mutex_lock_interruptible(dev);
3847         if (ret)
3848                 return ret;
3849
3850         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3851         if (&obj->base == NULL) {
3852                 ret = -ENOENT;
3853                 goto unlock;
3854         }
3855
3856         switch (obj->cache_level) {
3857         case I915_CACHE_LLC:
3858         case I915_CACHE_L3_LLC:
3859                 args->caching = I915_CACHING_CACHED;
3860                 break;
3861
3862         case I915_CACHE_WT:
3863                 args->caching = I915_CACHING_DISPLAY;
3864                 break;
3865
3866         default:
3867                 args->caching = I915_CACHING_NONE;
3868                 break;
3869         }
3870
3871         drm_gem_object_unreference(&obj->base);
3872 unlock:
3873         mutex_unlock(&dev->struct_mutex);
3874         return ret;
3875 }
3876
3877 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3878                                struct drm_file *file)
3879 {
3880         struct drm_i915_gem_caching *args = data;
3881         struct drm_i915_gem_object *obj;
3882         enum i915_cache_level level;
3883         int ret;
3884
3885         switch (args->caching) {
3886         case I915_CACHING_NONE:
3887                 level = I915_CACHE_NONE;
3888                 break;
3889         case I915_CACHING_CACHED:
3890                 level = I915_CACHE_LLC;
3891                 break;
3892         case I915_CACHING_DISPLAY:
3893                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3894                 break;
3895         default:
3896                 return -EINVAL;
3897         }
3898
3899         ret = i915_mutex_lock_interruptible(dev);
3900         if (ret)
3901                 return ret;
3902
3903         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3904         if (&obj->base == NULL) {
3905                 ret = -ENOENT;
3906                 goto unlock;
3907         }
3908
3909         ret = i915_gem_object_set_cache_level(obj, level);
3910
3911         drm_gem_object_unreference(&obj->base);
3912 unlock:
3913         mutex_unlock(&dev->struct_mutex);
3914         return ret;
3915 }
3916
3917 /*
3918  * Prepare buffer for display plane (scanout, cursors, etc).
3919  * Can be called from an uninterruptible phase (modesetting) and allows
3920  * any flushes to be pipelined (for pageflips).
3921  */
3922 int
3923 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3924                                      u32 alignment,
3925                                      struct intel_engine_cs *pipelined,
3926                                      const struct i915_ggtt_view *view)
3927 {
3928         u32 old_read_domains, old_write_domain;
3929         int ret;
3930
3931         if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) {
3932                 ret = i915_gem_object_sync(obj, pipelined);
3933                 if (ret)
3934                         return ret;
3935         }
3936
3937         /* Mark the pin_display early so that we account for the
3938          * display coherency whilst setting up the cache domains.
3939          */
3940         obj->pin_display++;
3941
3942         /* The display engine is not coherent with the LLC cache on gen6.  As
3943          * a result, we make sure that the pinning that is about to occur is
3944          * done with uncached PTEs. This is lowest common denominator for all
3945          * chipsets.
3946          *
3947          * However for gen6+, we could do better by using the GFDT bit instead
3948          * of uncaching, which would allow us to flush all the LLC-cached data
3949          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3950          */
3951         ret = i915_gem_object_set_cache_level(obj,
3952                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3953         if (ret)
3954                 goto err_unpin_display;
3955
3956         /* As the user may map the buffer once pinned in the display plane
3957          * (e.g. libkms for the bootup splash), we have to ensure that we
3958          * always use map_and_fenceable for all scanout buffers.
3959          */
3960         ret = i915_gem_object_ggtt_pin(obj, view, alignment,
3961                                        view->type == I915_GGTT_VIEW_NORMAL ?
3962                                        PIN_MAPPABLE : 0);
3963         if (ret)
3964                 goto err_unpin_display;
3965
3966         i915_gem_object_flush_cpu_write_domain(obj);
3967
3968         old_write_domain = obj->base.write_domain;
3969         old_read_domains = obj->base.read_domains;
3970
3971         /* It should now be out of any other write domains, and we can update
3972          * the domain values for our changes.
3973          */
3974         obj->base.write_domain = 0;
3975         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3976
3977         trace_i915_gem_object_change_domain(obj,
3978                                             old_read_domains,
3979                                             old_write_domain);
3980
3981         return 0;
3982
3983 err_unpin_display:
3984         obj->pin_display--;
3985         return ret;
3986 }
3987
3988 void
3989 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3990                                          const struct i915_ggtt_view *view)
3991 {
3992         if (WARN_ON(obj->pin_display == 0))
3993                 return;
3994
3995         i915_gem_object_ggtt_unpin_view(obj, view);
3996
3997         obj->pin_display--;
3998 }
3999
4000 int
4001 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4002 {
4003         int ret;
4004
4005         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4006                 return 0;
4007
4008         ret = i915_gem_object_wait_rendering(obj, false);
4009         if (ret)
4010                 return ret;
4011
4012         /* Ensure that we invalidate the GPU's caches and TLBs. */
4013         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4014         return 0;
4015 }
4016
4017 /**
4018  * Moves a single object to the CPU read, and possibly write domain.
4019  *
4020  * This function returns when the move is complete, including waiting on
4021  * flushes to occur.
4022  */
4023 int
4024 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4025 {
4026         uint32_t old_write_domain, old_read_domains;
4027         int ret;
4028
4029         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4030                 return 0;
4031
4032         ret = i915_gem_object_wait_rendering(obj, !write);
4033         if (ret)
4034                 return ret;
4035
4036         i915_gem_object_retire(obj);
4037         i915_gem_object_flush_gtt_write_domain(obj);
4038
4039         old_write_domain = obj->base.write_domain;
4040         old_read_domains = obj->base.read_domains;
4041
4042         /* Flush the CPU cache if it's still invalid. */
4043         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4044                 i915_gem_clflush_object(obj, false);
4045
4046                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4047         }
4048
4049         /* It should now be out of any other write domains, and we can update
4050          * the domain values for our changes.
4051          */
4052         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4053
4054         /* If we're writing through the CPU, then the GPU read domains will
4055          * need to be invalidated at next use.
4056          */
4057         if (write) {
4058                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4059                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4060         }
4061
4062         if (write)
4063                 intel_fb_obj_invalidate(obj, NULL, ORIGIN_CPU);
4064
4065         trace_i915_gem_object_change_domain(obj,
4066                                             old_read_domains,
4067                                             old_write_domain);
4068
4069         return 0;
4070 }
4071
4072 /* Throttle our rendering by waiting until the ring has completed our requests
4073  * emitted over 20 msec ago.
4074  *
4075  * Note that if we were to use the current jiffies each time around the loop,
4076  * we wouldn't escape the function with any frames outstanding if the time to
4077  * render a frame was over 20ms.
4078  *
4079  * This should get us reasonable parallelism between CPU and GPU but also
4080  * relatively low latency when blocking on a particular request to finish.
4081  */
4082 static int
4083 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4084 {
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         struct drm_i915_file_private *file_priv = file->driver_priv;
4087         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4088         struct drm_i915_gem_request *request, *target = NULL;
4089         unsigned reset_counter;
4090         int ret;
4091
4092         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4093         if (ret)
4094                 return ret;
4095
4096         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4097         if (ret)
4098                 return ret;
4099
4100         spin_lock(&file_priv->mm.lock);
4101         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4102                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4103                         break;
4104
4105                 target = request;
4106         }
4107         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4108         if (target)
4109                 i915_gem_request_reference(target);
4110         spin_unlock(&file_priv->mm.lock);
4111
4112         if (target == NULL)
4113                 return 0;
4114
4115         ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
4116         if (ret == 0)
4117                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4118
4119         i915_gem_request_unreference__unlocked(target);
4120
4121         return ret;
4122 }
4123
4124 static bool
4125 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4126 {
4127         struct drm_i915_gem_object *obj = vma->obj;
4128
4129         if (alignment &&
4130             vma->node.start & (alignment - 1))
4131                 return true;
4132
4133         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4134                 return true;
4135
4136         if (flags & PIN_OFFSET_BIAS &&
4137             vma->node.start < (flags & PIN_OFFSET_MASK))
4138                 return true;
4139
4140         return false;
4141 }
4142
4143 static int
4144 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4145                        struct i915_address_space *vm,
4146                        const struct i915_ggtt_view *ggtt_view,
4147                        uint32_t alignment,
4148                        uint64_t flags)
4149 {
4150         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4151         struct i915_vma *vma;
4152         unsigned bound;
4153         int ret;
4154
4155         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4156                 return -ENODEV;
4157
4158         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4159                 return -EINVAL;
4160
4161         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4162                 return -EINVAL;
4163
4164         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4165                 return -EINVAL;
4166
4167         vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4168                           i915_gem_obj_to_vma(obj, vm);
4169
4170         if (IS_ERR(vma))
4171                 return PTR_ERR(vma);
4172
4173         if (vma) {
4174                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4175                         return -EBUSY;
4176
4177                 if (i915_vma_misplaced(vma, alignment, flags)) {
4178                         unsigned long offset;
4179                         offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) :
4180                                              i915_gem_obj_offset(obj, vm);
4181                         WARN(vma->pin_count,
4182                              "bo is already pinned in %s with incorrect alignment:"
4183                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4184                              " obj->map_and_fenceable=%d\n",
4185                              ggtt_view ? "ggtt" : "ppgtt",
4186                              offset,
4187                              alignment,
4188                              !!(flags & PIN_MAPPABLE),
4189                              obj->map_and_fenceable);
4190                         ret = i915_vma_unbind(vma);
4191                         if (ret)
4192                                 return ret;
4193
4194                         vma = NULL;
4195                 }
4196         }
4197
4198         bound = vma ? vma->bound : 0;
4199         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4200                 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4201                                                  flags);
4202                 if (IS_ERR(vma))
4203                         return PTR_ERR(vma);
4204         } else {
4205                 ret = i915_vma_bind(vma, obj->cache_level, flags);
4206                 if (ret)
4207                         return ret;
4208         }
4209
4210         if ((bound ^ vma->bound) & GLOBAL_BIND) {
4211                 bool mappable, fenceable;
4212                 u32 fence_size, fence_alignment;
4213
4214                 fence_size = i915_gem_get_gtt_size(obj->base.dev,
4215                                                    obj->base.size,
4216                                                    obj->tiling_mode);
4217                 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4218                                                              obj->base.size,
4219                                                              obj->tiling_mode,
4220                                                              true);
4221
4222                 fenceable = (vma->node.size == fence_size &&
4223                              (vma->node.start & (fence_alignment - 1)) == 0);
4224
4225                 mappable = (vma->node.start + fence_size <=
4226                             dev_priv->gtt.mappable_end);
4227
4228                 obj->map_and_fenceable = mappable && fenceable;
4229         }
4230
4231         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4232
4233         vma->pin_count++;
4234         return 0;
4235 }
4236
4237 int
4238 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4239                     struct i915_address_space *vm,
4240                     uint32_t alignment,
4241                     uint64_t flags)
4242 {
4243         return i915_gem_object_do_pin(obj, vm,
4244                                       i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4245                                       alignment, flags);
4246 }
4247
4248 int
4249 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4250                          const struct i915_ggtt_view *view,
4251                          uint32_t alignment,
4252                          uint64_t flags)
4253 {
4254         if (WARN_ONCE(!view, "no view specified"))
4255                 return -EINVAL;
4256
4257         return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
4258                                       alignment, flags | PIN_GLOBAL);
4259 }
4260
4261 void
4262 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4263                                 const struct i915_ggtt_view *view)
4264 {
4265         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4266
4267         BUG_ON(!vma);
4268         WARN_ON(vma->pin_count == 0);
4269         WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4270
4271         --vma->pin_count;
4272 }
4273
4274 bool
4275 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4276 {
4277         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4278                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4279                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4280
4281                 WARN_ON(!ggtt_vma ||
4282                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4283                         ggtt_vma->pin_count);
4284                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4285                 return true;
4286         } else
4287                 return false;
4288 }
4289
4290 void
4291 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4292 {
4293         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4294                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4295                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4296                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4297         }
4298 }
4299
4300 int
4301 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4302                     struct drm_file *file)
4303 {
4304         struct drm_i915_gem_busy *args = data;
4305         struct drm_i915_gem_object *obj;
4306         int ret;
4307
4308         ret = i915_mutex_lock_interruptible(dev);
4309         if (ret)
4310                 return ret;
4311
4312         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4313         if (&obj->base == NULL) {
4314                 ret = -ENOENT;
4315                 goto unlock;
4316         }
4317
4318         /* Count all active objects as busy, even if they are currently not used
4319          * by the gpu. Users of this interface expect objects to eventually
4320          * become non-busy without any further actions, therefore emit any
4321          * necessary flushes here.
4322          */
4323         ret = i915_gem_object_flush_active(obj);
4324
4325         args->busy = obj->active;
4326         if (obj->last_read_req) {
4327                 struct intel_engine_cs *ring;
4328                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4329                 ring = i915_gem_request_get_ring(obj->last_read_req);
4330                 args->busy |= intel_ring_flag(ring) << 16;
4331         }
4332
4333         drm_gem_object_unreference(&obj->base);
4334 unlock:
4335         mutex_unlock(&dev->struct_mutex);
4336         return ret;
4337 }
4338
4339 int
4340 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4341                         struct drm_file *file_priv)
4342 {
4343         return i915_gem_ring_throttle(dev, file_priv);
4344 }
4345
4346 int
4347 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4348                        struct drm_file *file_priv)
4349 {
4350         struct drm_i915_private *dev_priv = dev->dev_private;
4351         struct drm_i915_gem_madvise *args = data;
4352         struct drm_i915_gem_object *obj;
4353         int ret;
4354
4355         switch (args->madv) {
4356         case I915_MADV_DONTNEED:
4357         case I915_MADV_WILLNEED:
4358             break;
4359         default:
4360             return -EINVAL;
4361         }
4362
4363         ret = i915_mutex_lock_interruptible(dev);
4364         if (ret)
4365                 return ret;
4366
4367         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4368         if (&obj->base == NULL) {
4369                 ret = -ENOENT;
4370                 goto unlock;
4371         }
4372
4373         if (i915_gem_obj_is_pinned(obj)) {
4374                 ret = -EINVAL;
4375                 goto out;
4376         }
4377
4378         if (obj->pages &&
4379             obj->tiling_mode != I915_TILING_NONE &&
4380             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4381                 if (obj->madv == I915_MADV_WILLNEED)
4382                         i915_gem_object_unpin_pages(obj);
4383                 if (args->madv == I915_MADV_WILLNEED)
4384                         i915_gem_object_pin_pages(obj);
4385         }
4386
4387         if (obj->madv != __I915_MADV_PURGED)
4388                 obj->madv = args->madv;
4389
4390         /* if the object is no longer attached, discard its backing storage */
4391         if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4392                 i915_gem_object_truncate(obj);
4393
4394         args->retained = obj->madv != __I915_MADV_PURGED;
4395
4396 out:
4397         drm_gem_object_unreference(&obj->base);
4398 unlock:
4399         mutex_unlock(&dev->struct_mutex);
4400         return ret;
4401 }
4402
4403 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4404                           const struct drm_i915_gem_object_ops *ops)
4405 {
4406         INIT_LIST_HEAD(&obj->global_list);
4407         INIT_LIST_HEAD(&obj->ring_list);
4408         INIT_LIST_HEAD(&obj->obj_exec_link);
4409         INIT_LIST_HEAD(&obj->vma_list);
4410         INIT_LIST_HEAD(&obj->batch_pool_link);
4411
4412         obj->ops = ops;
4413
4414         obj->fence_reg = I915_FENCE_REG_NONE;
4415         obj->madv = I915_MADV_WILLNEED;
4416
4417         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4418 }
4419
4420 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4421         .get_pages = i915_gem_object_get_pages_gtt,
4422         .put_pages = i915_gem_object_put_pages_gtt,
4423 };
4424
4425 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4426                                                   size_t size)
4427 {
4428         struct drm_i915_gem_object *obj;
4429         struct address_space *mapping;
4430         gfp_t mask;
4431
4432         obj = i915_gem_object_alloc(dev);
4433         if (obj == NULL)
4434                 return NULL;
4435
4436         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4437                 i915_gem_object_free(obj);
4438                 return NULL;
4439         }
4440
4441         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4442         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4443                 /* 965gm cannot relocate objects above 4GiB. */
4444                 mask &= ~__GFP_HIGHMEM;
4445                 mask |= __GFP_DMA32;
4446         }
4447
4448         mapping = file_inode(obj->base.filp)->i_mapping;
4449         mapping_set_gfp_mask(mapping, mask);
4450
4451         i915_gem_object_init(obj, &i915_gem_object_ops);
4452
4453         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4454         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4455
4456         if (HAS_LLC(dev)) {
4457                 /* On some devices, we can have the GPU use the LLC (the CPU
4458                  * cache) for about a 10% performance improvement
4459                  * compared to uncached.  Graphics requests other than
4460                  * display scanout are coherent with the CPU in
4461                  * accessing this cache.  This means in this mode we
4462                  * don't need to clflush on the CPU side, and on the
4463                  * GPU side we only need to flush internal caches to
4464                  * get data visible to the CPU.
4465                  *
4466                  * However, we maintain the display planes as UC, and so
4467                  * need to rebind when first used as such.
4468                  */
4469                 obj->cache_level = I915_CACHE_LLC;
4470         } else
4471                 obj->cache_level = I915_CACHE_NONE;
4472
4473         trace_i915_gem_object_create(obj);
4474
4475         return obj;
4476 }
4477
4478 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4479 {
4480         /* If we are the last user of the backing storage (be it shmemfs
4481          * pages or stolen etc), we know that the pages are going to be
4482          * immediately released. In this case, we can then skip copying
4483          * back the contents from the GPU.
4484          */
4485
4486         if (obj->madv != I915_MADV_WILLNEED)
4487                 return false;
4488
4489         if (obj->base.filp == NULL)
4490                 return true;
4491
4492         /* At first glance, this looks racy, but then again so would be
4493          * userspace racing mmap against close. However, the first external
4494          * reference to the filp can only be obtained through the
4495          * i915_gem_mmap_ioctl() which safeguards us against the user
4496          * acquiring such a reference whilst we are in the middle of
4497          * freeing the object.
4498          */
4499         return atomic_long_read(&obj->base.filp->f_count) == 1;
4500 }
4501
4502 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4503 {
4504         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4505         struct drm_device *dev = obj->base.dev;
4506         struct drm_i915_private *dev_priv = dev->dev_private;
4507         struct i915_vma *vma, *next;
4508
4509         intel_runtime_pm_get(dev_priv);
4510
4511         trace_i915_gem_object_destroy(obj);
4512
4513         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4514                 int ret;
4515
4516                 vma->pin_count = 0;
4517                 ret = i915_vma_unbind(vma);
4518                 if (WARN_ON(ret == -ERESTARTSYS)) {
4519                         bool was_interruptible;
4520
4521                         was_interruptible = dev_priv->mm.interruptible;
4522                         dev_priv->mm.interruptible = false;
4523
4524                         WARN_ON(i915_vma_unbind(vma));
4525
4526                         dev_priv->mm.interruptible = was_interruptible;
4527                 }
4528         }
4529
4530         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4531          * before progressing. */
4532         if (obj->stolen)
4533                 i915_gem_object_unpin_pages(obj);
4534
4535         WARN_ON(obj->frontbuffer_bits);
4536
4537         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4538             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4539             obj->tiling_mode != I915_TILING_NONE)
4540                 i915_gem_object_unpin_pages(obj);
4541
4542         if (WARN_ON(obj->pages_pin_count))
4543                 obj->pages_pin_count = 0;
4544         if (discard_backing_storage(obj))
4545                 obj->madv = I915_MADV_DONTNEED;
4546         i915_gem_object_put_pages(obj);
4547         i915_gem_object_free_mmap_offset(obj);
4548
4549         BUG_ON(obj->pages);
4550
4551         if (obj->base.import_attach)
4552                 drm_prime_gem_destroy(&obj->base, NULL);
4553
4554         if (obj->ops->release)
4555                 obj->ops->release(obj);
4556
4557         drm_gem_object_release(&obj->base);
4558         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4559
4560         kfree(obj->bit_17);
4561         i915_gem_object_free(obj);
4562
4563         intel_runtime_pm_put(dev_priv);
4564 }
4565
4566 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4567                                      struct i915_address_space *vm)
4568 {
4569         struct i915_vma *vma;
4570         list_for_each_entry(vma, &obj->vma_list, vma_link) {
4571                 if (i915_is_ggtt(vma->vm) &&
4572                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
4573                         continue;
4574                 if (vma->vm == vm)
4575                         return vma;
4576         }
4577         return NULL;
4578 }
4579
4580 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4581                                            const struct i915_ggtt_view *view)
4582 {
4583         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
4584         struct i915_vma *vma;
4585
4586         if (WARN_ONCE(!view, "no view specified"))
4587                 return ERR_PTR(-EINVAL);
4588
4589         list_for_each_entry(vma, &obj->vma_list, vma_link)
4590                 if (vma->vm == ggtt &&
4591                     i915_ggtt_view_equal(&vma->ggtt_view, view))
4592                         return vma;
4593         return NULL;
4594 }
4595
4596 void i915_gem_vma_destroy(struct i915_vma *vma)
4597 {
4598         struct i915_address_space *vm = NULL;
4599         WARN_ON(vma->node.allocated);
4600
4601         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4602         if (!list_empty(&vma->exec_list))
4603                 return;
4604
4605         vm = vma->vm;
4606
4607         if (!i915_is_ggtt(vm))
4608                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4609
4610         list_del(&vma->vma_link);
4611
4612         kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4613 }
4614
4615 static void
4616 i915_gem_stop_ringbuffers(struct drm_device *dev)
4617 {
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_engine_cs *ring;
4620         int i;
4621
4622         for_each_ring(ring, dev_priv, i)
4623                 dev_priv->gt.stop_ring(ring);
4624 }
4625
4626 int
4627 i915_gem_suspend(struct drm_device *dev)
4628 {
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630         int ret = 0;
4631
4632         mutex_lock(&dev->struct_mutex);
4633         ret = i915_gpu_idle(dev);
4634         if (ret)
4635                 goto err;
4636
4637         i915_gem_retire_requests(dev);
4638
4639         i915_gem_stop_ringbuffers(dev);
4640         mutex_unlock(&dev->struct_mutex);
4641
4642         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4643         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4644         flush_delayed_work(&dev_priv->mm.idle_work);
4645
4646         /* Assert that we sucessfully flushed all the work and
4647          * reset the GPU back to its idle, low power state.
4648          */
4649         WARN_ON(dev_priv->mm.busy);
4650
4651         return 0;
4652
4653 err:
4654         mutex_unlock(&dev->struct_mutex);
4655         return ret;
4656 }
4657
4658 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4659 {
4660         struct drm_device *dev = ring->dev;
4661         struct drm_i915_private *dev_priv = dev->dev_private;
4662         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4663         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4664         int i, ret;
4665
4666         if (!HAS_L3_DPF(dev) || !remap_info)
4667                 return 0;
4668
4669         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4670         if (ret)
4671                 return ret;
4672
4673         /*
4674          * Note: We do not worry about the concurrent register cacheline hang
4675          * here because no other code should access these registers other than
4676          * at initialization time.
4677          */
4678         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4679                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4680                 intel_ring_emit(ring, reg_base + i);
4681                 intel_ring_emit(ring, remap_info[i/4]);
4682         }
4683
4684         intel_ring_advance(ring);
4685
4686         return ret;
4687 }
4688
4689 void i915_gem_init_swizzling(struct drm_device *dev)
4690 {
4691         struct drm_i915_private *dev_priv = dev->dev_private;
4692
4693         if (INTEL_INFO(dev)->gen < 5 ||
4694             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4695                 return;
4696
4697         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4698                                  DISP_TILE_SURFACE_SWIZZLING);
4699
4700         if (IS_GEN5(dev))
4701                 return;
4702
4703         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4704         if (IS_GEN6(dev))
4705                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4706         else if (IS_GEN7(dev))
4707                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4708         else if (IS_GEN8(dev))
4709                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4710         else
4711                 BUG();
4712 }
4713
4714 static bool
4715 intel_enable_blt(struct drm_device *dev)
4716 {
4717         if (!HAS_BLT(dev))
4718                 return false;
4719
4720         /* The blitter was dysfunctional on early prototypes */
4721         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4722                 DRM_INFO("BLT not supported on this pre-production hardware;"
4723                          " graphics performance will be degraded.\n");
4724                 return false;
4725         }
4726
4727         return true;
4728 }
4729
4730 static void init_unused_ring(struct drm_device *dev, u32 base)
4731 {
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733
4734         I915_WRITE(RING_CTL(base), 0);
4735         I915_WRITE(RING_HEAD(base), 0);
4736         I915_WRITE(RING_TAIL(base), 0);
4737         I915_WRITE(RING_START(base), 0);
4738 }
4739
4740 static void init_unused_rings(struct drm_device *dev)
4741 {
4742         if (IS_I830(dev)) {
4743                 init_unused_ring(dev, PRB1_BASE);
4744                 init_unused_ring(dev, SRB0_BASE);
4745                 init_unused_ring(dev, SRB1_BASE);
4746                 init_unused_ring(dev, SRB2_BASE);
4747                 init_unused_ring(dev, SRB3_BASE);
4748         } else if (IS_GEN2(dev)) {
4749                 init_unused_ring(dev, SRB0_BASE);
4750                 init_unused_ring(dev, SRB1_BASE);
4751         } else if (IS_GEN3(dev)) {
4752                 init_unused_ring(dev, PRB1_BASE);
4753                 init_unused_ring(dev, PRB2_BASE);
4754         }
4755 }
4756
4757 int i915_gem_init_rings(struct drm_device *dev)
4758 {
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760         int ret;
4761
4762         ret = intel_init_render_ring_buffer(dev);
4763         if (ret)
4764                 return ret;
4765
4766         if (HAS_BSD(dev)) {
4767                 ret = intel_init_bsd_ring_buffer(dev);
4768                 if (ret)
4769                         goto cleanup_render_ring;
4770         }
4771
4772         if (intel_enable_blt(dev)) {
4773                 ret = intel_init_blt_ring_buffer(dev);
4774                 if (ret)
4775                         goto cleanup_bsd_ring;
4776         }
4777
4778         if (HAS_VEBOX(dev)) {
4779                 ret = intel_init_vebox_ring_buffer(dev);
4780                 if (ret)
4781                         goto cleanup_blt_ring;
4782         }
4783
4784         if (HAS_BSD2(dev)) {
4785                 ret = intel_init_bsd2_ring_buffer(dev);
4786                 if (ret)
4787                         goto cleanup_vebox_ring;
4788         }
4789
4790         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4791         if (ret)
4792                 goto cleanup_bsd2_ring;
4793
4794         return 0;
4795
4796 cleanup_bsd2_ring:
4797         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4798 cleanup_vebox_ring:
4799         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4800 cleanup_blt_ring:
4801         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4802 cleanup_bsd_ring:
4803         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4804 cleanup_render_ring:
4805         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4806
4807         return ret;
4808 }
4809
4810 int
4811 i915_gem_init_hw(struct drm_device *dev)
4812 {
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         struct intel_engine_cs *ring;
4815         int ret, i;
4816
4817         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4818                 return -EIO;
4819
4820         /* Double layer security blanket, see i915_gem_init() */
4821         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4822
4823         if (dev_priv->ellc_size)
4824                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4825
4826         if (IS_HASWELL(dev))
4827                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4828                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4829
4830         if (HAS_PCH_NOP(dev)) {
4831                 if (IS_IVYBRIDGE(dev)) {
4832                         u32 temp = I915_READ(GEN7_MSG_CTL);
4833                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4834                         I915_WRITE(GEN7_MSG_CTL, temp);
4835                 } else if (INTEL_INFO(dev)->gen >= 7) {
4836                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4837                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4838                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4839                 }
4840         }
4841
4842         i915_gem_init_swizzling(dev);
4843
4844         /*
4845          * At least 830 can leave some of the unused rings
4846          * "active" (ie. head != tail) after resume which
4847          * will prevent c3 entry. Makes sure all unused rings
4848          * are totally idle.
4849          */
4850         init_unused_rings(dev);
4851
4852         for_each_ring(ring, dev_priv, i) {
4853                 ret = ring->init_hw(ring);
4854                 if (ret)
4855                         goto out;
4856         }
4857
4858         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4859                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4860
4861         ret = i915_ppgtt_init_hw(dev);
4862         if (ret && ret != -EIO) {
4863                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4864                 i915_gem_cleanup_ringbuffer(dev);
4865         }
4866
4867         ret = i915_gem_context_enable(dev_priv);
4868         if (ret && ret != -EIO) {
4869                 DRM_ERROR("Context enable failed %d\n", ret);
4870                 i915_gem_cleanup_ringbuffer(dev);
4871
4872                 goto out;
4873         }
4874
4875 out:
4876         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4877         return ret;
4878 }
4879
4880 int i915_gem_init(struct drm_device *dev)
4881 {
4882         struct drm_i915_private *dev_priv = dev->dev_private;
4883         int ret;
4884
4885         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4886                         i915.enable_execlists);
4887
4888         mutex_lock(&dev->struct_mutex);
4889
4890         if (IS_VALLEYVIEW(dev)) {
4891                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4892                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4893                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4894                               VLV_GTLC_ALLOWWAKEACK), 10))
4895                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4896         }
4897
4898         if (!i915.enable_execlists) {
4899                 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4900                 dev_priv->gt.init_rings = i915_gem_init_rings;
4901                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4902                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4903         } else {
4904                 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4905                 dev_priv->gt.init_rings = intel_logical_rings_init;
4906                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4907                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4908         }
4909
4910         /* This is just a security blanket to placate dragons.
4911          * On some systems, we very sporadically observe that the first TLBs
4912          * used by the CS may be stale, despite us poking the TLB reset. If
4913          * we hold the forcewake during initialisation these problems
4914          * just magically go away.
4915          */
4916         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4917
4918         ret = i915_gem_init_userptr(dev);
4919         if (ret)
4920                 goto out_unlock;
4921
4922         i915_gem_init_global_gtt(dev);
4923
4924         ret = i915_gem_context_init(dev);
4925         if (ret)
4926                 goto out_unlock;
4927
4928         ret = dev_priv->gt.init_rings(dev);
4929         if (ret)
4930                 goto out_unlock;
4931
4932         ret = i915_gem_init_hw(dev);
4933         if (ret == -EIO) {
4934                 /* Allow ring initialisation to fail by marking the GPU as
4935                  * wedged. But we only want to do this where the GPU is angry,
4936                  * for all other failure, such as an allocation failure, bail.
4937                  */
4938                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4939                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4940                 ret = 0;
4941         }
4942
4943 out_unlock:
4944         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4945         mutex_unlock(&dev->struct_mutex);
4946
4947         return ret;
4948 }
4949
4950 void
4951 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4952 {
4953         struct drm_i915_private *dev_priv = dev->dev_private;
4954         struct intel_engine_cs *ring;
4955         int i;
4956
4957         for_each_ring(ring, dev_priv, i)
4958                 dev_priv->gt.cleanup_ring(ring);
4959 }
4960
4961 static void
4962 init_ring_lists(struct intel_engine_cs *ring)
4963 {
4964         INIT_LIST_HEAD(&ring->active_list);
4965         INIT_LIST_HEAD(&ring->request_list);
4966 }
4967
4968 void i915_init_vm(struct drm_i915_private *dev_priv,
4969                   struct i915_address_space *vm)
4970 {
4971         if (!i915_is_ggtt(vm))
4972                 drm_mm_init(&vm->mm, vm->start, vm->total);
4973         vm->dev = dev_priv->dev;
4974         INIT_LIST_HEAD(&vm->active_list);
4975         INIT_LIST_HEAD(&vm->inactive_list);
4976         INIT_LIST_HEAD(&vm->global_link);
4977         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4978 }
4979
4980 void
4981 i915_gem_load(struct drm_device *dev)
4982 {
4983         struct drm_i915_private *dev_priv = dev->dev_private;
4984         int i;
4985
4986         dev_priv->objects =
4987                 kmem_cache_create("i915_gem_object",
4988                                   sizeof(struct drm_i915_gem_object), 0,
4989                                   SLAB_HWCACHE_ALIGN,
4990                                   NULL);
4991         dev_priv->vmas =
4992                 kmem_cache_create("i915_gem_vma",
4993                                   sizeof(struct i915_vma), 0,
4994                                   SLAB_HWCACHE_ALIGN,
4995                                   NULL);
4996         dev_priv->requests =
4997                 kmem_cache_create("i915_gem_request",
4998                                   sizeof(struct drm_i915_gem_request), 0,
4999                                   SLAB_HWCACHE_ALIGN,
5000                                   NULL);
5001
5002         INIT_LIST_HEAD(&dev_priv->vm_list);
5003         i915_init_vm(dev_priv, &dev_priv->gtt.base);
5004
5005         INIT_LIST_HEAD(&dev_priv->context_list);
5006         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5007         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5008         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5009         for (i = 0; i < I915_NUM_RINGS; i++)
5010                 init_ring_lists(&dev_priv->ring[i]);
5011         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5012                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5013         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5014                           i915_gem_retire_work_handler);
5015         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5016                           i915_gem_idle_work_handler);
5017         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5018
5019         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5020
5021         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
5022                 dev_priv->num_fence_regs = 32;
5023         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5024                 dev_priv->num_fence_regs = 16;
5025         else
5026                 dev_priv->num_fence_regs = 8;
5027
5028         if (intel_vgpu_active(dev))
5029                 dev_priv->num_fence_regs =
5030                                 I915_READ(vgtif_reg(avail_rs.fence_num));
5031
5032         /* Initialize fence registers to zero */
5033         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5034         i915_gem_restore_fences(dev);
5035
5036         i915_gem_detect_bit_6_swizzle(dev);
5037         init_waitqueue_head(&dev_priv->pending_flip_queue);
5038
5039         dev_priv->mm.interruptible = true;
5040
5041         i915_gem_shrinker_init(dev_priv);
5042
5043         mutex_init(&dev_priv->fb_tracking.lock);
5044 }
5045
5046 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5047 {
5048         struct drm_i915_file_private *file_priv = file->driver_priv;
5049
5050         /* Clean up our request list when the client is going away, so that
5051          * later retire_requests won't dereference our soon-to-be-gone
5052          * file_priv.
5053          */
5054         spin_lock(&file_priv->mm.lock);
5055         while (!list_empty(&file_priv->mm.request_list)) {
5056                 struct drm_i915_gem_request *request;
5057
5058                 request = list_first_entry(&file_priv->mm.request_list,
5059                                            struct drm_i915_gem_request,
5060                                            client_list);
5061                 list_del(&request->client_list);
5062                 request->file_priv = NULL;
5063         }
5064         spin_unlock(&file_priv->mm.lock);
5065
5066         if (!list_empty(&file_priv->rps_boost)) {
5067                 mutex_lock(&to_i915(dev)->rps.hw_lock);
5068                 list_del(&file_priv->rps_boost);
5069                 mutex_unlock(&to_i915(dev)->rps.hw_lock);
5070         }
5071 }
5072
5073 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5074 {
5075         struct drm_i915_file_private *file_priv;
5076         int ret;
5077
5078         DRM_DEBUG_DRIVER("\n");
5079
5080         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5081         if (!file_priv)
5082                 return -ENOMEM;
5083
5084         file->driver_priv = file_priv;
5085         file_priv->dev_priv = dev->dev_private;
5086         file_priv->file = file;
5087         INIT_LIST_HEAD(&file_priv->rps_boost);
5088
5089         spin_lock_init(&file_priv->mm.lock);
5090         INIT_LIST_HEAD(&file_priv->mm.request_list);
5091
5092         ret = i915_gem_context_open(dev, file);
5093         if (ret)
5094                 kfree(file_priv);
5095
5096         return ret;
5097 }
5098
5099 /**
5100  * i915_gem_track_fb - update frontbuffer tracking
5101  * old: current GEM buffer for the frontbuffer slots
5102  * new: new GEM buffer for the frontbuffer slots
5103  * frontbuffer_bits: bitmask of frontbuffer slots
5104  *
5105  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5106  * from @old and setting them in @new. Both @old and @new can be NULL.
5107  */
5108 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5109                        struct drm_i915_gem_object *new,
5110                        unsigned frontbuffer_bits)
5111 {
5112         if (old) {
5113                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5114                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5115                 old->frontbuffer_bits &= ~frontbuffer_bits;
5116         }
5117
5118         if (new) {
5119                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5120                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5121                 new->frontbuffer_bits |= frontbuffer_bits;
5122         }
5123 }
5124
5125 /* All the new VM stuff */
5126 unsigned long
5127 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5128                     struct i915_address_space *vm)
5129 {
5130         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5131         struct i915_vma *vma;
5132
5133         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5134
5135         list_for_each_entry(vma, &o->vma_list, vma_link) {
5136                 if (i915_is_ggtt(vma->vm) &&
5137                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5138                         continue;
5139                 if (vma->vm == vm)
5140                         return vma->node.start;
5141         }
5142
5143         WARN(1, "%s vma for this object not found.\n",
5144              i915_is_ggtt(vm) ? "global" : "ppgtt");
5145         return -1;
5146 }
5147
5148 unsigned long
5149 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5150                               const struct i915_ggtt_view *view)
5151 {
5152         struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5153         struct i915_vma *vma;
5154
5155         list_for_each_entry(vma, &o->vma_list, vma_link)
5156                 if (vma->vm == ggtt &&
5157                     i915_ggtt_view_equal(&vma->ggtt_view, view))
5158                         return vma->node.start;
5159
5160         WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5161         return -1;
5162 }
5163
5164 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5165                         struct i915_address_space *vm)
5166 {
5167         struct i915_vma *vma;
5168
5169         list_for_each_entry(vma, &o->vma_list, vma_link) {
5170                 if (i915_is_ggtt(vma->vm) &&
5171                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5172                         continue;
5173                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5174                         return true;
5175         }
5176
5177         return false;
5178 }
5179
5180 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5181                                   const struct i915_ggtt_view *view)
5182 {
5183         struct i915_address_space *ggtt = i915_obj_to_ggtt(o);
5184         struct i915_vma *vma;
5185
5186         list_for_each_entry(vma, &o->vma_list, vma_link)
5187                 if (vma->vm == ggtt &&
5188                     i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5189                     drm_mm_node_allocated(&vma->node))
5190                         return true;
5191
5192         return false;
5193 }
5194
5195 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5196 {
5197         struct i915_vma *vma;
5198
5199         list_for_each_entry(vma, &o->vma_list, vma_link)
5200                 if (drm_mm_node_allocated(&vma->node))
5201                         return true;
5202
5203         return false;
5204 }
5205
5206 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5207                                 struct i915_address_space *vm)
5208 {
5209         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5210         struct i915_vma *vma;
5211
5212         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5213
5214         BUG_ON(list_empty(&o->vma_list));
5215
5216         list_for_each_entry(vma, &o->vma_list, vma_link) {
5217                 if (i915_is_ggtt(vma->vm) &&
5218                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5219                         continue;
5220                 if (vma->vm == vm)
5221                         return vma->node.size;
5222         }
5223         return 0;
5224 }
5225
5226 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5227 {
5228         struct i915_vma *vma;
5229         list_for_each_entry(vma, &obj->vma_list, vma_link) {
5230                 if (i915_is_ggtt(vma->vm) &&
5231                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5232                         continue;
5233                 if (vma->pin_count > 0)
5234                         return true;
5235         }
5236         return false;
5237 }
5238