Merge remote branch 'korg/drm-radeon-next' into drm-linus
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
36
37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43                                              int write);
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45                                                      uint64_t offset,
46                                                      uint64_t size);
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50                                            unsigned alignment);
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55                                 struct drm_i915_gem_pwrite *args,
56                                 struct drm_file *file_priv);
57
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
60
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62                      unsigned long end)
63 {
64         drm_i915_private_t *dev_priv = dev->dev_private;
65
66         if (start >= end ||
67             (start & (PAGE_SIZE - 1)) != 0 ||
68             (end & (PAGE_SIZE - 1)) != 0) {
69                 return -EINVAL;
70         }
71
72         drm_mm_init(&dev_priv->mm.gtt_space, start,
73                     end - start);
74
75         dev->gtt_total = (uint32_t) (end - start);
76
77         return 0;
78 }
79
80 int
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82                     struct drm_file *file_priv)
83 {
84         struct drm_i915_gem_init *args = data;
85         int ret;
86
87         mutex_lock(&dev->struct_mutex);
88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89         mutex_unlock(&dev->struct_mutex);
90
91         return ret;
92 }
93
94 int
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96                             struct drm_file *file_priv)
97 {
98         struct drm_i915_gem_get_aperture *args = data;
99
100         if (!(dev->driver->driver_features & DRIVER_GEM))
101                 return -ENODEV;
102
103         args->aper_size = dev->gtt_total;
104         args->aper_available_size = (args->aper_size -
105                                      atomic_read(&dev->pin_memory));
106
107         return 0;
108 }
109
110
111 /**
112  * Creates a new mm object and returns a handle to it.
113  */
114 int
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116                       struct drm_file *file_priv)
117 {
118         struct drm_i915_gem_create *args = data;
119         struct drm_gem_object *obj;
120         int ret;
121         u32 handle;
122
123         args->size = roundup(args->size, PAGE_SIZE);
124
125         /* Allocate the new object */
126         obj = drm_gem_object_alloc(dev, args->size);
127         if (obj == NULL)
128                 return -ENOMEM;
129
130         ret = drm_gem_handle_create(file_priv, obj, &handle);
131         mutex_lock(&dev->struct_mutex);
132         drm_gem_object_handle_unreference(obj);
133         mutex_unlock(&dev->struct_mutex);
134
135         if (ret)
136                 return ret;
137
138         args->handle = handle;
139
140         return 0;
141 }
142
143 static inline int
144 fast_shmem_read(struct page **pages,
145                 loff_t page_base, int page_offset,
146                 char __user *data,
147                 int length)
148 {
149         char __iomem *vaddr;
150         int unwritten;
151
152         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153         if (vaddr == NULL)
154                 return -ENOMEM;
155         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156         kunmap_atomic(vaddr, KM_USER0);
157
158         if (unwritten)
159                 return -EFAULT;
160
161         return 0;
162 }
163
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165 {
166         drm_i915_private_t *dev_priv = obj->dev->dev_private;
167         struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170                 obj_priv->tiling_mode != I915_TILING_NONE;
171 }
172
173 static inline int
174 slow_shmem_copy(struct page *dst_page,
175                 int dst_offset,
176                 struct page *src_page,
177                 int src_offset,
178                 int length)
179 {
180         char *dst_vaddr, *src_vaddr;
181
182         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183         if (dst_vaddr == NULL)
184                 return -ENOMEM;
185
186         src_vaddr = kmap_atomic(src_page, KM_USER1);
187         if (src_vaddr == NULL) {
188                 kunmap_atomic(dst_vaddr, KM_USER0);
189                 return -ENOMEM;
190         }
191
192         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194         kunmap_atomic(src_vaddr, KM_USER1);
195         kunmap_atomic(dst_vaddr, KM_USER0);
196
197         return 0;
198 }
199
200 static inline int
201 slow_shmem_bit17_copy(struct page *gpu_page,
202                       int gpu_offset,
203                       struct page *cpu_page,
204                       int cpu_offset,
205                       int length,
206                       int is_read)
207 {
208         char *gpu_vaddr, *cpu_vaddr;
209
210         /* Use the unswizzled path if this page isn't affected. */
211         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212                 if (is_read)
213                         return slow_shmem_copy(cpu_page, cpu_offset,
214                                                gpu_page, gpu_offset, length);
215                 else
216                         return slow_shmem_copy(gpu_page, gpu_offset,
217                                                cpu_page, cpu_offset, length);
218         }
219
220         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221         if (gpu_vaddr == NULL)
222                 return -ENOMEM;
223
224         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225         if (cpu_vaddr == NULL) {
226                 kunmap_atomic(gpu_vaddr, KM_USER0);
227                 return -ENOMEM;
228         }
229
230         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231          * XORing with the other bits (A9 for Y, A9 and A10 for X)
232          */
233         while (length > 0) {
234                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235                 int this_length = min(cacheline_end - gpu_offset, length);
236                 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238                 if (is_read) {
239                         memcpy(cpu_vaddr + cpu_offset,
240                                gpu_vaddr + swizzled_gpu_offset,
241                                this_length);
242                 } else {
243                         memcpy(gpu_vaddr + swizzled_gpu_offset,
244                                cpu_vaddr + cpu_offset,
245                                this_length);
246                 }
247                 cpu_offset += this_length;
248                 gpu_offset += this_length;
249                 length -= this_length;
250         }
251
252         kunmap_atomic(cpu_vaddr, KM_USER1);
253         kunmap_atomic(gpu_vaddr, KM_USER0);
254
255         return 0;
256 }
257
258 /**
259  * This is the fast shmem pread path, which attempts to copy_from_user directly
260  * from the backing pages of the object to the user's address space.  On a
261  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262  */
263 static int
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265                           struct drm_i915_gem_pread *args,
266                           struct drm_file *file_priv)
267 {
268         struct drm_i915_gem_object *obj_priv = obj->driver_private;
269         ssize_t remain;
270         loff_t offset, page_base;
271         char __user *user_data;
272         int page_offset, page_length;
273         int ret;
274
275         user_data = (char __user *) (uintptr_t) args->data_ptr;
276         remain = args->size;
277
278         mutex_lock(&dev->struct_mutex);
279
280         ret = i915_gem_object_get_pages(obj);
281         if (ret != 0)
282                 goto fail_unlock;
283
284         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285                                                         args->size);
286         if (ret != 0)
287                 goto fail_put_pages;
288
289         obj_priv = obj->driver_private;
290         offset = args->offset;
291
292         while (remain > 0) {
293                 /* Operation in this page
294                  *
295                  * page_base = page offset within aperture
296                  * page_offset = offset within page
297                  * page_length = bytes to copy for this page
298                  */
299                 page_base = (offset & ~(PAGE_SIZE-1));
300                 page_offset = offset & (PAGE_SIZE-1);
301                 page_length = remain;
302                 if ((page_offset + remain) > PAGE_SIZE)
303                         page_length = PAGE_SIZE - page_offset;
304
305                 ret = fast_shmem_read(obj_priv->pages,
306                                       page_base, page_offset,
307                                       user_data, page_length);
308                 if (ret)
309                         goto fail_put_pages;
310
311                 remain -= page_length;
312                 user_data += page_length;
313                 offset += page_length;
314         }
315
316 fail_put_pages:
317         i915_gem_object_put_pages(obj);
318 fail_unlock:
319         mutex_unlock(&dev->struct_mutex);
320
321         return ret;
322 }
323
324 static inline gfp_t
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326 {
327         return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328 }
329
330 static inline void
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332 {
333         mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334 }
335
336 static int
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338 {
339         int ret;
340
341         ret = i915_gem_object_get_pages(obj);
342
343         /* If we've insufficient memory to map in the pages, attempt
344          * to make some space by throwing out some old buffers.
345          */
346         if (ret == -ENOMEM) {
347                 struct drm_device *dev = obj->dev;
348                 gfp_t gfp;
349
350                 ret = i915_gem_evict_something(dev, obj->size);
351                 if (ret)
352                         return ret;
353
354                 gfp = i915_gem_object_get_page_gfp_mask(obj);
355                 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356                 ret = i915_gem_object_get_pages(obj);
357                 i915_gem_object_set_page_gfp_mask (obj, gfp);
358         }
359
360         return ret;
361 }
362
363 /**
364  * This is the fallback shmem pread path, which allocates temporary storage
365  * in kernel space to copy_to_user into outside of the struct_mutex, so we
366  * can copy out of the object's backing pages while holding the struct mutex
367  * and not take page faults.
368  */
369 static int
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371                           struct drm_i915_gem_pread *args,
372                           struct drm_file *file_priv)
373 {
374         struct drm_i915_gem_object *obj_priv = obj->driver_private;
375         struct mm_struct *mm = current->mm;
376         struct page **user_pages;
377         ssize_t remain;
378         loff_t offset, pinned_pages, i;
379         loff_t first_data_page, last_data_page, num_pages;
380         int shmem_page_index, shmem_page_offset;
381         int data_page_index,  data_page_offset;
382         int page_length;
383         int ret;
384         uint64_t data_ptr = args->data_ptr;
385         int do_bit17_swizzling;
386
387         remain = args->size;
388
389         /* Pin the user pages containing the data.  We can't fault while
390          * holding the struct mutex, yet we want to hold it while
391          * dereferencing the user data.
392          */
393         first_data_page = data_ptr / PAGE_SIZE;
394         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395         num_pages = last_data_page - first_data_page + 1;
396
397         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398         if (user_pages == NULL)
399                 return -ENOMEM;
400
401         down_read(&mm->mmap_sem);
402         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403                                       num_pages, 1, 0, user_pages, NULL);
404         up_read(&mm->mmap_sem);
405         if (pinned_pages < num_pages) {
406                 ret = -EFAULT;
407                 goto fail_put_user_pages;
408         }
409
410         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
412         mutex_lock(&dev->struct_mutex);
413
414         ret = i915_gem_object_get_pages_or_evict(obj);
415         if (ret)
416                 goto fail_unlock;
417
418         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419                                                         args->size);
420         if (ret != 0)
421                 goto fail_put_pages;
422
423         obj_priv = obj->driver_private;
424         offset = args->offset;
425
426         while (remain > 0) {
427                 /* Operation in this page
428                  *
429                  * shmem_page_index = page number within shmem file
430                  * shmem_page_offset = offset within page in shmem file
431                  * data_page_index = page number in get_user_pages return
432                  * data_page_offset = offset with data_page_index page.
433                  * page_length = bytes to copy for this page
434                  */
435                 shmem_page_index = offset / PAGE_SIZE;
436                 shmem_page_offset = offset & ~PAGE_MASK;
437                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438                 data_page_offset = data_ptr & ~PAGE_MASK;
439
440                 page_length = remain;
441                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442                         page_length = PAGE_SIZE - shmem_page_offset;
443                 if ((data_page_offset + page_length) > PAGE_SIZE)
444                         page_length = PAGE_SIZE - data_page_offset;
445
446                 if (do_bit17_swizzling) {
447                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448                                                     shmem_page_offset,
449                                                     user_pages[data_page_index],
450                                                     data_page_offset,
451                                                     page_length,
452                                                     1);
453                 } else {
454                         ret = slow_shmem_copy(user_pages[data_page_index],
455                                               data_page_offset,
456                                               obj_priv->pages[shmem_page_index],
457                                               shmem_page_offset,
458                                               page_length);
459                 }
460                 if (ret)
461                         goto fail_put_pages;
462
463                 remain -= page_length;
464                 data_ptr += page_length;
465                 offset += page_length;
466         }
467
468 fail_put_pages:
469         i915_gem_object_put_pages(obj);
470 fail_unlock:
471         mutex_unlock(&dev->struct_mutex);
472 fail_put_user_pages:
473         for (i = 0; i < pinned_pages; i++) {
474                 SetPageDirty(user_pages[i]);
475                 page_cache_release(user_pages[i]);
476         }
477         drm_free_large(user_pages);
478
479         return ret;
480 }
481
482 /**
483  * Reads data from the object referenced by handle.
484  *
485  * On error, the contents of *data are undefined.
486  */
487 int
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489                      struct drm_file *file_priv)
490 {
491         struct drm_i915_gem_pread *args = data;
492         struct drm_gem_object *obj;
493         struct drm_i915_gem_object *obj_priv;
494         int ret;
495
496         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497         if (obj == NULL)
498                 return -EBADF;
499         obj_priv = obj->driver_private;
500
501         /* Bounds check source.
502          *
503          * XXX: This could use review for overflow issues...
504          */
505         if (args->offset > obj->size || args->size > obj->size ||
506             args->offset + args->size > obj->size) {
507                 drm_gem_object_unreference(obj);
508                 return -EINVAL;
509         }
510
511         if (i915_gem_object_needs_bit17_swizzle(obj)) {
512                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
513         } else {
514                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515                 if (ret != 0)
516                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
517                                                         file_priv);
518         }
519
520         drm_gem_object_unreference(obj);
521
522         return ret;
523 }
524
525 /* This is the fast write path which cannot handle
526  * page faults in the source data
527  */
528
529 static inline int
530 fast_user_write(struct io_mapping *mapping,
531                 loff_t page_base, int page_offset,
532                 char __user *user_data,
533                 int length)
534 {
535         char *vaddr_atomic;
536         unsigned long unwritten;
537
538         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540                                                       user_data, length);
541         io_mapping_unmap_atomic(vaddr_atomic);
542         if (unwritten)
543                 return -EFAULT;
544         return 0;
545 }
546
547 /* Here's the write path which can sleep for
548  * page faults
549  */
550
551 static inline int
552 slow_kernel_write(struct io_mapping *mapping,
553                   loff_t gtt_base, int gtt_offset,
554                   struct page *user_page, int user_offset,
555                   int length)
556 {
557         char *src_vaddr, *dst_vaddr;
558         unsigned long unwritten;
559
560         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561         src_vaddr = kmap_atomic(user_page, KM_USER1);
562         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563                                                       src_vaddr + user_offset,
564                                                       length);
565         kunmap_atomic(src_vaddr, KM_USER1);
566         io_mapping_unmap_atomic(dst_vaddr);
567         if (unwritten)
568                 return -EFAULT;
569         return 0;
570 }
571
572 static inline int
573 fast_shmem_write(struct page **pages,
574                  loff_t page_base, int page_offset,
575                  char __user *data,
576                  int length)
577 {
578         char __iomem *vaddr;
579         unsigned long unwritten;
580
581         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582         if (vaddr == NULL)
583                 return -ENOMEM;
584         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585         kunmap_atomic(vaddr, KM_USER0);
586
587         if (unwritten)
588                 return -EFAULT;
589         return 0;
590 }
591
592 /**
593  * This is the fast pwrite path, where we copy the data directly from the
594  * user into the GTT, uncached.
595  */
596 static int
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598                          struct drm_i915_gem_pwrite *args,
599                          struct drm_file *file_priv)
600 {
601         struct drm_i915_gem_object *obj_priv = obj->driver_private;
602         drm_i915_private_t *dev_priv = dev->dev_private;
603         ssize_t remain;
604         loff_t offset, page_base;
605         char __user *user_data;
606         int page_offset, page_length;
607         int ret;
608
609         user_data = (char __user *) (uintptr_t) args->data_ptr;
610         remain = args->size;
611         if (!access_ok(VERIFY_READ, user_data, remain))
612                 return -EFAULT;
613
614
615         mutex_lock(&dev->struct_mutex);
616         ret = i915_gem_object_pin(obj, 0);
617         if (ret) {
618                 mutex_unlock(&dev->struct_mutex);
619                 return ret;
620         }
621         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
622         if (ret)
623                 goto fail;
624
625         obj_priv = obj->driver_private;
626         offset = obj_priv->gtt_offset + args->offset;
627
628         while (remain > 0) {
629                 /* Operation in this page
630                  *
631                  * page_base = page offset within aperture
632                  * page_offset = offset within page
633                  * page_length = bytes to copy for this page
634                  */
635                 page_base = (offset & ~(PAGE_SIZE-1));
636                 page_offset = offset & (PAGE_SIZE-1);
637                 page_length = remain;
638                 if ((page_offset + remain) > PAGE_SIZE)
639                         page_length = PAGE_SIZE - page_offset;
640
641                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642                                        page_offset, user_data, page_length);
643
644                 /* If we get a fault while copying data, then (presumably) our
645                  * source page isn't available.  Return the error and we'll
646                  * retry in the slow path.
647                  */
648                 if (ret)
649                         goto fail;
650
651                 remain -= page_length;
652                 user_data += page_length;
653                 offset += page_length;
654         }
655
656 fail:
657         i915_gem_object_unpin(obj);
658         mutex_unlock(&dev->struct_mutex);
659
660         return ret;
661 }
662
663 /**
664  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665  * the memory and maps it using kmap_atomic for copying.
666  *
667  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669  */
670 static int
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672                          struct drm_i915_gem_pwrite *args,
673                          struct drm_file *file_priv)
674 {
675         struct drm_i915_gem_object *obj_priv = obj->driver_private;
676         drm_i915_private_t *dev_priv = dev->dev_private;
677         ssize_t remain;
678         loff_t gtt_page_base, offset;
679         loff_t first_data_page, last_data_page, num_pages;
680         loff_t pinned_pages, i;
681         struct page **user_pages;
682         struct mm_struct *mm = current->mm;
683         int gtt_page_offset, data_page_offset, data_page_index, page_length;
684         int ret;
685         uint64_t data_ptr = args->data_ptr;
686
687         remain = args->size;
688
689         /* Pin the user pages containing the data.  We can't fault while
690          * holding the struct mutex, and all of the pwrite implementations
691          * want to hold it while dereferencing the user data.
692          */
693         first_data_page = data_ptr / PAGE_SIZE;
694         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695         num_pages = last_data_page - first_data_page + 1;
696
697         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698         if (user_pages == NULL)
699                 return -ENOMEM;
700
701         down_read(&mm->mmap_sem);
702         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703                                       num_pages, 0, 0, user_pages, NULL);
704         up_read(&mm->mmap_sem);
705         if (pinned_pages < num_pages) {
706                 ret = -EFAULT;
707                 goto out_unpin_pages;
708         }
709
710         mutex_lock(&dev->struct_mutex);
711         ret = i915_gem_object_pin(obj, 0);
712         if (ret)
713                 goto out_unlock;
714
715         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716         if (ret)
717                 goto out_unpin_object;
718
719         obj_priv = obj->driver_private;
720         offset = obj_priv->gtt_offset + args->offset;
721
722         while (remain > 0) {
723                 /* Operation in this page
724                  *
725                  * gtt_page_base = page offset within aperture
726                  * gtt_page_offset = offset within page in aperture
727                  * data_page_index = page number in get_user_pages return
728                  * data_page_offset = offset with data_page_index page.
729                  * page_length = bytes to copy for this page
730                  */
731                 gtt_page_base = offset & PAGE_MASK;
732                 gtt_page_offset = offset & ~PAGE_MASK;
733                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734                 data_page_offset = data_ptr & ~PAGE_MASK;
735
736                 page_length = remain;
737                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738                         page_length = PAGE_SIZE - gtt_page_offset;
739                 if ((data_page_offset + page_length) > PAGE_SIZE)
740                         page_length = PAGE_SIZE - data_page_offset;
741
742                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743                                         gtt_page_base, gtt_page_offset,
744                                         user_pages[data_page_index],
745                                         data_page_offset,
746                                         page_length);
747
748                 /* If we get a fault while copying data, then (presumably) our
749                  * source page isn't available.  Return the error and we'll
750                  * retry in the slow path.
751                  */
752                 if (ret)
753                         goto out_unpin_object;
754
755                 remain -= page_length;
756                 offset += page_length;
757                 data_ptr += page_length;
758         }
759
760 out_unpin_object:
761         i915_gem_object_unpin(obj);
762 out_unlock:
763         mutex_unlock(&dev->struct_mutex);
764 out_unpin_pages:
765         for (i = 0; i < pinned_pages; i++)
766                 page_cache_release(user_pages[i]);
767         drm_free_large(user_pages);
768
769         return ret;
770 }
771
772 /**
773  * This is the fast shmem pwrite path, which attempts to directly
774  * copy_from_user into the kmapped pages backing the object.
775  */
776 static int
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778                            struct drm_i915_gem_pwrite *args,
779                            struct drm_file *file_priv)
780 {
781         struct drm_i915_gem_object *obj_priv = obj->driver_private;
782         ssize_t remain;
783         loff_t offset, page_base;
784         char __user *user_data;
785         int page_offset, page_length;
786         int ret;
787
788         user_data = (char __user *) (uintptr_t) args->data_ptr;
789         remain = args->size;
790
791         mutex_lock(&dev->struct_mutex);
792
793         ret = i915_gem_object_get_pages(obj);
794         if (ret != 0)
795                 goto fail_unlock;
796
797         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
798         if (ret != 0)
799                 goto fail_put_pages;
800
801         obj_priv = obj->driver_private;
802         offset = args->offset;
803         obj_priv->dirty = 1;
804
805         while (remain > 0) {
806                 /* Operation in this page
807                  *
808                  * page_base = page offset within aperture
809                  * page_offset = offset within page
810                  * page_length = bytes to copy for this page
811                  */
812                 page_base = (offset & ~(PAGE_SIZE-1));
813                 page_offset = offset & (PAGE_SIZE-1);
814                 page_length = remain;
815                 if ((page_offset + remain) > PAGE_SIZE)
816                         page_length = PAGE_SIZE - page_offset;
817
818                 ret = fast_shmem_write(obj_priv->pages,
819                                        page_base, page_offset,
820                                        user_data, page_length);
821                 if (ret)
822                         goto fail_put_pages;
823
824                 remain -= page_length;
825                 user_data += page_length;
826                 offset += page_length;
827         }
828
829 fail_put_pages:
830         i915_gem_object_put_pages(obj);
831 fail_unlock:
832         mutex_unlock(&dev->struct_mutex);
833
834         return ret;
835 }
836
837 /**
838  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839  * the memory and maps it using kmap_atomic for copying.
840  *
841  * This avoids taking mmap_sem for faulting on the user's address while the
842  * struct_mutex is held.
843  */
844 static int
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846                            struct drm_i915_gem_pwrite *args,
847                            struct drm_file *file_priv)
848 {
849         struct drm_i915_gem_object *obj_priv = obj->driver_private;
850         struct mm_struct *mm = current->mm;
851         struct page **user_pages;
852         ssize_t remain;
853         loff_t offset, pinned_pages, i;
854         loff_t first_data_page, last_data_page, num_pages;
855         int shmem_page_index, shmem_page_offset;
856         int data_page_index,  data_page_offset;
857         int page_length;
858         int ret;
859         uint64_t data_ptr = args->data_ptr;
860         int do_bit17_swizzling;
861
862         remain = args->size;
863
864         /* Pin the user pages containing the data.  We can't fault while
865          * holding the struct mutex, and all of the pwrite implementations
866          * want to hold it while dereferencing the user data.
867          */
868         first_data_page = data_ptr / PAGE_SIZE;
869         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870         num_pages = last_data_page - first_data_page + 1;
871
872         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873         if (user_pages == NULL)
874                 return -ENOMEM;
875
876         down_read(&mm->mmap_sem);
877         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878                                       num_pages, 0, 0, user_pages, NULL);
879         up_read(&mm->mmap_sem);
880         if (pinned_pages < num_pages) {
881                 ret = -EFAULT;
882                 goto fail_put_user_pages;
883         }
884
885         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
887         mutex_lock(&dev->struct_mutex);
888
889         ret = i915_gem_object_get_pages_or_evict(obj);
890         if (ret)
891                 goto fail_unlock;
892
893         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894         if (ret != 0)
895                 goto fail_put_pages;
896
897         obj_priv = obj->driver_private;
898         offset = args->offset;
899         obj_priv->dirty = 1;
900
901         while (remain > 0) {
902                 /* Operation in this page
903                  *
904                  * shmem_page_index = page number within shmem file
905                  * shmem_page_offset = offset within page in shmem file
906                  * data_page_index = page number in get_user_pages return
907                  * data_page_offset = offset with data_page_index page.
908                  * page_length = bytes to copy for this page
909                  */
910                 shmem_page_index = offset / PAGE_SIZE;
911                 shmem_page_offset = offset & ~PAGE_MASK;
912                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913                 data_page_offset = data_ptr & ~PAGE_MASK;
914
915                 page_length = remain;
916                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917                         page_length = PAGE_SIZE - shmem_page_offset;
918                 if ((data_page_offset + page_length) > PAGE_SIZE)
919                         page_length = PAGE_SIZE - data_page_offset;
920
921                 if (do_bit17_swizzling) {
922                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923                                                     shmem_page_offset,
924                                                     user_pages[data_page_index],
925                                                     data_page_offset,
926                                                     page_length,
927                                                     0);
928                 } else {
929                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930                                               shmem_page_offset,
931                                               user_pages[data_page_index],
932                                               data_page_offset,
933                                               page_length);
934                 }
935                 if (ret)
936                         goto fail_put_pages;
937
938                 remain -= page_length;
939                 data_ptr += page_length;
940                 offset += page_length;
941         }
942
943 fail_put_pages:
944         i915_gem_object_put_pages(obj);
945 fail_unlock:
946         mutex_unlock(&dev->struct_mutex);
947 fail_put_user_pages:
948         for (i = 0; i < pinned_pages; i++)
949                 page_cache_release(user_pages[i]);
950         drm_free_large(user_pages);
951
952         return ret;
953 }
954
955 /**
956  * Writes data to the object referenced by handle.
957  *
958  * On error, the contents of the buffer that were to be modified are undefined.
959  */
960 int
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962                       struct drm_file *file_priv)
963 {
964         struct drm_i915_gem_pwrite *args = data;
965         struct drm_gem_object *obj;
966         struct drm_i915_gem_object *obj_priv;
967         int ret = 0;
968
969         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970         if (obj == NULL)
971                 return -EBADF;
972         obj_priv = obj->driver_private;
973
974         /* Bounds check destination.
975          *
976          * XXX: This could use review for overflow issues...
977          */
978         if (args->offset > obj->size || args->size > obj->size ||
979             args->offset + args->size > obj->size) {
980                 drm_gem_object_unreference(obj);
981                 return -EINVAL;
982         }
983
984         /* We can only do the GTT pwrite on untiled buffers, as otherwise
985          * it would end up going through the fenced access, and we'll get
986          * different detiling behavior between reading and writing.
987          * pread/pwrite currently are reading and writing from the CPU
988          * perspective, requiring manual detiling by the client.
989          */
990         if (obj_priv->phys_obj)
991                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993                  dev->gtt_total != 0) {
994                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995                 if (ret == -EFAULT) {
996                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997                                                        file_priv);
998                 }
999         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1001         } else {
1002                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003                 if (ret == -EFAULT) {
1004                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005                                                          file_priv);
1006                 }
1007         }
1008
1009 #if WATCH_PWRITE
1010         if (ret)
1011                 DRM_INFO("pwrite failed %d\n", ret);
1012 #endif
1013
1014         drm_gem_object_unreference(obj);
1015
1016         return ret;
1017 }
1018
1019 /**
1020  * Called when user space prepares to use an object with the CPU, either
1021  * through the mmap ioctl's mapping or a GTT mapping.
1022  */
1023 int
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025                           struct drm_file *file_priv)
1026 {
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct drm_i915_gem_set_domain *args = data;
1029         struct drm_gem_object *obj;
1030         struct drm_i915_gem_object *obj_priv;
1031         uint32_t read_domains = args->read_domains;
1032         uint32_t write_domain = args->write_domain;
1033         int ret;
1034
1035         if (!(dev->driver->driver_features & DRIVER_GEM))
1036                 return -ENODEV;
1037
1038         /* Only handle setting domains to types used by the CPU. */
1039         if (write_domain & I915_GEM_GPU_DOMAINS)
1040                 return -EINVAL;
1041
1042         if (read_domains & I915_GEM_GPU_DOMAINS)
1043                 return -EINVAL;
1044
1045         /* Having something in the write domain implies it's in the read
1046          * domain, and only that read domain.  Enforce that in the request.
1047          */
1048         if (write_domain != 0 && read_domains != write_domain)
1049                 return -EINVAL;
1050
1051         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052         if (obj == NULL)
1053                 return -EBADF;
1054         obj_priv = obj->driver_private;
1055
1056         mutex_lock(&dev->struct_mutex);
1057
1058         intel_mark_busy(dev, obj);
1059
1060 #if WATCH_BUF
1061         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062                  obj, obj->size, read_domains, write_domain);
1063 #endif
1064         if (read_domains & I915_GEM_DOMAIN_GTT) {
1065                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1066
1067                 /* Update the LRU on the fence for the CPU access that's
1068                  * about to occur.
1069                  */
1070                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071                         list_move_tail(&obj_priv->fence_list,
1072                                        &dev_priv->mm.fence_list);
1073                 }
1074
1075                 /* Silently promote "you're not bound, there was nothing to do"
1076                  * to success, since the client was just asking us to
1077                  * make sure everything was done.
1078                  */
1079                 if (ret == -EINVAL)
1080                         ret = 0;
1081         } else {
1082                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1083         }
1084
1085         drm_gem_object_unreference(obj);
1086         mutex_unlock(&dev->struct_mutex);
1087         return ret;
1088 }
1089
1090 /**
1091  * Called when user space has done writes to this buffer
1092  */
1093 int
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095                       struct drm_file *file_priv)
1096 {
1097         struct drm_i915_gem_sw_finish *args = data;
1098         struct drm_gem_object *obj;
1099         struct drm_i915_gem_object *obj_priv;
1100         int ret = 0;
1101
1102         if (!(dev->driver->driver_features & DRIVER_GEM))
1103                 return -ENODEV;
1104
1105         mutex_lock(&dev->struct_mutex);
1106         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107         if (obj == NULL) {
1108                 mutex_unlock(&dev->struct_mutex);
1109                 return -EBADF;
1110         }
1111
1112 #if WATCH_BUF
1113         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114                  __func__, args->handle, obj, obj->size);
1115 #endif
1116         obj_priv = obj->driver_private;
1117
1118         /* Pinned buffers may be scanout, so flush the cache */
1119         if (obj_priv->pin_count)
1120                 i915_gem_object_flush_cpu_write_domain(obj);
1121
1122         drm_gem_object_unreference(obj);
1123         mutex_unlock(&dev->struct_mutex);
1124         return ret;
1125 }
1126
1127 /**
1128  * Maps the contents of an object, returning the address it is mapped
1129  * into.
1130  *
1131  * While the mapping holds a reference on the contents of the object, it doesn't
1132  * imply a ref on the object itself.
1133  */
1134 int
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136                    struct drm_file *file_priv)
1137 {
1138         struct drm_i915_gem_mmap *args = data;
1139         struct drm_gem_object *obj;
1140         loff_t offset;
1141         unsigned long addr;
1142
1143         if (!(dev->driver->driver_features & DRIVER_GEM))
1144                 return -ENODEV;
1145
1146         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147         if (obj == NULL)
1148                 return -EBADF;
1149
1150         offset = args->offset;
1151
1152         down_write(&current->mm->mmap_sem);
1153         addr = do_mmap(obj->filp, 0, args->size,
1154                        PROT_READ | PROT_WRITE, MAP_SHARED,
1155                        args->offset);
1156         up_write(&current->mm->mmap_sem);
1157         mutex_lock(&dev->struct_mutex);
1158         drm_gem_object_unreference(obj);
1159         mutex_unlock(&dev->struct_mutex);
1160         if (IS_ERR((void *)addr))
1161                 return addr;
1162
1163         args->addr_ptr = (uint64_t) addr;
1164
1165         return 0;
1166 }
1167
1168 /**
1169  * i915_gem_fault - fault a page into the GTT
1170  * vma: VMA in question
1171  * vmf: fault info
1172  *
1173  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174  * from userspace.  The fault handler takes care of binding the object to
1175  * the GTT (if needed), allocating and programming a fence register (again,
1176  * only if needed based on whether the old reg is still valid or the object
1177  * is tiled) and inserting a new PTE into the faulting process.
1178  *
1179  * Note that the faulting process may involve evicting existing objects
1180  * from the GTT and/or fence registers to make room.  So performance may
1181  * suffer if the GTT working set is large or there are few fence registers
1182  * left.
1183  */
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185 {
1186         struct drm_gem_object *obj = vma->vm_private_data;
1187         struct drm_device *dev = obj->dev;
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190         pgoff_t page_offset;
1191         unsigned long pfn;
1192         int ret = 0;
1193         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1194
1195         /* We don't use vmf->pgoff since that has the fake offset */
1196         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197                 PAGE_SHIFT;
1198
1199         /* Now bind it into the GTT if needed */
1200         mutex_lock(&dev->struct_mutex);
1201         if (!obj_priv->gtt_space) {
1202                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1203                 if (ret)
1204                         goto unlock;
1205
1206                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1207
1208                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1209                 if (ret)
1210                         goto unlock;
1211         }
1212
1213         /* Need a new fence register? */
1214         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1215                 ret = i915_gem_object_get_fence_reg(obj);
1216                 if (ret)
1217                         goto unlock;
1218         }
1219
1220         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1221                 page_offset;
1222
1223         /* Finally, remap it using the new GTT offset */
1224         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1225 unlock:
1226         mutex_unlock(&dev->struct_mutex);
1227
1228         switch (ret) {
1229         case 0:
1230         case -ERESTARTSYS:
1231                 return VM_FAULT_NOPAGE;
1232         case -ENOMEM:
1233         case -EAGAIN:
1234                 return VM_FAULT_OOM;
1235         default:
1236                 return VM_FAULT_SIGBUS;
1237         }
1238 }
1239
1240 /**
1241  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242  * @obj: obj in question
1243  *
1244  * GEM memory mapping works by handing back to userspace a fake mmap offset
1245  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1246  * up the object based on the offset and sets up the various memory mapping
1247  * structures.
1248  *
1249  * This routine allocates and attaches a fake offset for @obj.
1250  */
1251 static int
1252 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1253 {
1254         struct drm_device *dev = obj->dev;
1255         struct drm_gem_mm *mm = dev->mm_private;
1256         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1257         struct drm_map_list *list;
1258         struct drm_local_map *map;
1259         int ret = 0;
1260
1261         /* Set the object up for mmap'ing */
1262         list = &obj->map_list;
1263         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1264         if (!list->map)
1265                 return -ENOMEM;
1266
1267         map = list->map;
1268         map->type = _DRM_GEM;
1269         map->size = obj->size;
1270         map->handle = obj;
1271
1272         /* Get a DRM GEM mmap offset allocated... */
1273         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1274                                                     obj->size / PAGE_SIZE, 0, 0);
1275         if (!list->file_offset_node) {
1276                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1277                 ret = -ENOMEM;
1278                 goto out_free_list;
1279         }
1280
1281         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1282                                                   obj->size / PAGE_SIZE, 0);
1283         if (!list->file_offset_node) {
1284                 ret = -ENOMEM;
1285                 goto out_free_list;
1286         }
1287
1288         list->hash.key = list->file_offset_node->start;
1289         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1290                 DRM_ERROR("failed to add to map hash\n");
1291                 ret = -ENOMEM;
1292                 goto out_free_mm;
1293         }
1294
1295         /* By now we should be all set, any drm_mmap request on the offset
1296          * below will get to our mmap & fault handler */
1297         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1298
1299         return 0;
1300
1301 out_free_mm:
1302         drm_mm_put_block(list->file_offset_node);
1303 out_free_list:
1304         kfree(list->map);
1305
1306         return ret;
1307 }
1308
1309 /**
1310  * i915_gem_release_mmap - remove physical page mappings
1311  * @obj: obj in question
1312  *
1313  * Preserve the reservation of the mmaping with the DRM core code, but
1314  * relinquish ownership of the pages back to the system.
1315  *
1316  * It is vital that we remove the page mapping if we have mapped a tiled
1317  * object through the GTT and then lose the fence register due to
1318  * resource pressure. Similarly if the object has been moved out of the
1319  * aperture, than pages mapped into userspace must be revoked. Removing the
1320  * mapping will then trigger a page fault on the next user access, allowing
1321  * fixup by i915_gem_fault().
1322  */
1323 void
1324 i915_gem_release_mmap(struct drm_gem_object *obj)
1325 {
1326         struct drm_device *dev = obj->dev;
1327         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1328
1329         if (dev->dev_mapping)
1330                 unmap_mapping_range(dev->dev_mapping,
1331                                     obj_priv->mmap_offset, obj->size, 1);
1332 }
1333
1334 static void
1335 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1336 {
1337         struct drm_device *dev = obj->dev;
1338         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1339         struct drm_gem_mm *mm = dev->mm_private;
1340         struct drm_map_list *list;
1341
1342         list = &obj->map_list;
1343         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1344
1345         if (list->file_offset_node) {
1346                 drm_mm_put_block(list->file_offset_node);
1347                 list->file_offset_node = NULL;
1348         }
1349
1350         if (list->map) {
1351                 kfree(list->map);
1352                 list->map = NULL;
1353         }
1354
1355         obj_priv->mmap_offset = 0;
1356 }
1357
1358 /**
1359  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1360  * @obj: object to check
1361  *
1362  * Return the required GTT alignment for an object, taking into account
1363  * potential fence register mapping if needed.
1364  */
1365 static uint32_t
1366 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1367 {
1368         struct drm_device *dev = obj->dev;
1369         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1370         int start, i;
1371
1372         /*
1373          * Minimum alignment is 4k (GTT page size), but might be greater
1374          * if a fence register is needed for the object.
1375          */
1376         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1377                 return 4096;
1378
1379         /*
1380          * Previous chips need to be aligned to the size of the smallest
1381          * fence register that can contain the object.
1382          */
1383         if (IS_I9XX(dev))
1384                 start = 1024*1024;
1385         else
1386                 start = 512*1024;
1387
1388         for (i = start; i < obj->size; i <<= 1)
1389                 ;
1390
1391         return i;
1392 }
1393
1394 /**
1395  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1396  * @dev: DRM device
1397  * @data: GTT mapping ioctl data
1398  * @file_priv: GEM object info
1399  *
1400  * Simply returns the fake offset to userspace so it can mmap it.
1401  * The mmap call will end up in drm_gem_mmap(), which will set things
1402  * up so we can get faults in the handler above.
1403  *
1404  * The fault handler will take care of binding the object into the GTT
1405  * (since it may have been evicted to make room for something), allocating
1406  * a fence register, and mapping the appropriate aperture address into
1407  * userspace.
1408  */
1409 int
1410 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1411                         struct drm_file *file_priv)
1412 {
1413         struct drm_i915_gem_mmap_gtt *args = data;
1414         struct drm_i915_private *dev_priv = dev->dev_private;
1415         struct drm_gem_object *obj;
1416         struct drm_i915_gem_object *obj_priv;
1417         int ret;
1418
1419         if (!(dev->driver->driver_features & DRIVER_GEM))
1420                 return -ENODEV;
1421
1422         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1423         if (obj == NULL)
1424                 return -EBADF;
1425
1426         mutex_lock(&dev->struct_mutex);
1427
1428         obj_priv = obj->driver_private;
1429
1430         if (obj_priv->madv != I915_MADV_WILLNEED) {
1431                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1432                 drm_gem_object_unreference(obj);
1433                 mutex_unlock(&dev->struct_mutex);
1434                 return -EINVAL;
1435         }
1436
1437
1438         if (!obj_priv->mmap_offset) {
1439                 ret = i915_gem_create_mmap_offset(obj);
1440                 if (ret) {
1441                         drm_gem_object_unreference(obj);
1442                         mutex_unlock(&dev->struct_mutex);
1443                         return ret;
1444                 }
1445         }
1446
1447         args->offset = obj_priv->mmap_offset;
1448
1449         /*
1450          * Pull it into the GTT so that we have a page list (makes the
1451          * initial fault faster and any subsequent flushing possible).
1452          */
1453         if (!obj_priv->agp_mem) {
1454                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1455                 if (ret) {
1456                         drm_gem_object_unreference(obj);
1457                         mutex_unlock(&dev->struct_mutex);
1458                         return ret;
1459                 }
1460                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1461         }
1462
1463         drm_gem_object_unreference(obj);
1464         mutex_unlock(&dev->struct_mutex);
1465
1466         return 0;
1467 }
1468
1469 void
1470 i915_gem_object_put_pages(struct drm_gem_object *obj)
1471 {
1472         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1473         int page_count = obj->size / PAGE_SIZE;
1474         int i;
1475
1476         BUG_ON(obj_priv->pages_refcount == 0);
1477         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1478
1479         if (--obj_priv->pages_refcount != 0)
1480                 return;
1481
1482         if (obj_priv->tiling_mode != I915_TILING_NONE)
1483                 i915_gem_object_save_bit_17_swizzle(obj);
1484
1485         if (obj_priv->madv == I915_MADV_DONTNEED)
1486                 obj_priv->dirty = 0;
1487
1488         for (i = 0; i < page_count; i++) {
1489                 if (obj_priv->pages[i] == NULL)
1490                         break;
1491
1492                 if (obj_priv->dirty)
1493                         set_page_dirty(obj_priv->pages[i]);
1494
1495                 if (obj_priv->madv == I915_MADV_WILLNEED)
1496                         mark_page_accessed(obj_priv->pages[i]);
1497
1498                 page_cache_release(obj_priv->pages[i]);
1499         }
1500         obj_priv->dirty = 0;
1501
1502         drm_free_large(obj_priv->pages);
1503         obj_priv->pages = NULL;
1504 }
1505
1506 static void
1507 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1508 {
1509         struct drm_device *dev = obj->dev;
1510         drm_i915_private_t *dev_priv = dev->dev_private;
1511         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1512
1513         /* Add a reference if we're newly entering the active list. */
1514         if (!obj_priv->active) {
1515                 drm_gem_object_reference(obj);
1516                 obj_priv->active = 1;
1517         }
1518         /* Move from whatever list we were on to the tail of execution. */
1519         spin_lock(&dev_priv->mm.active_list_lock);
1520         list_move_tail(&obj_priv->list,
1521                        &dev_priv->mm.active_list);
1522         spin_unlock(&dev_priv->mm.active_list_lock);
1523         obj_priv->last_rendering_seqno = seqno;
1524 }
1525
1526 static void
1527 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1528 {
1529         struct drm_device *dev = obj->dev;
1530         drm_i915_private_t *dev_priv = dev->dev_private;
1531         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1532
1533         BUG_ON(!obj_priv->active);
1534         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1535         obj_priv->last_rendering_seqno = 0;
1536 }
1537
1538 /* Immediately discard the backing storage */
1539 static void
1540 i915_gem_object_truncate(struct drm_gem_object *obj)
1541 {
1542         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1543         struct inode *inode;
1544
1545         inode = obj->filp->f_path.dentry->d_inode;
1546         if (inode->i_op->truncate)
1547                 inode->i_op->truncate (inode);
1548
1549         obj_priv->madv = __I915_MADV_PURGED;
1550 }
1551
1552 static inline int
1553 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1554 {
1555         return obj_priv->madv == I915_MADV_DONTNEED;
1556 }
1557
1558 static void
1559 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1560 {
1561         struct drm_device *dev = obj->dev;
1562         drm_i915_private_t *dev_priv = dev->dev_private;
1563         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1564
1565         i915_verify_inactive(dev, __FILE__, __LINE__);
1566         if (obj_priv->pin_count != 0)
1567                 list_del_init(&obj_priv->list);
1568         else
1569                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1570
1571         obj_priv->last_rendering_seqno = 0;
1572         if (obj_priv->active) {
1573                 obj_priv->active = 0;
1574                 drm_gem_object_unreference(obj);
1575         }
1576         i915_verify_inactive(dev, __FILE__, __LINE__);
1577 }
1578
1579 /**
1580  * Creates a new sequence number, emitting a write of it to the status page
1581  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1582  *
1583  * Must be called with struct_lock held.
1584  *
1585  * Returned sequence numbers are nonzero on success.
1586  */
1587 uint32_t
1588 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1589                  uint32_t flush_domains)
1590 {
1591         drm_i915_private_t *dev_priv = dev->dev_private;
1592         struct drm_i915_file_private *i915_file_priv = NULL;
1593         struct drm_i915_gem_request *request;
1594         uint32_t seqno;
1595         int was_empty;
1596         RING_LOCALS;
1597
1598         if (file_priv != NULL)
1599                 i915_file_priv = file_priv->driver_priv;
1600
1601         request = kzalloc(sizeof(*request), GFP_KERNEL);
1602         if (request == NULL)
1603                 return 0;
1604
1605         /* Grab the seqno we're going to make this request be, and bump the
1606          * next (skipping 0 so it can be the reserved no-seqno value).
1607          */
1608         seqno = dev_priv->mm.next_gem_seqno;
1609         dev_priv->mm.next_gem_seqno++;
1610         if (dev_priv->mm.next_gem_seqno == 0)
1611                 dev_priv->mm.next_gem_seqno++;
1612
1613         BEGIN_LP_RING(4);
1614         OUT_RING(MI_STORE_DWORD_INDEX);
1615         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1616         OUT_RING(seqno);
1617
1618         OUT_RING(MI_USER_INTERRUPT);
1619         ADVANCE_LP_RING();
1620
1621         DRM_DEBUG_DRIVER("%d\n", seqno);
1622
1623         request->seqno = seqno;
1624         request->emitted_jiffies = jiffies;
1625         was_empty = list_empty(&dev_priv->mm.request_list);
1626         list_add_tail(&request->list, &dev_priv->mm.request_list);
1627         if (i915_file_priv) {
1628                 list_add_tail(&request->client_list,
1629                               &i915_file_priv->mm.request_list);
1630         } else {
1631                 INIT_LIST_HEAD(&request->client_list);
1632         }
1633
1634         /* Associate any objects on the flushing list matching the write
1635          * domain we're flushing with our flush.
1636          */
1637         if (flush_domains != 0) {
1638                 struct drm_i915_gem_object *obj_priv, *next;
1639
1640                 list_for_each_entry_safe(obj_priv, next,
1641                                          &dev_priv->mm.flushing_list, list) {
1642                         struct drm_gem_object *obj = obj_priv->obj;
1643
1644                         if ((obj->write_domain & flush_domains) ==
1645                             obj->write_domain) {
1646                                 uint32_t old_write_domain = obj->write_domain;
1647
1648                                 obj->write_domain = 0;
1649                                 i915_gem_object_move_to_active(obj, seqno);
1650
1651                                 trace_i915_gem_object_change_domain(obj,
1652                                                                     obj->read_domains,
1653                                                                     old_write_domain);
1654                         }
1655                 }
1656
1657         }
1658
1659         if (!dev_priv->mm.suspended) {
1660                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1661                 if (was_empty)
1662                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1663         }
1664         return seqno;
1665 }
1666
1667 /**
1668  * Command execution barrier
1669  *
1670  * Ensures that all commands in the ring are finished
1671  * before signalling the CPU
1672  */
1673 static uint32_t
1674 i915_retire_commands(struct drm_device *dev)
1675 {
1676         drm_i915_private_t *dev_priv = dev->dev_private;
1677         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1678         uint32_t flush_domains = 0;
1679         RING_LOCALS;
1680
1681         /* The sampler always gets flushed on i965 (sigh) */
1682         if (IS_I965G(dev))
1683                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1684         BEGIN_LP_RING(2);
1685         OUT_RING(cmd);
1686         OUT_RING(0); /* noop */
1687         ADVANCE_LP_RING();
1688         return flush_domains;
1689 }
1690
1691 /**
1692  * Moves buffers associated only with the given active seqno from the active
1693  * to inactive list, potentially freeing them.
1694  */
1695 static void
1696 i915_gem_retire_request(struct drm_device *dev,
1697                         struct drm_i915_gem_request *request)
1698 {
1699         drm_i915_private_t *dev_priv = dev->dev_private;
1700
1701         trace_i915_gem_request_retire(dev, request->seqno);
1702
1703         /* Move any buffers on the active list that are no longer referenced
1704          * by the ringbuffer to the flushing/inactive lists as appropriate.
1705          */
1706         spin_lock(&dev_priv->mm.active_list_lock);
1707         while (!list_empty(&dev_priv->mm.active_list)) {
1708                 struct drm_gem_object *obj;
1709                 struct drm_i915_gem_object *obj_priv;
1710
1711                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1712                                             struct drm_i915_gem_object,
1713                                             list);
1714                 obj = obj_priv->obj;
1715
1716                 /* If the seqno being retired doesn't match the oldest in the
1717                  * list, then the oldest in the list must still be newer than
1718                  * this seqno.
1719                  */
1720                 if (obj_priv->last_rendering_seqno != request->seqno)
1721                         goto out;
1722
1723 #if WATCH_LRU
1724                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1725                          __func__, request->seqno, obj);
1726 #endif
1727
1728                 if (obj->write_domain != 0)
1729                         i915_gem_object_move_to_flushing(obj);
1730                 else {
1731                         /* Take a reference on the object so it won't be
1732                          * freed while the spinlock is held.  The list
1733                          * protection for this spinlock is safe when breaking
1734                          * the lock like this since the next thing we do
1735                          * is just get the head of the list again.
1736                          */
1737                         drm_gem_object_reference(obj);
1738                         i915_gem_object_move_to_inactive(obj);
1739                         spin_unlock(&dev_priv->mm.active_list_lock);
1740                         drm_gem_object_unreference(obj);
1741                         spin_lock(&dev_priv->mm.active_list_lock);
1742                 }
1743         }
1744 out:
1745         spin_unlock(&dev_priv->mm.active_list_lock);
1746 }
1747
1748 /**
1749  * Returns true if seq1 is later than seq2.
1750  */
1751 bool
1752 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1753 {
1754         return (int32_t)(seq1 - seq2) >= 0;
1755 }
1756
1757 uint32_t
1758 i915_get_gem_seqno(struct drm_device *dev)
1759 {
1760         drm_i915_private_t *dev_priv = dev->dev_private;
1761
1762         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1763 }
1764
1765 /**
1766  * This function clears the request list as sequence numbers are passed.
1767  */
1768 void
1769 i915_gem_retire_requests(struct drm_device *dev)
1770 {
1771         drm_i915_private_t *dev_priv = dev->dev_private;
1772         uint32_t seqno;
1773
1774         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1775                 return;
1776
1777         seqno = i915_get_gem_seqno(dev);
1778
1779         while (!list_empty(&dev_priv->mm.request_list)) {
1780                 struct drm_i915_gem_request *request;
1781                 uint32_t retiring_seqno;
1782
1783                 request = list_first_entry(&dev_priv->mm.request_list,
1784                                            struct drm_i915_gem_request,
1785                                            list);
1786                 retiring_seqno = request->seqno;
1787
1788                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1789                     atomic_read(&dev_priv->mm.wedged)) {
1790                         i915_gem_retire_request(dev, request);
1791
1792                         list_del(&request->list);
1793                         list_del(&request->client_list);
1794                         kfree(request);
1795                 } else
1796                         break;
1797         }
1798
1799         if (unlikely (dev_priv->trace_irq_seqno &&
1800                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1801                 i915_user_irq_put(dev);
1802                 dev_priv->trace_irq_seqno = 0;
1803         }
1804 }
1805
1806 void
1807 i915_gem_retire_work_handler(struct work_struct *work)
1808 {
1809         drm_i915_private_t *dev_priv;
1810         struct drm_device *dev;
1811
1812         dev_priv = container_of(work, drm_i915_private_t,
1813                                 mm.retire_work.work);
1814         dev = dev_priv->dev;
1815
1816         mutex_lock(&dev->struct_mutex);
1817         i915_gem_retire_requests(dev);
1818         if (!dev_priv->mm.suspended &&
1819             !list_empty(&dev_priv->mm.request_list))
1820                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1821         mutex_unlock(&dev->struct_mutex);
1822 }
1823
1824 int
1825 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1826 {
1827         drm_i915_private_t *dev_priv = dev->dev_private;
1828         u32 ier;
1829         int ret = 0;
1830
1831         BUG_ON(seqno == 0);
1832
1833         if (atomic_read(&dev_priv->mm.wedged))
1834                 return -EIO;
1835
1836         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1837                 if (IS_IRONLAKE(dev))
1838                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1839                 else
1840                         ier = I915_READ(IER);
1841                 if (!ier) {
1842                         DRM_ERROR("something (likely vbetool) disabled "
1843                                   "interrupts, re-enabling\n");
1844                         i915_driver_irq_preinstall(dev);
1845                         i915_driver_irq_postinstall(dev);
1846                 }
1847
1848                 trace_i915_gem_request_wait_begin(dev, seqno);
1849
1850                 dev_priv->mm.waiting_gem_seqno = seqno;
1851                 i915_user_irq_get(dev);
1852                 if (interruptible)
1853                         ret = wait_event_interruptible(dev_priv->irq_queue,
1854                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1855                                 atomic_read(&dev_priv->mm.wedged));
1856                 else
1857                         wait_event(dev_priv->irq_queue,
1858                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1859                                 atomic_read(&dev_priv->mm.wedged));
1860
1861                 i915_user_irq_put(dev);
1862                 dev_priv->mm.waiting_gem_seqno = 0;
1863
1864                 trace_i915_gem_request_wait_end(dev, seqno);
1865         }
1866         if (atomic_read(&dev_priv->mm.wedged))
1867                 ret = -EIO;
1868
1869         if (ret && ret != -ERESTARTSYS)
1870                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1871                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1872
1873         /* Directly dispatch request retiring.  While we have the work queue
1874          * to handle this, the waiter on a request often wants an associated
1875          * buffer to have made it to the inactive list, and we would need
1876          * a separate wait queue to handle that.
1877          */
1878         if (ret == 0)
1879                 i915_gem_retire_requests(dev);
1880
1881         return ret;
1882 }
1883
1884 /**
1885  * Waits for a sequence number to be signaled, and cleans up the
1886  * request and object lists appropriately for that event.
1887  */
1888 static int
1889 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1890 {
1891         return i915_do_wait_request(dev, seqno, 1);
1892 }
1893
1894 static void
1895 i915_gem_flush(struct drm_device *dev,
1896                uint32_t invalidate_domains,
1897                uint32_t flush_domains)
1898 {
1899         drm_i915_private_t *dev_priv = dev->dev_private;
1900         uint32_t cmd;
1901         RING_LOCALS;
1902
1903 #if WATCH_EXEC
1904         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1905                   invalidate_domains, flush_domains);
1906 #endif
1907         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1908                                      invalidate_domains, flush_domains);
1909
1910         if (flush_domains & I915_GEM_DOMAIN_CPU)
1911                 drm_agp_chipset_flush(dev);
1912
1913         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1914                 /*
1915                  * read/write caches:
1916                  *
1917                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1918                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1919                  * also flushed at 2d versus 3d pipeline switches.
1920                  *
1921                  * read-only caches:
1922                  *
1923                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1924                  * MI_READ_FLUSH is set, and is always flushed on 965.
1925                  *
1926                  * I915_GEM_DOMAIN_COMMAND may not exist?
1927                  *
1928                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1929                  * invalidated when MI_EXE_FLUSH is set.
1930                  *
1931                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1932                  * invalidated with every MI_FLUSH.
1933                  *
1934                  * TLBs:
1935                  *
1936                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1937                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1938                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1939                  * are flushed at any MI_FLUSH.
1940                  */
1941
1942                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1943                 if ((invalidate_domains|flush_domains) &
1944                     I915_GEM_DOMAIN_RENDER)
1945                         cmd &= ~MI_NO_WRITE_FLUSH;
1946                 if (!IS_I965G(dev)) {
1947                         /*
1948                          * On the 965, the sampler cache always gets flushed
1949                          * and this bit is reserved.
1950                          */
1951                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1952                                 cmd |= MI_READ_FLUSH;
1953                 }
1954                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1955                         cmd |= MI_EXE_FLUSH;
1956
1957 #if WATCH_EXEC
1958                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1959 #endif
1960                 BEGIN_LP_RING(2);
1961                 OUT_RING(cmd);
1962                 OUT_RING(MI_NOOP);
1963                 ADVANCE_LP_RING();
1964         }
1965 }
1966
1967 /**
1968  * Ensures that all rendering to the object has completed and the object is
1969  * safe to unbind from the GTT or access from the CPU.
1970  */
1971 static int
1972 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1973 {
1974         struct drm_device *dev = obj->dev;
1975         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1976         int ret;
1977
1978         /* This function only exists to support waiting for existing rendering,
1979          * not for emitting required flushes.
1980          */
1981         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1982
1983         /* If there is rendering queued on the buffer being evicted, wait for
1984          * it.
1985          */
1986         if (obj_priv->active) {
1987 #if WATCH_BUF
1988                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1989                           __func__, obj, obj_priv->last_rendering_seqno);
1990 #endif
1991                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1992                 if (ret != 0)
1993                         return ret;
1994         }
1995
1996         return 0;
1997 }
1998
1999 /**
2000  * Unbinds an object from the GTT aperture.
2001  */
2002 int
2003 i915_gem_object_unbind(struct drm_gem_object *obj)
2004 {
2005         struct drm_device *dev = obj->dev;
2006         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2007         int ret = 0;
2008
2009 #if WATCH_BUF
2010         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2011         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2012 #endif
2013         if (obj_priv->gtt_space == NULL)
2014                 return 0;
2015
2016         if (obj_priv->pin_count != 0) {
2017                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2018                 return -EINVAL;
2019         }
2020
2021         /* blow away mappings if mapped through GTT */
2022         i915_gem_release_mmap(obj);
2023
2024         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2025                 i915_gem_clear_fence_reg(obj);
2026
2027         /* Move the object to the CPU domain to ensure that
2028          * any possible CPU writes while it's not in the GTT
2029          * are flushed when we go to remap it. This will
2030          * also ensure that all pending GPU writes are finished
2031          * before we unbind.
2032          */
2033         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2034         if (ret) {
2035                 if (ret != -ERESTARTSYS)
2036                         DRM_ERROR("set_domain failed: %d\n", ret);
2037                 return ret;
2038         }
2039
2040         BUG_ON(obj_priv->active);
2041
2042         if (obj_priv->agp_mem != NULL) {
2043                 drm_unbind_agp(obj_priv->agp_mem);
2044                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2045                 obj_priv->agp_mem = NULL;
2046         }
2047
2048         i915_gem_object_put_pages(obj);
2049         BUG_ON(obj_priv->pages_refcount);
2050
2051         if (obj_priv->gtt_space) {
2052                 atomic_dec(&dev->gtt_count);
2053                 atomic_sub(obj->size, &dev->gtt_memory);
2054
2055                 drm_mm_put_block(obj_priv->gtt_space);
2056                 obj_priv->gtt_space = NULL;
2057         }
2058
2059         /* Remove ourselves from the LRU list if present. */
2060         if (!list_empty(&obj_priv->list))
2061                 list_del_init(&obj_priv->list);
2062
2063         if (i915_gem_object_is_purgeable(obj_priv))
2064                 i915_gem_object_truncate(obj);
2065
2066         trace_i915_gem_object_unbind(obj);
2067
2068         return 0;
2069 }
2070
2071 static struct drm_gem_object *
2072 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2073 {
2074         drm_i915_private_t *dev_priv = dev->dev_private;
2075         struct drm_i915_gem_object *obj_priv;
2076         struct drm_gem_object *best = NULL;
2077         struct drm_gem_object *first = NULL;
2078
2079         /* Try to find the smallest clean object */
2080         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2081                 struct drm_gem_object *obj = obj_priv->obj;
2082                 if (obj->size >= min_size) {
2083                         if ((!obj_priv->dirty ||
2084                              i915_gem_object_is_purgeable(obj_priv)) &&
2085                             (!best || obj->size < best->size)) {
2086                                 best = obj;
2087                                 if (best->size == min_size)
2088                                         return best;
2089                         }
2090                         if (!first)
2091                             first = obj;
2092                 }
2093         }
2094
2095         return best ? best : first;
2096 }
2097
2098 static int
2099 i915_gem_evict_everything(struct drm_device *dev)
2100 {
2101         drm_i915_private_t *dev_priv = dev->dev_private;
2102         uint32_t seqno;
2103         int ret;
2104         bool lists_empty;
2105
2106         spin_lock(&dev_priv->mm.active_list_lock);
2107         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2108                        list_empty(&dev_priv->mm.flushing_list) &&
2109                        list_empty(&dev_priv->mm.active_list));
2110         spin_unlock(&dev_priv->mm.active_list_lock);
2111
2112         if (lists_empty)
2113                 return -ENOSPC;
2114
2115         /* Flush everything (on to the inactive lists) and evict */
2116         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2117         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2118         if (seqno == 0)
2119                 return -ENOMEM;
2120
2121         ret = i915_wait_request(dev, seqno);
2122         if (ret)
2123                 return ret;
2124
2125         ret = i915_gem_evict_from_inactive_list(dev);
2126         if (ret)
2127                 return ret;
2128
2129         spin_lock(&dev_priv->mm.active_list_lock);
2130         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2131                        list_empty(&dev_priv->mm.flushing_list) &&
2132                        list_empty(&dev_priv->mm.active_list));
2133         spin_unlock(&dev_priv->mm.active_list_lock);
2134         BUG_ON(!lists_empty);
2135
2136         return 0;
2137 }
2138
2139 static int
2140 i915_gem_evict_something(struct drm_device *dev, int min_size)
2141 {
2142         drm_i915_private_t *dev_priv = dev->dev_private;
2143         struct drm_gem_object *obj;
2144         int ret;
2145
2146         for (;;) {
2147                 i915_gem_retire_requests(dev);
2148
2149                 /* If there's an inactive buffer available now, grab it
2150                  * and be done.
2151                  */
2152                 obj = i915_gem_find_inactive_object(dev, min_size);
2153                 if (obj) {
2154                         struct drm_i915_gem_object *obj_priv;
2155
2156 #if WATCH_LRU
2157                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2158 #endif
2159                         obj_priv = obj->driver_private;
2160                         BUG_ON(obj_priv->pin_count != 0);
2161                         BUG_ON(obj_priv->active);
2162
2163                         /* Wait on the rendering and unbind the buffer. */
2164                         return i915_gem_object_unbind(obj);
2165                 }
2166
2167                 /* If we didn't get anything, but the ring is still processing
2168                  * things, wait for the next to finish and hopefully leave us
2169                  * a buffer to evict.
2170                  */
2171                 if (!list_empty(&dev_priv->mm.request_list)) {
2172                         struct drm_i915_gem_request *request;
2173
2174                         request = list_first_entry(&dev_priv->mm.request_list,
2175                                                    struct drm_i915_gem_request,
2176                                                    list);
2177
2178                         ret = i915_wait_request(dev, request->seqno);
2179                         if (ret)
2180                                 return ret;
2181
2182                         continue;
2183                 }
2184
2185                 /* If we didn't have anything on the request list but there
2186                  * are buffers awaiting a flush, emit one and try again.
2187                  * When we wait on it, those buffers waiting for that flush
2188                  * will get moved to inactive.
2189                  */
2190                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2191                         struct drm_i915_gem_object *obj_priv;
2192
2193                         /* Find an object that we can immediately reuse */
2194                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2195                                 obj = obj_priv->obj;
2196                                 if (obj->size >= min_size)
2197                                         break;
2198
2199                                 obj = NULL;
2200                         }
2201
2202                         if (obj != NULL) {
2203                                 uint32_t seqno;
2204
2205                                 i915_gem_flush(dev,
2206                                                obj->write_domain,
2207                                                obj->write_domain);
2208                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2209                                 if (seqno == 0)
2210                                         return -ENOMEM;
2211
2212                                 ret = i915_wait_request(dev, seqno);
2213                                 if (ret)
2214                                         return ret;
2215
2216                                 continue;
2217                         }
2218                 }
2219
2220                 /* If we didn't do any of the above, there's no single buffer
2221                  * large enough to swap out for the new one, so just evict
2222                  * everything and start again. (This should be rare.)
2223                  */
2224                 if (!list_empty (&dev_priv->mm.inactive_list))
2225                         return i915_gem_evict_from_inactive_list(dev);
2226                 else
2227                         return i915_gem_evict_everything(dev);
2228         }
2229 }
2230
2231 int
2232 i915_gem_object_get_pages(struct drm_gem_object *obj)
2233 {
2234         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2235         int page_count, i;
2236         struct address_space *mapping;
2237         struct inode *inode;
2238         struct page *page;
2239         int ret;
2240
2241         if (obj_priv->pages_refcount++ != 0)
2242                 return 0;
2243
2244         /* Get the list of pages out of our struct file.  They'll be pinned
2245          * at this point until we release them.
2246          */
2247         page_count = obj->size / PAGE_SIZE;
2248         BUG_ON(obj_priv->pages != NULL);
2249         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2250         if (obj_priv->pages == NULL) {
2251                 obj_priv->pages_refcount--;
2252                 return -ENOMEM;
2253         }
2254
2255         inode = obj->filp->f_path.dentry->d_inode;
2256         mapping = inode->i_mapping;
2257         for (i = 0; i < page_count; i++) {
2258                 page = read_mapping_page(mapping, i, NULL);
2259                 if (IS_ERR(page)) {
2260                         ret = PTR_ERR(page);
2261                         i915_gem_object_put_pages(obj);
2262                         return ret;
2263                 }
2264                 obj_priv->pages[i] = page;
2265         }
2266
2267         if (obj_priv->tiling_mode != I915_TILING_NONE)
2268                 i915_gem_object_do_bit_17_swizzle(obj);
2269
2270         return 0;
2271 }
2272
2273 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2274 {
2275         struct drm_gem_object *obj = reg->obj;
2276         struct drm_device *dev = obj->dev;
2277         drm_i915_private_t *dev_priv = dev->dev_private;
2278         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2279         int regnum = obj_priv->fence_reg;
2280         uint64_t val;
2281
2282         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2283                     0xfffff000) << 32;
2284         val |= obj_priv->gtt_offset & 0xfffff000;
2285         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2286         if (obj_priv->tiling_mode == I915_TILING_Y)
2287                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2288         val |= I965_FENCE_REG_VALID;
2289
2290         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2291 }
2292
2293 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2294 {
2295         struct drm_gem_object *obj = reg->obj;
2296         struct drm_device *dev = obj->dev;
2297         drm_i915_private_t *dev_priv = dev->dev_private;
2298         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2299         int regnum = obj_priv->fence_reg;
2300         int tile_width;
2301         uint32_t fence_reg, val;
2302         uint32_t pitch_val;
2303
2304         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2305             (obj_priv->gtt_offset & (obj->size - 1))) {
2306                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2307                      __func__, obj_priv->gtt_offset, obj->size);
2308                 return;
2309         }
2310
2311         if (obj_priv->tiling_mode == I915_TILING_Y &&
2312             HAS_128_BYTE_Y_TILING(dev))
2313                 tile_width = 128;
2314         else
2315                 tile_width = 512;
2316
2317         /* Note: pitch better be a power of two tile widths */
2318         pitch_val = obj_priv->stride / tile_width;
2319         pitch_val = ffs(pitch_val) - 1;
2320
2321         val = obj_priv->gtt_offset;
2322         if (obj_priv->tiling_mode == I915_TILING_Y)
2323                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2324         val |= I915_FENCE_SIZE_BITS(obj->size);
2325         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2326         val |= I830_FENCE_REG_VALID;
2327
2328         if (regnum < 8)
2329                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2330         else
2331                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2332         I915_WRITE(fence_reg, val);
2333 }
2334
2335 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2336 {
2337         struct drm_gem_object *obj = reg->obj;
2338         struct drm_device *dev = obj->dev;
2339         drm_i915_private_t *dev_priv = dev->dev_private;
2340         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2341         int regnum = obj_priv->fence_reg;
2342         uint32_t val;
2343         uint32_t pitch_val;
2344         uint32_t fence_size_bits;
2345
2346         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2347             (obj_priv->gtt_offset & (obj->size - 1))) {
2348                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2349                      __func__, obj_priv->gtt_offset);
2350                 return;
2351         }
2352
2353         pitch_val = obj_priv->stride / 128;
2354         pitch_val = ffs(pitch_val) - 1;
2355         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2356
2357         val = obj_priv->gtt_offset;
2358         if (obj_priv->tiling_mode == I915_TILING_Y)
2359                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2360         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2361         WARN_ON(fence_size_bits & ~0x00000f00);
2362         val |= fence_size_bits;
2363         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2364         val |= I830_FENCE_REG_VALID;
2365
2366         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2367 }
2368
2369 /**
2370  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2371  * @obj: object to map through a fence reg
2372  *
2373  * When mapping objects through the GTT, userspace wants to be able to write
2374  * to them without having to worry about swizzling if the object is tiled.
2375  *
2376  * This function walks the fence regs looking for a free one for @obj,
2377  * stealing one if it can't find any.
2378  *
2379  * It then sets up the reg based on the object's properties: address, pitch
2380  * and tiling format.
2381  */
2382 int
2383 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2384 {
2385         struct drm_device *dev = obj->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2388         struct drm_i915_fence_reg *reg = NULL;
2389         struct drm_i915_gem_object *old_obj_priv = NULL;
2390         int i, ret, avail;
2391
2392         /* Just update our place in the LRU if our fence is getting used. */
2393         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2394                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2395                 return 0;
2396         }
2397
2398         switch (obj_priv->tiling_mode) {
2399         case I915_TILING_NONE:
2400                 WARN(1, "allocating a fence for non-tiled object?\n");
2401                 break;
2402         case I915_TILING_X:
2403                 if (!obj_priv->stride)
2404                         return -EINVAL;
2405                 WARN((obj_priv->stride & (512 - 1)),
2406                      "object 0x%08x is X tiled but has non-512B pitch\n",
2407                      obj_priv->gtt_offset);
2408                 break;
2409         case I915_TILING_Y:
2410                 if (!obj_priv->stride)
2411                         return -EINVAL;
2412                 WARN((obj_priv->stride & (128 - 1)),
2413                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2414                      obj_priv->gtt_offset);
2415                 break;
2416         }
2417
2418         /* First try to find a free reg */
2419         avail = 0;
2420         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2421                 reg = &dev_priv->fence_regs[i];
2422                 if (!reg->obj)
2423                         break;
2424
2425                 old_obj_priv = reg->obj->driver_private;
2426                 if (!old_obj_priv->pin_count)
2427                     avail++;
2428         }
2429
2430         /* None available, try to steal one or wait for a user to finish */
2431         if (i == dev_priv->num_fence_regs) {
2432                 struct drm_gem_object *old_obj = NULL;
2433
2434                 if (avail == 0)
2435                         return -ENOSPC;
2436
2437                 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2438                                     fence_list) {
2439                         old_obj = old_obj_priv->obj;
2440
2441                         if (old_obj_priv->pin_count)
2442                                 continue;
2443
2444                         /* Take a reference, as otherwise the wait_rendering
2445                          * below may cause the object to get freed out from
2446                          * under us.
2447                          */
2448                         drm_gem_object_reference(old_obj);
2449
2450                         /* i915 uses fences for GPU access to tiled buffers */
2451                         if (IS_I965G(dev) || !old_obj_priv->active)
2452                                 break;
2453
2454                         /* This brings the object to the head of the LRU if it
2455                          * had been written to.  The only way this should
2456                          * result in us waiting longer than the expected
2457                          * optimal amount of time is if there was a
2458                          * fence-using buffer later that was read-only.
2459                          */
2460                         i915_gem_object_flush_gpu_write_domain(old_obj);
2461                         ret = i915_gem_object_wait_rendering(old_obj);
2462                         if (ret != 0) {
2463                                 drm_gem_object_unreference(old_obj);
2464                                 return ret;
2465                         }
2466
2467                         break;
2468                 }
2469
2470                 /*
2471                  * Zap this virtual mapping so we can set up a fence again
2472                  * for this object next time we need it.
2473                  */
2474                 i915_gem_release_mmap(old_obj);
2475
2476                 i = old_obj_priv->fence_reg;
2477                 reg = &dev_priv->fence_regs[i];
2478
2479                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2480                 list_del_init(&old_obj_priv->fence_list);
2481
2482                 drm_gem_object_unreference(old_obj);
2483         }
2484
2485         obj_priv->fence_reg = i;
2486         list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2487
2488         reg->obj = obj;
2489
2490         if (IS_I965G(dev))
2491                 i965_write_fence_reg(reg);
2492         else if (IS_I9XX(dev))
2493                 i915_write_fence_reg(reg);
2494         else
2495                 i830_write_fence_reg(reg);
2496
2497         trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2498
2499         return 0;
2500 }
2501
2502 /**
2503  * i915_gem_clear_fence_reg - clear out fence register info
2504  * @obj: object to clear
2505  *
2506  * Zeroes out the fence register itself and clears out the associated
2507  * data structures in dev_priv and obj_priv.
2508  */
2509 static void
2510 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2511 {
2512         struct drm_device *dev = obj->dev;
2513         drm_i915_private_t *dev_priv = dev->dev_private;
2514         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2515
2516         if (IS_I965G(dev))
2517                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2518         else {
2519                 uint32_t fence_reg;
2520
2521                 if (obj_priv->fence_reg < 8)
2522                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2523                 else
2524                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2525                                                        8) * 4;
2526
2527                 I915_WRITE(fence_reg, 0);
2528         }
2529
2530         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2531         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2532         list_del_init(&obj_priv->fence_list);
2533 }
2534
2535 /**
2536  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2537  * to the buffer to finish, and then resets the fence register.
2538  * @obj: tiled object holding a fence register.
2539  *
2540  * Zeroes out the fence register itself and clears out the associated
2541  * data structures in dev_priv and obj_priv.
2542  */
2543 int
2544 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2545 {
2546         struct drm_device *dev = obj->dev;
2547         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2548
2549         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2550                 return 0;
2551
2552         /* On the i915, GPU access to tiled buffers is via a fence,
2553          * therefore we must wait for any outstanding access to complete
2554          * before clearing the fence.
2555          */
2556         if (!IS_I965G(dev)) {
2557                 int ret;
2558
2559                 i915_gem_object_flush_gpu_write_domain(obj);
2560                 i915_gem_object_flush_gtt_write_domain(obj);
2561                 ret = i915_gem_object_wait_rendering(obj);
2562                 if (ret != 0)
2563                         return ret;
2564         }
2565
2566         i915_gem_clear_fence_reg (obj);
2567
2568         return 0;
2569 }
2570
2571 /**
2572  * Finds free space in the GTT aperture and binds the object there.
2573  */
2574 static int
2575 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2576 {
2577         struct drm_device *dev = obj->dev;
2578         drm_i915_private_t *dev_priv = dev->dev_private;
2579         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2580         struct drm_mm_node *free_space;
2581         bool retry_alloc = false;
2582         int ret;
2583
2584         if (dev_priv->mm.suspended)
2585                 return -EBUSY;
2586
2587         if (obj_priv->madv != I915_MADV_WILLNEED) {
2588                 DRM_ERROR("Attempting to bind a purgeable object\n");
2589                 return -EINVAL;
2590         }
2591
2592         if (alignment == 0)
2593                 alignment = i915_gem_get_gtt_alignment(obj);
2594         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2595                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2596                 return -EINVAL;
2597         }
2598
2599  search_free:
2600         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2601                                         obj->size, alignment, 0);
2602         if (free_space != NULL) {
2603                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2604                                                        alignment);
2605                 if (obj_priv->gtt_space != NULL) {
2606                         obj_priv->gtt_space->private = obj;
2607                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2608                 }
2609         }
2610         if (obj_priv->gtt_space == NULL) {
2611                 /* If the gtt is empty and we're still having trouble
2612                  * fitting our object in, we're out of memory.
2613                  */
2614 #if WATCH_LRU
2615                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2616 #endif
2617                 ret = i915_gem_evict_something(dev, obj->size);
2618                 if (ret)
2619                         return ret;
2620
2621                 goto search_free;
2622         }
2623
2624 #if WATCH_BUF
2625         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2626                  obj->size, obj_priv->gtt_offset);
2627 #endif
2628         if (retry_alloc) {
2629                 i915_gem_object_set_page_gfp_mask (obj,
2630                                                    i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2631         }
2632         ret = i915_gem_object_get_pages(obj);
2633         if (retry_alloc) {
2634                 i915_gem_object_set_page_gfp_mask (obj,
2635                                                    i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2636         }
2637         if (ret) {
2638                 drm_mm_put_block(obj_priv->gtt_space);
2639                 obj_priv->gtt_space = NULL;
2640
2641                 if (ret == -ENOMEM) {
2642                         /* first try to clear up some space from the GTT */
2643                         ret = i915_gem_evict_something(dev, obj->size);
2644                         if (ret) {
2645                                 /* now try to shrink everyone else */
2646                                 if (! retry_alloc) {
2647                                     retry_alloc = true;
2648                                     goto search_free;
2649                                 }
2650
2651                                 return ret;
2652                         }
2653
2654                         goto search_free;
2655                 }
2656
2657                 return ret;
2658         }
2659
2660         /* Create an AGP memory structure pointing at our pages, and bind it
2661          * into the GTT.
2662          */
2663         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2664                                                obj_priv->pages,
2665                                                obj->size >> PAGE_SHIFT,
2666                                                obj_priv->gtt_offset,
2667                                                obj_priv->agp_type);
2668         if (obj_priv->agp_mem == NULL) {
2669                 i915_gem_object_put_pages(obj);
2670                 drm_mm_put_block(obj_priv->gtt_space);
2671                 obj_priv->gtt_space = NULL;
2672
2673                 ret = i915_gem_evict_something(dev, obj->size);
2674                 if (ret)
2675                         return ret;
2676
2677                 goto search_free;
2678         }
2679         atomic_inc(&dev->gtt_count);
2680         atomic_add(obj->size, &dev->gtt_memory);
2681
2682         /* Assert that the object is not currently in any GPU domain. As it
2683          * wasn't in the GTT, there shouldn't be any way it could have been in
2684          * a GPU cache
2685          */
2686         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2687         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2688
2689         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2690
2691         return 0;
2692 }
2693
2694 void
2695 i915_gem_clflush_object(struct drm_gem_object *obj)
2696 {
2697         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2698
2699         /* If we don't have a page list set up, then we're not pinned
2700          * to GPU, and we can ignore the cache flush because it'll happen
2701          * again at bind time.
2702          */
2703         if (obj_priv->pages == NULL)
2704                 return;
2705
2706         trace_i915_gem_object_clflush(obj);
2707
2708         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2709 }
2710
2711 /** Flushes any GPU write domain for the object if it's dirty. */
2712 static void
2713 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2714 {
2715         struct drm_device *dev = obj->dev;
2716         uint32_t seqno;
2717         uint32_t old_write_domain;
2718
2719         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2720                 return;
2721
2722         /* Queue the GPU write cache flushing we need. */
2723         old_write_domain = obj->write_domain;
2724         i915_gem_flush(dev, 0, obj->write_domain);
2725         seqno = i915_add_request(dev, NULL, obj->write_domain);
2726         obj->write_domain = 0;
2727         i915_gem_object_move_to_active(obj, seqno);
2728
2729         trace_i915_gem_object_change_domain(obj,
2730                                             obj->read_domains,
2731                                             old_write_domain);
2732 }
2733
2734 /** Flushes the GTT write domain for the object if it's dirty. */
2735 static void
2736 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2737 {
2738         uint32_t old_write_domain;
2739
2740         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2741                 return;
2742
2743         /* No actual flushing is required for the GTT write domain.   Writes
2744          * to it immediately go to main memory as far as we know, so there's
2745          * no chipset flush.  It also doesn't land in render cache.
2746          */
2747         old_write_domain = obj->write_domain;
2748         obj->write_domain = 0;
2749
2750         trace_i915_gem_object_change_domain(obj,
2751                                             obj->read_domains,
2752                                             old_write_domain);
2753 }
2754
2755 /** Flushes the CPU write domain for the object if it's dirty. */
2756 static void
2757 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2758 {
2759         struct drm_device *dev = obj->dev;
2760         uint32_t old_write_domain;
2761
2762         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2763                 return;
2764
2765         i915_gem_clflush_object(obj);
2766         drm_agp_chipset_flush(dev);
2767         old_write_domain = obj->write_domain;
2768         obj->write_domain = 0;
2769
2770         trace_i915_gem_object_change_domain(obj,
2771                                             obj->read_domains,
2772                                             old_write_domain);
2773 }
2774
2775 void
2776 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2777 {
2778         switch (obj->write_domain) {
2779         case I915_GEM_DOMAIN_GTT:
2780                 i915_gem_object_flush_gtt_write_domain(obj);
2781                 break;
2782         case I915_GEM_DOMAIN_CPU:
2783                 i915_gem_object_flush_cpu_write_domain(obj);
2784                 break;
2785         default:
2786                 i915_gem_object_flush_gpu_write_domain(obj);
2787                 break;
2788         }
2789 }
2790
2791 /**
2792  * Moves a single object to the GTT read, and possibly write domain.
2793  *
2794  * This function returns when the move is complete, including waiting on
2795  * flushes to occur.
2796  */
2797 int
2798 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2799 {
2800         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2801         uint32_t old_write_domain, old_read_domains;
2802         int ret;
2803
2804         /* Not valid to be called on unbound objects. */
2805         if (obj_priv->gtt_space == NULL)
2806                 return -EINVAL;
2807
2808         i915_gem_object_flush_gpu_write_domain(obj);
2809         /* Wait on any GPU rendering and flushing to occur. */
2810         ret = i915_gem_object_wait_rendering(obj);
2811         if (ret != 0)
2812                 return ret;
2813
2814         old_write_domain = obj->write_domain;
2815         old_read_domains = obj->read_domains;
2816
2817         /* If we're writing through the GTT domain, then CPU and GPU caches
2818          * will need to be invalidated at next use.
2819          */
2820         if (write)
2821                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2822
2823         i915_gem_object_flush_cpu_write_domain(obj);
2824
2825         /* It should now be out of any other write domains, and we can update
2826          * the domain values for our changes.
2827          */
2828         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2829         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2830         if (write) {
2831                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2832                 obj_priv->dirty = 1;
2833         }
2834
2835         trace_i915_gem_object_change_domain(obj,
2836                                             old_read_domains,
2837                                             old_write_domain);
2838
2839         return 0;
2840 }
2841
2842 /**
2843  * Moves a single object to the CPU read, and possibly write domain.
2844  *
2845  * This function returns when the move is complete, including waiting on
2846  * flushes to occur.
2847  */
2848 static int
2849 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2850 {
2851         uint32_t old_write_domain, old_read_domains;
2852         int ret;
2853
2854         i915_gem_object_flush_gpu_write_domain(obj);
2855         /* Wait on any GPU rendering and flushing to occur. */
2856         ret = i915_gem_object_wait_rendering(obj);
2857         if (ret != 0)
2858                 return ret;
2859
2860         i915_gem_object_flush_gtt_write_domain(obj);
2861
2862         /* If we have a partially-valid cache of the object in the CPU,
2863          * finish invalidating it and free the per-page flags.
2864          */
2865         i915_gem_object_set_to_full_cpu_read_domain(obj);
2866
2867         old_write_domain = obj->write_domain;
2868         old_read_domains = obj->read_domains;
2869
2870         /* Flush the CPU cache if it's still invalid. */
2871         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2872                 i915_gem_clflush_object(obj);
2873
2874                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2875         }
2876
2877         /* It should now be out of any other write domains, and we can update
2878          * the domain values for our changes.
2879          */
2880         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2881
2882         /* If we're writing through the CPU, then the GPU read domains will
2883          * need to be invalidated at next use.
2884          */
2885         if (write) {
2886                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2887                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2888         }
2889
2890         trace_i915_gem_object_change_domain(obj,
2891                                             old_read_domains,
2892                                             old_write_domain);
2893
2894         return 0;
2895 }
2896
2897 /*
2898  * Set the next domain for the specified object. This
2899  * may not actually perform the necessary flushing/invaliding though,
2900  * as that may want to be batched with other set_domain operations
2901  *
2902  * This is (we hope) the only really tricky part of gem. The goal
2903  * is fairly simple -- track which caches hold bits of the object
2904  * and make sure they remain coherent. A few concrete examples may
2905  * help to explain how it works. For shorthand, we use the notation
2906  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2907  * a pair of read and write domain masks.
2908  *
2909  * Case 1: the batch buffer
2910  *
2911  *      1. Allocated
2912  *      2. Written by CPU
2913  *      3. Mapped to GTT
2914  *      4. Read by GPU
2915  *      5. Unmapped from GTT
2916  *      6. Freed
2917  *
2918  *      Let's take these a step at a time
2919  *
2920  *      1. Allocated
2921  *              Pages allocated from the kernel may still have
2922  *              cache contents, so we set them to (CPU, CPU) always.
2923  *      2. Written by CPU (using pwrite)
2924  *              The pwrite function calls set_domain (CPU, CPU) and
2925  *              this function does nothing (as nothing changes)
2926  *      3. Mapped by GTT
2927  *              This function asserts that the object is not
2928  *              currently in any GPU-based read or write domains
2929  *      4. Read by GPU
2930  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2931  *              As write_domain is zero, this function adds in the
2932  *              current read domains (CPU+COMMAND, 0).
2933  *              flush_domains is set to CPU.
2934  *              invalidate_domains is set to COMMAND
2935  *              clflush is run to get data out of the CPU caches
2936  *              then i915_dev_set_domain calls i915_gem_flush to
2937  *              emit an MI_FLUSH and drm_agp_chipset_flush
2938  *      5. Unmapped from GTT
2939  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2940  *              flush_domains and invalidate_domains end up both zero
2941  *              so no flushing/invalidating happens
2942  *      6. Freed
2943  *              yay, done
2944  *
2945  * Case 2: The shared render buffer
2946  *
2947  *      1. Allocated
2948  *      2. Mapped to GTT
2949  *      3. Read/written by GPU
2950  *      4. set_domain to (CPU,CPU)
2951  *      5. Read/written by CPU
2952  *      6. Read/written by GPU
2953  *
2954  *      1. Allocated
2955  *              Same as last example, (CPU, CPU)
2956  *      2. Mapped to GTT
2957  *              Nothing changes (assertions find that it is not in the GPU)
2958  *      3. Read/written by GPU
2959  *              execbuffer calls set_domain (RENDER, RENDER)
2960  *              flush_domains gets CPU
2961  *              invalidate_domains gets GPU
2962  *              clflush (obj)
2963  *              MI_FLUSH and drm_agp_chipset_flush
2964  *      4. set_domain (CPU, CPU)
2965  *              flush_domains gets GPU
2966  *              invalidate_domains gets CPU
2967  *              wait_rendering (obj) to make sure all drawing is complete.
2968  *              This will include an MI_FLUSH to get the data from GPU
2969  *              to memory
2970  *              clflush (obj) to invalidate the CPU cache
2971  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2972  *      5. Read/written by CPU
2973  *              cache lines are loaded and dirtied
2974  *      6. Read written by GPU
2975  *              Same as last GPU access
2976  *
2977  * Case 3: The constant buffer
2978  *
2979  *      1. Allocated
2980  *      2. Written by CPU
2981  *      3. Read by GPU
2982  *      4. Updated (written) by CPU again
2983  *      5. Read by GPU
2984  *
2985  *      1. Allocated
2986  *              (CPU, CPU)
2987  *      2. Written by CPU
2988  *              (CPU, CPU)
2989  *      3. Read by GPU
2990  *              (CPU+RENDER, 0)
2991  *              flush_domains = CPU
2992  *              invalidate_domains = RENDER
2993  *              clflush (obj)
2994  *              MI_FLUSH
2995  *              drm_agp_chipset_flush
2996  *      4. Updated (written) by CPU again
2997  *              (CPU, CPU)
2998  *              flush_domains = 0 (no previous write domain)
2999  *              invalidate_domains = 0 (no new read domains)
3000  *      5. Read by GPU
3001  *              (CPU+RENDER, 0)
3002  *              flush_domains = CPU
3003  *              invalidate_domains = RENDER
3004  *              clflush (obj)
3005  *              MI_FLUSH
3006  *              drm_agp_chipset_flush
3007  */
3008 static void
3009 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3010 {
3011         struct drm_device               *dev = obj->dev;
3012         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
3013         uint32_t                        invalidate_domains = 0;
3014         uint32_t                        flush_domains = 0;
3015         uint32_t                        old_read_domains;
3016
3017         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3018         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3019
3020         intel_mark_busy(dev, obj);
3021
3022 #if WATCH_BUF
3023         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3024                  __func__, obj,
3025                  obj->read_domains, obj->pending_read_domains,
3026                  obj->write_domain, obj->pending_write_domain);
3027 #endif
3028         /*
3029          * If the object isn't moving to a new write domain,
3030          * let the object stay in multiple read domains
3031          */
3032         if (obj->pending_write_domain == 0)
3033                 obj->pending_read_domains |= obj->read_domains;
3034         else
3035                 obj_priv->dirty = 1;
3036
3037         /*
3038          * Flush the current write domain if
3039          * the new read domains don't match. Invalidate
3040          * any read domains which differ from the old
3041          * write domain
3042          */
3043         if (obj->write_domain &&
3044             obj->write_domain != obj->pending_read_domains) {
3045                 flush_domains |= obj->write_domain;
3046                 invalidate_domains |=
3047                         obj->pending_read_domains & ~obj->write_domain;
3048         }
3049         /*
3050          * Invalidate any read caches which may have
3051          * stale data. That is, any new read domains.
3052          */
3053         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3054         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3055 #if WATCH_BUF
3056                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3057                          __func__, flush_domains, invalidate_domains);
3058 #endif
3059                 i915_gem_clflush_object(obj);
3060         }
3061
3062         old_read_domains = obj->read_domains;
3063
3064         /* The actual obj->write_domain will be updated with
3065          * pending_write_domain after we emit the accumulated flush for all
3066          * of our domain changes in execbuffers (which clears objects'
3067          * write_domains).  So if we have a current write domain that we
3068          * aren't changing, set pending_write_domain to that.
3069          */
3070         if (flush_domains == 0 && obj->pending_write_domain == 0)
3071                 obj->pending_write_domain = obj->write_domain;
3072         obj->read_domains = obj->pending_read_domains;
3073
3074         dev->invalidate_domains |= invalidate_domains;
3075         dev->flush_domains |= flush_domains;
3076 #if WATCH_BUF
3077         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3078                  __func__,
3079                  obj->read_domains, obj->write_domain,
3080                  dev->invalidate_domains, dev->flush_domains);
3081 #endif
3082
3083         trace_i915_gem_object_change_domain(obj,
3084                                             old_read_domains,
3085                                             obj->write_domain);
3086 }
3087
3088 /**
3089  * Moves the object from a partially CPU read to a full one.
3090  *
3091  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3092  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3093  */
3094 static void
3095 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3096 {
3097         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3098
3099         if (!obj_priv->page_cpu_valid)
3100                 return;
3101
3102         /* If we're partially in the CPU read domain, finish moving it in.
3103          */
3104         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3105                 int i;
3106
3107                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3108                         if (obj_priv->page_cpu_valid[i])
3109                                 continue;
3110                         drm_clflush_pages(obj_priv->pages + i, 1);
3111                 }
3112         }
3113
3114         /* Free the page_cpu_valid mappings which are now stale, whether
3115          * or not we've got I915_GEM_DOMAIN_CPU.
3116          */
3117         kfree(obj_priv->page_cpu_valid);
3118         obj_priv->page_cpu_valid = NULL;
3119 }
3120
3121 /**
3122  * Set the CPU read domain on a range of the object.
3123  *
3124  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3125  * not entirely valid.  The page_cpu_valid member of the object flags which
3126  * pages have been flushed, and will be respected by
3127  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3128  * of the whole object.
3129  *
3130  * This function returns when the move is complete, including waiting on
3131  * flushes to occur.
3132  */
3133 static int
3134 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3135                                           uint64_t offset, uint64_t size)
3136 {
3137         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3138         uint32_t old_read_domains;
3139         int i, ret;
3140
3141         if (offset == 0 && size == obj->size)
3142                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3143
3144         i915_gem_object_flush_gpu_write_domain(obj);
3145         /* Wait on any GPU rendering and flushing to occur. */
3146         ret = i915_gem_object_wait_rendering(obj);
3147         if (ret != 0)
3148                 return ret;
3149         i915_gem_object_flush_gtt_write_domain(obj);
3150
3151         /* If we're already fully in the CPU read domain, we're done. */
3152         if (obj_priv->page_cpu_valid == NULL &&
3153             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3154