1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_connector.h>
58 #include <drm/i915_mei_hdcp_interface.h>
60 #include "i915_fixed.h"
61 #include "i915_params.h"
63 #include "i915_utils.h"
65 #include "intel_bios.h"
66 #include "intel_device_info.h"
67 #include "intel_display.h"
68 #include "intel_dpll_mgr.h"
69 #include "intel_lrc.h"
70 #include "intel_opregion.h"
71 #include "intel_ringbuffer.h"
72 #include "intel_uncore.h"
73 #include "intel_wopcm.h"
74 #include "intel_workarounds.h"
78 #include "i915_gem_context.h"
79 #include "i915_gem_fence_reg.h"
80 #include "i915_gem_object.h"
81 #include "i915_gem_gtt.h"
82 #include "i915_gpu_error.h"
83 #include "i915_request.h"
84 #include "i915_scheduler.h"
85 #include "i915_timeline.h"
88 #include "intel_gvt.h"
90 /* General customization:
93 #define DRIVER_NAME "i915"
94 #define DRIVER_DESC "Intel Graphics"
95 #define DRIVER_DATE "20190311"
96 #define DRIVER_TIMESTAMP 1552292224
98 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
99 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
100 * which may not necessarily be a user visible problem. This will either
101 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
102 * enable distros and users to tailor their preferred amount of i915 abrt
105 #define I915_STATE_WARN(condition, format...) ({ \
106 int __ret_warn_on = !!(condition); \
107 if (unlikely(__ret_warn_on)) \
108 if (!WARN(i915_modparams.verbose_state_checks, format)) \
110 unlikely(__ret_warn_on); \
113 #define I915_STATE_WARN_ON(x) \
114 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
116 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
118 bool __i915_inject_load_failure(const char *func, int line);
119 #define i915_inject_load_failure() \
120 __i915_inject_load_failure(__func__, __LINE__)
122 bool i915_error_injected(void);
126 #define i915_inject_load_failure() false
127 #define i915_error_injected() false
131 #define i915_load_error(i915, fmt, ...) \
132 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
135 typedef depot_stack_handle_t intel_wakeref_t;
139 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
152 #define for_each_hpd_pin(__pin) \
153 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
155 /* Threshold == 5 for long IRQs, 50 for short */
156 #define HPD_STORM_DEFAULT_THRESHOLD 50
158 struct i915_hotplug {
159 struct work_struct hotplug_work;
162 unsigned long last_jiffies;
167 HPD_MARK_DISABLED = 2
169 } stats[HPD_NUM_PINS];
171 struct delayed_work reenable_work;
175 struct work_struct dig_port_work;
177 struct work_struct poll_init_work;
180 unsigned int hpd_storm_threshold;
181 /* Whether or not to count short HPD IRQs in HPD storms */
182 u8 hpd_short_storm_enabled;
185 * if we get a HPD irq from DP and a HPD irq from non-DP
186 * the non-DP HPD could block the workqueue on a mode config
187 * mutex getting, that userspace may have taken. However
188 * userspace is waiting on the DP workqueue to run which is
189 * blocked behind the non-DP one.
191 struct workqueue_struct *dp_wq;
194 #define I915_GEM_GPU_DOMAINS \
195 (I915_GEM_DOMAIN_RENDER | \
196 I915_GEM_DOMAIN_SAMPLER | \
197 I915_GEM_DOMAIN_COMMAND | \
198 I915_GEM_DOMAIN_INSTRUCTION | \
199 I915_GEM_DOMAIN_VERTEX)
201 struct drm_i915_private;
202 struct i915_mm_struct;
203 struct i915_mmu_object;
205 struct drm_i915_file_private {
206 struct drm_i915_private *dev_priv;
207 struct drm_file *file;
211 struct list_head request_list;
212 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
213 * chosen to prevent the CPU getting more than a frame ahead of the GPU
214 * (when using lax throttling for the frontbuffer). We also use it to
215 * offer free GPU waitboosts for severely congested workloads.
217 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
219 struct idr context_idr;
221 unsigned int bsd_engine;
224 * Every context ban increments per client ban score. Also
225 * hangs in short succession increments ban score. If ban threshold
226 * is reached, client is considered banned and submitting more work
227 * will fail. This is a stop gap measure to limit the badly behaving
228 * clients access to gpu. Note that unbannable contexts never increment
229 * the client ban score.
231 #define I915_CLIENT_SCORE_HANG_FAST 1
232 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
233 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
234 #define I915_CLIENT_SCORE_BANNED 9
235 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
237 unsigned long hang_timestamp;
240 /* Interface history:
243 * 1.2: Add Power Management
244 * 1.3: Add vblank support
245 * 1.4: Fix cmdbuffer path, add heap destroy
246 * 1.5: Add vblank pipe configuration
247 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
248 * - Support vertical blank on secondary display pipe
250 #define DRIVER_MAJOR 1
251 #define DRIVER_MINOR 6
252 #define DRIVER_PATCHLEVEL 0
254 struct intel_overlay;
255 struct intel_overlay_error_state;
257 struct sdvo_device_mapping {
266 struct intel_connector;
267 struct intel_encoder;
268 struct intel_atomic_state;
269 struct intel_crtc_state;
270 struct intel_initial_plane_config;
274 struct intel_cdclk_state;
276 struct drm_i915_display_funcs {
277 void (*get_cdclk)(struct drm_i915_private *dev_priv,
278 struct intel_cdclk_state *cdclk_state);
279 void (*set_cdclk)(struct drm_i915_private *dev_priv,
280 const struct intel_cdclk_state *cdclk_state);
281 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
282 enum i9xx_plane_id i9xx_plane);
283 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
284 int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
285 void (*initial_watermarks)(struct intel_atomic_state *state,
286 struct intel_crtc_state *cstate);
287 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
288 struct intel_crtc_state *cstate);
289 void (*optimize_watermarks)(struct intel_atomic_state *state,
290 struct intel_crtc_state *cstate);
291 int (*compute_global_watermarks)(struct intel_atomic_state *state);
292 void (*update_wm)(struct intel_crtc *crtc);
293 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
294 /* Returns the active state of the crtc, and if the crtc is active,
295 * fills out the pipe-config with the hw state. */
296 bool (*get_pipe_config)(struct intel_crtc *,
297 struct intel_crtc_state *);
298 void (*get_initial_plane_config)(struct intel_crtc *,
299 struct intel_initial_plane_config *);
300 int (*crtc_compute_clock)(struct intel_crtc *crtc,
301 struct intel_crtc_state *crtc_state);
302 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
303 struct drm_atomic_state *old_state);
304 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
305 struct drm_atomic_state *old_state);
306 void (*update_crtcs)(struct drm_atomic_state *state);
307 void (*audio_codec_enable)(struct intel_encoder *encoder,
308 const struct intel_crtc_state *crtc_state,
309 const struct drm_connector_state *conn_state);
310 void (*audio_codec_disable)(struct intel_encoder *encoder,
311 const struct intel_crtc_state *old_crtc_state,
312 const struct drm_connector_state *old_conn_state);
313 void (*fdi_link_train)(struct intel_crtc *crtc,
314 const struct intel_crtc_state *crtc_state);
315 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
316 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
317 /* clock updates for mode set */
319 /* render clock increase/decrease */
320 /* display clock increase/decrease */
321 /* pll clock increase/decrease */
324 * Program double buffered color management registers during
325 * vblank evasion. The registers should then latch during the
326 * next vblank start, alongside any other double buffered registers
327 * involved with the same commit.
329 void (*color_commit)(const struct intel_crtc_state *crtc_state);
331 * Load LUTs (and other single buffered color management
332 * registers). Will (hopefully) be called during the vblank
333 * following the latching of any double buffered registers
334 * involved with the same commit.
336 void (*load_luts)(const struct intel_crtc_state *crtc_state);
339 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
340 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
341 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
344 struct work_struct work;
346 u32 required_version;
347 u32 max_fw_size; /* bytes */
349 u32 dmc_fw_size; /* dwords */
352 i915_reg_t mmioaddr[8];
356 intel_wakeref_t wakeref;
359 enum i915_cache_level {
361 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
362 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
363 caches, eg sampler/render caches, and the
364 large Last-Level-Cache. LLC is coherent with
365 the CPU, but L3 is only visible to the GPU. */
366 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
369 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
380 /* This is always the inner lock when overlapping with struct_mutex and
381 * it's the outer lock when overlapping with stolen_lock. */
384 unsigned int possible_framebuffer_bits;
385 unsigned int busy_bits;
386 unsigned int visible_pipes_mask;
387 struct intel_crtc *crtc;
389 struct drm_mm_node compressed_fb;
390 struct drm_mm_node *compressed_llb;
398 bool underrun_detected;
399 struct work_struct underrun_work;
402 * Due to the atomic rules we can't access some structures without the
403 * appropriate locking, so we cache information here in order to avoid
406 struct intel_fbc_state_cache {
407 struct i915_vma *vma;
411 unsigned int mode_flags;
412 u32 hsw_bdw_pixel_rate;
416 unsigned int rotation;
421 * Display surface base address adjustement for
422 * pageflips. Note that on gen4+ this only adjusts up
423 * to a tile, offsets within a tile are handled in
424 * the hw itself (with the TILEOFF register).
431 u16 pixel_blend_mode;
435 const struct drm_format_info *format;
441 * This structure contains everything that's relevant to program the
442 * hardware registers. When we want to figure out if we need to disable
443 * and re-enable FBC for a new configuration we just check if there's
444 * something different in the struct. The genx_fbc_activate functions
445 * are supposed to read from it in order to program the registers.
447 struct intel_fbc_reg_params {
448 struct i915_vma *vma;
453 enum i9xx_plane_id i9xx_plane;
454 unsigned int fence_y_offset;
458 const struct drm_format_info *format;
463 unsigned int gen9_wa_cfb_stride;
466 const char *no_fbc_reason;
470 * HIGH_RR is the highest eDP panel refresh rate read from EDID
471 * LOW_RR is the lowest eDP panel refresh rate found from EDID
472 * parsing for same resolution.
474 enum drrs_refresh_rate_type {
477 DRRS_MAX_RR, /* RR count */
480 enum drrs_support_type {
481 DRRS_NOT_SUPPORTED = 0,
482 STATIC_DRRS_SUPPORT = 1,
483 SEAMLESS_DRRS_SUPPORT = 2
489 struct delayed_work work;
491 unsigned busy_frontbuffer_bits;
492 enum drrs_refresh_rate_type refresh_rate_type;
493 enum drrs_support_type type;
499 #define I915_PSR_DEBUG_MODE_MASK 0x0f
500 #define I915_PSR_DEBUG_DEFAULT 0x00
501 #define I915_PSR_DEBUG_DISABLE 0x01
502 #define I915_PSR_DEBUG_ENABLE 0x02
503 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
504 #define I915_PSR_DEBUG_IRQ 0x10
512 struct work_struct work;
513 unsigned busy_frontbuffer_bits;
514 bool sink_psr2_support;
516 bool colorimetry_support;
518 u8 sink_sync_latency;
519 ktime_t last_entry_attempt;
521 bool sink_not_reliable;
523 u16 su_x_granularity;
527 * Sorted by south display engine compatibility.
528 * If the new PCH comes with a south display engine that is not
529 * inherited from the latest item, please do not add it to the
530 * end. Instead, add it right after its "parent" PCH.
533 PCH_NOP = -1, /* PCH without south display */
534 PCH_NONE = 0, /* No PCH present */
535 PCH_IBX, /* Ibexpeak PCH */
536 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
537 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
538 PCH_SPT, /* Sunrisepoint PCH */
539 PCH_KBP, /* Kaby Lake PCH */
540 PCH_CNP, /* Cannon Lake PCH */
541 PCH_ICP, /* Ice Lake PCH */
544 enum intel_sbi_destination {
549 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
550 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
551 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
552 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
553 #define QUIRK_INCREASE_T12_DELAY (1<<6)
554 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
557 struct intel_fbc_work;
560 struct i2c_adapter adapter;
561 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
565 struct i2c_algo_bit_data bit_algo;
566 struct drm_i915_private *dev_priv;
569 struct i915_suspend_saved_registers {
572 u32 saveCACHE_MODE_0;
573 u32 saveMI_ARB_STATE;
577 u64 saveFENCE[I915_MAX_NUM_FENCES];
578 u32 savePCH_PORT_HOTPLUG;
582 struct vlv_s0ix_state {
589 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
590 u32 media_max_req_count;
591 u32 gfx_max_req_count;
623 /* Display 1 CZ domain */
628 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
630 /* GT SA CZ domain */
637 /* Display 2 CZ domain */
644 struct intel_rps_ei {
652 * work, interrupts_enabled and pm_iir are protected by
655 struct work_struct work;
656 bool interrupts_enabled;
659 /* PM interrupt bits that should never be masked */
662 /* Frequencies are stored in potentially platform dependent multiples.
663 * In other words, *_freq needs to be multiplied by X to be interesting.
664 * Soft limits are those which are used for the dynamic reclocking done
665 * by the driver (raise frequencies under heavy loads, and lower for
666 * lighter loads). Hard limits are those imposed by the hardware.
668 * A distinction is made for overclocking, which is never enabled by
669 * default, and is considered to be above the hard limit if it's
672 u8 cur_freq; /* Current frequency (cached, may not == HW) */
673 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
674 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
675 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
676 u8 min_freq; /* AKA RPn. Minimum frequency */
677 u8 boost_freq; /* Frequency to request when wait boosting */
678 u8 idle_freq; /* Frequency to request when we are idle */
679 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
680 u8 rp1_freq; /* "less than" RP0 power/freqency */
681 u8 rp0_freq; /* Non-overclocked max frequency. */
682 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
689 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
690 unsigned int interactive;
692 u8 up_threshold; /* Current %busy required to uplock */
693 u8 down_threshold; /* Current %busy required to downclock */
697 atomic_t num_waiters;
700 /* manual wa residency calculations */
701 struct intel_rps_ei ei;
706 u64 prev_hw_residency[4];
707 u64 cur_residency[4];
710 struct intel_llc_pstate {
714 struct intel_gen6_power_mgmt {
715 struct intel_rps rps;
716 struct intel_rc6 rc6;
717 struct intel_llc_pstate llc_pstate;
720 /* defined intel_pm.c */
721 extern spinlock_t mchdev_lock;
723 struct intel_ilk_power_mgmt {
731 unsigned long last_time1;
732 unsigned long chipset_power;
735 unsigned long gfx_power;
742 struct drm_i915_private;
743 struct i915_power_well;
745 struct i915_power_well_ops {
747 * Synchronize the well's hw state to match the current sw state, for
748 * example enable/disable it based on the current refcount. Called
749 * during driver init and resume time, possibly after first calling
750 * the enable/disable handlers.
752 void (*sync_hw)(struct drm_i915_private *dev_priv,
753 struct i915_power_well *power_well);
755 * Enable the well and resources that depend on it (for example
756 * interrupts located on the well). Called after the 0->1 refcount
759 void (*enable)(struct drm_i915_private *dev_priv,
760 struct i915_power_well *power_well);
762 * Disable the well and resources that depend on it. Called after
763 * the 1->0 refcount transition.
765 void (*disable)(struct drm_i915_private *dev_priv,
766 struct i915_power_well *power_well);
767 /* Returns the hw enabled state. */
768 bool (*is_enabled)(struct drm_i915_private *dev_priv,
769 struct i915_power_well *power_well);
772 struct i915_power_well_regs {
779 /* Power well structure for haswell */
780 struct i915_power_well_desc {
784 /* unique identifier for this power well */
785 enum i915_power_well_id id;
787 * Arbitraty data associated with this power well. Platform and power
793 * request/status flag index in the PUNIT power well
794 * control/status registers.
802 const struct i915_power_well_regs *regs;
804 * request/status flag index in the power well
805 * constrol/status registers.
808 /* Mask of pipes whose IRQ logic is backed by the pw */
810 /* The pw is backing the VGA functionality */
814 * The pw is for an ICL+ TypeC PHY port in
820 const struct i915_power_well_ops *ops;
823 struct i915_power_well {
824 const struct i915_power_well_desc *desc;
825 /* power well enable/disable usage count */
827 /* cached hw enabled state */
831 struct i915_power_domains {
833 * Power wells needed for initialization at driver init and suspend
834 * time are on. They are kept on until after the first modeset.
837 bool display_core_suspended;
838 int power_well_count;
840 intel_wakeref_t wakeref;
843 int domain_use_count[POWER_DOMAIN_NUM];
844 struct i915_power_well *power_wells;
847 #define MAX_L3_SLICES 2
848 struct intel_l3_parity {
849 u32 *remap_info[MAX_L3_SLICES];
850 struct work_struct error_work;
855 /** Memory allocator for GTT stolen memory */
856 struct drm_mm stolen;
857 /** Protects the usage of the GTT stolen memory allocator. This is
858 * always the inner lock when overlapping with struct_mutex. */
859 struct mutex stolen_lock;
861 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
864 /** List of all objects in gtt_space. Used to restore gtt
865 * mappings on resume */
866 struct list_head bound_list;
868 * List of objects which are not bound to the GTT (thus
869 * are idle and not used by the GPU). These objects may or may
870 * not actually have any pages attached.
872 struct list_head unbound_list;
874 /** List of all objects in gtt_space, currently mmaped by userspace.
875 * All objects within this list must also be on bound_list.
877 struct list_head userfault_list;
880 * List of objects which are pending destruction.
882 struct llist_head free_list;
883 struct work_struct free_work;
884 spinlock_t free_lock;
886 * Count of objects pending destructions. Used to skip needlessly
887 * waiting on an RCU barrier if no objects are waiting to be freed.
892 * Small stash of WC pages
894 struct pagestash wc_stash;
897 * tmpfs instance used for shmem backed objects
899 struct vfsmount *gemfs;
901 /** PPGTT used for aliasing the PPGTT with the GTT */
902 struct i915_hw_ppgtt *aliasing_ppgtt;
904 struct notifier_block oom_notifier;
905 struct notifier_block vmap_notifier;
906 struct shrinker shrinker;
908 /** LRU list of objects with fence regs on them. */
909 struct list_head fence_list;
912 * Workqueue to fault in userptr pages, flushed by the execbuf
913 * when required but otherwise left to userspace to try again
916 struct workqueue_struct *userptr_wq;
918 u64 unordered_timeline;
920 /* the indicator for dispatch video commands on two BSD rings */
921 atomic_t bsd_engine_dispatch_index;
923 /** Bit 6 swizzling required for X tiling */
925 /** Bit 6 swizzling required for Y tiling */
928 /* accounting, useful for userland debugging */
929 spinlock_t object_stat_lock;
934 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
936 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
937 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
939 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
940 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
942 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
944 struct ddi_vbt_port_info {
948 * This is an index in the HDMI/DVI DDI buffer translation table.
949 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
950 * populate this field.
952 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
959 u8 supports_typec_usb:1;
962 u8 alternate_aux_channel;
963 u8 alternate_ddc_pin;
967 int dp_max_link_rate; /* 0 for not limited by VBT */
970 enum psr_lines_to_wait {
971 PSR_0_LINES_TO_WAIT = 0,
977 struct intel_vbt_data {
978 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
979 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
982 unsigned int int_tv_support:1;
983 unsigned int lvds_dither:1;
984 unsigned int int_crt_support:1;
985 unsigned int lvds_use_ssc:1;
986 unsigned int int_lvds_support:1;
987 unsigned int display_clock_mode:1;
988 unsigned int fdi_rx_polarity_inverted:1;
989 unsigned int panel_type:4;
991 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
992 enum drm_panel_orientation orientation;
994 enum drrs_support_type drrs_type;
1004 struct edp_power_seq pps;
1010 bool require_aux_wakeup;
1012 enum psr_lines_to_wait lines_to_wait;
1013 int tp1_wakeup_time_us;
1014 int tp2_tp3_wakeup_time_us;
1015 int psr2_tp2_tp3_wakeup_time_us;
1021 bool active_low_pwm;
1022 u8 min_brightness; /* min_brightness/255 of max */
1023 u8 controller; /* brightness controller number */
1024 enum intel_backlight_type type;
1030 struct mipi_config *config;
1031 struct mipi_pps_data *pps;
1037 const u8 *sequence[MIPI_SEQ_MAX];
1038 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1039 enum drm_panel_orientation orientation;
1045 struct child_device_config *child_dev;
1047 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1048 struct sdvo_device_mapping sdvo_mappings[2];
1051 enum intel_ddb_partitioning {
1053 INTEL_DDB_PART_5_6, /* IVB+ */
1056 struct intel_wm_level {
1064 struct ilk_wm_values {
1070 enum intel_ddb_partitioning partitioning;
1073 struct g4x_pipe_wm {
1074 u16 plane[I915_MAX_PLANES];
1084 struct vlv_wm_ddl_values {
1085 u8 plane[I915_MAX_PLANES];
1088 struct vlv_wm_values {
1089 struct g4x_pipe_wm pipe[3];
1090 struct g4x_sr_wm sr;
1091 struct vlv_wm_ddl_values ddl[3];
1096 struct g4x_wm_values {
1097 struct g4x_pipe_wm pipe[2];
1098 struct g4x_sr_wm sr;
1099 struct g4x_sr_wm hpll;
1105 struct skl_ddb_entry {
1106 u16 start, end; /* in number of blocks, 'end' is exclusive */
1109 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1111 return entry->end - entry->start;
1114 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1115 const struct skl_ddb_entry *e2)
1117 if (e1->start == e2->start && e1->end == e2->end)
1123 struct skl_ddb_allocation {
1124 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1127 struct skl_ddb_values {
1128 unsigned dirty_pipes;
1129 struct skl_ddb_allocation ddb;
1132 struct skl_wm_level {
1140 /* Stores plane specific WM parameters */
1141 struct skl_wm_params {
1142 bool x_tiled, y_tiled;
1147 u32 plane_pixel_rate;
1148 u32 y_min_scanlines;
1149 u32 plane_bytes_per_line;
1150 uint_fixed_16_16_t plane_blocks_per_line;
1151 uint_fixed_16_16_t y_tile_minimum;
1153 u32 dbuf_block_size;
1157 * This struct helps tracking the state needed for runtime PM, which puts the
1158 * device in PCI D3 state. Notice that when this happens, nothing on the
1159 * graphics device works, even register access, so we don't get interrupts nor
1162 * Every piece of our code that needs to actually touch the hardware needs to
1163 * either call intel_runtime_pm_get or call intel_display_power_get with the
1164 * appropriate power domain.
1166 * Our driver uses the autosuspend delay feature, which means we'll only really
1167 * suspend if we stay with zero refcount for a certain amount of time. The
1168 * default value is currently very conservative (see intel_runtime_pm_enable), but
1169 * it can be changed with the standard runtime PM files from sysfs.
1171 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1172 * goes back to false exactly before we reenable the IRQs. We use this variable
1173 * to check if someone is trying to enable/disable IRQs while they're supposed
1174 * to be disabled. This shouldn't happen and we'll print some error messages in
1177 * For more, read the Documentation/power/runtime_pm.txt.
1179 struct i915_runtime_pm {
1180 atomic_t wakeref_count;
1184 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1186 * To aide detection of wakeref leaks and general misuse, we
1187 * track all wakeref holders. With manual markup (i.e. returning
1188 * a cookie to each rpm_get caller which they then supply to their
1189 * paired rpm_put) we can remove corresponding pairs of and keep
1190 * the array trimmed to active wakerefs.
1192 struct intel_runtime_pm_debug {
1195 depot_stack_handle_t last_acquire;
1196 depot_stack_handle_t last_release;
1198 depot_stack_handle_t *owners;
1199 unsigned long count;
1204 enum intel_pipe_crc_source {
1205 INTEL_PIPE_CRC_SOURCE_NONE,
1206 INTEL_PIPE_CRC_SOURCE_PLANE1,
1207 INTEL_PIPE_CRC_SOURCE_PLANE2,
1208 INTEL_PIPE_CRC_SOURCE_PLANE3,
1209 INTEL_PIPE_CRC_SOURCE_PLANE4,
1210 INTEL_PIPE_CRC_SOURCE_PLANE5,
1211 INTEL_PIPE_CRC_SOURCE_PLANE6,
1212 INTEL_PIPE_CRC_SOURCE_PLANE7,
1213 INTEL_PIPE_CRC_SOURCE_PIPE,
1214 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1215 INTEL_PIPE_CRC_SOURCE_TV,
1216 INTEL_PIPE_CRC_SOURCE_DP_B,
1217 INTEL_PIPE_CRC_SOURCE_DP_C,
1218 INTEL_PIPE_CRC_SOURCE_DP_D,
1219 INTEL_PIPE_CRC_SOURCE_AUTO,
1220 INTEL_PIPE_CRC_SOURCE_MAX,
1223 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1224 struct intel_pipe_crc {
1227 enum intel_pipe_crc_source source;
1230 struct i915_frontbuffer_tracking {
1234 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1241 struct i915_virtual_gpu {
1246 /* used in computing the new watermarks state */
1247 struct intel_wm_config {
1248 unsigned int num_pipes_active;
1249 bool sprites_enabled;
1250 bool sprites_scaled;
1253 struct i915_oa_format {
1258 struct i915_oa_reg {
1263 struct i915_oa_config {
1264 char uuid[UUID_STRING_LEN + 1];
1267 const struct i915_oa_reg *mux_regs;
1269 const struct i915_oa_reg *b_counter_regs;
1270 u32 b_counter_regs_len;
1271 const struct i915_oa_reg *flex_regs;
1274 struct attribute_group sysfs_metric;
1275 struct attribute *attrs[2];
1276 struct device_attribute sysfs_metric_id;
1281 struct i915_perf_stream;
1284 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1286 struct i915_perf_stream_ops {
1288 * @enable: Enables the collection of HW samples, either in response to
1289 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1290 * without `I915_PERF_FLAG_DISABLED`.
1292 void (*enable)(struct i915_perf_stream *stream);
1295 * @disable: Disables the collection of HW samples, either in response
1296 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1299 void (*disable)(struct i915_perf_stream *stream);
1302 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1303 * once there is something ready to read() for the stream
1305 void (*poll_wait)(struct i915_perf_stream *stream,
1310 * @wait_unlocked: For handling a blocking read, wait until there is
1311 * something to ready to read() for the stream. E.g. wait on the same
1312 * wait queue that would be passed to poll_wait().
1314 int (*wait_unlocked)(struct i915_perf_stream *stream);
1317 * @read: Copy buffered metrics as records to userspace
1318 * **buf**: the userspace, destination buffer
1319 * **count**: the number of bytes to copy, requested by userspace
1320 * **offset**: zero at the start of the read, updated as the read
1321 * proceeds, it represents how many bytes have been copied so far and
1322 * the buffer offset for copying the next record.
1324 * Copy as many buffered i915 perf samples and records for this stream
1325 * to userspace as will fit in the given buffer.
1327 * Only write complete records; returning -%ENOSPC if there isn't room
1328 * for a complete record.
1330 * Return any error condition that results in a short read such as
1331 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1332 * returning to userspace.
1334 int (*read)(struct i915_perf_stream *stream,
1340 * @destroy: Cleanup any stream specific resources.
1342 * The stream will always be disabled before this is called.
1344 void (*destroy)(struct i915_perf_stream *stream);
1348 * struct i915_perf_stream - state for a single open stream FD
1350 struct i915_perf_stream {
1352 * @dev_priv: i915 drm device
1354 struct drm_i915_private *dev_priv;
1357 * @link: Links the stream into ``&drm_i915_private->streams``
1359 struct list_head link;
1362 * @wakeref: As we keep the device awake while the perf stream is
1363 * active, we track our runtime pm reference for later release.
1365 intel_wakeref_t wakeref;
1368 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1369 * properties given when opening a stream, representing the contents
1370 * of a single sample as read() by userspace.
1375 * @sample_size: Considering the configured contents of a sample
1376 * combined with the required header size, this is the total size
1377 * of a single sample record.
1382 * @ctx: %NULL if measuring system-wide across all contexts or a
1383 * specific context that is being monitored.
1385 struct i915_gem_context *ctx;
1388 * @enabled: Whether the stream is currently enabled, considering
1389 * whether the stream was opened in a disabled state and based
1390 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1395 * @ops: The callbacks providing the implementation of this specific
1396 * type of configured stream.
1398 const struct i915_perf_stream_ops *ops;
1401 * @oa_config: The OA configuration used by the stream.
1403 struct i915_oa_config *oa_config;
1407 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1409 struct i915_oa_ops {
1411 * @is_valid_b_counter_reg: Validates register's address for
1412 * programming boolean counters for a particular platform.
1414 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1418 * @is_valid_mux_reg: Validates register's address for programming mux
1419 * for a particular platform.
1421 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1424 * @is_valid_flex_reg: Validates register's address for programming
1425 * flex EU filtering for a particular platform.
1427 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1430 * @enable_metric_set: Selects and applies any MUX configuration to set
1431 * up the Boolean and Custom (B/C) counters that are part of the
1432 * counter reports being sampled. May apply system constraints such as
1433 * disabling EU clock gating as required.
1435 int (*enable_metric_set)(struct i915_perf_stream *stream);
1438 * @disable_metric_set: Remove system constraints associated with using
1441 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1444 * @oa_enable: Enable periodic sampling
1446 void (*oa_enable)(struct i915_perf_stream *stream);
1449 * @oa_disable: Disable periodic sampling
1451 void (*oa_disable)(struct i915_perf_stream *stream);
1454 * @read: Copy data from the circular OA buffer into a given userspace
1457 int (*read)(struct i915_perf_stream *stream,
1463 * @oa_hw_tail_read: read the OA tail pointer register
1465 * In particular this enables us to share all the fiddly code for
1466 * handling the OA unit tail pointer race that affects multiple
1469 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1472 struct intel_cdclk_state {
1473 unsigned int cdclk, vco, ref, bypass;
1477 struct drm_i915_private {
1478 struct drm_device drm;
1480 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1481 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1482 struct intel_driver_caps caps;
1485 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1486 * end of stolen which we can optionally use to create GEM objects
1487 * backed by stolen memory. Note that stolen_usable_size tells us
1488 * exactly how much of this we are actually allowed to use, given that
1489 * some portion of it is in fact reserved for use by hardware functions.
1491 struct resource dsm;
1493 * Reseved portion of Data Stolen Memory
1495 struct resource dsm_reserved;
1498 * Stolen memory is segmented in hardware with different portions
1499 * offlimits to certain functions.
1501 * The drm_mm is initialised to the total accessible range, as found
1502 * from the PCI config. On Broadwell+, this is further restricted to
1503 * avoid the first page! The upper end of stolen memory is reserved for
1504 * hardware functions and similarly removed from the accessible range.
1506 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1510 struct intel_uncore uncore;
1512 struct i915_virtual_gpu vgpu;
1514 struct intel_gvt *gvt;
1516 struct intel_wopcm wopcm;
1518 struct intel_huc huc;
1519 struct intel_guc guc;
1521 struct intel_csr csr;
1523 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1525 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1526 * controller on different i2c buses. */
1527 struct mutex gmbus_mutex;
1530 * Base address of where the gmbus and gpio blocks are located (either
1531 * on PCH or on SoC for platforms without PCH).
1535 /* MMIO base address for MIPI regs */
1542 wait_queue_head_t gmbus_wait_queue;
1544 struct pci_dev *bridge_dev;
1545 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1546 /* Context used internally to idle the GPU and setup initial state */
1547 struct i915_gem_context *kernel_context;
1548 /* Context only to be used for injecting preemption commands */
1549 struct i915_gem_context *preempt_context;
1550 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1551 [MAX_ENGINE_INSTANCE + 1];
1553 struct resource mch_res;
1555 /* protects the irq masks */
1556 spinlock_t irq_lock;
1558 bool display_irqs_enabled;
1560 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1561 struct pm_qos_request pm_qos;
1563 /* Sideband mailbox protection */
1564 struct mutex sb_lock;
1566 /** Cached value of IMR to avoid reads in updating the bitfield */
1569 u32 de_irq_mask[I915_MAX_PIPES];
1576 u32 pipestat_irq_mask[I915_MAX_PIPES];
1578 struct i915_hotplug hotplug;
1579 struct intel_fbc fbc;
1580 struct i915_drrs drrs;
1581 struct intel_opregion opregion;
1582 struct intel_vbt_data vbt;
1584 bool preserve_bios_swizzle;
1587 struct intel_overlay *overlay;
1589 /* backlight registers and fields in struct intel_panel */
1590 struct mutex backlight_lock;
1593 bool no_aux_handshake;
1595 /* protects panel power sequencer state */
1596 struct mutex pps_mutex;
1598 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1599 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1601 unsigned int fsb_freq, mem_freq, is_ddr3;
1602 unsigned int skl_preferred_vco_freq;
1603 unsigned int max_cdclk_freq;
1605 unsigned int max_dotclk_freq;
1606 unsigned int rawclk_freq;
1607 unsigned int hpll_freq;
1608 unsigned int fdi_pll_freq;
1609 unsigned int czclk_freq;
1613 * The current logical cdclk state.
1614 * See intel_atomic_state.cdclk.logical
1616 * For reading holding any crtc lock is sufficient,
1617 * for writing must hold all of them.
1619 struct intel_cdclk_state logical;
1621 * The current actual cdclk state.
1622 * See intel_atomic_state.cdclk.actual
1624 struct intel_cdclk_state actual;
1625 /* The current hardware cdclk state */
1626 struct intel_cdclk_state hw;
1630 * wq - Driver workqueue for GEM.
1632 * NOTE: Work items scheduled here are not allowed to grab any modeset
1633 * locks, for otherwise the flushing done in the pageflip code will
1634 * result in deadlocks.
1636 struct workqueue_struct *wq;
1638 /* ordered wq for modesets */
1639 struct workqueue_struct *modeset_wq;
1641 /* Display functions */
1642 struct drm_i915_display_funcs display;
1644 /* PCH chipset type */
1645 enum intel_pch pch_type;
1646 unsigned short pch_id;
1648 unsigned long quirks;
1650 struct drm_atomic_state *modeset_restore_state;
1651 struct drm_modeset_acquire_ctx reset_ctx;
1653 struct i915_ggtt ggtt; /* VM representing the global address space */
1655 struct i915_gem_mm mm;
1656 DECLARE_HASHTABLE(mm_structs, 7);
1657 struct mutex mm_lock;
1659 struct intel_ppat ppat;
1661 /* Kernel Modesetting */
1663 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1664 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1666 #ifdef CONFIG_DEBUG_FS
1667 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1670 /* dpll and cdclk state is protected by connection_mutex */
1671 int num_shared_dpll;
1672 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1673 const struct intel_dpll_mgr *dpll_mgr;
1676 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1677 * Must be global rather than per dpll, because on some platforms
1678 * plls share registers.
1680 struct mutex dpll_lock;
1682 unsigned int active_crtcs;
1683 /* minimum acceptable cdclk for each pipe */
1684 int min_cdclk[I915_MAX_PIPES];
1685 /* minimum acceptable voltage level for each pipe */
1686 u8 min_voltage_level[I915_MAX_PIPES];
1688 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1690 struct i915_wa_list gt_wa_list;
1692 struct i915_frontbuffer_tracking fb_tracking;
1694 struct intel_atomic_helper {
1695 struct llist_head free_list;
1696 struct work_struct free_work;
1701 bool mchbar_need_disable;
1703 struct intel_l3_parity l3_parity;
1705 /* Cannot be determined by PCIID. You must always read a register. */
1709 * Protects RPS/RC6 register access and PCU communication.
1710 * Must be taken after struct_mutex if nested. Note that
1711 * this lock may be held for long periods of time when
1712 * talking to hw - so only take it when talking to hw!
1714 struct mutex pcu_lock;
1716 /* gen6+ GT PM state */
1717 struct intel_gen6_power_mgmt gt_pm;
1719 /* ilk-only ips/rps state. Everything in here is protected by the global
1720 * mchdev_lock in intel_pm.c */
1721 struct intel_ilk_power_mgmt ips;
1723 struct i915_power_domains power_domains;
1725 struct i915_psr psr;
1727 struct i915_gpu_error gpu_error;
1729 struct drm_i915_gem_object *vlv_pctx;
1731 /* list of fbdev register on this device */
1732 struct intel_fbdev *fbdev;
1733 struct work_struct fbdev_suspend_work;
1735 struct drm_property *broadcast_rgb_property;
1736 struct drm_property *force_audio_property;
1738 /* hda/i915 audio component */
1739 struct i915_audio_component *audio_component;
1740 bool audio_component_registered;
1742 * av_mutex - mutex for audio/video sync
1745 struct mutex av_mutex;
1749 struct list_head list;
1750 struct llist_head free_list;
1751 struct work_struct free_work;
1753 /* The hw wants to have a stable context identifier for the
1754 * lifetime of the context (for OA, PASID, faults, etc).
1755 * This is limited in execlists to 21 bits.
1758 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1759 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1760 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1761 struct list_head hw_id_list;
1766 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1767 u32 chv_phy_control;
1769 * Shadows for CHV DPLL_MD regs to keep the state
1770 * checker somewhat working in the presence hardware
1771 * crappiness (can't read out DPLL_MD for pipes B & C).
1773 u32 chv_dpll_md[I915_MAX_PIPES];
1777 bool power_domains_suspended;
1778 struct i915_suspend_saved_registers regfile;
1779 struct vlv_s0ix_state vlv_s0ix_state;
1782 I915_SAGV_UNKNOWN = 0,
1785 I915_SAGV_NOT_CONTROLLED
1790 * Raw watermark latency values:
1791 * in 0.1us units for WM0,
1792 * in 0.5us units for WM1+.
1801 * Raw watermark memory latency values
1802 * for SKL for all 8 levels
1807 /* current hardware state */
1809 struct ilk_wm_values hw;
1810 struct skl_ddb_values skl_hw;
1811 struct vlv_wm_values vlv;
1812 struct g4x_wm_values g4x;
1818 * Should be held around atomic WM register writing; also
1819 * protects * intel_crtc->wm.active and
1820 * cstate->wm.need_postvbl_update.
1822 struct mutex wm_mutex;
1825 * Set during HW readout of watermarks/DDB. Some platforms
1826 * need to know when we're still using BIOS-provided values
1827 * (which we don't fully trust).
1829 bool distrust_bios_wm;
1838 bool symmetric_memory;
1839 enum intel_dram_type {
1848 struct i915_runtime_pm runtime_pm;
1853 struct kobject *metrics_kobj;
1854 struct ctl_table_header *sysctl_header;
1857 * Lock associated with adding/modifying/removing OA configs
1858 * in dev_priv->perf.metrics_idr.
1860 struct mutex metrics_lock;
1863 * List of dynamic configurations, you need to hold
1864 * dev_priv->perf.metrics_lock to access it.
1866 struct idr metrics_idr;
1869 * Lock associated with anything below within this structure
1870 * except exclusive_stream.
1873 struct list_head streams;
1877 * The stream currently using the OA unit. If accessed
1878 * outside a syscall associated to its file
1879 * descriptor, you need to hold
1880 * dev_priv->drm.struct_mutex.
1882 struct i915_perf_stream *exclusive_stream;
1884 struct intel_context *pinned_ctx;
1885 u32 specific_ctx_id;
1886 u32 specific_ctx_id_mask;
1888 struct hrtimer poll_check_timer;
1889 wait_queue_head_t poll_wq;
1893 * For rate limiting any notifications of spurious
1894 * invalid OA reports
1896 struct ratelimit_state spurious_report_rs;
1899 int period_exponent;
1901 struct i915_oa_config test_config;
1904 struct i915_vma *vma;
1911 * Locks reads and writes to all head/tail state
1913 * Consider: the head and tail pointer state
1914 * needs to be read consistently from a hrtimer
1915 * callback (atomic context) and read() fop
1916 * (user context) with tail pointer updates
1917 * happening in atomic context and head updates
1918 * in user context and the (unlikely)
1919 * possibility of read() errors needing to
1920 * reset all head/tail state.
1922 * Note: Contention or performance aren't
1923 * currently a significant concern here
1924 * considering the relatively low frequency of
1925 * hrtimer callbacks (5ms period) and that
1926 * reads typically only happen in response to a
1927 * hrtimer event and likely complete before the
1930 * Note: This lock is not held *while* reading
1931 * and copying data to userspace so the value
1932 * of head observed in htrimer callbacks won't
1933 * represent any partial consumption of data.
1935 spinlock_t ptr_lock;
1938 * One 'aging' tail pointer and one 'aged'
1939 * tail pointer ready to used for reading.
1941 * Initial values of 0xffffffff are invalid
1942 * and imply that an update is required
1943 * (and should be ignored by an attempted
1951 * Index for the aged tail ready to read()
1954 unsigned int aged_tail_idx;
1957 * A monotonic timestamp for when the current
1958 * aging tail pointer was read; used to
1959 * determine when it is old enough to trust.
1961 u64 aging_timestamp;
1964 * Although we can always read back the head
1965 * pointer register, we prefer to avoid
1966 * trusting the HW state, just to avoid any
1967 * risk that some hardware condition could
1968 * somehow bump the head pointer unpredictably
1969 * and cause us to forward the wrong OA buffer
1970 * data to userspace.
1975 u32 gen7_latched_oastatus1;
1976 u32 ctx_oactxctrl_offset;
1977 u32 ctx_flexeu0_offset;
1980 * The RPT_ID/reason field for Gen8+ includes a bit
1981 * to determine if the CTX ID in the report is valid
1982 * but the specific bit differs between Gen 8 and 9
1984 u32 gen8_valid_ctx_bit;
1986 struct i915_oa_ops ops;
1987 const struct i915_oa_format *oa_formats;
1991 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1993 void (*resume)(struct drm_i915_private *);
1994 void (*cleanup_engine)(struct intel_engine_cs *engine);
1996 struct i915_gt_timelines {
1997 struct mutex mutex; /* protects list, tainted by GPU */
1998 struct list_head active_list;
2000 /* Pack multiple timelines' seqnos into the same page */
2001 spinlock_t hwsp_lock;
2002 struct list_head hwsp_free_list;
2005 intel_engine_mask_t active_engines;
2006 struct list_head active_rings;
2007 struct list_head closed_vma;
2008 u32 active_requests;
2011 * Is the GPU currently considered idle, or busy executing
2012 * userspace requests? Whilst idle, we allow runtime power
2013 * management to power down the hardware and display clocks.
2014 * In order to reduce the effect on performance, there
2015 * is a slight delay before we do so.
2017 intel_wakeref_t awake;
2020 * We leave the user IRQ off as much as possible,
2021 * but this means that requests will finish and never
2022 * be retired once the system goes idle. Set a timer to
2023 * fire periodically while the ring is running. When it
2024 * fires, go retire requests.
2026 struct delayed_work retire_work;
2029 * When we detect an idle GPU, we want to turn on
2030 * powersaving features. So once we see that there
2031 * are no more requests outstanding and no more
2032 * arrive within a small period of time, we fire
2033 * off the idle_work.
2035 struct delayed_work idle_work;
2037 ktime_t last_init_time;
2039 struct i915_vma *scratch;
2042 /* perform PHY state sanity checks? */
2043 bool chv_phy_assert[2];
2047 /* Used to save the pipe-to-encoder mapping for audio */
2048 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2050 /* necessary resource sharing with HDMI LPE audio driver. */
2052 struct platform_device *platdev;
2056 struct i915_pmu pmu;
2058 struct i915_hdcp_comp_master *hdcp_master;
2059 bool hdcp_comp_added;
2061 /* Mutex to protect the above hdcp component related values. */
2062 struct mutex hdcp_comp_mutex;
2065 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2066 * will be rejected. Instead look for a better place.
2070 struct dram_dimm_info {
2071 u8 size, width, ranks;
2074 struct dram_channel_info {
2075 struct dram_dimm_info dimm_l, dimm_s;
2080 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2082 return container_of(dev, struct drm_i915_private, drm);
2085 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2087 return to_i915(dev_get_drvdata(kdev));
2090 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2092 return container_of(wopcm, struct drm_i915_private, wopcm);
2095 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2097 return container_of(guc, struct drm_i915_private, guc);
2100 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2102 return container_of(huc, struct drm_i915_private, huc);
2105 /* Simple iterator over all initialised engines */
2106 #define for_each_engine(engine__, dev_priv__, id__) \
2108 (id__) < I915_NUM_ENGINES; \
2110 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2112 /* Iterator over subset of engines selected by mask */
2113 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2114 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
2116 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2119 enum hdmi_force_audio {
2120 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2121 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2122 HDMI_AUDIO_AUTO, /* trust EDID */
2123 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2126 #define I915_GTT_OFFSET_NONE ((u32)-1)
2129 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2130 * considered to be the frontbuffer for the given plane interface-wise. This
2131 * doesn't mean that the hw necessarily already scans it out, but that any
2132 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2134 * We have one bit per pipe and per scanout plane type.
2136 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2137 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2138 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2139 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2140 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2142 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2143 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2144 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2145 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2146 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2149 * Optimised SGL iterator for GEM objects
2151 static __always_inline struct sgt_iter {
2152 struct scatterlist *sgp;
2159 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2160 struct sgt_iter s = { .sgp = sgl };
2163 s.max = s.curr = s.sgp->offset;
2164 s.max += s.sgp->length;
2166 s.dma = sg_dma_address(s.sgp);
2168 s.pfn = page_to_pfn(sg_page(s.sgp));
2174 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2177 if (unlikely(sg_is_chain(sg)))
2178 sg = sg_chain_ptr(sg);
2183 * __sg_next - return the next scatterlist entry in a list
2184 * @sg: The current sg entry
2187 * If the entry is the last, return NULL; otherwise, step to the next
2188 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2189 * otherwise just return the pointer to the current element.
2191 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2193 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2197 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2198 * @__dmap: DMA address (output)
2199 * @__iter: 'struct sgt_iter' (iterator state, internal)
2200 * @__sgt: sg_table to iterate over (input)
2202 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2203 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2204 ((__dmap) = (__iter).dma + (__iter).curr); \
2205 (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ? \
2206 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2209 * for_each_sgt_page - iterate over the pages of the given sg_table
2210 * @__pp: page pointer (output)
2211 * @__iter: 'struct sgt_iter' (iterator state, internal)
2212 * @__sgt: sg_table to iterate over (input)
2214 #define for_each_sgt_page(__pp, __iter, __sgt) \
2215 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2216 ((__pp) = (__iter).pfn == 0 ? NULL : \
2217 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2218 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2219 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2221 bool i915_sg_trim(struct sg_table *orig_st);
2223 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2225 unsigned int page_sizes;
2229 GEM_BUG_ON(sg->offset);
2230 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2231 page_sizes |= sg->length;
2238 static inline unsigned int i915_sg_segment_size(void)
2240 unsigned int size = swiotlb_max_segment();
2243 return SCATTERLIST_MAX_SEGMENT;
2245 size = rounddown(size, PAGE_SIZE);
2246 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2247 if (size < PAGE_SIZE)
2253 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
2254 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
2255 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2257 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
2258 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
2260 #define REVID_FOREVER 0xff
2261 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2263 #define INTEL_GEN_MASK(s, e) ( \
2264 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2265 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2266 GENMASK((e) - 1, (s) - 1))
2268 /* Returns true if Gen is in inclusive range [Start, End] */
2269 #define IS_GEN_RANGE(dev_priv, s, e) \
2270 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2272 #define IS_GEN(dev_priv, n) \
2273 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2274 INTEL_INFO(dev_priv)->gen == (n))
2277 * Return true if revision is in range [since,until] inclusive.
2279 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2281 #define IS_REVID(p, since, until) \
2282 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2284 #define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
2286 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2287 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2288 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2289 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2290 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2291 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2292 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2293 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2294 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2295 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2296 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2297 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2298 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2299 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2300 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2301 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2302 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2303 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2304 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2305 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2306 INTEL_INFO(dev_priv)->gt == 1)
2307 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2308 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2309 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2310 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2311 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2312 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2313 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2314 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2315 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2316 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2317 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2318 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
2319 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2320 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2321 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2322 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2323 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2324 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2325 /* ULX machines are also considered ULT. */
2326 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2327 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2328 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2329 INTEL_INFO(dev_priv)->gt == 3)
2330 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2331 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2332 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2333 INTEL_INFO(dev_priv)->gt == 3)
2334 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
2335 INTEL_INFO(dev_priv)->gt == 1)
2336 /* ULX machines are also considered ULT. */
2337 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2338 INTEL_DEVID(dev_priv) == 0x0A1E)
2339 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2340 INTEL_DEVID(dev_priv) == 0x1913 || \
2341 INTEL_DEVID(dev_priv) == 0x1916 || \
2342 INTEL_DEVID(dev_priv) == 0x1921 || \
2343 INTEL_DEVID(dev_priv) == 0x1926)
2344 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2345 INTEL_DEVID(dev_priv) == 0x1915 || \
2346 INTEL_DEVID(dev_priv) == 0x191E)
2347 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2348 INTEL_DEVID(dev_priv) == 0x5913 || \
2349 INTEL_DEVID(dev_priv) == 0x5916 || \
2350 INTEL_DEVID(dev_priv) == 0x5921 || \
2351 INTEL_DEVID(dev_priv) == 0x5926)
2352 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2353 INTEL_DEVID(dev_priv) == 0x5915 || \
2354 INTEL_DEVID(dev_priv) == 0x591E)
2355 #define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
2356 INTEL_DEVID(dev_priv) == 0x87C0)
2357 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2358 INTEL_INFO(dev_priv)->gt == 2)
2359 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2360 INTEL_INFO(dev_priv)->gt == 3)
2361 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2362 INTEL_INFO(dev_priv)->gt == 4)
2363 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2364 INTEL_INFO(dev_priv)->gt == 2)
2365 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2366 INTEL_INFO(dev_priv)->gt == 3)
2367 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2368 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2369 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2370 INTEL_INFO(dev_priv)->gt == 2)
2371 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2372 INTEL_INFO(dev_priv)->gt == 3)
2373 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2374 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2375 #define IS_ICL_WITH_PORT_F(dev_priv) (IS_ICELAKE(dev_priv) && \
2376 INTEL_DEVID(dev_priv) != 0x8A51)
2378 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2380 #define SKL_REVID_A0 0x0
2381 #define SKL_REVID_B0 0x1
2382 #define SKL_REVID_C0 0x2
2383 #define SKL_REVID_D0 0x3
2384 #define SKL_REVID_E0 0x4
2385 #define SKL_REVID_F0 0x5
2386 #define SKL_REVID_G0 0x6
2387 #define SKL_REVID_H0 0x7
2389 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2391 #define BXT_REVID_A0 0x0
2392 #define BXT_REVID_A1 0x1
2393 #define BXT_REVID_B0 0x3
2394 #define BXT_REVID_B_LAST 0x8
2395 #define BXT_REVID_C0 0x9
2397 #define IS_BXT_REVID(dev_priv, since, until) \
2398 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2400 #define KBL_REVID_A0 0x0
2401 #define KBL_REVID_B0 0x1
2402 #define KBL_REVID_C0 0x2
2403 #define KBL_REVID_D0 0x3
2404 #define KBL_REVID_E0 0x4
2406 #define IS_KBL_REVID(dev_priv, since, until) \
2407 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2409 #define GLK_REVID_A0 0x0
2410 #define GLK_REVID_A1 0x1
2412 #define IS_GLK_REVID(dev_priv, since, until) \
2413 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2415 #define CNL_REVID_A0 0x0
2416 #define CNL_REVID_B0 0x1
2417 #define CNL_REVID_C0 0x2
2419 #define IS_CNL_REVID(p, since, until) \
2420 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2422 #define ICL_REVID_A0 0x0
2423 #define ICL_REVID_A2 0x1
2424 #define ICL_REVID_B0 0x3
2425 #define ICL_REVID_B2 0x4
2426 #define ICL_REVID_C0 0x5
2428 #define IS_ICL_REVID(p, since, until) \
2429 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2431 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2432 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2433 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2435 #define ALL_ENGINES (~0u)
2436 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2438 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2439 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2440 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2441 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2442 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2444 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2446 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2447 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2448 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2449 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2450 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2451 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2453 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2455 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2456 #define HAS_PPGTT(dev_priv) \
2457 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2458 #define HAS_FULL_PPGTT(dev_priv) \
2459 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2461 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2462 GEM_BUG_ON((sizes) == 0); \
2463 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2466 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2467 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2468 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2470 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2471 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2473 /* WaRsDisableCoarsePowerGating:skl,cnl */
2474 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2475 (IS_CANNONLAKE(dev_priv) || \
2476 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2478 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2479 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2480 IS_GEMINILAKE(dev_priv) || \
2481 IS_KABYLAKE(dev_priv))
2483 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2484 * rows, which changed the alignment requirements and fence programming.
2486 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2487 !(IS_I915G(dev_priv) || \
2488 IS_I915GM(dev_priv)))
2489 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2490 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2492 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2493 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2494 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2496 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2498 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2500 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2501 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2502 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2503 #define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2505 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2506 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2507 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2509 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2511 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2512 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2514 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2517 * For now, anything with a GuC requires uCode loading, and then supports
2518 * command submission once loaded. But these are logically independent
2519 * properties, so we have separate macros to test them.
2521 #define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
2522 #define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
2523 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2524 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2526 /* For now, anything with a GuC has also HuC */
2527 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2528 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2530 /* Having a GuC is not the same as using a GuC */
2531 #define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
2532 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
2533 #define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
2535 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2537 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2538 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2539 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2540 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2541 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2542 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2543 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2544 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2545 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2546 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2547 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2548 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2549 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2550 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2551 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2552 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2553 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2555 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2556 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2557 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2558 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2559 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2560 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2561 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2562 #define HAS_PCH_LPT_LP(dev_priv) \
2563 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2564 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2565 #define HAS_PCH_LPT_H(dev_priv) \
2566 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2567 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2568 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2569 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2570 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2571 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2573 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2575 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2577 /* DPF == dynamic parity feature */
2578 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2579 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2580 2 : HAS_L3_DPF(dev_priv))
2582 #define GT_FREQUENCY_MULTIPLIER 50
2583 #define GEN9_FREQ_SCALER 3
2585 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2587 #include "i915_trace.h"
2589 static inline bool intel_vtd_active(void)
2591 #ifdef CONFIG_INTEL_IOMMU
2592 if (intel_iommu_gfx_mapped)
2598 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2600 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2604 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2606 return IS_BROXTON(dev_priv) && intel_vtd_active();
2611 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2612 const char *fmt, ...);
2614 #define i915_report_error(dev_priv, fmt, ...) \
2615 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2617 #ifdef CONFIG_COMPAT
2618 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2621 #define i915_compat_ioctl NULL
2623 extern const struct dev_pm_ops i915_pm_ops;
2625 extern int i915_driver_load(struct pci_dev *pdev,
2626 const struct pci_device_id *ent);
2627 extern void i915_driver_unload(struct drm_device *dev);
2629 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2630 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2631 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2632 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2633 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2634 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2635 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2637 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2638 int intel_engines_init(struct drm_i915_private *dev_priv);
2640 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2642 /* intel_hotplug.c */
2643 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2644 u32 pin_mask, u32 long_mask);
2645 void intel_hpd_init(struct drm_i915_private *dev_priv);
2646 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2647 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2648 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2650 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2651 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2654 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2656 unsigned long delay;
2658 if (unlikely(!i915_modparams.enable_hangcheck))
2661 /* Don't continually defer the hangcheck so that it is always run at
2662 * least once after work has been scheduled on any ring. Otherwise,
2663 * we will ignore a hung ring if a second ring is kept busy.
2666 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2667 queue_delayed_work(system_long_wq,
2668 &dev_priv->gpu_error.hangcheck_work, delay);
2671 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2672 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2673 int intel_irq_install(struct drm_i915_private *dev_priv);
2674 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2676 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2678 return dev_priv->gvt;
2681 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2683 return dev_priv->vgpu.active;
2686 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2689 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2693 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2696 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2697 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2698 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2701 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2703 u32 enabled_irq_mask);
2705 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2707 ilk_update_display_irq(dev_priv, bits, bits);
2710 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2712 ilk_update_display_irq(dev_priv, bits, 0);
2714 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2717 u32 enabled_irq_mask);
2718 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2719 enum pipe pipe, u32 bits)
2721 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2723 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2724 enum pipe pipe, u32 bits)
2726 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2728 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2730 u32 enabled_irq_mask);
2732 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2734 ibx_display_interrupt_update(dev_priv, bits, bits);
2737 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2739 ibx_display_interrupt_update(dev_priv, bits, 0);
2743 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2744 struct drm_file *file_priv);
2745 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2746 struct drm_file *file_priv);
2747 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2748 struct drm_file *file_priv);
2749 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2750 struct drm_file *file_priv);
2751 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2752 struct drm_file *file_priv);
2753 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2754 struct drm_file *file_priv);
2755 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2756 struct drm_file *file_priv);
2757 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2758 struct drm_file *file_priv);
2759 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2760 struct drm_file *file_priv);
2761 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2762 struct drm_file *file_priv);
2763 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2764 struct drm_file *file);
2765 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2766 struct drm_file *file);
2767 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2768 struct drm_file *file_priv);
2769 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2770 struct drm_file *file_priv);
2771 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2772 struct drm_file *file_priv);
2773 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2774 struct drm_file *file_priv);
2775 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2776 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2777 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2778 struct drm_file *file);
2779 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2780 struct drm_file *file_priv);
2781 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2782 struct drm_file *file_priv);
2783 void i915_gem_sanitize(struct drm_i915_private *i915);
2784 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2785 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2786 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2787 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2788 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2790 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2791 const struct drm_i915_gem_object_ops *ops);
2792 struct drm_i915_gem_object *
2793 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2794 struct drm_i915_gem_object *
2795 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2796 const void *data, size_t size);
2797 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2798 void i915_gem_free_object(struct drm_gem_object *obj);
2800 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2802 if (!atomic_read(&i915->mm.free_count))
2805 /* A single pass should suffice to release all the freed objects (along
2806 * most call paths) , but be a little more paranoid in that freeing
2807 * the objects does take a little amount of time, during which the rcu
2808 * callbacks could have added new objects into the freed list, and
2809 * armed the work again.
2813 } while (flush_work(&i915->mm.free_work));
2816 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2819 * Similar to objects above (see i915_gem_drain_freed-objects), in
2820 * general we have workers that are armed by RCU and then rearm
2821 * themselves in their callbacks. To be paranoid, we need to
2822 * drain the workqueue a second time after waiting for the RCU
2823 * grace period so that we catch work queued via RCU from the first
2824 * pass. As neither drain_workqueue() nor flush_workqueue() report
2825 * a result, we make an assumption that we only don't require more
2826 * than 2 passes to catch all recursive RCU delayed work.
2832 drain_workqueue(i915->wq);
2836 struct i915_vma * __must_check
2837 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2838 const struct i915_ggtt_view *view,
2843 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2844 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2846 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2848 static inline int __sg_page_count(const struct scatterlist *sg)
2850 return sg->length >> PAGE_SHIFT;
2853 struct scatterlist *
2854 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2855 unsigned int n, unsigned int *offset);
2858 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2862 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2866 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2869 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2870 struct sg_table *pages,
2871 unsigned int sg_page_sizes);
2872 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2874 static inline int __must_check
2875 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2877 might_lock(&obj->mm.lock);
2879 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2882 return __i915_gem_object_get_pages(obj);
2886 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2888 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2892 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2894 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2896 atomic_inc(&obj->mm.pages_pin_count);
2900 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2902 return atomic_read(&obj->mm.pages_pin_count);
2906 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2908 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2909 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2911 atomic_dec(&obj->mm.pages_pin_count);
2915 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2917 __i915_gem_object_unpin_pages(obj);
2920 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
2922 I915_MM_SHRINKER /* called "recursively" from direct-reclaim-esque */
2925 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2926 enum i915_mm_subclass subclass);
2927 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
2929 enum i915_map_type {
2932 #define I915_MAP_OVERRIDE BIT(31)
2933 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
2934 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
2937 static inline enum i915_map_type
2938 i915_coherent_map_type(struct drm_i915_private *i915)
2940 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2944 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2945 * @obj: the object to map into kernel address space
2946 * @type: the type of mapping, used to select pgprot_t
2948 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2949 * pages and then returns a contiguous mapping of the backing storage into
2950 * the kernel address space. Based on the @type of mapping, the PTE will be
2951 * set to either WriteBack or WriteCombine (via pgprot_t).
2953 * The caller is responsible for calling i915_gem_object_unpin_map() when the
2954 * mapping is no longer required.
2956 * Returns the pointer through which to access the mapped object, or an
2957 * ERR_PTR() on error.
2959 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2960 enum i915_map_type type);
2963 * i915_gem_object_unpin_map - releases an earlier mapping
2964 * @obj: the object to unmap
2966 * After pinning the object and mapping its pages, once you are finished
2967 * with your access, call i915_gem_object_unpin_map() to release the pin
2968 * upon the mapping. Once the pin count reaches zero, that mapping may be
2971 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
2973 i915_gem_object_unpin_pages(obj);
2976 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2977 unsigned int *needs_clflush);
2978 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
2979 unsigned int *needs_clflush);
2980 #define CLFLUSH_BEFORE BIT(0)
2981 #define CLFLUSH_AFTER BIT(1)
2982 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
2985 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
2987 i915_gem_object_unpin_pages(obj);
2990 static inline int __must_check
2991 i915_mutex_lock_interruptible(struct drm_device *dev)
2993 return mutex_lock_interruptible(&dev->struct_mutex);
2996 int i915_gem_dumb_create(struct drm_file *file_priv,
2997 struct drm_device *dev,
2998 struct drm_mode_create_dumb *args);
2999 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3000 u32 handle, u64 *offset);
3001 int i915_gem_mmap_gtt_version(void);
3003 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3004 struct drm_i915_gem_object *new,
3005 unsigned frontbuffer_bits);
3007 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3009 static inline bool __i915_wedged(struct i915_gpu_error *error)
3011 return unlikely(test_bit(I915_WEDGED, &error->flags));
3014 static inline bool i915_reset_failed(struct drm_i915_private *i915)
3016 return __i915_wedged(&i915->gpu_error);
3019 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3021 return READ_ONCE(error->reset_count);
3024 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3025 struct intel_engine_cs *engine)
3027 return READ_ONCE(error->reset_engine_count[engine->id]);
3030 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3031 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3033 void i915_gem_init_mmio(struct drm_i915_private *i915);
3034 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3035 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3036 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3037 void i915_gem_fini(struct drm_i915_private *dev_priv);
3038 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3039 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3040 unsigned int flags, long timeout);
3041 void i915_gem_suspend(struct drm_i915_private *dev_priv);
3042 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3043 void i915_gem_resume(struct drm_i915_private *dev_priv);
3044 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3045 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3048 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3050 const struct i915_sched_attr *attr);
3051 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3054 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3056 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3058 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3059 struct i915_vma * __must_check
3060 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3062 const struct i915_ggtt_view *view,
3063 unsigned int flags);
3064 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3065 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3067 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3068 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3070 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3071 enum i915_cache_level cache_level);
3073 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3074 struct dma_buf *dma_buf);
3076 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3077 struct drm_gem_object *gem_obj, int flags);
3079 static inline struct i915_hw_ppgtt *
3080 i915_vm_to_ppgtt(struct i915_address_space *vm)
3082 return container_of(vm, struct i915_hw_ppgtt, vm);
3085 /* i915_gem_fence_reg.c */
3086 struct drm_i915_fence_reg *
3087 i915_reserve_fence(struct drm_i915_private *dev_priv);
3088 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3090 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3092 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3093 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3094 struct sg_table *pages);
3095 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3096 struct sg_table *pages);
3098 static inline struct i915_gem_context *
3099 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3101 return idr_find(&file_priv->context_idr, id);
3104 static inline struct i915_gem_context *
3105 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3107 struct i915_gem_context *ctx;
3110 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3111 if (ctx && !kref_get_unless_zero(&ctx->ref))
3118 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3119 struct drm_file *file);
3120 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3121 struct drm_file *file);
3122 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3123 struct drm_file *file);
3124 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3125 struct intel_context *ce,
3128 /* i915_gem_evict.c */
3129 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3130 u64 min_size, u64 alignment,
3131 unsigned cache_level,
3134 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3135 struct drm_mm_node *node,
3136 unsigned int flags);
3137 int i915_gem_evict_vm(struct i915_address_space *vm);
3139 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3141 /* belongs in i915_gem_gtt.h */
3142 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3145 if (INTEL_GEN(dev_priv) < 6)
3146 intel_gtt_chipset_flush();
3149 /* i915_gem_stolen.c */
3150 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3151 struct drm_mm_node *node, u64 size,
3152 unsigned alignment);
3153 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3154 struct drm_mm_node *node, u64 size,
3155 unsigned alignment, u64 start,
3157 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3158 struct drm_mm_node *node);
3159 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3160 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3161 struct drm_i915_gem_object *
3162 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3163 resource_size_t size);
3164 struct drm_i915_gem_object *
3165 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3166 resource_size_t stolen_offset,
3167 resource_size_t gtt_offset,
3168 resource_size_t size);
3170 /* i915_gem_internal.c */
3171 struct drm_i915_gem_object *
3172 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3175 /* i915_gem_shrinker.c */
3176 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3177 unsigned long target,
3178 unsigned long *nr_scanned,
3180 #define I915_SHRINK_PURGEABLE 0x1
3181 #define I915_SHRINK_UNBOUND 0x2
3182 #define I915_SHRINK_BOUND 0x4
3183 #define I915_SHRINK_ACTIVE 0x8
3184 #define I915_SHRINK_VMAPS 0x10
3185 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3186 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3187 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3188 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
3189 struct mutex *mutex);
3191 /* i915_gem_tiling.c */
3192 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3194 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3196 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3197 i915_gem_object_is_tiled(obj);
3200 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3201 unsigned int tiling, unsigned int stride);
3202 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3203 unsigned int tiling, unsigned int stride);
3205 /* i915_debugfs.c */
3206 #ifdef CONFIG_DEBUG_FS
3207 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3208 int i915_debugfs_connector_add(struct drm_connector *connector);
3209 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3211 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3212 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3214 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3217 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3219 /* i915_cmd_parser.c */
3220 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3221 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3222 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3223 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3224 struct drm_i915_gem_object *batch_obj,
3225 struct drm_i915_gem_object *shadow_batch_obj,
3226 u32 batch_start_offset,
3231 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3232 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3233 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3234 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3236 /* i915_suspend.c */
3237 extern int i915_save_state(struct drm_i915_private *dev_priv);
3238 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3241 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3242 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3244 /* intel_lpe_audio.c */
3245 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3246 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3247 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3248 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3249 enum pipe pipe, enum port port,
3250 const void *eld, int ls_clock, bool dp_output);
3253 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3254 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3255 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3257 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3259 extern struct i2c_adapter *
3260 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3261 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3262 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3263 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3265 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3267 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3270 void intel_bios_init(struct drm_i915_private *dev_priv);
3271 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3272 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3273 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3274 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3275 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3276 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3277 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3278 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3279 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3281 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3283 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
3287 extern void intel_register_dsm_handler(void);
3288 extern void intel_unregister_dsm_handler(void);
3290 static inline void intel_register_dsm_handler(void) { return; }
3291 static inline void intel_unregister_dsm_handler(void) { return; }
3292 #endif /* CONFIG_ACPI */
3294 /* intel_device_info.c */
3295 static inline struct intel_device_info *
3296 mkwrite_device_info(struct drm_i915_private *dev_priv)
3298 return (struct intel_device_info *)INTEL_INFO(dev_priv);
3301 static inline struct intel_sseu
3302 intel_device_default_sseu(struct drm_i915_private *i915)
3304 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
3305 struct intel_sseu value = {
3306 .slice_mask = sseu->slice_mask,
3307 .subslice_mask = sseu->subslice_mask[0],
3308 .min_eus_per_subslice = sseu->max_eus_per_subslice,
3309 .max_eus_per_subslice = sseu->max_eus_per_subslice,
3316 extern void intel_modeset_init_hw(struct drm_device *dev);
3317 extern int intel_modeset_init(struct drm_device *dev);
3318 extern void intel_modeset_cleanup(struct drm_device *dev);
3319 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3321 extern void intel_display_resume(struct drm_device *dev);
3322 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3323 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3324 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3325 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3326 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3327 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3329 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3331 void intel_dsc_enable(struct intel_encoder *encoder,
3332 const struct intel_crtc_state *crtc_state);
3333 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
3335 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3336 struct drm_file *file);
3339 extern struct intel_overlay_error_state *
3340 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3341 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3342 struct intel_overlay_error_state *error);
3344 extern struct intel_display_error_state *
3345 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3346 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3347 struct intel_display_error_state *error);
3349 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3350 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3351 u32 val, int fast_timeout_us,
3352 int slow_timeout_ms);
3353 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3354 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3356 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3357 u32 reply_mask, u32 reply, int timeout_base_ms);
3359 /* intel_sideband.c */
3360 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3361 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3362 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3363 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3364 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3365 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3366 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3367 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3368 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3369 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3370 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3371 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3372 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3373 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3374 enum intel_sbi_destination destination);
3375 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3376 enum intel_sbi_destination destination);
3377 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3378 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3380 /* intel_dpio_phy.c */
3381 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3382 enum dpio_phy *phy, enum dpio_channel *ch);
3383 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3384 enum port port, u32 margin, u32 scale,
3385 u32 enable, u32 deemphasis);
3386 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3387 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3388 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3390 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3392 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
3393 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3394 u8 lane_lat_optim_mask);
3395 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3397 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3398 u32 deemph_reg_value, u32 margin_reg_value,
3399 bool uniq_trans_scale);
3400 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3401 const struct intel_crtc_state *crtc_state,
3403 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3404 const struct intel_crtc_state *crtc_state);
3405 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3406 const struct intel_crtc_state *crtc_state);
3407 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3408 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3409 const struct intel_crtc_state *old_crtc_state);
3411 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3412 u32 demph_reg_value, u32 preemph_reg_value,
3413 u32 uniqtranscale_reg_value, u32 tx3_demph);
3414 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3415 const struct intel_crtc_state *crtc_state);
3416 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3417 const struct intel_crtc_state *crtc_state);
3418 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3419 const struct intel_crtc_state *old_crtc_state);
3421 /* intel_combo_phy.c */
3422 void icl_combo_phys_init(struct drm_i915_private *dev_priv);
3423 void icl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3424 void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
3425 void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
3427 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3428 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3429 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3430 const i915_reg_t reg);
3432 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3434 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3435 const i915_reg_t reg)
3437 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3440 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3441 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3443 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3444 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3445 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3446 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3448 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3449 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3450 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3451 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3453 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3454 * will be implemented using 2 32-bit writes in an arbitrary order with
3455 * an arbitrary delay between them. This can cause the hardware to
3456 * act upon the intermediate value, possibly leading to corruption and
3457 * machine death. For this reason we do not support I915_WRITE64, or
3458 * dev_priv->uncore.funcs.mmio_writeq.
3460 * When reading a 64-bit value as two 32-bit values, the delay may cause
3461 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3462 * occasionally a 64-bit register does not actualy support a full readq
3463 * and must be read using two 32-bit reads.
3465 * You have been warned.
3467 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3469 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3470 u32 upper, lower, old_upper, loop = 0; \
3471 upper = I915_READ(upper_reg); \
3473 old_upper = upper; \
3474 lower = I915_READ(lower_reg); \
3475 upper = I915_READ(upper_reg); \
3476 } while (upper != old_upper && loop++ < 2); \
3477 (u64)upper << 32 | lower; })
3479 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3480 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3482 #define __raw_read(x, s) \
3483 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3486 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3489 #define __raw_write(x, s) \
3490 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3491 i915_reg_t reg, uint##x##_t val) \
3493 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3508 /* These are untraced mmio-accessors that are only valid to be used inside
3509 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3512 * Think twice, and think again, before using these.
3514 * As an example, these accessors can possibly be used between:
3516 * spin_lock_irq(&dev_priv->uncore.lock);
3517 * intel_uncore_forcewake_get__locked();
3521 * intel_uncore_forcewake_put__locked();
3522 * spin_unlock_irq(&dev_priv->uncore.lock);
3525 * Note: some registers may not need forcewake held, so
3526 * intel_uncore_forcewake_{get,put} can be omitted, see
3527 * intel_uncore_forcewake_for_reg().
3529 * Certain architectures will die if the same cacheline is concurrently accessed
3530 * by different clients (e.g. on Ivybridge). Access to registers should
3531 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3532 * a more localised lock guarding all access to that bank of registers.
3534 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3535 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3536 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3537 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3539 /* "Broadcast RGB" property */
3540 #define INTEL_BROADCAST_RGB_AUTO 0
3541 #define INTEL_BROADCAST_RGB_FULL 1
3542 #define INTEL_BROADCAST_RGB_LIMITED 2
3544 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3546 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3547 return VLV_VGACNTRL;
3548 else if (INTEL_GEN(dev_priv) >= 5)
3549 return CPU_VGACNTRL;
3554 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3556 unsigned long j = msecs_to_jiffies(m);
3558 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3561 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3563 /* nsecs_to_jiffies64() does not guard against overflow */
3564 if (NSEC_PER_SEC % HZ &&
3565 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3566 return MAX_JIFFY_OFFSET;
3568 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3572 * If you need to wait X milliseconds between events A and B, but event B
3573 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3574 * when event A happened, then just before event B you call this function and
3575 * pass the timestamp as the first argument, and X as the second argument.
3578 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3580 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3583 * Don't re-read the value of "jiffies" every time since it may change
3584 * behind our back and break the math.
3586 tmp_jiffies = jiffies;
3587 target_jiffies = timestamp_jiffies +
3588 msecs_to_jiffies_timeout(to_wait_ms);
3590 if (time_after(target_jiffies, tmp_jiffies)) {
3591 remaining_jiffies = target_jiffies - tmp_jiffies;
3592 while (remaining_jiffies)
3594 schedule_timeout_uninterruptible(remaining_jiffies);
3598 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3599 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3601 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3602 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3603 * perform the operation. To check beforehand, pass in the parameters to
3604 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3605 * you only need to pass in the minor offsets, page-aligned pointers are
3608 * For just checking for SSE4.1, in the foreknowledge that the future use
3609 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3611 #define i915_can_memcpy_from_wc(dst, src, len) \
3612 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3614 #define i915_has_memcpy_from_wc() \
3615 i915_memcpy_from_wc(NULL, NULL, 0)
3618 int remap_io_mapping(struct vm_area_struct *vma,
3619 unsigned long addr, unsigned long pfn, unsigned long size,
3620 struct io_mapping *iomap);
3622 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3624 if (INTEL_GEN(i915) >= 10)
3625 return CNL_HWS_CSB_WRITE_INDEX;
3627 return I915_HWS_CSB_WRITE_INDEX;
3630 static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
3632 return i915_ggtt_offset(i915->gt.scratch);