1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/perf_event.h>
44 #include <linux/pm_qos.h>
45 #include <linux/reservation.h>
46 #include <linux/shmem_fs.h>
49 #include <drm/intel-gtt.h>
50 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
51 #include <drm/drm_gem.h>
52 #include <drm/drm_auth.h>
53 #include <drm/drm_cache.h>
55 #include "i915_params.h"
57 #include "i915_utils.h"
59 #include "intel_bios.h"
60 #include "intel_device_info.h"
61 #include "intel_display.h"
62 #include "intel_dpll_mgr.h"
63 #include "intel_lrc.h"
64 #include "intel_opregion.h"
65 #include "intel_ringbuffer.h"
66 #include "intel_uncore.h"
70 #include "i915_gem_context.h"
71 #include "i915_gem_fence_reg.h"
72 #include "i915_gem_object.h"
73 #include "i915_gem_gtt.h"
74 #include "i915_gem_request.h"
75 #include "i915_gem_timeline.h"
79 #include "intel_gvt.h"
81 /* General customization:
84 #define DRIVER_NAME "i915"
85 #define DRIVER_DESC "Intel Graphics"
86 #define DRIVER_DATE "20171222"
87 #define DRIVER_TIMESTAMP 1513971710
89 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
90 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
91 * which may not necessarily be a user visible problem. This will either
92 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
93 * enable distros and users to tailor their preferred amount of i915 abrt
96 #define I915_STATE_WARN(condition, format...) ({ \
97 int __ret_warn_on = !!(condition); \
98 if (unlikely(__ret_warn_on)) \
99 if (!WARN(i915_modparams.verbose_state_checks, format)) \
101 unlikely(__ret_warn_on); \
104 #define I915_STATE_WARN_ON(x) \
105 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
107 bool __i915_inject_load_failure(const char *func, int line);
108 #define i915_inject_load_failure() \
109 __i915_inject_load_failure(__func__, __LINE__)
113 } uint_fixed_16_16_t;
115 #define FP_16_16_MAX ({ \
116 uint_fixed_16_16_t fp; \
121 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
128 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
130 uint_fixed_16_16_t fp;
132 WARN_ON(val > U16_MAX);
138 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
140 return DIV_ROUND_UP(fp.val, 1 << 16);
143 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
148 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
149 uint_fixed_16_16_t min2)
151 uint_fixed_16_16_t min;
153 min.val = min(min1.val, min2.val);
157 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
158 uint_fixed_16_16_t max2)
160 uint_fixed_16_16_t max;
162 max.val = max(max1.val, max2.val);
166 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
168 uint_fixed_16_16_t fp;
169 WARN_ON(val > U32_MAX);
170 fp.val = (uint32_t) val;
174 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
175 uint_fixed_16_16_t d)
177 return DIV_ROUND_UP(val.val, d.val);
180 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
181 uint_fixed_16_16_t mul)
183 uint64_t intermediate_val;
185 intermediate_val = (uint64_t) val * mul.val;
186 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
187 WARN_ON(intermediate_val > U32_MAX);
188 return (uint32_t) intermediate_val;
191 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
192 uint_fixed_16_16_t mul)
194 uint64_t intermediate_val;
196 intermediate_val = (uint64_t) val.val * mul.val;
197 intermediate_val = intermediate_val >> 16;
198 return clamp_u64_to_fixed16(intermediate_val);
201 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
205 interm_val = (uint64_t)val << 16;
206 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
207 return clamp_u64_to_fixed16(interm_val);
210 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
211 uint_fixed_16_16_t d)
215 interm_val = (uint64_t)val << 16;
216 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
217 WARN_ON(interm_val > U32_MAX);
218 return (uint32_t) interm_val;
221 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
222 uint_fixed_16_16_t mul)
224 uint64_t intermediate_val;
226 intermediate_val = (uint64_t) val * mul.val;
227 return clamp_u64_to_fixed16(intermediate_val);
230 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
231 uint_fixed_16_16_t add2)
235 interm_sum = (uint64_t) add1.val + add2.val;
236 return clamp_u64_to_fixed16(interm_sum);
239 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
243 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
245 interm_sum = (uint64_t) add1.val + interm_add2.val;
246 return clamp_u64_to_fixed16(interm_sum);
251 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
263 #define for_each_hpd_pin(__pin) \
264 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
266 #define HPD_STORM_DEFAULT_THRESHOLD 5
268 struct i915_hotplug {
269 struct work_struct hotplug_work;
272 unsigned long last_jiffies;
277 HPD_MARK_DISABLED = 2
279 } stats[HPD_NUM_PINS];
281 struct delayed_work reenable_work;
283 struct intel_digital_port *irq_port[I915_MAX_PORTS];
286 struct work_struct dig_port_work;
288 struct work_struct poll_init_work;
291 unsigned int hpd_storm_threshold;
294 * if we get a HPD irq from DP and a HPD irq from non-DP
295 * the non-DP HPD could block the workqueue on a mode config
296 * mutex getting, that userspace may have taken. However
297 * userspace is waiting on the DP workqueue to run which is
298 * blocked behind the non-DP one.
300 struct workqueue_struct *dp_wq;
303 #define I915_GEM_GPU_DOMAINS \
304 (I915_GEM_DOMAIN_RENDER | \
305 I915_GEM_DOMAIN_SAMPLER | \
306 I915_GEM_DOMAIN_COMMAND | \
307 I915_GEM_DOMAIN_INSTRUCTION | \
308 I915_GEM_DOMAIN_VERTEX)
310 struct drm_i915_private;
311 struct i915_mm_struct;
312 struct i915_mmu_object;
314 struct drm_i915_file_private {
315 struct drm_i915_private *dev_priv;
316 struct drm_file *file;
320 struct list_head request_list;
321 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
322 * chosen to prevent the CPU getting more than a frame ahead of the GPU
323 * (when using lax throttling for the frontbuffer). We also use it to
324 * offer free GPU waitboosts for severely congested workloads.
326 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
328 struct idr context_idr;
330 struct intel_rps_client {
334 unsigned int bsd_engine;
336 /* Client can have a maximum of 3 contexts banned before
337 * it is denied of creating new contexts. As one context
338 * ban needs 4 consecutive hangs, and more if there is
339 * progress in between, this is a last resort stop gap measure
340 * to limit the badly behaving clients access to gpu.
342 #define I915_MAX_CLIENT_CONTEXT_BANS 3
343 atomic_t context_bans;
346 /* Interface history:
349 * 1.2: Add Power Management
350 * 1.3: Add vblank support
351 * 1.4: Fix cmdbuffer path, add heap destroy
352 * 1.5: Add vblank pipe configuration
353 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
354 * - Support vertical blank on secondary display pipe
356 #define DRIVER_MAJOR 1
357 #define DRIVER_MINOR 6
358 #define DRIVER_PATCHLEVEL 0
360 struct intel_overlay;
361 struct intel_overlay_error_state;
363 struct sdvo_device_mapping {
372 struct intel_connector;
373 struct intel_encoder;
374 struct intel_atomic_state;
375 struct intel_crtc_state;
376 struct intel_initial_plane_config;
380 struct intel_cdclk_state;
382 struct drm_i915_display_funcs {
383 void (*get_cdclk)(struct drm_i915_private *dev_priv,
384 struct intel_cdclk_state *cdclk_state);
385 void (*set_cdclk)(struct drm_i915_private *dev_priv,
386 const struct intel_cdclk_state *cdclk_state);
387 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
388 enum i9xx_plane_id i9xx_plane);
389 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
390 int (*compute_intermediate_wm)(struct drm_device *dev,
391 struct intel_crtc *intel_crtc,
392 struct intel_crtc_state *newstate);
393 void (*initial_watermarks)(struct intel_atomic_state *state,
394 struct intel_crtc_state *cstate);
395 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
396 struct intel_crtc_state *cstate);
397 void (*optimize_watermarks)(struct intel_atomic_state *state,
398 struct intel_crtc_state *cstate);
399 int (*compute_global_watermarks)(struct drm_atomic_state *state);
400 void (*update_wm)(struct intel_crtc *crtc);
401 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
402 /* Returns the active state of the crtc, and if the crtc is active,
403 * fills out the pipe-config with the hw state. */
404 bool (*get_pipe_config)(struct intel_crtc *,
405 struct intel_crtc_state *);
406 void (*get_initial_plane_config)(struct intel_crtc *,
407 struct intel_initial_plane_config *);
408 int (*crtc_compute_clock)(struct intel_crtc *crtc,
409 struct intel_crtc_state *crtc_state);
410 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
411 struct drm_atomic_state *old_state);
412 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
413 struct drm_atomic_state *old_state);
414 void (*update_crtcs)(struct drm_atomic_state *state);
415 void (*audio_codec_enable)(struct intel_encoder *encoder,
416 const struct intel_crtc_state *crtc_state,
417 const struct drm_connector_state *conn_state);
418 void (*audio_codec_disable)(struct intel_encoder *encoder,
419 const struct intel_crtc_state *old_crtc_state,
420 const struct drm_connector_state *old_conn_state);
421 void (*fdi_link_train)(struct intel_crtc *crtc,
422 const struct intel_crtc_state *crtc_state);
423 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
424 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
425 /* clock updates for mode set */
427 /* render clock increase/decrease */
428 /* display clock increase/decrease */
429 /* pll clock increase/decrease */
431 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
432 void (*load_luts)(struct drm_crtc_state *crtc_state);
435 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
436 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
437 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
440 struct work_struct work;
442 uint32_t *dmc_payload;
443 uint32_t dmc_fw_size;
446 i915_reg_t mmioaddr[8];
447 uint32_t mmiodata[8];
449 uint32_t allowed_dc_mask;
452 struct intel_display_error_state;
454 struct i915_gpu_state {
460 struct drm_i915_private *i915;
470 struct intel_device_info device_info;
471 struct i915_params params;
473 struct i915_error_uc {
474 struct intel_uc_fw guc_fw;
475 struct intel_uc_fw huc_fw;
476 struct drm_i915_error_object *guc_log;
479 /* Generic register state */
483 u32 gtier[4], ngtier;
487 u32 error; /* gen6+ */
488 u32 err_int; /* gen7 */
489 u32 fault_data0; /* gen8, gen9 */
490 u32 fault_data1; /* gen8, gen9 */
498 u64 fence[I915_MAX_NUM_FENCES];
499 struct intel_overlay_error_state *overlay;
500 struct intel_display_error_state *display;
502 struct drm_i915_error_engine {
504 /* Software tracked state */
508 unsigned long hangcheck_timestamp;
509 bool hangcheck_stalled;
510 enum intel_engine_hangcheck_action hangcheck_action;
511 struct i915_address_space *vm;
515 /* position of active request inside the ring */
516 u32 rq_head, rq_post, rq_tail;
518 /* our own tracking of ring head and tail */
541 u32 rc_psmi; /* sleep state */
542 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
543 struct intel_instdone instdone;
545 struct drm_i915_error_context {
546 char comm[TASK_COMM_LEN];
556 struct drm_i915_error_object {
562 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
564 struct drm_i915_error_object **user_bo;
567 struct drm_i915_error_object *wa_ctx;
568 struct drm_i915_error_object *default_state;
570 struct drm_i915_error_request {
579 } *requests, execlist[EXECLIST_MAX_PORTS];
580 unsigned int num_ports;
582 struct drm_i915_error_waiter {
583 char comm[TASK_COMM_LEN];
595 } engine[I915_NUM_ENGINES];
597 struct drm_i915_error_buffer {
600 u32 rseqno[I915_NUM_ENGINES], wseqno;
604 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
611 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
612 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
613 struct i915_address_space *active_vm[I915_NUM_ENGINES];
616 enum i915_cache_level {
618 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
619 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
620 caches, eg sampler/render caches, and the
621 large Last-Level-Cache. LLC is coherent with
622 the CPU, but L3 is only visible to the GPU. */
623 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
626 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
637 /* This is always the inner lock when overlapping with struct_mutex and
638 * it's the outer lock when overlapping with stolen_lock. */
641 unsigned int possible_framebuffer_bits;
642 unsigned int busy_bits;
643 unsigned int visible_pipes_mask;
644 struct intel_crtc *crtc;
646 struct drm_mm_node compressed_fb;
647 struct drm_mm_node *compressed_llb;
654 bool underrun_detected;
655 struct work_struct underrun_work;
658 * Due to the atomic rules we can't access some structures without the
659 * appropriate locking, so we cache information here in order to avoid
662 struct intel_fbc_state_cache {
663 struct i915_vma *vma;
666 unsigned int mode_flags;
667 uint32_t hsw_bdw_pixel_rate;
671 unsigned int rotation;
676 * Display surface base address adjustement for
677 * pageflips. Note that on gen4+ this only adjusts up
678 * to a tile, offsets within a tile are handled in
679 * the hw itself (with the TILEOFF register).
688 const struct drm_format_info *format;
694 * This structure contains everything that's relevant to program the
695 * hardware registers. When we want to figure out if we need to disable
696 * and re-enable FBC for a new configuration we just check if there's
697 * something different in the struct. The genx_fbc_activate functions
698 * are supposed to read from it in order to program the registers.
700 struct intel_fbc_reg_params {
701 struct i915_vma *vma;
705 enum i9xx_plane_id i9xx_plane;
706 unsigned int fence_y_offset;
710 const struct drm_format_info *format;
715 unsigned int gen9_wa_cfb_stride;
718 struct intel_fbc_work {
720 u32 scheduled_vblank;
721 struct work_struct work;
724 const char *no_fbc_reason;
728 * HIGH_RR is the highest eDP panel refresh rate read from EDID
729 * LOW_RR is the lowest eDP panel refresh rate found from EDID
730 * parsing for same resolution.
732 enum drrs_refresh_rate_type {
735 DRRS_MAX_RR, /* RR count */
738 enum drrs_support_type {
739 DRRS_NOT_SUPPORTED = 0,
740 STATIC_DRRS_SUPPORT = 1,
741 SEAMLESS_DRRS_SUPPORT = 2
747 struct delayed_work work;
749 unsigned busy_frontbuffer_bits;
750 enum drrs_refresh_rate_type refresh_rate_type;
751 enum drrs_support_type type;
757 struct intel_dp *enabled;
759 struct delayed_work work;
760 unsigned busy_frontbuffer_bits;
765 bool colorimetry_support;
768 void (*enable_source)(struct intel_dp *,
769 const struct intel_crtc_state *);
770 void (*disable_source)(struct intel_dp *,
771 const struct intel_crtc_state *);
772 void (*enable_sink)(struct intel_dp *);
773 void (*activate)(struct intel_dp *);
774 void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
778 PCH_NONE = 0, /* No PCH present */
779 PCH_IBX, /* Ibexpeak PCH */
780 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
781 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
782 PCH_SPT, /* Sunrisepoint PCH */
783 PCH_KBP, /* Kaby Lake PCH */
784 PCH_CNP, /* Cannon Lake PCH */
785 PCH_ICP, /* Ice Lake PCH */
789 enum intel_sbi_destination {
794 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
795 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
796 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
797 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
798 #define QUIRK_INCREASE_T12_DELAY (1<<6)
801 struct intel_fbc_work;
804 struct i2c_adapter adapter;
805 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
809 struct i2c_algo_bit_data bit_algo;
810 struct drm_i915_private *dev_priv;
813 struct i915_suspend_saved_registers {
816 u32 saveCACHE_MODE_0;
817 u32 saveMI_ARB_STATE;
821 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
822 u32 savePCH_PORT_HOTPLUG;
826 struct vlv_s0ix_state {
833 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
834 u32 media_max_req_count;
835 u32 gfx_max_req_count;
867 /* Display 1 CZ domain */
872 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
874 /* GT SA CZ domain */
881 /* Display 2 CZ domain */
888 struct intel_rps_ei {
896 * work, interrupts_enabled and pm_iir are protected by
899 struct work_struct work;
900 bool interrupts_enabled;
903 /* PM interrupt bits that should never be masked */
906 /* Frequencies are stored in potentially platform dependent multiples.
907 * In other words, *_freq needs to be multiplied by X to be interesting.
908 * Soft limits are those which are used for the dynamic reclocking done
909 * by the driver (raise frequencies under heavy loads, and lower for
910 * lighter loads). Hard limits are those imposed by the hardware.
912 * A distinction is made for overclocking, which is never enabled by
913 * default, and is considered to be above the hard limit if it's
916 u8 cur_freq; /* Current frequency (cached, may not == HW) */
917 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
918 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
919 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
920 u8 min_freq; /* AKA RPn. Minimum frequency */
921 u8 boost_freq; /* Frequency to request when wait boosting */
922 u8 idle_freq; /* Frequency to request when we are idle */
923 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
924 u8 rp1_freq; /* "less than" RP0 power/freqency */
925 u8 rp0_freq; /* Non-overclocked max frequency. */
926 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
928 u8 up_threshold; /* Current %busy required to uplock */
929 u8 down_threshold; /* Current %busy required to downclock */
932 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
935 atomic_t num_waiters;
938 /* manual wa residency calculations */
939 struct intel_rps_ei ei;
946 struct intel_llc_pstate {
950 struct intel_gen6_power_mgmt {
951 struct intel_rps rps;
952 struct intel_rc6 rc6;
953 struct intel_llc_pstate llc_pstate;
956 /* defined intel_pm.c */
957 extern spinlock_t mchdev_lock;
959 struct intel_ilk_power_mgmt {
967 unsigned long last_time1;
968 unsigned long chipset_power;
971 unsigned long gfx_power;
978 struct drm_i915_private;
979 struct i915_power_well;
981 struct i915_power_well_ops {
983 * Synchronize the well's hw state to match the current sw state, for
984 * example enable/disable it based on the current refcount. Called
985 * during driver init and resume time, possibly after first calling
986 * the enable/disable handlers.
988 void (*sync_hw)(struct drm_i915_private *dev_priv,
989 struct i915_power_well *power_well);
991 * Enable the well and resources that depend on it (for example
992 * interrupts located on the well). Called after the 0->1 refcount
995 void (*enable)(struct drm_i915_private *dev_priv,
996 struct i915_power_well *power_well);
998 * Disable the well and resources that depend on it. Called after
999 * the 1->0 refcount transition.
1001 void (*disable)(struct drm_i915_private *dev_priv,
1002 struct i915_power_well *power_well);
1003 /* Returns the hw enabled state. */
1004 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1005 struct i915_power_well *power_well);
1008 /* Power well structure for haswell */
1009 struct i915_power_well {
1012 /* power well enable/disable usage count */
1014 /* cached hw enabled state */
1017 /* unique identifier for this power well */
1018 enum i915_power_well_id id;
1020 * Arbitraty data associated with this power well. Platform and power
1028 /* Mask of pipes whose IRQ logic is backed by the pw */
1030 /* The pw is backing the VGA functionality */
1035 const struct i915_power_well_ops *ops;
1038 struct i915_power_domains {
1040 * Power wells needed for initialization at driver init and suspend
1041 * time are on. They are kept on until after the first modeset.
1045 int power_well_count;
1048 int domain_use_count[POWER_DOMAIN_NUM];
1049 struct i915_power_well *power_wells;
1052 #define MAX_L3_SLICES 2
1053 struct intel_l3_parity {
1054 u32 *remap_info[MAX_L3_SLICES];
1055 struct work_struct error_work;
1059 struct i915_gem_mm {
1060 /** Memory allocator for GTT stolen memory */
1061 struct drm_mm stolen;
1062 /** Protects the usage of the GTT stolen memory allocator. This is
1063 * always the inner lock when overlapping with struct_mutex. */
1064 struct mutex stolen_lock;
1066 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
1067 spinlock_t obj_lock;
1069 /** List of all objects in gtt_space. Used to restore gtt
1070 * mappings on resume */
1071 struct list_head bound_list;
1073 * List of objects which are not bound to the GTT (thus
1074 * are idle and not used by the GPU). These objects may or may
1075 * not actually have any pages attached.
1077 struct list_head unbound_list;
1079 /** List of all objects in gtt_space, currently mmaped by userspace.
1080 * All objects within this list must also be on bound_list.
1082 struct list_head userfault_list;
1085 * List of objects which are pending destruction.
1087 struct llist_head free_list;
1088 struct work_struct free_work;
1089 spinlock_t free_lock;
1092 * Small stash of WC pages
1094 struct pagevec wc_stash;
1097 * tmpfs instance used for shmem backed objects
1099 struct vfsmount *gemfs;
1101 /** PPGTT used for aliasing the PPGTT with the GTT */
1102 struct i915_hw_ppgtt *aliasing_ppgtt;
1104 struct notifier_block oom_notifier;
1105 struct notifier_block vmap_notifier;
1106 struct shrinker shrinker;
1108 /** LRU list of objects with fence regs on them. */
1109 struct list_head fence_list;
1112 * Workqueue to fault in userptr pages, flushed by the execbuf
1113 * when required but otherwise left to userspace to try again
1116 struct workqueue_struct *userptr_wq;
1118 u64 unordered_timeline;
1120 /* the indicator for dispatch video commands on two BSD rings */
1121 atomic_t bsd_engine_dispatch_index;
1123 /** Bit 6 swizzling required for X tiling */
1124 uint32_t bit_6_swizzle_x;
1125 /** Bit 6 swizzling required for Y tiling */
1126 uint32_t bit_6_swizzle_y;
1128 /* accounting, useful for userland debugging */
1129 spinlock_t object_stat_lock;
1134 struct drm_i915_error_state_buf {
1135 struct drm_i915_private *i915;
1144 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1146 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1147 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1149 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1150 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1152 struct i915_gpu_error {
1153 /* For hangcheck timer */
1154 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1155 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1157 struct delayed_work hangcheck_work;
1159 /* For reset and error_state handling. */
1161 /* Protected by the above dev->gpu_error.lock. */
1162 struct i915_gpu_state *first_error;
1164 atomic_t pending_fb_pin;
1166 unsigned long missed_irq_rings;
1169 * State variable controlling the reset flow and count
1171 * This is a counter which gets incremented when reset is triggered,
1173 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1174 * meaning that any waiters holding onto the struct_mutex should
1175 * relinquish the lock immediately in order for the reset to start.
1177 * If reset is not completed succesfully, the I915_WEDGE bit is
1178 * set meaning that hardware is terminally sour and there is no
1179 * recovery. All waiters on the reset_queue will be woken when
1182 * This counter is used by the wait_seqno code to notice that reset
1183 * event happened and it needs to restart the entire ioctl (since most
1184 * likely the seqno it waited for won't ever signal anytime soon).
1186 * This is important for lock-free wait paths, where no contended lock
1187 * naturally enforces the correct ordering between the bail-out of the
1188 * waiter and the gpu reset work code.
1190 unsigned long reset_count;
1193 * flags: Control various stages of the GPU reset
1195 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
1196 * other users acquiring the struct_mutex. To do this we set the
1197 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
1198 * and then check for that bit before acquiring the struct_mutex (in
1199 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
1200 * secondary role in preventing two concurrent global reset attempts.
1202 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
1203 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
1204 * but it may be held by some long running waiter (that we cannot
1205 * interrupt without causing trouble). Once we are ready to do the GPU
1206 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
1207 * they already hold the struct_mutex and want to participate they can
1208 * inspect the bit and do the reset directly, otherwise the worker
1209 * waits for the struct_mutex.
1211 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
1212 * acquire the struct_mutex to reset an engine, we need an explicit
1213 * flag to prevent two concurrent reset attempts in the same engine.
1214 * As the number of engines continues to grow, allocate the flags from
1215 * the most significant bits.
1217 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
1218 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
1219 * i915_gem_request_alloc(), this bit is checked and the sequence
1220 * aborted (with -EIO reported to userspace) if set.
1222 unsigned long flags;
1223 #define I915_RESET_BACKOFF 0
1224 #define I915_RESET_HANDOFF 1
1225 #define I915_RESET_MODESET 2
1226 #define I915_WEDGED (BITS_PER_LONG - 1)
1227 #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
1229 /** Number of times an engine has been reset */
1230 u32 reset_engine_count[I915_NUM_ENGINES];
1233 * Waitqueue to signal when a hang is detected. Used to for waiters
1234 * to release the struct_mutex for the reset to procede.
1236 wait_queue_head_t wait_queue;
1239 * Waitqueue to signal when the reset has completed. Used by clients
1240 * that wait for dev_priv->mm.wedged to settle.
1242 wait_queue_head_t reset_queue;
1244 /* For missed irq/seqno simulation. */
1245 unsigned long test_irq_rings;
1248 enum modeset_restore {
1249 MODESET_ON_LID_OPEN,
1254 #define DP_AUX_A 0x40
1255 #define DP_AUX_B 0x10
1256 #define DP_AUX_C 0x20
1257 #define DP_AUX_D 0x30
1258 #define DP_AUX_F 0x60
1260 #define DDC_PIN_B 0x05
1261 #define DDC_PIN_C 0x04
1262 #define DDC_PIN_D 0x06
1264 struct ddi_vbt_port_info {
1268 * This is an index in the HDMI/DVI DDI buffer translation table.
1269 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1270 * populate this field.
1272 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1273 uint8_t hdmi_level_shift;
1275 uint8_t supports_dvi:1;
1276 uint8_t supports_hdmi:1;
1277 uint8_t supports_dp:1;
1278 uint8_t supports_edp:1;
1280 uint8_t alternate_aux_channel;
1281 uint8_t alternate_ddc_pin;
1283 uint8_t dp_boost_level;
1284 uint8_t hdmi_boost_level;
1287 enum psr_lines_to_wait {
1288 PSR_0_LINES_TO_WAIT = 0,
1290 PSR_4_LINES_TO_WAIT,
1294 struct intel_vbt_data {
1295 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1296 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1299 unsigned int int_tv_support:1;
1300 unsigned int lvds_dither:1;
1301 unsigned int lvds_vbt:1;
1302 unsigned int int_crt_support:1;
1303 unsigned int lvds_use_ssc:1;
1304 unsigned int display_clock_mode:1;
1305 unsigned int fdi_rx_polarity_inverted:1;
1306 unsigned int panel_type:4;
1308 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1310 enum drrs_support_type drrs_type;
1321 struct edp_power_seq pps;
1326 bool require_aux_wakeup;
1328 enum psr_lines_to_wait lines_to_wait;
1329 int tp1_wakeup_time;
1330 int tp2_tp3_wakeup_time;
1336 bool active_low_pwm;
1337 u8 min_brightness; /* min_brightness/255 of max */
1338 u8 controller; /* brightness controller number */
1339 enum intel_backlight_type type;
1345 struct mipi_config *config;
1346 struct mipi_pps_data *pps;
1352 const u8 *sequence[MIPI_SEQ_MAX];
1358 struct child_device_config *child_dev;
1360 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1361 struct sdvo_device_mapping sdvo_mappings[2];
1364 enum intel_ddb_partitioning {
1366 INTEL_DDB_PART_5_6, /* IVB+ */
1369 struct intel_wm_level {
1377 struct ilk_wm_values {
1378 uint32_t wm_pipe[3];
1380 uint32_t wm_lp_spr[3];
1381 uint32_t wm_linetime[3];
1383 enum intel_ddb_partitioning partitioning;
1386 struct g4x_pipe_wm {
1387 uint16_t plane[I915_MAX_PLANES];
1397 struct vlv_wm_ddl_values {
1398 uint8_t plane[I915_MAX_PLANES];
1401 struct vlv_wm_values {
1402 struct g4x_pipe_wm pipe[3];
1403 struct g4x_sr_wm sr;
1404 struct vlv_wm_ddl_values ddl[3];
1409 struct g4x_wm_values {
1410 struct g4x_pipe_wm pipe[2];
1411 struct g4x_sr_wm sr;
1412 struct g4x_sr_wm hpll;
1418 struct skl_ddb_entry {
1419 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1422 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1424 return entry->end - entry->start;
1427 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1428 const struct skl_ddb_entry *e2)
1430 if (e1->start == e2->start && e1->end == e2->end)
1436 struct skl_ddb_allocation {
1437 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1438 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1441 struct skl_wm_values {
1442 unsigned dirty_pipes;
1443 struct skl_ddb_allocation ddb;
1446 struct skl_wm_level {
1448 uint16_t plane_res_b;
1449 uint8_t plane_res_l;
1452 /* Stores plane specific WM parameters */
1453 struct skl_wm_params {
1454 bool x_tiled, y_tiled;
1458 uint32_t plane_pixel_rate;
1459 uint32_t y_min_scanlines;
1460 uint32_t plane_bytes_per_line;
1461 uint_fixed_16_16_t plane_blocks_per_line;
1462 uint_fixed_16_16_t y_tile_minimum;
1463 uint32_t linetime_us;
1467 * This struct helps tracking the state needed for runtime PM, which puts the
1468 * device in PCI D3 state. Notice that when this happens, nothing on the
1469 * graphics device works, even register access, so we don't get interrupts nor
1472 * Every piece of our code that needs to actually touch the hardware needs to
1473 * either call intel_runtime_pm_get or call intel_display_power_get with the
1474 * appropriate power domain.
1476 * Our driver uses the autosuspend delay feature, which means we'll only really
1477 * suspend if we stay with zero refcount for a certain amount of time. The
1478 * default value is currently very conservative (see intel_runtime_pm_enable), but
1479 * it can be changed with the standard runtime PM files from sysfs.
1481 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1482 * goes back to false exactly before we reenable the IRQs. We use this variable
1483 * to check if someone is trying to enable/disable IRQs while they're supposed
1484 * to be disabled. This shouldn't happen and we'll print some error messages in
1487 * For more, read the Documentation/power/runtime_pm.txt.
1489 struct i915_runtime_pm {
1490 atomic_t wakeref_count;
1495 enum intel_pipe_crc_source {
1496 INTEL_PIPE_CRC_SOURCE_NONE,
1497 INTEL_PIPE_CRC_SOURCE_PLANE1,
1498 INTEL_PIPE_CRC_SOURCE_PLANE2,
1499 INTEL_PIPE_CRC_SOURCE_PF,
1500 INTEL_PIPE_CRC_SOURCE_PIPE,
1501 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1502 INTEL_PIPE_CRC_SOURCE_TV,
1503 INTEL_PIPE_CRC_SOURCE_DP_B,
1504 INTEL_PIPE_CRC_SOURCE_DP_C,
1505 INTEL_PIPE_CRC_SOURCE_DP_D,
1506 INTEL_PIPE_CRC_SOURCE_AUTO,
1507 INTEL_PIPE_CRC_SOURCE_MAX,
1510 struct intel_pipe_crc_entry {
1515 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1516 struct intel_pipe_crc {
1518 bool opened; /* exclusive access to the result file */
1519 struct intel_pipe_crc_entry *entries;
1520 enum intel_pipe_crc_source source;
1522 wait_queue_head_t wq;
1526 struct i915_frontbuffer_tracking {
1530 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1537 struct i915_wa_reg {
1540 /* bitmask representing WA bits */
1544 #define I915_MAX_WA_REGS 16
1546 struct i915_workarounds {
1547 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1549 u32 hw_whitelist_count[I915_NUM_ENGINES];
1552 struct i915_virtual_gpu {
1557 /* used in computing the new watermarks state */
1558 struct intel_wm_config {
1559 unsigned int num_pipes_active;
1560 bool sprites_enabled;
1561 bool sprites_scaled;
1564 struct i915_oa_format {
1569 struct i915_oa_reg {
1574 struct i915_oa_config {
1575 char uuid[UUID_STRING_LEN + 1];
1578 const struct i915_oa_reg *mux_regs;
1580 const struct i915_oa_reg *b_counter_regs;
1581 u32 b_counter_regs_len;
1582 const struct i915_oa_reg *flex_regs;
1585 struct attribute_group sysfs_metric;
1586 struct attribute *attrs[2];
1587 struct device_attribute sysfs_metric_id;
1592 struct i915_perf_stream;
1595 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1597 struct i915_perf_stream_ops {
1599 * @enable: Enables the collection of HW samples, either in response to
1600 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1601 * without `I915_PERF_FLAG_DISABLED`.
1603 void (*enable)(struct i915_perf_stream *stream);
1606 * @disable: Disables the collection of HW samples, either in response
1607 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1610 void (*disable)(struct i915_perf_stream *stream);
1613 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1614 * once there is something ready to read() for the stream
1616 void (*poll_wait)(struct i915_perf_stream *stream,
1621 * @wait_unlocked: For handling a blocking read, wait until there is
1622 * something to ready to read() for the stream. E.g. wait on the same
1623 * wait queue that would be passed to poll_wait().
1625 int (*wait_unlocked)(struct i915_perf_stream *stream);
1628 * @read: Copy buffered metrics as records to userspace
1629 * **buf**: the userspace, destination buffer
1630 * **count**: the number of bytes to copy, requested by userspace
1631 * **offset**: zero at the start of the read, updated as the read
1632 * proceeds, it represents how many bytes have been copied so far and
1633 * the buffer offset for copying the next record.
1635 * Copy as many buffered i915 perf samples and records for this stream
1636 * to userspace as will fit in the given buffer.
1638 * Only write complete records; returning -%ENOSPC if there isn't room
1639 * for a complete record.
1641 * Return any error condition that results in a short read such as
1642 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1643 * returning to userspace.
1645 int (*read)(struct i915_perf_stream *stream,
1651 * @destroy: Cleanup any stream specific resources.
1653 * The stream will always be disabled before this is called.
1655 void (*destroy)(struct i915_perf_stream *stream);
1659 * struct i915_perf_stream - state for a single open stream FD
1661 struct i915_perf_stream {
1663 * @dev_priv: i915 drm device
1665 struct drm_i915_private *dev_priv;
1668 * @link: Links the stream into ``&drm_i915_private->streams``
1670 struct list_head link;
1673 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1674 * properties given when opening a stream, representing the contents
1675 * of a single sample as read() by userspace.
1680 * @sample_size: Considering the configured contents of a sample
1681 * combined with the required header size, this is the total size
1682 * of a single sample record.
1687 * @ctx: %NULL if measuring system-wide across all contexts or a
1688 * specific context that is being monitored.
1690 struct i915_gem_context *ctx;
1693 * @enabled: Whether the stream is currently enabled, considering
1694 * whether the stream was opened in a disabled state and based
1695 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1700 * @ops: The callbacks providing the implementation of this specific
1701 * type of configured stream.
1703 const struct i915_perf_stream_ops *ops;
1706 * @oa_config: The OA configuration used by the stream.
1708 struct i915_oa_config *oa_config;
1712 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1714 struct i915_oa_ops {
1716 * @is_valid_b_counter_reg: Validates register's address for
1717 * programming boolean counters for a particular platform.
1719 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1723 * @is_valid_mux_reg: Validates register's address for programming mux
1724 * for a particular platform.
1726 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1729 * @is_valid_flex_reg: Validates register's address for programming
1730 * flex EU filtering for a particular platform.
1732 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1735 * @init_oa_buffer: Resets the head and tail pointers of the
1736 * circular buffer for periodic OA reports.
1738 * Called when first opening a stream for OA metrics, but also may be
1739 * called in response to an OA buffer overflow or other error
1742 * Note it may be necessary to clear the full OA buffer here as part of
1743 * maintaining the invariable that new reports must be written to
1744 * zeroed memory for us to be able to reliable detect if an expected
1745 * report has not yet landed in memory. (At least on Haswell the OA
1746 * buffer tail pointer is not synchronized with reports being visible
1749 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1752 * @enable_metric_set: Selects and applies any MUX configuration to set
1753 * up the Boolean and Custom (B/C) counters that are part of the
1754 * counter reports being sampled. May apply system constraints such as
1755 * disabling EU clock gating as required.
1757 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1758 const struct i915_oa_config *oa_config);
1761 * @disable_metric_set: Remove system constraints associated with using
1764 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1767 * @oa_enable: Enable periodic sampling
1769 void (*oa_enable)(struct drm_i915_private *dev_priv);
1772 * @oa_disable: Disable periodic sampling
1774 void (*oa_disable)(struct drm_i915_private *dev_priv);
1777 * @read: Copy data from the circular OA buffer into a given userspace
1780 int (*read)(struct i915_perf_stream *stream,
1786 * @oa_hw_tail_read: read the OA tail pointer register
1788 * In particular this enables us to share all the fiddly code for
1789 * handling the OA unit tail pointer race that affects multiple
1792 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1795 struct intel_cdclk_state {
1796 unsigned int cdclk, vco, ref, bypass;
1800 struct drm_i915_private {
1801 struct drm_device drm;
1803 struct kmem_cache *objects;
1804 struct kmem_cache *vmas;
1805 struct kmem_cache *luts;
1806 struct kmem_cache *requests;
1807 struct kmem_cache *dependencies;
1808 struct kmem_cache *priorities;
1810 const struct intel_device_info info;
1813 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1814 * end of stolen which we can optionally use to create GEM objects
1815 * backed by stolen memory. Note that stolen_usable_size tells us
1816 * exactly how much of this we are actually allowed to use, given that
1817 * some portion of it is in fact reserved for use by hardware functions.
1819 struct resource dsm;
1821 * Reseved portion of Data Stolen Memory
1823 struct resource dsm_reserved;
1826 * Stolen memory is segmented in hardware with different portions
1827 * offlimits to certain functions.
1829 * The drm_mm is initialised to the total accessible range, as found
1830 * from the PCI config. On Broadwell+, this is further restricted to
1831 * avoid the first page! The upper end of stolen memory is reserved for
1832 * hardware functions and similarly removed from the accessible range.
1834 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1838 struct intel_uncore uncore;
1840 struct i915_virtual_gpu vgpu;
1842 struct intel_gvt *gvt;
1844 struct intel_huc huc;
1845 struct intel_guc guc;
1847 struct intel_csr csr;
1849 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1851 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1852 * controller on different i2c buses. */
1853 struct mutex gmbus_mutex;
1856 * Base address of the gmbus and gpio block.
1858 uint32_t gpio_mmio_base;
1860 /* MMIO base address for MIPI regs */
1861 uint32_t mipi_mmio_base;
1863 uint32_t psr_mmio_base;
1865 uint32_t pps_mmio_base;
1867 wait_queue_head_t gmbus_wait_queue;
1869 struct pci_dev *bridge_dev;
1870 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1871 /* Context used internally to idle the GPU and setup initial state */
1872 struct i915_gem_context *kernel_context;
1873 /* Context only to be used for injecting preemption commands */
1874 struct i915_gem_context *preempt_context;
1875 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1876 [MAX_ENGINE_INSTANCE + 1];
1878 struct drm_dma_handle *status_page_dmah;
1879 struct resource mch_res;
1881 /* protects the irq masks */
1882 spinlock_t irq_lock;
1884 bool display_irqs_enabled;
1886 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1887 struct pm_qos_request pm_qos;
1889 /* Sideband mailbox protection */
1890 struct mutex sb_lock;
1892 /** Cached value of IMR to avoid reads in updating the bitfield */
1895 u32 de_irq_mask[I915_MAX_PIPES];
1902 u32 pipestat_irq_mask[I915_MAX_PIPES];
1904 struct i915_hotplug hotplug;
1905 struct intel_fbc fbc;
1906 struct i915_drrs drrs;
1907 struct intel_opregion opregion;
1908 struct intel_vbt_data vbt;
1910 bool preserve_bios_swizzle;
1913 struct intel_overlay *overlay;
1915 /* backlight registers and fields in struct intel_panel */
1916 struct mutex backlight_lock;
1919 bool no_aux_handshake;
1921 /* protects panel power sequencer state */
1922 struct mutex pps_mutex;
1924 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1925 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1927 unsigned int fsb_freq, mem_freq, is_ddr3;
1928 unsigned int skl_preferred_vco_freq;
1929 unsigned int max_cdclk_freq;
1931 unsigned int max_dotclk_freq;
1932 unsigned int rawclk_freq;
1933 unsigned int hpll_freq;
1934 unsigned int fdi_pll_freq;
1935 unsigned int czclk_freq;
1939 * The current logical cdclk state.
1940 * See intel_atomic_state.cdclk.logical
1942 * For reading holding any crtc lock is sufficient,
1943 * for writing must hold all of them.
1945 struct intel_cdclk_state logical;
1947 * The current actual cdclk state.
1948 * See intel_atomic_state.cdclk.actual
1950 struct intel_cdclk_state actual;
1951 /* The current hardware cdclk state */
1952 struct intel_cdclk_state hw;
1956 * wq - Driver workqueue for GEM.
1958 * NOTE: Work items scheduled here are not allowed to grab any modeset
1959 * locks, for otherwise the flushing done in the pageflip code will
1960 * result in deadlocks.
1962 struct workqueue_struct *wq;
1964 /* ordered wq for modesets */
1965 struct workqueue_struct *modeset_wq;
1967 /* Display functions */
1968 struct drm_i915_display_funcs display;
1970 /* PCH chipset type */
1971 enum intel_pch pch_type;
1972 unsigned short pch_id;
1974 unsigned long quirks;
1976 enum modeset_restore modeset_restore;
1977 struct mutex modeset_restore_lock;
1978 struct drm_atomic_state *modeset_restore_state;
1979 struct drm_modeset_acquire_ctx reset_ctx;
1981 struct list_head vm_list; /* Global list of all address spaces */
1982 struct i915_ggtt ggtt; /* VM representing the global address space */
1984 struct i915_gem_mm mm;
1985 DECLARE_HASHTABLE(mm_structs, 7);
1986 struct mutex mm_lock;
1988 struct intel_ppat ppat;
1990 /* Kernel Modesetting */
1992 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1993 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1995 #ifdef CONFIG_DEBUG_FS
1996 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1999 /* dpll and cdclk state is protected by connection_mutex */
2000 int num_shared_dpll;
2001 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2002 const struct intel_dpll_mgr *dpll_mgr;
2005 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
2006 * Must be global rather than per dpll, because on some platforms
2007 * plls share registers.
2009 struct mutex dpll_lock;
2011 unsigned int active_crtcs;
2012 /* minimum acceptable cdclk for each pipe */
2013 int min_cdclk[I915_MAX_PIPES];
2014 /* minimum acceptable voltage level for each pipe */
2015 u8 min_voltage_level[I915_MAX_PIPES];
2017 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2019 struct i915_workarounds workarounds;
2021 struct i915_frontbuffer_tracking fb_tracking;
2023 struct intel_atomic_helper {
2024 struct llist_head free_list;
2025 struct work_struct free_work;
2030 bool mchbar_need_disable;
2032 struct intel_l3_parity l3_parity;
2034 /* Cannot be determined by PCIID. You must always read a register. */
2038 * Protects RPS/RC6 register access and PCU communication.
2039 * Must be taken after struct_mutex if nested. Note that
2040 * this lock may be held for long periods of time when
2041 * talking to hw - so only take it when talking to hw!
2043 struct mutex pcu_lock;
2045 /* gen6+ GT PM state */
2046 struct intel_gen6_power_mgmt gt_pm;
2048 /* ilk-only ips/rps state. Everything in here is protected by the global
2049 * mchdev_lock in intel_pm.c */
2050 struct intel_ilk_power_mgmt ips;
2052 struct i915_power_domains power_domains;
2054 struct i915_psr psr;
2056 struct i915_gpu_error gpu_error;
2058 struct drm_i915_gem_object *vlv_pctx;
2060 /* list of fbdev register on this device */
2061 struct intel_fbdev *fbdev;
2062 struct work_struct fbdev_suspend_work;
2064 struct drm_property *broadcast_rgb_property;
2065 struct drm_property *force_audio_property;
2067 /* hda/i915 audio component */
2068 struct i915_audio_component *audio_component;
2069 bool audio_component_registered;
2071 * av_mutex - mutex for audio/video sync
2074 struct mutex av_mutex;
2077 struct list_head list;
2078 struct llist_head free_list;
2079 struct work_struct free_work;
2081 /* The hw wants to have a stable context identifier for the
2082 * lifetime of the context (for OA, PASID, faults, etc).
2083 * This is limited in execlists to 21 bits.
2086 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
2091 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2092 u32 chv_phy_control;
2094 * Shadows for CHV DPLL_MD regs to keep the state
2095 * checker somewhat working in the presence hardware
2096 * crappiness (can't read out DPLL_MD for pipes B & C).
2098 u32 chv_dpll_md[I915_MAX_PIPES];
2102 bool suspended_to_idle;
2103 struct i915_suspend_saved_registers regfile;
2104 struct vlv_s0ix_state vlv_s0ix_state;
2107 I915_SAGV_UNKNOWN = 0,
2110 I915_SAGV_NOT_CONTROLLED
2115 * Raw watermark latency values:
2116 * in 0.1us units for WM0,
2117 * in 0.5us units for WM1+.
2120 uint16_t pri_latency[5];
2122 uint16_t spr_latency[5];
2124 uint16_t cur_latency[5];
2126 * Raw watermark memory latency values
2127 * for SKL for all 8 levels
2130 uint16_t skl_latency[8];
2132 /* current hardware state */
2134 struct ilk_wm_values hw;
2135 struct skl_wm_values skl_hw;
2136 struct vlv_wm_values vlv;
2137 struct g4x_wm_values g4x;
2143 * Should be held around atomic WM register writing; also
2144 * protects * intel_crtc->wm.active and
2145 * cstate->wm.need_postvbl_update.
2147 struct mutex wm_mutex;
2150 * Set during HW readout of watermarks/DDB. Some platforms
2151 * need to know when we're still using BIOS-provided values
2152 * (which we don't fully trust).
2154 bool distrust_bios_wm;
2157 struct i915_runtime_pm runtime_pm;
2162 struct kobject *metrics_kobj;
2163 struct ctl_table_header *sysctl_header;
2166 * Lock associated with adding/modifying/removing OA configs
2167 * in dev_priv->perf.metrics_idr.
2169 struct mutex metrics_lock;
2172 * List of dynamic configurations, you need to hold
2173 * dev_priv->perf.metrics_lock to access it.
2175 struct idr metrics_idr;
2178 * Lock associated with anything below within this structure
2179 * except exclusive_stream.
2182 struct list_head streams;
2186 * The stream currently using the OA unit. If accessed
2187 * outside a syscall associated to its file
2188 * descriptor, you need to hold
2189 * dev_priv->drm.struct_mutex.
2191 struct i915_perf_stream *exclusive_stream;
2193 u32 specific_ctx_id;
2195 struct hrtimer poll_check_timer;
2196 wait_queue_head_t poll_wq;
2200 * For rate limiting any notifications of spurious
2201 * invalid OA reports
2203 struct ratelimit_state spurious_report_rs;
2206 int period_exponent;
2208 struct i915_oa_config test_config;
2211 struct i915_vma *vma;
2218 * Locks reads and writes to all head/tail state
2220 * Consider: the head and tail pointer state
2221 * needs to be read consistently from a hrtimer
2222 * callback (atomic context) and read() fop
2223 * (user context) with tail pointer updates
2224 * happening in atomic context and head updates
2225 * in user context and the (unlikely)
2226 * possibility of read() errors needing to
2227 * reset all head/tail state.
2229 * Note: Contention or performance aren't
2230 * currently a significant concern here
2231 * considering the relatively low frequency of
2232 * hrtimer callbacks (5ms period) and that
2233 * reads typically only happen in response to a
2234 * hrtimer event and likely complete before the
2237 * Note: This lock is not held *while* reading
2238 * and copying data to userspace so the value
2239 * of head observed in htrimer callbacks won't
2240 * represent any partial consumption of data.
2242 spinlock_t ptr_lock;
2245 * One 'aging' tail pointer and one 'aged'
2246 * tail pointer ready to used for reading.
2248 * Initial values of 0xffffffff are invalid
2249 * and imply that an update is required
2250 * (and should be ignored by an attempted
2258 * Index for the aged tail ready to read()
2261 unsigned int aged_tail_idx;
2264 * A monotonic timestamp for when the current
2265 * aging tail pointer was read; used to
2266 * determine when it is old enough to trust.
2268 u64 aging_timestamp;
2271 * Although we can always read back the head
2272 * pointer register, we prefer to avoid
2273 * trusting the HW state, just to avoid any
2274 * risk that some hardware condition could
2275 * somehow bump the head pointer unpredictably
2276 * and cause us to forward the wrong OA buffer
2277 * data to userspace.
2282 u32 gen7_latched_oastatus1;
2283 u32 ctx_oactxctrl_offset;
2284 u32 ctx_flexeu0_offset;
2287 * The RPT_ID/reason field for Gen8+ includes a bit
2288 * to determine if the CTX ID in the report is valid
2289 * but the specific bit differs between Gen 8 and 9
2291 u32 gen8_valid_ctx_bit;
2293 struct i915_oa_ops ops;
2294 const struct i915_oa_format *oa_formats;
2298 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2300 void (*resume)(struct drm_i915_private *);
2301 void (*cleanup_engine)(struct intel_engine_cs *engine);
2303 struct list_head timelines;
2304 struct i915_gem_timeline global_timeline;
2305 u32 active_requests;
2308 * Is the GPU currently considered idle, or busy executing
2309 * userspace requests? Whilst idle, we allow runtime power
2310 * management to power down the hardware and display clocks.
2311 * In order to reduce the effect on performance, there
2312 * is a slight delay before we do so.
2317 * The number of times we have woken up.
2320 #define I915_EPOCH_INVALID 0
2323 * We leave the user IRQ off as much as possible,
2324 * but this means that requests will finish and never
2325 * be retired once the system goes idle. Set a timer to
2326 * fire periodically while the ring is running. When it
2327 * fires, go retire requests.
2329 struct delayed_work retire_work;
2332 * When we detect an idle GPU, we want to turn on
2333 * powersaving features. So once we see that there
2334 * are no more requests outstanding and no more
2335 * arrive within a small period of time, we fire
2336 * off the idle_work.
2338 struct delayed_work idle_work;
2340 ktime_t last_init_time;
2343 /* perform PHY state sanity checks? */
2344 bool chv_phy_assert[2];
2348 /* Used to save the pipe-to-encoder mapping for audio */
2349 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2351 /* necessary resource sharing with HDMI LPE audio driver. */
2353 struct platform_device *platdev;
2357 struct i915_pmu pmu;
2360 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2361 * will be rejected. Instead look for a better place.
2365 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2367 return container_of(dev, struct drm_i915_private, drm);
2370 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2372 return to_i915(dev_get_drvdata(kdev));
2375 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2377 return container_of(guc, struct drm_i915_private, guc);
2380 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2382 return container_of(huc, struct drm_i915_private, huc);
2385 /* Simple iterator over all initialised engines */
2386 #define for_each_engine(engine__, dev_priv__, id__) \
2388 (id__) < I915_NUM_ENGINES; \
2390 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2392 /* Iterator over subset of engines selected by mask */
2393 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2394 for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \
2395 tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2397 enum hdmi_force_audio {
2398 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2399 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2400 HDMI_AUDIO_AUTO, /* trust EDID */
2401 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2404 #define I915_GTT_OFFSET_NONE ((u32)-1)
2407 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2408 * considered to be the frontbuffer for the given plane interface-wise. This
2409 * doesn't mean that the hw necessarily already scans it out, but that any
2410 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2412 * We have one bit per pipe and per scanout plane type.
2414 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2415 #define INTEL_FRONTBUFFER(pipe, plane_id) \
2416 (1 << ((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2417 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2418 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2419 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2420 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2423 * Optimised SGL iterator for GEM objects
2425 static __always_inline struct sgt_iter {
2426 struct scatterlist *sgp;
2433 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2434 struct sgt_iter s = { .sgp = sgl };
2437 s.max = s.curr = s.sgp->offset;
2438 s.max += s.sgp->length;
2440 s.dma = sg_dma_address(s.sgp);
2442 s.pfn = page_to_pfn(sg_page(s.sgp));
2448 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2451 if (unlikely(sg_is_chain(sg)))
2452 sg = sg_chain_ptr(sg);
2457 * __sg_next - return the next scatterlist entry in a list
2458 * @sg: The current sg entry
2461 * If the entry is the last, return NULL; otherwise, step to the next
2462 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2463 * otherwise just return the pointer to the current element.
2465 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2467 #ifdef CONFIG_DEBUG_SG
2468 BUG_ON(sg->sg_magic != SG_MAGIC);
2470 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2474 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2475 * @__dmap: DMA address (output)
2476 * @__iter: 'struct sgt_iter' (iterator state, internal)
2477 * @__sgt: sg_table to iterate over (input)
2479 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2480 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2481 ((__dmap) = (__iter).dma + (__iter).curr); \
2482 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2483 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2486 * for_each_sgt_page - iterate over the pages of the given sg_table
2487 * @__pp: page pointer (output)
2488 * @__iter: 'struct sgt_iter' (iterator state, internal)
2489 * @__sgt: sg_table to iterate over (input)
2491 #define for_each_sgt_page(__pp, __iter, __sgt) \
2492 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2493 ((__pp) = (__iter).pfn == 0 ? NULL : \
2494 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2495 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2496 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2498 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2500 unsigned int page_sizes;
2504 GEM_BUG_ON(sg->offset);
2505 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2506 page_sizes |= sg->length;
2513 static inline unsigned int i915_sg_segment_size(void)
2515 unsigned int size = swiotlb_max_segment();
2518 return SCATTERLIST_MAX_SEGMENT;
2520 size = rounddown(size, PAGE_SIZE);
2521 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2522 if (size < PAGE_SIZE)
2528 static inline const struct intel_device_info *
2529 intel_info(const struct drm_i915_private *dev_priv)
2531 return &dev_priv->info;
2534 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2536 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2537 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2539 #define REVID_FOREVER 0xff
2540 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2542 #define GEN_FOREVER (0)
2544 #define INTEL_GEN_MASK(s, e) ( \
2545 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2546 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2547 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2548 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2552 * Returns true if Gen is in inclusive range [Start, End].
2554 * Use GEN_FOREVER for unbound start and or end.
2556 #define IS_GEN(dev_priv, s, e) \
2557 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2560 * Return true if revision is in range [since,until] inclusive.
2562 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2564 #define IS_REVID(p, since, until) \
2565 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2567 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2569 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2570 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2571 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2572 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2573 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2574 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2575 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2576 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2577 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2578 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2579 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2580 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2581 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2582 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2583 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2584 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2585 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2586 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2587 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2588 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2589 (dev_priv)->info.gt == 1)
2590 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2591 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2592 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2593 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2594 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2595 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2596 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2597 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2598 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2599 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2600 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2601 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2602 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2603 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2604 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2605 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2606 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2607 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2608 /* ULX machines are also considered ULT. */
2609 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2610 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2611 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2612 (dev_priv)->info.gt == 3)
2613 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2614 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2615 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2616 (dev_priv)->info.gt == 3)
2617 /* ULX machines are also considered ULT. */
2618 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2619 INTEL_DEVID(dev_priv) == 0x0A1E)
2620 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2621 INTEL_DEVID(dev_priv) == 0x1913 || \
2622 INTEL_DEVID(dev_priv) == 0x1916 || \
2623 INTEL_DEVID(dev_priv) == 0x1921 || \
2624 INTEL_DEVID(dev_priv) == 0x1926)
2625 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2626 INTEL_DEVID(dev_priv) == 0x1915 || \
2627 INTEL_DEVID(dev_priv) == 0x191E)
2628 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2629 INTEL_DEVID(dev_priv) == 0x5913 || \
2630 INTEL_DEVID(dev_priv) == 0x5916 || \
2631 INTEL_DEVID(dev_priv) == 0x5921 || \
2632 INTEL_DEVID(dev_priv) == 0x5926)
2633 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2634 INTEL_DEVID(dev_priv) == 0x5915 || \
2635 INTEL_DEVID(dev_priv) == 0x591E)
2636 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2637 (dev_priv)->info.gt == 2)
2638 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2639 (dev_priv)->info.gt == 3)
2640 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2641 (dev_priv)->info.gt == 4)
2642 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2643 (dev_priv)->info.gt == 2)
2644 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2645 (dev_priv)->info.gt == 3)
2646 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2647 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2648 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2649 (dev_priv)->info.gt == 2)
2650 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2651 (dev_priv)->info.gt == 3)
2652 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2653 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2655 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2657 #define SKL_REVID_A0 0x0
2658 #define SKL_REVID_B0 0x1
2659 #define SKL_REVID_C0 0x2
2660 #define SKL_REVID_D0 0x3
2661 #define SKL_REVID_E0 0x4
2662 #define SKL_REVID_F0 0x5
2663 #define SKL_REVID_G0 0x6
2664 #define SKL_REVID_H0 0x7
2666 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2668 #define BXT_REVID_A0 0x0
2669 #define BXT_REVID_A1 0x1
2670 #define BXT_REVID_B0 0x3
2671 #define BXT_REVID_B_LAST 0x8
2672 #define BXT_REVID_C0 0x9
2674 #define IS_BXT_REVID(dev_priv, since, until) \
2675 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2677 #define KBL_REVID_A0 0x0
2678 #define KBL_REVID_B0 0x1
2679 #define KBL_REVID_C0 0x2
2680 #define KBL_REVID_D0 0x3
2681 #define KBL_REVID_E0 0x4
2683 #define IS_KBL_REVID(dev_priv, since, until) \
2684 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2686 #define GLK_REVID_A0 0x0
2687 #define GLK_REVID_A1 0x1
2689 #define IS_GLK_REVID(dev_priv, since, until) \
2690 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2692 #define CNL_REVID_A0 0x0
2693 #define CNL_REVID_B0 0x1
2694 #define CNL_REVID_C0 0x2
2696 #define IS_CNL_REVID(p, since, until) \
2697 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2700 * The genX designation typically refers to the render engine, so render
2701 * capability related checks should use IS_GEN, while display and other checks
2702 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2705 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2706 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2707 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2708 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2709 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2710 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2711 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2712 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2713 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2714 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2716 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2717 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2718 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2720 #define ENGINE_MASK(id) BIT(id)
2721 #define RENDER_RING ENGINE_MASK(RCS)
2722 #define BSD_RING ENGINE_MASK(VCS)
2723 #define BLT_RING ENGINE_MASK(BCS)
2724 #define VEBOX_RING ENGINE_MASK(VECS)
2725 #define BSD2_RING ENGINE_MASK(VCS2)
2726 #define ALL_ENGINES (~0)
2728 #define HAS_ENGINE(dev_priv, id) \
2729 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2731 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2732 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2733 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2734 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2736 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2738 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2739 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2740 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2741 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2742 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2744 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2746 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2747 ((dev_priv)->info.has_logical_ring_contexts)
2748 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2749 ((dev_priv)->info.has_logical_ring_preemption)
2751 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2753 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2754 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2755 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2756 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2757 GEM_BUG_ON((sizes) == 0); \
2758 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2761 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2762 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2763 ((dev_priv)->info.overlay_needs_physical)
2765 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2766 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2768 /* WaRsDisableCoarsePowerGating:skl,bxt */
2769 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2770 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2773 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2774 * even when in MSI mode. This results in spurious interrupt warnings if the
2775 * legacy irq no. is shared with another device. The kernel then disables that
2776 * interrupt source and so prevents the other device from working properly.
2778 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
2781 #define HAS_AUX_IRQ(dev_priv) true
2782 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2784 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2785 * rows, which changed the alignment requirements and fence programming.
2787 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2788 !(IS_I915G(dev_priv) || \
2789 IS_I915GM(dev_priv)))
2790 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2791 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2793 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2794 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2795 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2797 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2799 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2801 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2802 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2803 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2805 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2806 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2807 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2809 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2811 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2812 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2814 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2817 * For now, anything with a GuC requires uCode loading, and then supports
2818 * command submission once loaded. But these are logically independent
2819 * properties, so we have separate macros to test them.
2821 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2822 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2823 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2824 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2826 /* For now, anything with a GuC has also HuC */
2827 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2828 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2830 /* Having a GuC is not the same as using a GuC */
2831 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2832 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2833 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2835 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2837 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2839 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2840 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2841 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2842 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2843 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2844 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2845 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2846 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2847 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2848 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2849 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2850 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2851 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2852 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2853 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2854 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2855 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2857 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2858 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2859 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2860 #define HAS_PCH_CNP_LP(dev_priv) \
2861 ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2862 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2863 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2864 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2865 #define HAS_PCH_LPT_LP(dev_priv) \
2866 ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2867 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2868 #define HAS_PCH_LPT_H(dev_priv) \
2869 ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2870 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2871 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2872 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2873 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2874 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2876 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2878 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2880 /* DPF == dynamic parity feature */
2881 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2882 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2883 2 : HAS_L3_DPF(dev_priv))
2885 #define GT_FREQUENCY_MULTIPLIER 50
2886 #define GEN9_FREQ_SCALER 3
2888 #include "i915_trace.h"
2890 static inline bool intel_vtd_active(void)
2892 #ifdef CONFIG_INTEL_IOMMU
2893 if (intel_iommu_gfx_mapped)
2899 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2901 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2905 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2907 return IS_BROXTON(dev_priv) && intel_vtd_active();
2910 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2915 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2916 const char *fmt, ...);
2918 #define i915_report_error(dev_priv, fmt, ...) \
2919 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2921 #ifdef CONFIG_COMPAT
2922 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2925 #define i915_compat_ioctl NULL
2927 extern const struct dev_pm_ops i915_pm_ops;
2929 extern int i915_driver_load(struct pci_dev *pdev,
2930 const struct pci_device_id *ent);
2931 extern void i915_driver_unload(struct drm_device *dev);
2932 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2933 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2935 #define I915_RESET_QUIET BIT(0)
2936 extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
2937 extern int i915_reset_engine(struct intel_engine_cs *engine,
2938 unsigned int flags);
2940 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2941 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2942 extern int intel_guc_reset_engine(struct intel_guc *guc,
2943 struct intel_engine_cs *engine);
2944 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2945 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2946 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2947 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2948 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2949 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2950 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2952 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2953 int intel_engines_init(struct drm_i915_private *dev_priv);
2955 /* intel_hotplug.c */
2956 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2957 u32 pin_mask, u32 long_mask);
2958 void intel_hpd_init(struct drm_i915_private *dev_priv);
2959 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2960 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2961 enum port intel_hpd_pin_to_port(enum hpd_pin pin);
2962 enum hpd_pin intel_hpd_pin(enum port port);
2963 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2964 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2967 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2969 unsigned long delay;
2971 if (unlikely(!i915_modparams.enable_hangcheck))
2974 /* Don't continually defer the hangcheck so that it is always run at
2975 * least once after work has been scheduled on any ring. Otherwise,
2976 * we will ignore a hung ring if a second ring is kept busy.
2979 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2980 queue_delayed_work(system_long_wq,
2981 &dev_priv->gpu_error.hangcheck_work, delay);
2985 void i915_handle_error(struct drm_i915_private *dev_priv,
2987 const char *fmt, ...);
2989 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2990 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2991 int intel_irq_install(struct drm_i915_private *dev_priv);
2992 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2994 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2996 return dev_priv->gvt;
2999 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3001 return dev_priv->vgpu.active;
3004 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
3007 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3011 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3014 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3015 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3016 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3019 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3020 uint32_t interrupt_mask,
3021 uint32_t enabled_irq_mask);
3023 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3025 ilk_update_display_irq(dev_priv, bits, bits);
3028 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3030 ilk_update_display_irq(dev_priv, bits, 0);
3032 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3034 uint32_t interrupt_mask,
3035 uint32_t enabled_irq_mask);
3036 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3037 enum pipe pipe, uint32_t bits)
3039 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3041 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3042 enum pipe pipe, uint32_t bits)
3044 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3046 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3047 uint32_t interrupt_mask,
3048 uint32_t enabled_irq_mask);
3050 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3052 ibx_display_interrupt_update(dev_priv, bits, bits);
3055 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3057 ibx_display_interrupt_update(dev_priv, bits, 0);
3061 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3062 struct drm_file *file_priv);
3063 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3064 struct drm_file *file_priv);
3065 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3066 struct drm_file *file_priv);
3067 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3068 struct drm_file *file_priv);
3069 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3070 struct drm_file *file_priv);
3071 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3072 struct drm_file *file_priv);
3073 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3074 struct drm_file *file_priv);
3075 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3076 struct drm_file *file_priv);
3077 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3078 struct drm_file *file_priv);
3079 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3080 struct drm_file *file_priv);
3081 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3082 struct drm_file *file);
3083 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3084 struct drm_file *file);
3085 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3086 struct drm_file *file_priv);
3087 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3088 struct drm_file *file_priv);
3089 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
3090 struct drm_file *file_priv);
3091 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
3092 struct drm_file *file_priv);
3093 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3094 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3095 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3096 struct drm_file *file);
3097 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3098 struct drm_file *file_priv);
3099 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3100 struct drm_file *file_priv);
3101 void i915_gem_sanitize(struct drm_i915_private *i915);
3102 int i915_gem_load_init(struct drm_i915_private *dev_priv);
3103 void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3104 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3105 int i915_gem_freeze(struct drm_i915_private *dev_priv);
3106 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3108 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3109 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3110 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3111 const struct drm_i915_gem_object_ops *ops);
3112 struct drm_i915_gem_object *
3113 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
3114 struct drm_i915_gem_object *
3115 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
3116 const void *data, size_t size);
3117 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3118 void i915_gem_free_object(struct drm_gem_object *obj);
3120 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
3122 /* A single pass should suffice to release all the freed objects (along
3123 * most call paths) , but be a little more paranoid in that freeing
3124 * the objects does take a little amount of time, during which the rcu
3125 * callbacks could have added new objects into the freed list, and
3126 * armed the work again.
3130 } while (flush_work(&i915->mm.free_work));
3133 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
3136 * Similar to objects above (see i915_gem_drain_freed-objects), in
3137 * general we have workers that are armed by RCU and then rearm
3138 * themselves in their callbacks. To be paranoid, we need to
3139 * drain the workqueue a second time after waiting for the RCU
3140 * grace period so that we catch work queued via RCU from the first
3141 * pass. As neither drain_workqueue() nor flush_workqueue() report
3142 * a result, we make an assumption that we only don't require more
3143 * than 2 passes to catch all recursive RCU delayed work.
3149 drain_workqueue(i915->wq);
3153 struct i915_vma * __must_check
3154 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3155 const struct i915_ggtt_view *view,
3160 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3161 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3163 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
3165 static inline int __sg_page_count(const struct scatterlist *sg)
3167 return sg->length >> PAGE_SHIFT;
3170 struct scatterlist *
3171 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
3172 unsigned int n, unsigned int *offset);
3175 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
3179 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
3183 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
3186 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3187 struct sg_table *pages,
3188 unsigned int sg_page_sizes);
3189 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3191 static inline int __must_check
3192 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3194 might_lock(&obj->mm.lock);
3196 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
3199 return __i915_gem_object_get_pages(obj);
3203 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
3205 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
3209 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3211 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3213 atomic_inc(&obj->mm.pages_pin_count);
3217 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3219 return atomic_read(&obj->mm.pages_pin_count);
3223 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3225 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3226 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3228 atomic_dec(&obj->mm.pages_pin_count);
3232 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3234 __i915_gem_object_unpin_pages(obj);
3237 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3242 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3243 enum i915_mm_subclass subclass);
3244 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3246 enum i915_map_type {
3249 #define I915_MAP_OVERRIDE BIT(31)
3250 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3251 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3255 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3256 * @obj: the object to map into kernel address space
3257 * @type: the type of mapping, used to select pgprot_t
3259 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3260 * pages and then returns a contiguous mapping of the backing storage into
3261 * the kernel address space. Based on the @type of mapping, the PTE will be
3262 * set to either WriteBack or WriteCombine (via pgprot_t).
3264 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3265 * mapping is no longer required.
3267 * Returns the pointer through which to access the mapped object, or an
3268 * ERR_PTR() on error.
3270 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3271 enum i915_map_type type);
3274 * i915_gem_object_unpin_map - releases an earlier mapping
3275 * @obj: the object to unmap
3277 * After pinning the object and mapping its pages, once you are finished
3278 * with your access, call i915_gem_object_unpin_map() to release the pin
3279 * upon the mapping. Once the pin count reaches zero, that mapping may be
3282 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3284 i915_gem_object_unpin_pages(obj);
3287 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3288 unsigned int *needs_clflush);
3289 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3290 unsigned int *needs_clflush);
3291 #define CLFLUSH_BEFORE BIT(0)
3292 #define CLFLUSH_AFTER BIT(1)
3293 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3296 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3298 i915_gem_object_unpin_pages(obj);
3301 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3302 void i915_vma_move_to_active(struct i915_vma *vma,
3303 struct drm_i915_gem_request *req,
3304 unsigned int flags);
3305 int i915_gem_dumb_create(struct drm_file *file_priv,
3306 struct drm_device *dev,
3307 struct drm_mode_create_dumb *args);
3308 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3309 uint32_t handle, uint64_t *offset);
3310 int i915_gem_mmap_gtt_version(void);
3312 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3313 struct drm_i915_gem_object *new,
3314 unsigned frontbuffer_bits);
3316 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3318 struct drm_i915_gem_request *
3319 i915_gem_find_active_request(struct intel_engine_cs *engine);
3321 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3323 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3325 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3328 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3330 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3333 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3335 return unlikely(test_bit(I915_WEDGED, &error->flags));
3338 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3340 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3343 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3345 return READ_ONCE(error->reset_count);
3348 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3349 struct intel_engine_cs *engine)
3351 return READ_ONCE(error->reset_engine_count[engine->id]);
3354 struct drm_i915_gem_request *
3355 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3356 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3357 void i915_gem_reset(struct drm_i915_private *dev_priv);
3358 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3359 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3360 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3361 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3362 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3363 struct drm_i915_gem_request *request);
3365 void i915_gem_init_mmio(struct drm_i915_private *i915);
3366 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3367 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3368 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3369 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3370 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3371 unsigned int flags);
3372 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3373 void i915_gem_resume(struct drm_i915_private *dev_priv);
3374 int i915_gem_fault(struct vm_fault *vmf);
3375 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3378 struct intel_rps_client *rps);
3379 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3382 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3385 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3387 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3389 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3390 struct i915_vma * __must_check
3391 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3393 const struct i915_ggtt_view *view);
3394 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3395 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3397 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3398 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3400 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3401 enum i915_cache_level cache_level);
3403 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3404 struct dma_buf *dma_buf);
3406 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3407 struct drm_gem_object *gem_obj, int flags);
3409 static inline struct i915_hw_ppgtt *
3410 i915_vm_to_ppgtt(struct i915_address_space *vm)
3412 return container_of(vm, struct i915_hw_ppgtt, base);
3415 /* i915_gem_fence_reg.c */
3416 struct drm_i915_fence_reg *
3417 i915_reserve_fence(struct drm_i915_private *dev_priv);
3418 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3420 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3421 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3423 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3424 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3425 struct sg_table *pages);
3426 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3427 struct sg_table *pages);
3429 static inline struct i915_gem_context *
3430 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3432 return idr_find(&file_priv->context_idr, id);
3435 static inline struct i915_gem_context *
3436 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3438 struct i915_gem_context *ctx;
3441 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3442 if (ctx && !kref_get_unless_zero(&ctx->ref))
3449 static inline struct intel_timeline *
3450 i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
3451 struct intel_engine_cs *engine)
3453 struct i915_address_space *vm;
3455 vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
3456 return &vm->timeline.engine[engine->id];
3459 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3460 struct drm_file *file);
3461 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3462 struct drm_file *file);
3463 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3464 struct drm_file *file);
3465 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3466 struct i915_gem_context *ctx,
3467 uint32_t *reg_state);
3469 /* i915_gem_evict.c */
3470 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3471 u64 min_size, u64 alignment,
3472 unsigned cache_level,
3475 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3476 struct drm_mm_node *node,
3477 unsigned int flags);
3478 int i915_gem_evict_vm(struct i915_address_space *vm);
3480 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3482 /* belongs in i915_gem_gtt.h */
3483 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3486 if (INTEL_GEN(dev_priv) < 6)
3487 intel_gtt_chipset_flush();
3490 /* i915_gem_stolen.c */
3491 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3492 struct drm_mm_node *node, u64 size,
3493 unsigned alignment);
3494 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3495 struct drm_mm_node *node, u64 size,
3496 unsigned alignment, u64 start,
3498 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3499 struct drm_mm_node *node);
3500 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3501 void i915_gem_cleanup_stolen(struct drm_device *dev);
3502 struct drm_i915_gem_object *
3503 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3504 resource_size_t size);
3505 struct drm_i915_gem_object *
3506 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3507 resource_size_t stolen_offset,
3508 resource_size_t gtt_offset,
3509 resource_size_t size);
3511 /* i915_gem_internal.c */
3512 struct drm_i915_gem_object *
3513 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3516 /* i915_gem_shrinker.c */
3517 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3518 unsigned long target,
3519 unsigned long *nr_scanned,
3521 #define I915_SHRINK_PURGEABLE 0x1
3522 #define I915_SHRINK_UNBOUND 0x2
3523 #define I915_SHRINK_BOUND 0x4
3524 #define I915_SHRINK_ACTIVE 0x8
3525 #define I915_SHRINK_VMAPS 0x10
3526 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3527 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3528 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3531 /* i915_gem_tiling.c */
3532 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3534 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3536 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3537 i915_gem_object_is_tiled(obj);
3540 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3541 unsigned int tiling, unsigned int stride);
3542 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3543 unsigned int tiling, unsigned int stride);
3545 /* i915_debugfs.c */
3546 #ifdef CONFIG_DEBUG_FS
3547 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3548 int i915_debugfs_connector_add(struct drm_connector *connector);
3549 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3551 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3552 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3554 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3557 /* i915_gpu_error.c */
3558 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
3561 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3562 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3563 const struct i915_gpu_state *gpu);
3564 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3565 struct drm_i915_private *i915,
3566 size_t count, loff_t pos);
3567 static inline void i915_error_state_buf_release(
3568 struct drm_i915_error_state_buf *eb)
3573 struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3574 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3576 const char *error_msg);
3578 static inline struct i915_gpu_state *
3579 i915_gpu_state_get(struct i915_gpu_state *gpu)
3581 kref_get(&gpu->ref);
3585 void __i915_gpu_state_free(struct kref *kref);
3586 static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
3589 kref_put(&gpu->ref, __i915_gpu_state_free);
3592 struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
3593 void i915_reset_error_state(struct drm_i915_private *i915);
3597 static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
3599 const char *error_msg)
3603 static inline struct i915_gpu_state *
3604 i915_first_error_state(struct drm_i915_private *i915)
3609 static inline void i915_reset_error_state(struct drm_i915_private *i915)
3615 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3617 /* i915_cmd_parser.c */
3618 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3619 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3620 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3621 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3622 struct drm_i915_gem_object *batch_obj,
3623 struct drm_i915_gem_object *shadow_batch_obj,
3624 u32 batch_start_offset,
3629 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3630 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3631 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3632 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3634 /* i915_suspend.c */
3635 extern int i915_save_state(struct drm_i915_private *dev_priv);
3636 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3639 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3640 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3642 /* intel_lpe_audio.c */
3643 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3644 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3645 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3646 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3647 enum pipe pipe, enum port port,
3648 const void *eld, int ls_clock, bool dp_output);
3651 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3652 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3653 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3656 extern struct i2c_adapter *
3657 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3658 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3659 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3660 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3662 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3664 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3667 void intel_bios_init(struct drm_i915_private *dev_priv);
3668 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3669 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3670 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3671 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3672 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3673 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3674 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3675 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3677 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3682 extern void intel_register_dsm_handler(void);
3683 extern void intel_unregister_dsm_handler(void);
3685 static inline void intel_register_dsm_handler(void) { return; }
3686 static inline void intel_unregister_dsm_handler(void) { return; }
3687 #endif /* CONFIG_ACPI */
3689 /* intel_device_info.c */
3690 static inline struct intel_device_info *
3691 mkwrite_device_info(struct drm_i915_private *dev_priv)
3693 return (struct intel_device_info *)&dev_priv->info;
3697 extern void intel_modeset_init_hw(struct drm_device *dev);
3698 extern int intel_modeset_init(struct drm_device *dev);
3699 extern void intel_modeset_cleanup(struct drm_device *dev);
3700 extern int intel_connector_register(struct drm_connector *);
3701 extern void intel_connector_unregister(struct drm_connector *);
3702 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3704 extern void intel_display_resume(struct drm_device *dev);
3705 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3706 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3707 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3708 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3709 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3710 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3713 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3714 struct drm_file *file);
3717 extern struct intel_overlay_error_state *
3718 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3719 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3720 struct intel_overlay_error_state *error);
3722 extern struct intel_display_error_state *
3723 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3724 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3725 struct intel_display_error_state *error);
3727 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3728 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3729 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3730 u32 reply_mask, u32 reply, int timeout_base_ms);
3732 /* intel_sideband.c */
3733 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3734 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3735 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3736 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3737 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3738 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3739 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3740 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3741 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3742 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3743 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3744 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3745 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3746 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3747 enum intel_sbi_destination destination);
3748 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3749 enum intel_sbi_destination destination);
3750 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3751 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3753 /* intel_dpio_phy.c */
3754 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3755 enum dpio_phy *phy, enum dpio_channel *ch);
3756 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3757 enum port port, u32 margin, u32 scale,
3758 u32 enable, u32 deemphasis);
3759 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3760 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3761 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3763 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3765 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3766 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3767 uint8_t lane_lat_optim_mask);
3768 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3770 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3771 u32 deemph_reg_value, u32 margin_reg_value,
3772 bool uniq_trans_scale);
3773 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3774 const struct intel_crtc_state *crtc_state,
3776 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3777 const struct intel_crtc_state *crtc_state);
3778 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3779 const struct intel_crtc_state *crtc_state);
3780 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3781 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3782 const struct intel_crtc_state *old_crtc_state);
3784 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3785 u32 demph_reg_value, u32 preemph_reg_value,
3786 u32 uniqtranscale_reg_value, u32 tx3_demph);
3787 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3788 const struct intel_crtc_state *crtc_state);
3789 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3790 const struct intel_crtc_state *crtc_state);
3791 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3792 const struct intel_crtc_state *old_crtc_state);
3794 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3795 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3796 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3797 const i915_reg_t reg);
3799 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3801 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3802 const i915_reg_t reg)
3804 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3807 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3808 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3810 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3811 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3812 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3813 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3815 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3816 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3817 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3818 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3820 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3821 * will be implemented using 2 32-bit writes in an arbitrary order with
3822 * an arbitrary delay between them. This can cause the hardware to
3823 * act upon the intermediate value, possibly leading to corruption and
3824 * machine death. For this reason we do not support I915_WRITE64, or
3825 * dev_priv->uncore.funcs.mmio_writeq.
3827 * When reading a 64-bit value as two 32-bit values, the delay may cause
3828 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3829 * occasionally a 64-bit register does not actualy support a full readq
3830 * and must be read using two 32-bit reads.
3832 * You have been warned.
3834 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3836 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3837 u32 upper, lower, old_upper, loop = 0; \
3838 upper = I915_READ(upper_reg); \
3840 old_upper = upper; \
3841 lower = I915_READ(lower_reg); \
3842 upper = I915_READ(upper_reg); \
3843 } while (upper != old_upper && loop++ < 2); \
3844 (u64)upper << 32 | lower; })
3846 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3847 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3849 #define __raw_read(x, s) \
3850 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3853 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3856 #define __raw_write(x, s) \
3857 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3858 i915_reg_t reg, uint##x##_t val) \
3860 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3875 /* These are untraced mmio-accessors that are only valid to be used inside
3876 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3879 * Think twice, and think again, before using these.
3881 * As an example, these accessors can possibly be used between:
3883 * spin_lock_irq(&dev_priv->uncore.lock);
3884 * intel_uncore_forcewake_get__locked();
3888 * intel_uncore_forcewake_put__locked();
3889 * spin_unlock_irq(&dev_priv->uncore.lock);
3892 * Note: some registers may not need forcewake held, so
3893 * intel_uncore_forcewake_{get,put} can be omitted, see
3894 * intel_uncore_forcewake_for_reg().
3896 * Certain architectures will die if the same cacheline is concurrently accessed
3897 * by different clients (e.g. on Ivybridge). Access to registers should
3898 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3899 * a more localised lock guarding all access to that bank of registers.
3901 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3902 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3903 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3904 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3906 /* "Broadcast RGB" property */
3907 #define INTEL_BROADCAST_RGB_AUTO 0
3908 #define INTEL_BROADCAST_RGB_FULL 1
3909 #define INTEL_BROADCAST_RGB_LIMITED 2
3911 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3913 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3914 return VLV_VGACNTRL;
3915 else if (INTEL_GEN(dev_priv) >= 5)
3916 return CPU_VGACNTRL;
3921 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3923 unsigned long j = msecs_to_jiffies(m);
3925 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3928 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3930 /* nsecs_to_jiffies64() does not guard against overflow */
3931 if (NSEC_PER_SEC % HZ &&
3932 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3933 return MAX_JIFFY_OFFSET;
3935 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3938 static inline unsigned long
3939 timespec_to_jiffies_timeout(const struct timespec *value)
3941 unsigned long j = timespec_to_jiffies(value);
3943 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3947 * If you need to wait X milliseconds between events A and B, but event B
3948 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3949 * when event A happened, then just before event B you call this function and
3950 * pass the timestamp as the first argument, and X as the second argument.
3953 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3955 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3958 * Don't re-read the value of "jiffies" every time since it may change
3959 * behind our back and break the math.
3961 tmp_jiffies = jiffies;
3962 target_jiffies = timestamp_jiffies +
3963 msecs_to_jiffies_timeout(to_wait_ms);
3965 if (time_after(target_jiffies, tmp_jiffies)) {
3966 remaining_jiffies = target_jiffies - tmp_jiffies;
3967 while (remaining_jiffies)
3969 schedule_timeout_uninterruptible(remaining_jiffies);
3974 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
3976 struct intel_engine_cs *engine = req->engine;
3979 /* Note that the engine may have wrapped around the seqno, and
3980 * so our request->global_seqno will be ahead of the hardware,
3981 * even though it completed the request before wrapping. We catch
3982 * this by kicking all the waiters before resetting the seqno
3983 * in hardware, and also signal the fence.
3985 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
3988 /* The request was dequeued before we were awoken. We check after
3989 * inspecting the hw to confirm that this was the same request
3990 * that generated the HWS update. The memory barriers within
3991 * the request execution are sufficient to ensure that a check
3992 * after reading the value from hw matches this request.
3994 seqno = i915_gem_request_global_seqno(req);
3998 /* Before we do the heavier coherent read of the seqno,
3999 * check the value (hopefully) in the CPU cacheline.
4001 if (__i915_gem_request_completed(req, seqno))
4004 /* Ensure our read of the seqno is coherent so that we
4005 * do not "miss an interrupt" (i.e. if this is the last
4006 * request and the seqno write from the GPU is not visible
4007 * by the time the interrupt fires, we will see that the
4008 * request is incomplete and go back to sleep awaiting
4009 * another interrupt that will never come.)
4011 * Strictly, we only need to do this once after an interrupt,
4012 * but it is easier and safer to do it every time the waiter
4015 if (engine->irq_seqno_barrier &&
4016 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4017 struct intel_breadcrumbs *b = &engine->breadcrumbs;
4019 /* The ordering of irq_posted versus applying the barrier
4020 * is crucial. The clearing of the current irq_posted must
4021 * be visible before we perform the barrier operation,
4022 * such that if a subsequent interrupt arrives, irq_posted
4023 * is reasserted and our task rewoken (which causes us to
4024 * do another __i915_request_irq_complete() immediately
4025 * and reapply the barrier). Conversely, if the clear
4026 * occurs after the barrier, then an interrupt that arrived
4027 * whilst we waited on the barrier would not trigger a
4028 * barrier on the next pass, and the read may not see the
4031 engine->irq_seqno_barrier(engine);
4033 /* If we consume the irq, but we are no longer the bottom-half,
4034 * the real bottom-half may not have serialised their own
4035 * seqno check with the irq-barrier (i.e. may have inspected
4036 * the seqno before we believe it coherent since they see
4037 * irq_posted == false but we are still running).
4039 spin_lock_irq(&b->irq_lock);
4040 if (b->irq_wait && b->irq_wait->tsk != current)
4041 /* Note that if the bottom-half is changed as we
4042 * are sending the wake-up, the new bottom-half will
4043 * be woken by whomever made the change. We only have
4044 * to worry about when we steal the irq-posted for
4047 wake_up_process(b->irq_wait->tsk);
4048 spin_unlock_irq(&b->irq_lock);
4050 if (__i915_gem_request_completed(req, seqno))
4057 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
4058 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
4060 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
4061 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
4062 * perform the operation. To check beforehand, pass in the parameters to
4063 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
4064 * you only need to pass in the minor offsets, page-aligned pointers are
4067 * For just checking for SSE4.1, in the foreknowledge that the future use
4068 * will be correctly aligned, just use i915_has_memcpy_from_wc().
4070 #define i915_can_memcpy_from_wc(dst, src, len) \
4071 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
4073 #define i915_has_memcpy_from_wc() \
4074 i915_memcpy_from_wc(NULL, NULL, 0)
4077 int remap_io_mapping(struct vm_area_struct *vma,
4078 unsigned long addr, unsigned long pfn, unsigned long size,
4079 struct io_mapping *iomap);
4081 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
4083 if (INTEL_GEN(i915) >= 10)
4084 return CNL_HWS_CSB_WRITE_INDEX;
4086 return I915_HWS_CSB_WRITE_INDEX;