Merge tag 'drm-misc-next-2019-03-21' of git://anongit.freedesktop.org/drm/drm-misc...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
35
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48 #include <linux/stackdepot.h>
49
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55 #include <drm/drm_util.h>
56 #include <drm/drm_dsc.h>
57 #include <drm/drm_connector.h>
58
59 #include "i915_fixed.h"
60 #include "i915_params.h"
61 #include "i915_reg.h"
62 #include "i915_utils.h"
63
64 #include "intel_bios.h"
65 #include "intel_device_info.h"
66 #include "intel_display.h"
67 #include "intel_dpll_mgr.h"
68 #include "intel_lrc.h"
69 #include "intel_opregion.h"
70 #include "intel_ringbuffer.h"
71 #include "intel_uncore.h"
72 #include "intel_wopcm.h"
73 #include "intel_workarounds.h"
74 #include "intel_uc.h"
75
76 #include "i915_gem.h"
77 #include "i915_gem_context.h"
78 #include "i915_gem_fence_reg.h"
79 #include "i915_gem_object.h"
80 #include "i915_gem_gtt.h"
81 #include "i915_gpu_error.h"
82 #include "i915_request.h"
83 #include "i915_scheduler.h"
84 #include "i915_timeline.h"
85 #include "i915_vma.h"
86
87 #include "intel_gvt.h"
88
89 /* General customization:
90  */
91
92 #define DRIVER_NAME             "i915"
93 #define DRIVER_DESC             "Intel Graphics"
94 #define DRIVER_DATE             "20190207"
95 #define DRIVER_TIMESTAMP        1549572331
96
97 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
98  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
99  * which may not necessarily be a user visible problem.  This will either
100  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
101  * enable distros and users to tailor their preferred amount of i915 abrt
102  * spam.
103  */
104 #define I915_STATE_WARN(condition, format...) ({                        \
105         int __ret_warn_on = !!(condition);                              \
106         if (unlikely(__ret_warn_on))                                    \
107                 if (!WARN(i915_modparams.verbose_state_checks, format)) \
108                         DRM_ERROR(format);                              \
109         unlikely(__ret_warn_on);                                        \
110 })
111
112 #define I915_STATE_WARN_ON(x)                                           \
113         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
114
115 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
116
117 bool __i915_inject_load_failure(const char *func, int line);
118 #define i915_inject_load_failure() \
119         __i915_inject_load_failure(__func__, __LINE__)
120
121 bool i915_error_injected(void);
122
123 #else
124
125 #define i915_inject_load_failure() false
126 #define i915_error_injected() false
127
128 #endif
129
130 #define i915_load_error(i915, fmt, ...)                                  \
131         __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
132                       fmt, ##__VA_ARGS__)
133
134 typedef depot_stack_handle_t intel_wakeref_t;
135
136 enum hpd_pin {
137         HPD_NONE = 0,
138         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
139         HPD_CRT,
140         HPD_SDVO_B,
141         HPD_SDVO_C,
142         HPD_PORT_A,
143         HPD_PORT_B,
144         HPD_PORT_C,
145         HPD_PORT_D,
146         HPD_PORT_E,
147         HPD_PORT_F,
148         HPD_NUM_PINS
149 };
150
151 #define for_each_hpd_pin(__pin) \
152         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
153
154 /* Threshold == 5 for long IRQs, 50 for short */
155 #define HPD_STORM_DEFAULT_THRESHOLD 50
156
157 struct i915_hotplug {
158         struct work_struct hotplug_work;
159
160         struct {
161                 unsigned long last_jiffies;
162                 int count;
163                 enum {
164                         HPD_ENABLED = 0,
165                         HPD_DISABLED = 1,
166                         HPD_MARK_DISABLED = 2
167                 } state;
168         } stats[HPD_NUM_PINS];
169         u32 event_bits;
170         struct delayed_work reenable_work;
171
172         u32 long_port_mask;
173         u32 short_port_mask;
174         struct work_struct dig_port_work;
175
176         struct work_struct poll_init_work;
177         bool poll_enabled;
178
179         unsigned int hpd_storm_threshold;
180         /* Whether or not to count short HPD IRQs in HPD storms */
181         u8 hpd_short_storm_enabled;
182
183         /*
184          * if we get a HPD irq from DP and a HPD irq from non-DP
185          * the non-DP HPD could block the workqueue on a mode config
186          * mutex getting, that userspace may have taken. However
187          * userspace is waiting on the DP workqueue to run which is
188          * blocked behind the non-DP one.
189          */
190         struct workqueue_struct *dp_wq;
191 };
192
193 #define I915_GEM_GPU_DOMAINS \
194         (I915_GEM_DOMAIN_RENDER | \
195          I915_GEM_DOMAIN_SAMPLER | \
196          I915_GEM_DOMAIN_COMMAND | \
197          I915_GEM_DOMAIN_INSTRUCTION | \
198          I915_GEM_DOMAIN_VERTEX)
199
200 struct drm_i915_private;
201 struct i915_mm_struct;
202 struct i915_mmu_object;
203
204 struct drm_i915_file_private {
205         struct drm_i915_private *dev_priv;
206         struct drm_file *file;
207
208         struct {
209                 spinlock_t lock;
210                 struct list_head request_list;
211 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
212  * chosen to prevent the CPU getting more than a frame ahead of the GPU
213  * (when using lax throttling for the frontbuffer). We also use it to
214  * offer free GPU waitboosts for severely congested workloads.
215  */
216 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
217         } mm;
218         struct idr context_idr;
219
220         struct intel_rps_client {
221                 atomic_t boosts;
222         } rps_client;
223
224         unsigned int bsd_engine;
225
226 /*
227  * Every context ban increments per client ban score. Also
228  * hangs in short succession increments ban score. If ban threshold
229  * is reached, client is considered banned and submitting more work
230  * will fail. This is a stop gap measure to limit the badly behaving
231  * clients access to gpu. Note that unbannable contexts never increment
232  * the client ban score.
233  */
234 #define I915_CLIENT_SCORE_HANG_FAST     1
235 #define   I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
236 #define I915_CLIENT_SCORE_CONTEXT_BAN   3
237 #define I915_CLIENT_SCORE_BANNED        9
238         /** ban_score: Accumulated score of all ctx bans and fast hangs. */
239         atomic_t ban_score;
240         unsigned long hang_timestamp;
241 };
242
243 /* Interface history:
244  *
245  * 1.1: Original.
246  * 1.2: Add Power Management
247  * 1.3: Add vblank support
248  * 1.4: Fix cmdbuffer path, add heap destroy
249  * 1.5: Add vblank pipe configuration
250  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
251  *      - Support vertical blank on secondary display pipe
252  */
253 #define DRIVER_MAJOR            1
254 #define DRIVER_MINOR            6
255 #define DRIVER_PATCHLEVEL       0
256
257 struct intel_overlay;
258 struct intel_overlay_error_state;
259
260 struct sdvo_device_mapping {
261         u8 initialized;
262         u8 dvo_port;
263         u8 slave_addr;
264         u8 dvo_wiring;
265         u8 i2c_pin;
266         u8 ddc_pin;
267 };
268
269 struct intel_connector;
270 struct intel_encoder;
271 struct intel_atomic_state;
272 struct intel_crtc_state;
273 struct intel_initial_plane_config;
274 struct intel_crtc;
275 struct intel_limit;
276 struct dpll;
277 struct intel_cdclk_state;
278
279 struct drm_i915_display_funcs {
280         void (*get_cdclk)(struct drm_i915_private *dev_priv,
281                           struct intel_cdclk_state *cdclk_state);
282         void (*set_cdclk)(struct drm_i915_private *dev_priv,
283                           const struct intel_cdclk_state *cdclk_state);
284         int (*get_fifo_size)(struct drm_i915_private *dev_priv,
285                              enum i9xx_plane_id i9xx_plane);
286         int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
287         int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
288         void (*initial_watermarks)(struct intel_atomic_state *state,
289                                    struct intel_crtc_state *cstate);
290         void (*atomic_update_watermarks)(struct intel_atomic_state *state,
291                                          struct intel_crtc_state *cstate);
292         void (*optimize_watermarks)(struct intel_atomic_state *state,
293                                     struct intel_crtc_state *cstate);
294         int (*compute_global_watermarks)(struct intel_atomic_state *state);
295         void (*update_wm)(struct intel_crtc *crtc);
296         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
297         /* Returns the active state of the crtc, and if the crtc is active,
298          * fills out the pipe-config with the hw state. */
299         bool (*get_pipe_config)(struct intel_crtc *,
300                                 struct intel_crtc_state *);
301         void (*get_initial_plane_config)(struct intel_crtc *,
302                                          struct intel_initial_plane_config *);
303         int (*crtc_compute_clock)(struct intel_crtc *crtc,
304                                   struct intel_crtc_state *crtc_state);
305         void (*crtc_enable)(struct intel_crtc_state *pipe_config,
306                             struct drm_atomic_state *old_state);
307         void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
308                              struct drm_atomic_state *old_state);
309         void (*update_crtcs)(struct drm_atomic_state *state);
310         void (*audio_codec_enable)(struct intel_encoder *encoder,
311                                    const struct intel_crtc_state *crtc_state,
312                                    const struct drm_connector_state *conn_state);
313         void (*audio_codec_disable)(struct intel_encoder *encoder,
314                                     const struct intel_crtc_state *old_crtc_state,
315                                     const struct drm_connector_state *old_conn_state);
316         void (*fdi_link_train)(struct intel_crtc *crtc,
317                                const struct intel_crtc_state *crtc_state);
318         void (*init_clock_gating)(struct drm_i915_private *dev_priv);
319         void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
320         /* clock updates for mode set */
321         /* cursor updates */
322         /* render clock increase/decrease */
323         /* display clock increase/decrease */
324         /* pll clock increase/decrease */
325
326         /*
327          * Program double buffered color management registers during
328          * vblank evasion. The registers should then latch during the
329          * next vblank start, alongside any other double buffered registers
330          * involved with the same commit.
331          */
332         void (*color_commit)(const struct intel_crtc_state *crtc_state);
333         /*
334          * Load LUTs (and other single buffered color management
335          * registers). Will (hopefully) be called during the vblank
336          * following the latching of any double buffered registers
337          * involved with the same commit.
338          */
339         void (*load_luts)(const struct intel_crtc_state *crtc_state);
340 };
341
342 #define CSR_VERSION(major, minor)       ((major) << 16 | (minor))
343 #define CSR_VERSION_MAJOR(version)      ((version) >> 16)
344 #define CSR_VERSION_MINOR(version)      ((version) & 0xffff)
345
346 struct intel_csr {
347         struct work_struct work;
348         const char *fw_path;
349         u32 required_version;
350         u32 max_fw_size; /* bytes */
351         u32 *dmc_payload;
352         u32 dmc_fw_size; /* dwords */
353         u32 version;
354         u32 mmio_count;
355         i915_reg_t mmioaddr[8];
356         u32 mmiodata[8];
357         u32 dc_state;
358         u32 allowed_dc_mask;
359         intel_wakeref_t wakeref;
360 };
361
362 enum i915_cache_level {
363         I915_CACHE_NONE = 0,
364         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
365         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
366                               caches, eg sampler/render caches, and the
367                               large Last-Level-Cache. LLC is coherent with
368                               the CPU, but L3 is only visible to the GPU. */
369         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
370 };
371
372 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
373
374 enum fb_op_origin {
375         ORIGIN_GTT,
376         ORIGIN_CPU,
377         ORIGIN_CS,
378         ORIGIN_FLIP,
379         ORIGIN_DIRTYFB,
380 };
381
382 struct intel_fbc {
383         /* This is always the inner lock when overlapping with struct_mutex and
384          * it's the outer lock when overlapping with stolen_lock. */
385         struct mutex lock;
386         unsigned threshold;
387         unsigned int possible_framebuffer_bits;
388         unsigned int busy_bits;
389         unsigned int visible_pipes_mask;
390         struct intel_crtc *crtc;
391
392         struct drm_mm_node compressed_fb;
393         struct drm_mm_node *compressed_llb;
394
395         bool false_color;
396
397         bool enabled;
398         bool active;
399         bool flip_pending;
400
401         bool underrun_detected;
402         struct work_struct underrun_work;
403
404         /*
405          * Due to the atomic rules we can't access some structures without the
406          * appropriate locking, so we cache information here in order to avoid
407          * these problems.
408          */
409         struct intel_fbc_state_cache {
410                 struct i915_vma *vma;
411                 unsigned long flags;
412
413                 struct {
414                         unsigned int mode_flags;
415                         u32 hsw_bdw_pixel_rate;
416                 } crtc;
417
418                 struct {
419                         unsigned int rotation;
420                         int src_w;
421                         int src_h;
422                         bool visible;
423                         /*
424                          * Display surface base address adjustement for
425                          * pageflips. Note that on gen4+ this only adjusts up
426                          * to a tile, offsets within a tile are handled in
427                          * the hw itself (with the TILEOFF register).
428                          */
429                         int adjusted_x;
430                         int adjusted_y;
431
432                         int y;
433
434                         u16 pixel_blend_mode;
435                 } plane;
436
437                 struct {
438                         const struct drm_format_info *format;
439                         unsigned int stride;
440                 } fb;
441         } state_cache;
442
443         /*
444          * This structure contains everything that's relevant to program the
445          * hardware registers. When we want to figure out if we need to disable
446          * and re-enable FBC for a new configuration we just check if there's
447          * something different in the struct. The genx_fbc_activate functions
448          * are supposed to read from it in order to program the registers.
449          */
450         struct intel_fbc_reg_params {
451                 struct i915_vma *vma;
452                 unsigned long flags;
453
454                 struct {
455                         enum pipe pipe;
456                         enum i9xx_plane_id i9xx_plane;
457                         unsigned int fence_y_offset;
458                 } crtc;
459
460                 struct {
461                         const struct drm_format_info *format;
462                         unsigned int stride;
463                 } fb;
464
465                 int cfb_size;
466                 unsigned int gen9_wa_cfb_stride;
467         } params;
468
469         const char *no_fbc_reason;
470 };
471
472 /*
473  * HIGH_RR is the highest eDP panel refresh rate read from EDID
474  * LOW_RR is the lowest eDP panel refresh rate found from EDID
475  * parsing for same resolution.
476  */
477 enum drrs_refresh_rate_type {
478         DRRS_HIGH_RR,
479         DRRS_LOW_RR,
480         DRRS_MAX_RR, /* RR count */
481 };
482
483 enum drrs_support_type {
484         DRRS_NOT_SUPPORTED = 0,
485         STATIC_DRRS_SUPPORT = 1,
486         SEAMLESS_DRRS_SUPPORT = 2
487 };
488
489 struct intel_dp;
490 struct i915_drrs {
491         struct mutex mutex;
492         struct delayed_work work;
493         struct intel_dp *dp;
494         unsigned busy_frontbuffer_bits;
495         enum drrs_refresh_rate_type refresh_rate_type;
496         enum drrs_support_type type;
497 };
498
499 struct i915_psr {
500         struct mutex lock;
501
502 #define I915_PSR_DEBUG_MODE_MASK        0x0f
503 #define I915_PSR_DEBUG_DEFAULT          0x00
504 #define I915_PSR_DEBUG_DISABLE          0x01
505 #define I915_PSR_DEBUG_ENABLE           0x02
506 #define I915_PSR_DEBUG_FORCE_PSR1       0x03
507 #define I915_PSR_DEBUG_IRQ              0x10
508
509         u32 debug;
510         bool sink_support;
511         bool prepared, enabled;
512         struct intel_dp *dp;
513         enum pipe pipe;
514         bool active;
515         struct work_struct work;
516         unsigned busy_frontbuffer_bits;
517         bool sink_psr2_support;
518         bool link_standby;
519         bool colorimetry_support;
520         bool psr2_enabled;
521         u8 sink_sync_latency;
522         ktime_t last_entry_attempt;
523         ktime_t last_exit;
524         bool sink_not_reliable;
525         bool irq_aux_error;
526         u16 su_x_granularity;
527 };
528
529 enum intel_pch {
530         PCH_NONE = 0,   /* No PCH present */
531         PCH_IBX,        /* Ibexpeak PCH */
532         PCH_CPT,        /* Cougarpoint/Pantherpoint PCH */
533         PCH_LPT,        /* Lynxpoint/Wildcatpoint PCH */
534         PCH_SPT,        /* Sunrisepoint PCH */
535         PCH_KBP,        /* Kaby Lake PCH */
536         PCH_CNP,        /* Cannon Lake PCH */
537         PCH_ICP,        /* Ice Lake PCH */
538         PCH_NOP,        /* PCH without south display */
539 };
540
541 enum intel_sbi_destination {
542         SBI_ICLK,
543         SBI_MPHY,
544 };
545
546 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
547 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
548 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
549 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
550 #define QUIRK_INCREASE_T12_DELAY (1<<6)
551 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
552
553 struct intel_fbdev;
554 struct intel_fbc_work;
555
556 struct intel_gmbus {
557         struct i2c_adapter adapter;
558 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
559         u32 force_bit;
560         u32 reg0;
561         i915_reg_t gpio_reg;
562         struct i2c_algo_bit_data bit_algo;
563         struct drm_i915_private *dev_priv;
564 };
565
566 struct i915_suspend_saved_registers {
567         u32 saveDSPARB;
568         u32 saveFBC_CONTROL;
569         u32 saveCACHE_MODE_0;
570         u32 saveMI_ARB_STATE;
571         u32 saveSWF0[16];
572         u32 saveSWF1[16];
573         u32 saveSWF3[3];
574         u64 saveFENCE[I915_MAX_NUM_FENCES];
575         u32 savePCH_PORT_HOTPLUG;
576         u16 saveGCDGMBUS;
577 };
578
579 struct vlv_s0ix_state {
580         /* GAM */
581         u32 wr_watermark;
582         u32 gfx_prio_ctrl;
583         u32 arb_mode;
584         u32 gfx_pend_tlb0;
585         u32 gfx_pend_tlb1;
586         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
587         u32 media_max_req_count;
588         u32 gfx_max_req_count;
589         u32 render_hwsp;
590         u32 ecochk;
591         u32 bsd_hwsp;
592         u32 blt_hwsp;
593         u32 tlb_rd_addr;
594
595         /* MBC */
596         u32 g3dctl;
597         u32 gsckgctl;
598         u32 mbctl;
599
600         /* GCP */
601         u32 ucgctl1;
602         u32 ucgctl3;
603         u32 rcgctl1;
604         u32 rcgctl2;
605         u32 rstctl;
606         u32 misccpctl;
607
608         /* GPM */
609         u32 gfxpause;
610         u32 rpdeuhwtc;
611         u32 rpdeuc;
612         u32 ecobus;
613         u32 pwrdwnupctl;
614         u32 rp_down_timeout;
615         u32 rp_deucsw;
616         u32 rcubmabdtmr;
617         u32 rcedata;
618         u32 spare2gh;
619
620         /* Display 1 CZ domain */
621         u32 gt_imr;
622         u32 gt_ier;
623         u32 pm_imr;
624         u32 pm_ier;
625         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
626
627         /* GT SA CZ domain */
628         u32 tilectl;
629         u32 gt_fifoctl;
630         u32 gtlc_wake_ctrl;
631         u32 gtlc_survive;
632         u32 pmwgicz;
633
634         /* Display 2 CZ domain */
635         u32 gu_ctl0;
636         u32 gu_ctl1;
637         u32 pcbr;
638         u32 clock_gate_dis2;
639 };
640
641 struct intel_rps_ei {
642         ktime_t ktime;
643         u32 render_c0;
644         u32 media_c0;
645 };
646
647 struct intel_rps {
648         /*
649          * work, interrupts_enabled and pm_iir are protected by
650          * dev_priv->irq_lock
651          */
652         struct work_struct work;
653         bool interrupts_enabled;
654         u32 pm_iir;
655
656         /* PM interrupt bits that should never be masked */
657         u32 pm_intrmsk_mbz;
658
659         /* Frequencies are stored in potentially platform dependent multiples.
660          * In other words, *_freq needs to be multiplied by X to be interesting.
661          * Soft limits are those which are used for the dynamic reclocking done
662          * by the driver (raise frequencies under heavy loads, and lower for
663          * lighter loads). Hard limits are those imposed by the hardware.
664          *
665          * A distinction is made for overclocking, which is never enabled by
666          * default, and is considered to be above the hard limit if it's
667          * possible at all.
668          */
669         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
670         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
671         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
672         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
673         u8 min_freq;            /* AKA RPn. Minimum frequency */
674         u8 boost_freq;          /* Frequency to request when wait boosting */
675         u8 idle_freq;           /* Frequency to request when we are idle */
676         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
677         u8 rp1_freq;            /* "less than" RP0 power/freqency */
678         u8 rp0_freq;            /* Non-overclocked max frequency. */
679         u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
680
681         int last_adj;
682
683         struct {
684                 struct mutex mutex;
685
686                 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
687                 unsigned int interactive;
688
689                 u8 up_threshold; /* Current %busy required to uplock */
690                 u8 down_threshold; /* Current %busy required to downclock */
691         } power;
692
693         bool enabled;
694         atomic_t num_waiters;
695         atomic_t boosts;
696
697         /* manual wa residency calculations */
698         struct intel_rps_ei ei;
699 };
700
701 struct intel_rc6 {
702         bool enabled;
703         u64 prev_hw_residency[4];
704         u64 cur_residency[4];
705 };
706
707 struct intel_llc_pstate {
708         bool enabled;
709 };
710
711 struct intel_gen6_power_mgmt {
712         struct intel_rps rps;
713         struct intel_rc6 rc6;
714         struct intel_llc_pstate llc_pstate;
715 };
716
717 /* defined intel_pm.c */
718 extern spinlock_t mchdev_lock;
719
720 struct intel_ilk_power_mgmt {
721         u8 cur_delay;
722         u8 min_delay;
723         u8 max_delay;
724         u8 fmax;
725         u8 fstart;
726
727         u64 last_count1;
728         unsigned long last_time1;
729         unsigned long chipset_power;
730         u64 last_count2;
731         u64 last_time2;
732         unsigned long gfx_power;
733         u8 corr;
734
735         int c_m;
736         int r_t;
737 };
738
739 struct drm_i915_private;
740 struct i915_power_well;
741
742 struct i915_power_well_ops {
743         /*
744          * Synchronize the well's hw state to match the current sw state, for
745          * example enable/disable it based on the current refcount. Called
746          * during driver init and resume time, possibly after first calling
747          * the enable/disable handlers.
748          */
749         void (*sync_hw)(struct drm_i915_private *dev_priv,
750                         struct i915_power_well *power_well);
751         /*
752          * Enable the well and resources that depend on it (for example
753          * interrupts located on the well). Called after the 0->1 refcount
754          * transition.
755          */
756         void (*enable)(struct drm_i915_private *dev_priv,
757                        struct i915_power_well *power_well);
758         /*
759          * Disable the well and resources that depend on it. Called after
760          * the 1->0 refcount transition.
761          */
762         void (*disable)(struct drm_i915_private *dev_priv,
763                         struct i915_power_well *power_well);
764         /* Returns the hw enabled state. */
765         bool (*is_enabled)(struct drm_i915_private *dev_priv,
766                            struct i915_power_well *power_well);
767 };
768
769 struct i915_power_well_regs {
770         i915_reg_t bios;
771         i915_reg_t driver;
772         i915_reg_t kvmr;
773         i915_reg_t debug;
774 };
775
776 /* Power well structure for haswell */
777 struct i915_power_well_desc {
778         const char *name;
779         bool always_on;
780         u64 domains;
781         /* unique identifier for this power well */
782         enum i915_power_well_id id;
783         /*
784          * Arbitraty data associated with this power well. Platform and power
785          * well specific.
786          */
787         union {
788                 struct {
789                         /*
790                          * request/status flag index in the PUNIT power well
791                          * control/status registers.
792                          */
793                         u8 idx;
794                 } vlv;
795                 struct {
796                         enum dpio_phy phy;
797                 } bxt;
798                 struct {
799                         const struct i915_power_well_regs *regs;
800                         /*
801                          * request/status flag index in the power well
802                          * constrol/status registers.
803                          */
804                         u8 idx;
805                         /* Mask of pipes whose IRQ logic is backed by the pw */
806                         u8 irq_pipe_mask;
807                         /* The pw is backing the VGA functionality */
808                         bool has_vga:1;
809                         bool has_fuses:1;
810                         /*
811                          * The pw is for an ICL+ TypeC PHY port in
812                          * Thunderbolt mode.
813                          */
814                         bool is_tc_tbt:1;
815                 } hsw;
816         };
817         const struct i915_power_well_ops *ops;
818 };
819
820 struct i915_power_well {
821         const struct i915_power_well_desc *desc;
822         /* power well enable/disable usage count */
823         int count;
824         /* cached hw enabled state */
825         bool hw_enabled;
826 };
827
828 struct i915_power_domains {
829         /*
830          * Power wells needed for initialization at driver init and suspend
831          * time are on. They are kept on until after the first modeset.
832          */
833         bool initializing;
834         bool display_core_suspended;
835         int power_well_count;
836
837         intel_wakeref_t wakeref;
838
839         struct mutex lock;
840         int domain_use_count[POWER_DOMAIN_NUM];
841         struct i915_power_well *power_wells;
842 };
843
844 #define MAX_L3_SLICES 2
845 struct intel_l3_parity {
846         u32 *remap_info[MAX_L3_SLICES];
847         struct work_struct error_work;
848         int which_slice;
849 };
850
851 struct i915_gem_mm {
852         /** Memory allocator for GTT stolen memory */
853         struct drm_mm stolen;
854         /** Protects the usage of the GTT stolen memory allocator. This is
855          * always the inner lock when overlapping with struct_mutex. */
856         struct mutex stolen_lock;
857
858         /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
859         spinlock_t obj_lock;
860
861         /** List of all objects in gtt_space. Used to restore gtt
862          * mappings on resume */
863         struct list_head bound_list;
864         /**
865          * List of objects which are not bound to the GTT (thus
866          * are idle and not used by the GPU). These objects may or may
867          * not actually have any pages attached.
868          */
869         struct list_head unbound_list;
870
871         /** List of all objects in gtt_space, currently mmaped by userspace.
872          * All objects within this list must also be on bound_list.
873          */
874         struct list_head userfault_list;
875
876         /**
877          * List of objects which are pending destruction.
878          */
879         struct llist_head free_list;
880         struct work_struct free_work;
881         spinlock_t free_lock;
882         /**
883          * Count of objects pending destructions. Used to skip needlessly
884          * waiting on an RCU barrier if no objects are waiting to be freed.
885          */
886         atomic_t free_count;
887
888         /**
889          * Small stash of WC pages
890          */
891         struct pagestash wc_stash;
892
893         /**
894          * tmpfs instance used for shmem backed objects
895          */
896         struct vfsmount *gemfs;
897
898         /** PPGTT used for aliasing the PPGTT with the GTT */
899         struct i915_hw_ppgtt *aliasing_ppgtt;
900
901         struct notifier_block oom_notifier;
902         struct notifier_block vmap_notifier;
903         struct shrinker shrinker;
904
905         /** LRU list of objects with fence regs on them. */
906         struct list_head fence_list;
907
908         /**
909          * Workqueue to fault in userptr pages, flushed by the execbuf
910          * when required but otherwise left to userspace to try again
911          * on EAGAIN.
912          */
913         struct workqueue_struct *userptr_wq;
914
915         u64 unordered_timeline;
916
917         /* the indicator for dispatch video commands on two BSD rings */
918         atomic_t bsd_engine_dispatch_index;
919
920         /** Bit 6 swizzling required for X tiling */
921         u32 bit_6_swizzle_x;
922         /** Bit 6 swizzling required for Y tiling */
923         u32 bit_6_swizzle_y;
924
925         /* accounting, useful for userland debugging */
926         spinlock_t object_stat_lock;
927         u64 object_memory;
928         u32 object_count;
929 };
930
931 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
932
933 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
934 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
935
936 #define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
937 #define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */
938
939 #define I915_ENGINE_WEDGED_TIMEOUT  (60 * HZ)  /* Reset but no recovery? */
940
941 struct ddi_vbt_port_info {
942         int max_tmds_clock;
943
944         /*
945          * This is an index in the HDMI/DVI DDI buffer translation table.
946          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
947          * populate this field.
948          */
949 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
950         u8 hdmi_level_shift;
951
952         u8 supports_dvi:1;
953         u8 supports_hdmi:1;
954         u8 supports_dp:1;
955         u8 supports_edp:1;
956         u8 supports_typec_usb:1;
957         u8 supports_tbt:1;
958
959         u8 alternate_aux_channel;
960         u8 alternate_ddc_pin;
961
962         u8 dp_boost_level;
963         u8 hdmi_boost_level;
964         int dp_max_link_rate;           /* 0 for not limited by VBT */
965 };
966
967 enum psr_lines_to_wait {
968         PSR_0_LINES_TO_WAIT = 0,
969         PSR_1_LINE_TO_WAIT,
970         PSR_4_LINES_TO_WAIT,
971         PSR_8_LINES_TO_WAIT
972 };
973
974 struct intel_vbt_data {
975         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
976         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
977
978         /* Feature bits */
979         unsigned int int_tv_support:1;
980         unsigned int lvds_dither:1;
981         unsigned int int_crt_support:1;
982         unsigned int lvds_use_ssc:1;
983         unsigned int int_lvds_support:1;
984         unsigned int display_clock_mode:1;
985         unsigned int fdi_rx_polarity_inverted:1;
986         unsigned int panel_type:4;
987         int lvds_ssc_freq;
988         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
989         enum drm_panel_orientation orientation;
990
991         enum drrs_support_type drrs_type;
992
993         struct {
994                 int rate;
995                 int lanes;
996                 int preemphasis;
997                 int vswing;
998                 bool low_vswing;
999                 bool initialized;
1000                 int bpp;
1001                 struct edp_power_seq pps;
1002         } edp;
1003
1004         struct {
1005                 bool enable;
1006                 bool full_link;
1007                 bool require_aux_wakeup;
1008                 int idle_frames;
1009                 enum psr_lines_to_wait lines_to_wait;
1010                 int tp1_wakeup_time_us;
1011                 int tp2_tp3_wakeup_time_us;
1012         } psr;
1013
1014         struct {
1015                 u16 pwm_freq_hz;
1016                 bool present;
1017                 bool active_low_pwm;
1018                 u8 min_brightness;      /* min_brightness/255 of max */
1019                 u8 controller;          /* brightness controller number */
1020                 enum intel_backlight_type type;
1021         } backlight;
1022
1023         /* MIPI DSI */
1024         struct {
1025                 u16 panel_id;
1026                 struct mipi_config *config;
1027                 struct mipi_pps_data *pps;
1028                 u16 bl_ports;
1029                 u16 cabc_ports;
1030                 u8 seq_version;
1031                 u32 size;
1032                 u8 *data;
1033                 const u8 *sequence[MIPI_SEQ_MAX];
1034                 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1035                 enum drm_panel_orientation orientation;
1036         } dsi;
1037
1038         int crt_ddc_pin;
1039
1040         int child_dev_num;
1041         struct child_device_config *child_dev;
1042
1043         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1044         struct sdvo_device_mapping sdvo_mappings[2];
1045 };
1046
1047 enum intel_ddb_partitioning {
1048         INTEL_DDB_PART_1_2,
1049         INTEL_DDB_PART_5_6, /* IVB+ */
1050 };
1051
1052 struct intel_wm_level {
1053         bool enable;
1054         u32 pri_val;
1055         u32 spr_val;
1056         u32 cur_val;
1057         u32 fbc_val;
1058 };
1059
1060 struct ilk_wm_values {
1061         u32 wm_pipe[3];
1062         u32 wm_lp[3];
1063         u32 wm_lp_spr[3];
1064         u32 wm_linetime[3];
1065         bool enable_fbc_wm;
1066         enum intel_ddb_partitioning partitioning;
1067 };
1068
1069 struct g4x_pipe_wm {
1070         u16 plane[I915_MAX_PLANES];
1071         u16 fbc;
1072 };
1073
1074 struct g4x_sr_wm {
1075         u16 plane;
1076         u16 cursor;
1077         u16 fbc;
1078 };
1079
1080 struct vlv_wm_ddl_values {
1081         u8 plane[I915_MAX_PLANES];
1082 };
1083
1084 struct vlv_wm_values {
1085         struct g4x_pipe_wm pipe[3];
1086         struct g4x_sr_wm sr;
1087         struct vlv_wm_ddl_values ddl[3];
1088         u8 level;
1089         bool cxsr;
1090 };
1091
1092 struct g4x_wm_values {
1093         struct g4x_pipe_wm pipe[2];
1094         struct g4x_sr_wm sr;
1095         struct g4x_sr_wm hpll;
1096         bool cxsr;
1097         bool hpll_en;
1098         bool fbc_en;
1099 };
1100
1101 struct skl_ddb_entry {
1102         u16 start, end; /* in number of blocks, 'end' is exclusive */
1103 };
1104
1105 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1106 {
1107         return entry->end - entry->start;
1108 }
1109
1110 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1111                                        const struct skl_ddb_entry *e2)
1112 {
1113         if (e1->start == e2->start && e1->end == e2->end)
1114                 return true;
1115
1116         return false;
1117 }
1118
1119 struct skl_ddb_allocation {
1120         u8 enabled_slices; /* GEN11 has configurable 2 slices */
1121 };
1122
1123 struct skl_ddb_values {
1124         unsigned dirty_pipes;
1125         struct skl_ddb_allocation ddb;
1126 };
1127
1128 struct skl_wm_level {
1129         u16 min_ddb_alloc;
1130         u16 plane_res_b;
1131         u8 plane_res_l;
1132         bool plane_en;
1133 };
1134
1135 /* Stores plane specific WM parameters */
1136 struct skl_wm_params {
1137         bool x_tiled, y_tiled;
1138         bool rc_surface;
1139         bool is_planar;
1140         u32 width;
1141         u8 cpp;
1142         u32 plane_pixel_rate;
1143         u32 y_min_scanlines;
1144         u32 plane_bytes_per_line;
1145         uint_fixed_16_16_t plane_blocks_per_line;
1146         uint_fixed_16_16_t y_tile_minimum;
1147         u32 linetime_us;
1148         u32 dbuf_block_size;
1149 };
1150
1151 /*
1152  * This struct helps tracking the state needed for runtime PM, which puts the
1153  * device in PCI D3 state. Notice that when this happens, nothing on the
1154  * graphics device works, even register access, so we don't get interrupts nor
1155  * anything else.
1156  *
1157  * Every piece of our code that needs to actually touch the hardware needs to
1158  * either call intel_runtime_pm_get or call intel_display_power_get with the
1159  * appropriate power domain.
1160  *
1161  * Our driver uses the autosuspend delay feature, which means we'll only really
1162  * suspend if we stay with zero refcount for a certain amount of time. The
1163  * default value is currently very conservative (see intel_runtime_pm_enable), but
1164  * it can be changed with the standard runtime PM files from sysfs.
1165  *
1166  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1167  * goes back to false exactly before we reenable the IRQs. We use this variable
1168  * to check if someone is trying to enable/disable IRQs while they're supposed
1169  * to be disabled. This shouldn't happen and we'll print some error messages in
1170  * case it happens.
1171  *
1172  * For more, read the Documentation/power/runtime_pm.txt.
1173  */
1174 struct i915_runtime_pm {
1175         atomic_t wakeref_count;
1176         bool suspended;
1177         bool irqs_enabled;
1178
1179 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1180         /*
1181          * To aide detection of wakeref leaks and general misuse, we
1182          * track all wakeref holders. With manual markup (i.e. returning
1183          * a cookie to each rpm_get caller which they then supply to their
1184          * paired rpm_put) we can remove corresponding pairs of and keep
1185          * the array trimmed to active wakerefs.
1186          */
1187         struct intel_runtime_pm_debug {
1188                 spinlock_t lock;
1189
1190                 depot_stack_handle_t last_acquire;
1191                 depot_stack_handle_t last_release;
1192
1193                 depot_stack_handle_t *owners;
1194                 unsigned long count;
1195         } debug;
1196 #endif
1197 };
1198
1199 enum intel_pipe_crc_source {
1200         INTEL_PIPE_CRC_SOURCE_NONE,
1201         INTEL_PIPE_CRC_SOURCE_PLANE1,
1202         INTEL_PIPE_CRC_SOURCE_PLANE2,
1203         INTEL_PIPE_CRC_SOURCE_PF,
1204         INTEL_PIPE_CRC_SOURCE_PIPE,
1205         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1206         INTEL_PIPE_CRC_SOURCE_TV,
1207         INTEL_PIPE_CRC_SOURCE_DP_B,
1208         INTEL_PIPE_CRC_SOURCE_DP_C,
1209         INTEL_PIPE_CRC_SOURCE_DP_D,
1210         INTEL_PIPE_CRC_SOURCE_AUTO,
1211         INTEL_PIPE_CRC_SOURCE_MAX,
1212 };
1213
1214 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1215 struct intel_pipe_crc {
1216         spinlock_t lock;
1217         int skipped;
1218         enum intel_pipe_crc_source source;
1219 };
1220
1221 struct i915_frontbuffer_tracking {
1222         spinlock_t lock;
1223
1224         /*
1225          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1226          * scheduled flips.
1227          */
1228         unsigned busy_bits;
1229         unsigned flip_bits;
1230 };
1231
1232 struct i915_virtual_gpu {
1233         bool active;
1234         u32 caps;
1235 };
1236
1237 /* used in computing the new watermarks state */
1238 struct intel_wm_config {
1239         unsigned int num_pipes_active;
1240         bool sprites_enabled;
1241         bool sprites_scaled;
1242 };
1243
1244 struct i915_oa_format {
1245         u32 format;
1246         int size;
1247 };
1248
1249 struct i915_oa_reg {
1250         i915_reg_t addr;
1251         u32 value;
1252 };
1253
1254 struct i915_oa_config {
1255         char uuid[UUID_STRING_LEN + 1];
1256         int id;
1257
1258         const struct i915_oa_reg *mux_regs;
1259         u32 mux_regs_len;
1260         const struct i915_oa_reg *b_counter_regs;
1261         u32 b_counter_regs_len;
1262         const struct i915_oa_reg *flex_regs;
1263         u32 flex_regs_len;
1264
1265         struct attribute_group sysfs_metric;
1266         struct attribute *attrs[2];
1267         struct device_attribute sysfs_metric_id;
1268
1269         atomic_t ref_count;
1270 };
1271
1272 struct i915_perf_stream;
1273
1274 /**
1275  * struct i915_perf_stream_ops - the OPs to support a specific stream type
1276  */
1277 struct i915_perf_stream_ops {
1278         /**
1279          * @enable: Enables the collection of HW samples, either in response to
1280          * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1281          * without `I915_PERF_FLAG_DISABLED`.
1282          */
1283         void (*enable)(struct i915_perf_stream *stream);
1284
1285         /**
1286          * @disable: Disables the collection of HW samples, either in response
1287          * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1288          * the stream.
1289          */
1290         void (*disable)(struct i915_perf_stream *stream);
1291
1292         /**
1293          * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1294          * once there is something ready to read() for the stream
1295          */
1296         void (*poll_wait)(struct i915_perf_stream *stream,
1297                           struct file *file,
1298                           poll_table *wait);
1299
1300         /**
1301          * @wait_unlocked: For handling a blocking read, wait until there is
1302          * something to ready to read() for the stream. E.g. wait on the same
1303          * wait queue that would be passed to poll_wait().
1304          */
1305         int (*wait_unlocked)(struct i915_perf_stream *stream);
1306
1307         /**
1308          * @read: Copy buffered metrics as records to userspace
1309          * **buf**: the userspace, destination buffer
1310          * **count**: the number of bytes to copy, requested by userspace
1311          * **offset**: zero at the start of the read, updated as the read
1312          * proceeds, it represents how many bytes have been copied so far and
1313          * the buffer offset for copying the next record.
1314          *
1315          * Copy as many buffered i915 perf samples and records for this stream
1316          * to userspace as will fit in the given buffer.
1317          *
1318          * Only write complete records; returning -%ENOSPC if there isn't room
1319          * for a complete record.
1320          *
1321          * Return any error condition that results in a short read such as
1322          * -%ENOSPC or -%EFAULT, even though these may be squashed before
1323          * returning to userspace.
1324          */
1325         int (*read)(struct i915_perf_stream *stream,
1326                     char __user *buf,
1327                     size_t count,
1328                     size_t *offset);
1329
1330         /**
1331          * @destroy: Cleanup any stream specific resources.
1332          *
1333          * The stream will always be disabled before this is called.
1334          */
1335         void (*destroy)(struct i915_perf_stream *stream);
1336 };
1337
1338 /**
1339  * struct i915_perf_stream - state for a single open stream FD
1340  */
1341 struct i915_perf_stream {
1342         /**
1343          * @dev_priv: i915 drm device
1344          */
1345         struct drm_i915_private *dev_priv;
1346
1347         /**
1348          * @link: Links the stream into ``&drm_i915_private->streams``
1349          */
1350         struct list_head link;
1351
1352         /**
1353          * @wakeref: As we keep the device awake while the perf stream is
1354          * active, we track our runtime pm reference for later release.
1355          */
1356         intel_wakeref_t wakeref;
1357
1358         /**
1359          * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1360          * properties given when opening a stream, representing the contents
1361          * of a single sample as read() by userspace.
1362          */
1363         u32 sample_flags;
1364
1365         /**
1366          * @sample_size: Considering the configured contents of a sample
1367          * combined with the required header size, this is the total size
1368          * of a single sample record.
1369          */
1370         int sample_size;
1371
1372         /**
1373          * @ctx: %NULL if measuring system-wide across all contexts or a
1374          * specific context that is being monitored.
1375          */
1376         struct i915_gem_context *ctx;
1377
1378         /**
1379          * @enabled: Whether the stream is currently enabled, considering
1380          * whether the stream was opened in a disabled state and based
1381          * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1382          */
1383         bool enabled;
1384
1385         /**
1386          * @ops: The callbacks providing the implementation of this specific
1387          * type of configured stream.
1388          */
1389         const struct i915_perf_stream_ops *ops;
1390
1391         /**
1392          * @oa_config: The OA configuration used by the stream.
1393          */
1394         struct i915_oa_config *oa_config;
1395 };
1396
1397 /**
1398  * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1399  */
1400 struct i915_oa_ops {
1401         /**
1402          * @is_valid_b_counter_reg: Validates register's address for
1403          * programming boolean counters for a particular platform.
1404          */
1405         bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1406                                        u32 addr);
1407
1408         /**
1409          * @is_valid_mux_reg: Validates register's address for programming mux
1410          * for a particular platform.
1411          */
1412         bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1413
1414         /**
1415          * @is_valid_flex_reg: Validates register's address for programming
1416          * flex EU filtering for a particular platform.
1417          */
1418         bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1419
1420         /**
1421          * @enable_metric_set: Selects and applies any MUX configuration to set
1422          * up the Boolean and Custom (B/C) counters that are part of the
1423          * counter reports being sampled. May apply system constraints such as
1424          * disabling EU clock gating as required.
1425          */
1426         int (*enable_metric_set)(struct i915_perf_stream *stream);
1427
1428         /**
1429          * @disable_metric_set: Remove system constraints associated with using
1430          * the OA unit.
1431          */
1432         void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1433
1434         /**
1435          * @oa_enable: Enable periodic sampling
1436          */
1437         void (*oa_enable)(struct i915_perf_stream *stream);
1438
1439         /**
1440          * @oa_disable: Disable periodic sampling
1441          */
1442         void (*oa_disable)(struct i915_perf_stream *stream);
1443
1444         /**
1445          * @read: Copy data from the circular OA buffer into a given userspace
1446          * buffer.
1447          */
1448         int (*read)(struct i915_perf_stream *stream,
1449                     char __user *buf,
1450                     size_t count,
1451                     size_t *offset);
1452
1453         /**
1454          * @oa_hw_tail_read: read the OA tail pointer register
1455          *
1456          * In particular this enables us to share all the fiddly code for
1457          * handling the OA unit tail pointer race that affects multiple
1458          * generations.
1459          */
1460         u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1461 };
1462
1463 struct intel_cdclk_state {
1464         unsigned int cdclk, vco, ref, bypass;
1465         u8 voltage_level;
1466 };
1467
1468 struct drm_i915_private {
1469         struct drm_device drm;
1470
1471         struct kmem_cache *objects;
1472         struct kmem_cache *vmas;
1473         struct kmem_cache *luts;
1474         struct kmem_cache *requests;
1475         struct kmem_cache *dependencies;
1476         struct kmem_cache *priorities;
1477
1478         const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1479         struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1480         struct intel_driver_caps caps;
1481
1482         /**
1483          * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1484          * end of stolen which we can optionally use to create GEM objects
1485          * backed by stolen memory. Note that stolen_usable_size tells us
1486          * exactly how much of this we are actually allowed to use, given that
1487          * some portion of it is in fact reserved for use by hardware functions.
1488          */
1489         struct resource dsm;
1490         /**
1491          * Reseved portion of Data Stolen Memory
1492          */
1493         struct resource dsm_reserved;
1494
1495         /*
1496          * Stolen memory is segmented in hardware with different portions
1497          * offlimits to certain functions.
1498          *
1499          * The drm_mm is initialised to the total accessible range, as found
1500          * from the PCI config. On Broadwell+, this is further restricted to
1501          * avoid the first page! The upper end of stolen memory is reserved for
1502          * hardware functions and similarly removed from the accessible range.
1503          */
1504         resource_size_t stolen_usable_size;     /* Total size minus reserved ranges */
1505
1506         void __iomem *regs;
1507
1508         struct intel_uncore uncore;
1509
1510         struct i915_virtual_gpu vgpu;
1511
1512         struct intel_gvt *gvt;
1513
1514         struct intel_wopcm wopcm;
1515
1516         struct intel_huc huc;
1517         struct intel_guc guc;
1518
1519         struct intel_csr csr;
1520
1521         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1522
1523         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1524          * controller on different i2c buses. */
1525         struct mutex gmbus_mutex;
1526
1527         /**
1528          * Base address of where the gmbus and gpio blocks are located (either
1529          * on PCH or on SoC for platforms without PCH).
1530          */
1531         u32 gpio_mmio_base;
1532
1533         /* MMIO base address for MIPI regs */
1534         u32 mipi_mmio_base;
1535
1536         u32 psr_mmio_base;
1537
1538         u32 pps_mmio_base;
1539
1540         wait_queue_head_t gmbus_wait_queue;
1541
1542         struct pci_dev *bridge_dev;
1543         struct intel_engine_cs *engine[I915_NUM_ENGINES];
1544         /* Context used internally to idle the GPU and setup initial state */
1545         struct i915_gem_context *kernel_context;
1546         /* Context only to be used for injecting preemption commands */
1547         struct i915_gem_context *preempt_context;
1548         struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1549                                             [MAX_ENGINE_INSTANCE + 1];
1550
1551         struct resource mch_res;
1552
1553         /* protects the irq masks */
1554         spinlock_t irq_lock;
1555
1556         bool display_irqs_enabled;
1557
1558         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1559         struct pm_qos_request pm_qos;
1560
1561         /* Sideband mailbox protection */
1562         struct mutex sb_lock;
1563
1564         /** Cached value of IMR to avoid reads in updating the bitfield */
1565         union {
1566                 u32 irq_mask;
1567                 u32 de_irq_mask[I915_MAX_PIPES];
1568         };
1569         u32 gt_irq_mask;
1570         u32 pm_imr;
1571         u32 pm_ier;
1572         u32 pm_rps_events;
1573         u32 pm_guc_events;
1574         u32 pipestat_irq_mask[I915_MAX_PIPES];
1575
1576         struct i915_hotplug hotplug;
1577         struct intel_fbc fbc;
1578         struct i915_drrs drrs;
1579         struct intel_opregion opregion;
1580         struct intel_vbt_data vbt;
1581
1582         bool preserve_bios_swizzle;
1583
1584         /* overlay */
1585         struct intel_overlay *overlay;
1586
1587         /* backlight registers and fields in struct intel_panel */
1588         struct mutex backlight_lock;
1589
1590         /* LVDS info */
1591         bool no_aux_handshake;
1592
1593         /* protects panel power sequencer state */
1594         struct mutex pps_mutex;
1595
1596         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1597         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1598
1599         unsigned int fsb_freq, mem_freq, is_ddr3;
1600         unsigned int skl_preferred_vco_freq;
1601         unsigned int max_cdclk_freq;
1602
1603         unsigned int max_dotclk_freq;
1604         unsigned int rawclk_freq;
1605         unsigned int hpll_freq;
1606         unsigned int fdi_pll_freq;
1607         unsigned int czclk_freq;
1608
1609         struct {
1610                 /*
1611                  * The current logical cdclk state.
1612                  * See intel_atomic_state.cdclk.logical
1613                  *
1614                  * For reading holding any crtc lock is sufficient,
1615                  * for writing must hold all of them.
1616                  */
1617                 struct intel_cdclk_state logical;
1618                 /*
1619                  * The current actual cdclk state.
1620                  * See intel_atomic_state.cdclk.actual
1621                  */
1622                 struct intel_cdclk_state actual;
1623                 /* The current hardware cdclk state */
1624                 struct intel_cdclk_state hw;
1625         } cdclk;
1626
1627         /**
1628          * wq - Driver workqueue for GEM.
1629          *
1630          * NOTE: Work items scheduled here are not allowed to grab any modeset
1631          * locks, for otherwise the flushing done in the pageflip code will
1632          * result in deadlocks.
1633          */
1634         struct workqueue_struct *wq;
1635
1636         /* ordered wq for modesets */
1637         struct workqueue_struct *modeset_wq;
1638
1639         /* Display functions */
1640         struct drm_i915_display_funcs display;
1641
1642         /* PCH chipset type */
1643         enum intel_pch pch_type;
1644         unsigned short pch_id;
1645
1646         unsigned long quirks;
1647
1648         struct drm_atomic_state *modeset_restore_state;
1649         struct drm_modeset_acquire_ctx reset_ctx;
1650
1651         struct i915_ggtt ggtt; /* VM representing the global address space */
1652
1653         struct i915_gem_mm mm;
1654         DECLARE_HASHTABLE(mm_structs, 7);
1655         struct mutex mm_lock;
1656
1657         struct intel_ppat ppat;
1658
1659         /* Kernel Modesetting */
1660
1661         struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1662         struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1663
1664 #ifdef CONFIG_DEBUG_FS
1665         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1666 #endif
1667
1668         /* dpll and cdclk state is protected by connection_mutex */
1669         int num_shared_dpll;
1670         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1671         const struct intel_dpll_mgr *dpll_mgr;
1672
1673         /*
1674          * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1675          * Must be global rather than per dpll, because on some platforms
1676          * plls share registers.
1677          */
1678         struct mutex dpll_lock;
1679
1680         unsigned int active_crtcs;
1681         /* minimum acceptable cdclk for each pipe */
1682         int min_cdclk[I915_MAX_PIPES];
1683         /* minimum acceptable voltage level for each pipe */
1684         u8 min_voltage_level[I915_MAX_PIPES];
1685
1686         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1687
1688         struct i915_wa_list gt_wa_list;
1689
1690         struct i915_frontbuffer_tracking fb_tracking;
1691
1692         struct intel_atomic_helper {
1693                 struct llist_head free_list;
1694                 struct work_struct free_work;
1695         } atomic_helper;
1696
1697         u16 orig_clock;
1698
1699         bool mchbar_need_disable;
1700
1701         struct intel_l3_parity l3_parity;
1702
1703         /* Cannot be determined by PCIID. You must always read a register. */
1704         u32 edram_cap;
1705
1706         /*
1707          * Protects RPS/RC6 register access and PCU communication.
1708          * Must be taken after struct_mutex if nested. Note that
1709          * this lock may be held for long periods of time when
1710          * talking to hw - so only take it when talking to hw!
1711          */
1712         struct mutex pcu_lock;
1713
1714         /* gen6+ GT PM state */
1715         struct intel_gen6_power_mgmt gt_pm;
1716
1717         /* ilk-only ips/rps state. Everything in here is protected by the global
1718          * mchdev_lock in intel_pm.c */
1719         struct intel_ilk_power_mgmt ips;
1720
1721         struct i915_power_domains power_domains;
1722
1723         struct i915_psr psr;
1724
1725         struct i915_gpu_error gpu_error;
1726
1727         struct drm_i915_gem_object *vlv_pctx;
1728
1729         /* list of fbdev register on this device */
1730         struct intel_fbdev *fbdev;
1731         struct work_struct fbdev_suspend_work;
1732
1733         struct drm_property *broadcast_rgb_property;
1734         struct drm_property *force_audio_property;
1735
1736         /* hda/i915 audio component */
1737         struct i915_audio_component *audio_component;
1738         bool audio_component_registered;
1739         /**
1740          * av_mutex - mutex for audio/video sync
1741          *
1742          */
1743         struct mutex av_mutex;
1744
1745         struct {
1746                 struct mutex mutex;
1747                 struct list_head list;
1748                 struct llist_head free_list;
1749                 struct work_struct free_work;
1750
1751                 /* The hw wants to have a stable context identifier for the
1752                  * lifetime of the context (for OA, PASID, faults, etc).
1753                  * This is limited in execlists to 21 bits.
1754                  */
1755                 struct ida hw_ida;
1756 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1757 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1758 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1759                 struct list_head hw_id_list;
1760         } contexts;
1761
1762         u32 fdi_rx_config;
1763
1764         /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1765         u32 chv_phy_control;
1766         /*
1767          * Shadows for CHV DPLL_MD regs to keep the state
1768          * checker somewhat working in the presence hardware
1769          * crappiness (can't read out DPLL_MD for pipes B & C).
1770          */
1771         u32 chv_dpll_md[I915_MAX_PIPES];
1772         u32 bxt_phy_grc;
1773
1774         u32 suspend_count;
1775         bool power_domains_suspended;
1776         struct i915_suspend_saved_registers regfile;
1777         struct vlv_s0ix_state vlv_s0ix_state;
1778
1779         enum {
1780                 I915_SAGV_UNKNOWN = 0,
1781                 I915_SAGV_DISABLED,
1782                 I915_SAGV_ENABLED,
1783                 I915_SAGV_NOT_CONTROLLED
1784         } sagv_status;
1785
1786         struct {
1787                 /*
1788                  * Raw watermark latency values:
1789                  * in 0.1us units for WM0,
1790                  * in 0.5us units for WM1+.
1791                  */
1792                 /* primary */
1793                 u16 pri_latency[5];
1794                 /* sprite */
1795                 u16 spr_latency[5];
1796                 /* cursor */
1797                 u16 cur_latency[5];
1798                 /*
1799                  * Raw watermark memory latency values
1800                  * for SKL for all 8 levels
1801                  * in 1us units.
1802                  */
1803                 u16 skl_latency[8];
1804
1805                 /* current hardware state */
1806                 union {
1807                         struct ilk_wm_values hw;
1808                         struct skl_ddb_values skl_hw;
1809                         struct vlv_wm_values vlv;
1810                         struct g4x_wm_values g4x;
1811                 };
1812
1813                 u8 max_level;
1814
1815                 /*
1816                  * Should be held around atomic WM register writing; also
1817                  * protects * intel_crtc->wm.active and
1818                  * cstate->wm.need_postvbl_update.
1819                  */
1820                 struct mutex wm_mutex;
1821
1822                 /*
1823                  * Set during HW readout of watermarks/DDB.  Some platforms
1824                  * need to know when we're still using BIOS-provided values
1825                  * (which we don't fully trust).
1826                  */
1827                 bool distrust_bios_wm;
1828         } wm;
1829
1830         struct dram_info {
1831                 bool valid;
1832                 bool is_16gb_dimm;
1833                 u8 num_channels;
1834                 enum dram_rank {
1835                         I915_DRAM_RANK_INVALID = 0,
1836                         I915_DRAM_RANK_SINGLE,
1837                         I915_DRAM_RANK_DUAL
1838                 } rank;
1839                 u32 bandwidth_kbps;
1840                 bool symmetric_memory;
1841         } dram_info;
1842
1843         struct i915_runtime_pm runtime_pm;
1844
1845         struct {
1846                 bool initialized;
1847
1848                 struct kobject *metrics_kobj;
1849                 struct ctl_table_header *sysctl_header;
1850
1851                 /*
1852                  * Lock associated with adding/modifying/removing OA configs
1853                  * in dev_priv->perf.metrics_idr.
1854                  */
1855                 struct mutex metrics_lock;
1856
1857                 /*
1858                  * List of dynamic configurations, you need to hold
1859                  * dev_priv->perf.metrics_lock to access it.
1860                  */
1861                 struct idr metrics_idr;
1862
1863                 /*
1864                  * Lock associated with anything below within this structure
1865                  * except exclusive_stream.
1866                  */
1867                 struct mutex lock;
1868                 struct list_head streams;
1869
1870                 struct {
1871                         /*
1872                          * The stream currently using the OA unit. If accessed
1873                          * outside a syscall associated to its file
1874                          * descriptor, you need to hold
1875                          * dev_priv->drm.struct_mutex.
1876                          */
1877                         struct i915_perf_stream *exclusive_stream;
1878
1879                         struct intel_context *pinned_ctx;
1880                         u32 specific_ctx_id;
1881                         u32 specific_ctx_id_mask;
1882
1883                         struct hrtimer poll_check_timer;
1884                         wait_queue_head_t poll_wq;
1885                         bool pollin;
1886
1887                         /**
1888                          * For rate limiting any notifications of spurious
1889                          * invalid OA reports
1890                          */
1891                         struct ratelimit_state spurious_report_rs;
1892
1893                         bool periodic;
1894                         int period_exponent;
1895
1896                         struct i915_oa_config test_config;
1897
1898                         struct {
1899                                 struct i915_vma *vma;
1900                                 u8 *vaddr;
1901                                 u32 last_ctx_id;
1902                                 int format;
1903                                 int format_size;
1904
1905                                 /**
1906                                  * Locks reads and writes to all head/tail state
1907                                  *
1908                                  * Consider: the head and tail pointer state
1909                                  * needs to be read consistently from a hrtimer
1910                                  * callback (atomic context) and read() fop
1911                                  * (user context) with tail pointer updates
1912                                  * happening in atomic context and head updates
1913                                  * in user context and the (unlikely)
1914                                  * possibility of read() errors needing to
1915                                  * reset all head/tail state.
1916                                  *
1917                                  * Note: Contention or performance aren't
1918                                  * currently a significant concern here
1919                                  * considering the relatively low frequency of
1920                                  * hrtimer callbacks (5ms period) and that
1921                                  * reads typically only happen in response to a
1922                                  * hrtimer event and likely complete before the
1923                                  * next callback.
1924                                  *
1925                                  * Note: This lock is not held *while* reading
1926                                  * and copying data to userspace so the value
1927                                  * of head observed in htrimer callbacks won't
1928                                  * represent any partial consumption of data.
1929                                  */
1930                                 spinlock_t ptr_lock;
1931
1932                                 /**
1933                                  * One 'aging' tail pointer and one 'aged'
1934                                  * tail pointer ready to used for reading.
1935                                  *
1936                                  * Initial values of 0xffffffff are invalid
1937                                  * and imply that an update is required
1938                                  * (and should be ignored by an attempted
1939                                  * read)
1940                                  */
1941                                 struct {
1942                                         u32 offset;
1943                                 } tails[2];
1944
1945                                 /**
1946                                  * Index for the aged tail ready to read()
1947                                  * data up to.
1948                                  */
1949                                 unsigned int aged_tail_idx;
1950
1951                                 /**
1952                                  * A monotonic timestamp for when the current
1953                                  * aging tail pointer was read; used to
1954                                  * determine when it is old enough to trust.
1955                                  */
1956                                 u64 aging_timestamp;
1957
1958                                 /**
1959                                  * Although we can always read back the head
1960                                  * pointer register, we prefer to avoid
1961                                  * trusting the HW state, just to avoid any
1962                                  * risk that some hardware condition could
1963                                  * somehow bump the head pointer unpredictably
1964                                  * and cause us to forward the wrong OA buffer
1965                                  * data to userspace.
1966                                  */
1967                                 u32 head;
1968                         } oa_buffer;
1969
1970                         u32 gen7_latched_oastatus1;
1971                         u32 ctx_oactxctrl_offset;
1972                         u32 ctx_flexeu0_offset;
1973
1974                         /**
1975                          * The RPT_ID/reason field for Gen8+ includes a bit
1976                          * to determine if the CTX ID in the report is valid
1977                          * but the specific bit differs between Gen 8 and 9
1978                          */
1979                         u32 gen8_valid_ctx_bit;
1980
1981                         struct i915_oa_ops ops;
1982                         const struct i915_oa_format *oa_formats;
1983                 } oa;
1984         } perf;
1985
1986         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1987         struct {
1988                 void (*resume)(struct drm_i915_private *);
1989                 void (*cleanup_engine)(struct intel_engine_cs *engine);
1990
1991                 struct i915_gt_timelines {
1992                         struct mutex mutex; /* protects list, tainted by GPU */
1993                         struct list_head active_list;
1994
1995                         /* Pack multiple timelines' seqnos into the same page */
1996                         spinlock_t hwsp_lock;
1997                         struct list_head hwsp_free_list;
1998                 } timelines;
1999
2000                 struct list_head active_rings;
2001                 struct list_head closed_vma;
2002                 u32 active_requests;
2003
2004                 /**
2005                  * Is the GPU currently considered idle, or busy executing
2006                  * userspace requests? Whilst idle, we allow runtime power
2007                  * management to power down the hardware and display clocks.
2008                  * In order to reduce the effect on performance, there
2009                  * is a slight delay before we do so.
2010                  */
2011                 intel_wakeref_t awake;
2012
2013                 /**
2014                  * The number of times we have woken up.
2015                  */
2016                 unsigned int epoch;
2017 #define I915_EPOCH_INVALID 0
2018
2019                 /**
2020                  * We leave the user IRQ off as much as possible,
2021                  * but this means that requests will finish and never
2022                  * be retired once the system goes idle. Set a timer to
2023                  * fire periodically while the ring is running. When it
2024                  * fires, go retire requests.
2025                  */
2026                 struct delayed_work retire_work;
2027
2028                 /**
2029                  * When we detect an idle GPU, we want to turn on
2030                  * powersaving features. So once we see that there
2031                  * are no more requests outstanding and no more
2032                  * arrive within a small period of time, we fire
2033                  * off the idle_work.
2034                  */
2035                 struct delayed_work idle_work;
2036
2037                 ktime_t last_init_time;
2038
2039                 struct i915_vma *scratch;
2040         } gt;
2041
2042         /* perform PHY state sanity checks? */
2043         bool chv_phy_assert[2];
2044
2045         bool ipc_enabled;
2046
2047         /* Used to save the pipe-to-encoder mapping for audio */
2048         struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2049
2050         /* necessary resource sharing with HDMI LPE audio driver. */
2051         struct {
2052                 struct platform_device *platdev;
2053                 int     irq;
2054         } lpe_audio;
2055
2056         struct i915_pmu pmu;
2057
2058         /*
2059          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2060          * will be rejected. Instead look for a better place.
2061          */
2062 };
2063
2064 struct dram_channel_info {
2065         struct info {
2066                 u8 size, width;
2067                 enum dram_rank rank;
2068         } l_info, s_info;
2069         enum dram_rank rank;
2070         bool is_16gb_dimm;
2071 };
2072
2073 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2074 {
2075         return container_of(dev, struct drm_i915_private, drm);
2076 }
2077
2078 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2079 {
2080         return to_i915(dev_get_drvdata(kdev));
2081 }
2082
2083 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2084 {
2085         return container_of(wopcm, struct drm_i915_private, wopcm);
2086 }
2087
2088 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2089 {
2090         return container_of(guc, struct drm_i915_private, guc);
2091 }
2092
2093 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2094 {
2095         return container_of(huc, struct drm_i915_private, huc);
2096 }
2097
2098 /* Simple iterator over all initialised engines */
2099 #define for_each_engine(engine__, dev_priv__, id__) \
2100         for ((id__) = 0; \
2101              (id__) < I915_NUM_ENGINES; \
2102              (id__)++) \
2103                 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2104
2105 /* Iterator over subset of engines selected by mask */
2106 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2107         for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2108              (tmp__) ? \
2109              ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2110              0;)
2111
2112 enum hdmi_force_audio {
2113         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
2114         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
2115         HDMI_AUDIO_AUTO,                /* trust EDID */
2116         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
2117 };
2118
2119 #define I915_GTT_OFFSET_NONE ((u32)-1)
2120
2121 /*
2122  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2123  * considered to be the frontbuffer for the given plane interface-wise. This
2124  * doesn't mean that the hw necessarily already scans it out, but that any
2125  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2126  *
2127  * We have one bit per pipe and per scanout plane type.
2128  */
2129 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2130 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2131         BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2132         BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2133         BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2134 })
2135 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2136         BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2137 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2138         GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2139                 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2140
2141 /*
2142  * Optimised SGL iterator for GEM objects
2143  */
2144 static __always_inline struct sgt_iter {
2145         struct scatterlist *sgp;
2146         union {
2147                 unsigned long pfn;
2148                 dma_addr_t dma;
2149         };
2150         unsigned int curr;
2151         unsigned int max;
2152 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2153         struct sgt_iter s = { .sgp = sgl };
2154
2155         if (s.sgp) {
2156                 s.max = s.curr = s.sgp->offset;
2157                 s.max += s.sgp->length;
2158                 if (dma)
2159                         s.dma = sg_dma_address(s.sgp);
2160                 else
2161                         s.pfn = page_to_pfn(sg_page(s.sgp));
2162         }
2163
2164         return s;
2165 }
2166
2167 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2168 {
2169         ++sg;
2170         if (unlikely(sg_is_chain(sg)))
2171                 sg = sg_chain_ptr(sg);
2172         return sg;
2173 }
2174
2175 /**
2176  * __sg_next - return the next scatterlist entry in a list
2177  * @sg:         The current sg entry
2178  *
2179  * Description:
2180  *   If the entry is the last, return NULL; otherwise, step to the next
2181  *   element in the array (@sg@+1). If that's a chain pointer, follow it;
2182  *   otherwise just return the pointer to the current element.
2183  **/
2184 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2185 {
2186         return sg_is_last(sg) ? NULL : ____sg_next(sg);
2187 }
2188
2189 /**
2190  * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2191  * @__dmap:     DMA address (output)
2192  * @__iter:     'struct sgt_iter' (iterator state, internal)
2193  * @__sgt:      sg_table to iterate over (input)
2194  */
2195 #define for_each_sgt_dma(__dmap, __iter, __sgt)                         \
2196         for ((__iter) = __sgt_iter((__sgt)->sgl, true);                 \
2197              ((__dmap) = (__iter).dma + (__iter).curr);                 \
2198              (((__iter).curr += I915_GTT_PAGE_SIZE) >= (__iter).max) ?  \
2199              (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2200
2201 /**
2202  * for_each_sgt_page - iterate over the pages of the given sg_table
2203  * @__pp:       page pointer (output)
2204  * @__iter:     'struct sgt_iter' (iterator state, internal)
2205  * @__sgt:      sg_table to iterate over (input)
2206  */
2207 #define for_each_sgt_page(__pp, __iter, __sgt)                          \
2208         for ((__iter) = __sgt_iter((__sgt)->sgl, false);                \
2209              ((__pp) = (__iter).pfn == 0 ? NULL :                       \
2210               pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2211              (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?           \
2212              (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2213
2214 bool i915_sg_trim(struct sg_table *orig_st);
2215
2216 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2217 {
2218         unsigned int page_sizes;
2219
2220         page_sizes = 0;
2221         while (sg) {
2222                 GEM_BUG_ON(sg->offset);
2223                 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2224                 page_sizes |= sg->length;
2225                 sg = __sg_next(sg);
2226         }
2227
2228         return page_sizes;
2229 }
2230
2231 static inline unsigned int i915_sg_segment_size(void)
2232 {
2233         unsigned int size = swiotlb_max_segment();
2234
2235         if (size == 0)
2236                 return SCATTERLIST_MAX_SEGMENT;
2237
2238         size = rounddown(size, PAGE_SIZE);
2239         /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2240         if (size < PAGE_SIZE)
2241                 size = PAGE_SIZE;
2242
2243         return size;
2244 }
2245
2246 #define INTEL_INFO(dev_priv)    (&(dev_priv)->__info)
2247 #define RUNTIME_INFO(dev_priv)  (&(dev_priv)->__runtime)
2248 #define DRIVER_CAPS(dev_priv)   (&(dev_priv)->caps)
2249
2250 #define INTEL_GEN(dev_priv)     (INTEL_INFO(dev_priv)->gen)
2251 #define INTEL_DEVID(dev_priv)   (RUNTIME_INFO(dev_priv)->device_id)
2252
2253 #define REVID_FOREVER           0xff
2254 #define INTEL_REVID(dev_priv)   ((dev_priv)->drm.pdev->revision)
2255
2256 #define INTEL_GEN_MASK(s, e) ( \
2257         BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2258         BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2259         GENMASK((e) - 1, (s) - 1))
2260
2261 /* Returns true if Gen is in inclusive range [Start, End] */
2262 #define IS_GEN_RANGE(dev_priv, s, e) \
2263         (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
2264
2265 #define IS_GEN(dev_priv, n) \
2266         (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
2267          INTEL_INFO(dev_priv)->gen == (n))
2268
2269 /*
2270  * Return true if revision is in range [since,until] inclusive.
2271  *
2272  * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2273  */
2274 #define IS_REVID(p, since, until) \
2275         (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2276
2277 #define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
2278
2279 #define IS_I830(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I830)
2280 #define IS_I845G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I845G)
2281 #define IS_I85X(dev_priv)       IS_PLATFORM(dev_priv, INTEL_I85X)
2282 #define IS_I865G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I865G)
2283 #define IS_I915G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I915G)
2284 #define IS_I915GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I915GM)
2285 #define IS_I945G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I945G)
2286 #define IS_I945GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I945GM)
2287 #define IS_I965G(dev_priv)      IS_PLATFORM(dev_priv, INTEL_I965G)
2288 #define IS_I965GM(dev_priv)     IS_PLATFORM(dev_priv, INTEL_I965GM)
2289 #define IS_G45(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G45)
2290 #define IS_GM45(dev_priv)       IS_PLATFORM(dev_priv, INTEL_GM45)
2291 #define IS_G4X(dev_priv)        (IS_G45(dev_priv) || IS_GM45(dev_priv))
2292 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2293 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2294 #define IS_PINEVIEW(dev_priv)   IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2295 #define IS_G33(dev_priv)        IS_PLATFORM(dev_priv, INTEL_G33)
2296 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2297 #define IS_IVYBRIDGE(dev_priv)  IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2298 #define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
2299                                  INTEL_INFO(dev_priv)->gt == 1)
2300 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2301 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2302 #define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
2303 #define IS_BROADWELL(dev_priv)  IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2304 #define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2305 #define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
2306 #define IS_KABYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2307 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2308 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2309 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2310 #define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2311 #define IS_MOBILE(dev_priv)     (INTEL_INFO(dev_priv)->is_mobile)
2312 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2313                                     (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2314 #define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
2315                                  ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||       \
2316                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||        \
2317                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2318 /* ULX machines are also considered ULT. */
2319 #define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
2320                                  (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2321 #define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
2322                                  INTEL_INFO(dev_priv)->gt == 3)
2323 #define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
2324                                  (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2325 #define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
2326                                  INTEL_INFO(dev_priv)->gt == 3)
2327 #define IS_HSW_GT1(dev_priv)    (IS_HASWELL(dev_priv) && \
2328                                  INTEL_INFO(dev_priv)->gt == 1)
2329 /* ULX machines are also considered ULT. */
2330 #define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
2331                                  INTEL_DEVID(dev_priv) == 0x0A1E)
2332 #define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
2333                                  INTEL_DEVID(dev_priv) == 0x1913 || \
2334                                  INTEL_DEVID(dev_priv) == 0x1916 || \
2335                                  INTEL_DEVID(dev_priv) == 0x1921 || \
2336                                  INTEL_DEVID(dev_priv) == 0x1926)
2337 #define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
2338                                  INTEL_DEVID(dev_priv) == 0x1915 || \
2339                                  INTEL_DEVID(dev_priv) == 0x191E)
2340 #define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
2341                                  INTEL_DEVID(dev_priv) == 0x5913 || \
2342                                  INTEL_DEVID(dev_priv) == 0x5916 || \
2343                                  INTEL_DEVID(dev_priv) == 0x5921 || \
2344                                  INTEL_DEVID(dev_priv) == 0x5926)
2345 #define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
2346                                  INTEL_DEVID(dev_priv) == 0x5915 || \
2347                                  INTEL_DEVID(dev_priv) == 0x591E)
2348 #define IS_AML_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x591C || \
2349                                  INTEL_DEVID(dev_priv) == 0x87C0)
2350 #define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2351                                  INTEL_INFO(dev_priv)->gt == 2)
2352 #define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2353                                  INTEL_INFO(dev_priv)->gt == 3)
2354 #define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
2355                                  INTEL_INFO(dev_priv)->gt == 4)
2356 #define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
2357                                  INTEL_INFO(dev_priv)->gt == 2)
2358 #define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
2359                                  INTEL_INFO(dev_priv)->gt == 3)
2360 #define IS_CFL_ULT(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
2361                                  (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2362 #define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
2363                                  INTEL_INFO(dev_priv)->gt == 2)
2364 #define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
2365                                  INTEL_INFO(dev_priv)->gt == 3)
2366 #define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
2367                                         (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2368 #define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
2369                                         INTEL_DEVID(dev_priv) != 0x8A51)
2370
2371 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2372
2373 #define SKL_REVID_A0            0x0
2374 #define SKL_REVID_B0            0x1
2375 #define SKL_REVID_C0            0x2
2376 #define SKL_REVID_D0            0x3
2377 #define SKL_REVID_E0            0x4
2378 #define SKL_REVID_F0            0x5
2379 #define SKL_REVID_G0            0x6
2380 #define SKL_REVID_H0            0x7
2381
2382 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2383
2384 #define BXT_REVID_A0            0x0
2385 #define BXT_REVID_A1            0x1
2386 #define BXT_REVID_B0            0x3
2387 #define BXT_REVID_B_LAST        0x8
2388 #define BXT_REVID_C0            0x9
2389
2390 #define IS_BXT_REVID(dev_priv, since, until) \
2391         (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2392
2393 #define KBL_REVID_A0            0x0
2394 #define KBL_REVID_B0            0x1
2395 #define KBL_REVID_C0            0x2
2396 #define KBL_REVID_D0            0x3
2397 #define KBL_REVID_E0            0x4
2398
2399 #define IS_KBL_REVID(dev_priv, since, until) \
2400         (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2401
2402 #define GLK_REVID_A0            0x0
2403 #define GLK_REVID_A1            0x1
2404
2405 #define IS_GLK_REVID(dev_priv, since, until) \
2406         (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2407
2408 #define CNL_REVID_A0            0x0
2409 #define CNL_REVID_B0            0x1
2410 #define CNL_REVID_C0            0x2
2411
2412 #define IS_CNL_REVID(p, since, until) \
2413         (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2414
2415 #define ICL_REVID_A0            0x0
2416 #define ICL_REVID_A2            0x1
2417 #define ICL_REVID_B0            0x3
2418 #define ICL_REVID_B2            0x4
2419 #define ICL_REVID_C0            0x5
2420
2421 #define IS_ICL_REVID(p, since, until) \
2422         (IS_ICELAKE(p) && IS_REVID(p, since, until))
2423
2424 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2425 #define IS_GEN9_LP(dev_priv)    (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2426 #define IS_GEN9_BC(dev_priv)    (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2427
2428 #define ENGINE_MASK(id) BIT(id)
2429 #define RENDER_RING     ENGINE_MASK(RCS)
2430 #define BSD_RING        ENGINE_MASK(VCS)
2431 #define BLT_RING        ENGINE_MASK(BCS)
2432 #define VEBOX_RING      ENGINE_MASK(VECS)
2433 #define BSD2_RING       ENGINE_MASK(VCS2)
2434 #define BSD3_RING       ENGINE_MASK(VCS3)
2435 #define BSD4_RING       ENGINE_MASK(VCS4)
2436 #define VEBOX2_RING     ENGINE_MASK(VECS2)
2437 #define ALL_ENGINES     (~0)
2438
2439 #define HAS_ENGINE(dev_priv, id) \
2440         (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2441
2442 #define HAS_BSD(dev_priv)       HAS_ENGINE(dev_priv, VCS)
2443 #define HAS_BSD2(dev_priv)      HAS_ENGINE(dev_priv, VCS2)
2444 #define HAS_BLT(dev_priv)       HAS_ENGINE(dev_priv, BCS)
2445 #define HAS_VEBOX(dev_priv)     HAS_ENGINE(dev_priv, VECS)
2446
2447 #define HAS_LLC(dev_priv)       (INTEL_INFO(dev_priv)->has_llc)
2448 #define HAS_SNOOP(dev_priv)     (INTEL_INFO(dev_priv)->has_snoop)
2449 #define HAS_EDRAM(dev_priv)     (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2450 #define HAS_WT(dev_priv)        ((IS_HASWELL(dev_priv) || \
2451                                  IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2452
2453 #define HWS_NEEDS_PHYSICAL(dev_priv)    (INTEL_INFO(dev_priv)->hws_needs_physical)
2454
2455 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2456                 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2457 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2458                 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2459 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2460                 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2461
2462 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2463
2464 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
2465 #define HAS_PPGTT(dev_priv) \
2466         (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2467 #define HAS_FULL_PPGTT(dev_priv) \
2468         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2469 #define HAS_FULL_48BIT_PPGTT(dev_priv)  \
2470         (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
2471
2472 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2473         GEM_BUG_ON((sizes) == 0); \
2474         ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2475 })
2476
2477 #define HAS_OVERLAY(dev_priv)            (INTEL_INFO(dev_priv)->display.has_overlay)
2478 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2479                 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2480
2481 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2482 #define HAS_BROKEN_CS_TLB(dev_priv)     (IS_I830(dev_priv) || IS_I845G(dev_priv))
2483
2484 /* WaRsDisableCoarsePowerGating:skl,cnl */
2485 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2486         (IS_CANNONLAKE(dev_priv) || \
2487          IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2488
2489 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2490 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2491                                         IS_GEMINILAKE(dev_priv) || \
2492                                         IS_KABYLAKE(dev_priv))
2493
2494 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2495  * rows, which changed the alignment requirements and fence programming.
2496  */
2497 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2498                                          !(IS_I915G(dev_priv) || \
2499                                          IS_I915GM(dev_priv)))
2500 #define SUPPORTS_TV(dev_priv)           (INTEL_INFO(dev_priv)->display.supports_tv)
2501 #define I915_HAS_HOTPLUG(dev_priv)      (INTEL_INFO(dev_priv)->display.has_hotplug)
2502
2503 #define HAS_FW_BLC(dev_priv)    (INTEL_GEN(dev_priv) > 2)
2504 #define HAS_FBC(dev_priv)       (INTEL_INFO(dev_priv)->display.has_fbc)
2505 #define HAS_CUR_FBC(dev_priv)   (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2506
2507 #define HAS_IPS(dev_priv)       (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2508
2509 #define HAS_DP_MST(dev_priv)    (INTEL_INFO(dev_priv)->display.has_dp_mst)
2510
2511 #define HAS_DDI(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ddi)
2512 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2513 #define HAS_PSR(dev_priv)                (INTEL_INFO(dev_priv)->display.has_psr)
2514
2515 #define HAS_RC6(dev_priv)                (INTEL_INFO(dev_priv)->has_rc6)
2516 #define HAS_RC6p(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6p)
2517 #define HAS_RC6pp(dev_priv)              (false) /* HW was never validated */
2518
2519 #define HAS_CSR(dev_priv)       (INTEL_INFO(dev_priv)->display.has_csr)
2520
2521 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2522 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2523
2524 #define HAS_IPC(dev_priv)                (INTEL_INFO(dev_priv)->display.has_ipc)
2525
2526 /*
2527  * For now, anything with a GuC requires uCode loading, and then supports
2528  * command submission once loaded. But these are logically independent
2529  * properties, so we have separate macros to test them.
2530  */
2531 #define HAS_GUC(dev_priv)       (INTEL_INFO(dev_priv)->has_guc)
2532 #define HAS_GUC_CT(dev_priv)    (INTEL_INFO(dev_priv)->has_guc_ct)
2533 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2534 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2535
2536 /* For now, anything with a GuC has also HuC */
2537 #define HAS_HUC(dev_priv)       (HAS_GUC(dev_priv))
2538 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2539
2540 /* Having a GuC is not the same as using a GuC */
2541 #define USES_GUC(dev_priv)              intel_uc_is_using_guc(dev_priv)
2542 #define USES_GUC_SUBMISSION(dev_priv)   intel_uc_is_using_guc_submission(dev_priv)
2543 #define USES_HUC(dev_priv)              intel_uc_is_using_huc(dev_priv)
2544
2545 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2546
2547 #define INTEL_PCH_DEVICE_ID_MASK                0xff80
2548 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2549 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2550 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2551 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2552 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2553 #define INTEL_PCH_WPT_DEVICE_ID_TYPE            0x8c80
2554 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE         0x9c80
2555 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2556 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2557 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA280
2558 #define INTEL_PCH_CNP_DEVICE_ID_TYPE            0xA300
2559 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE         0x9D80
2560 #define INTEL_PCH_ICP_DEVICE_ID_TYPE            0x3480
2561 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
2562 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
2563 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
2564
2565 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2566 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2567 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2568 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2569 #define HAS_PCH_CNP_LP(dev_priv) \
2570         (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2571 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2572 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2573 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2574 #define HAS_PCH_LPT_LP(dev_priv) \
2575         (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2576          INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2577 #define HAS_PCH_LPT_H(dev_priv) \
2578         (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2579          INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2580 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2581 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2582 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2583 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2584
2585 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2586
2587 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2588
2589 /* DPF == dynamic parity feature */
2590 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2591 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2592                                  2 : HAS_L3_DPF(dev_priv))
2593
2594 #define GT_FREQUENCY_MULTIPLIER 50
2595 #define GEN9_FREQ_SCALER 3
2596
2597 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2598
2599 #include "i915_trace.h"
2600
2601 static inline bool intel_vtd_active(void)
2602 {
2603 #ifdef CONFIG_INTEL_IOMMU
2604         if (intel_iommu_gfx_mapped)
2605                 return true;
2606 #endif
2607         return false;
2608 }
2609
2610 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2611 {
2612         return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2613 }
2614
2615 static inline bool
2616 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2617 {
2618         return IS_BROXTON(dev_priv) && intel_vtd_active();
2619 }
2620
2621 /* i915_drv.c */
2622 void __printf(3, 4)
2623 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2624               const char *fmt, ...);
2625
2626 #define i915_report_error(dev_priv, fmt, ...)                              \
2627         __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2628
2629 #ifdef CONFIG_COMPAT
2630 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2631                               unsigned long arg);
2632 #else
2633 #define i915_compat_ioctl NULL
2634 #endif
2635 extern const struct dev_pm_ops i915_pm_ops;
2636
2637 extern int i915_driver_load(struct pci_dev *pdev,
2638                             const struct pci_device_id *ent);
2639 extern void i915_driver_unload(struct drm_device *dev);
2640
2641 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2642 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2643 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2644 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2645 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2646 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2647 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2648
2649 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2650 int intel_engines_init(struct drm_i915_private *dev_priv);
2651
2652 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2653
2654 /* intel_hotplug.c */
2655 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2656                            u32 pin_mask, u32 long_mask);
2657 void intel_hpd_init(struct drm_i915_private *dev_priv);
2658 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2659 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2660 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2661                                    enum port port);
2662 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2663 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2664
2665 /* i915_irq.c */
2666 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2667 {
2668         unsigned long delay;
2669
2670         if (unlikely(!i915_modparams.enable_hangcheck))
2671                 return;
2672
2673         /* Don't continually defer the hangcheck so that it is always run at
2674          * least once after work has been scheduled on any ring. Otherwise,
2675          * we will ignore a hung ring if a second ring is kept busy.
2676          */
2677
2678         delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2679         queue_delayed_work(system_long_wq,
2680                            &dev_priv->gpu_error.hangcheck_work, delay);
2681 }
2682
2683 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2684 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2685 int intel_irq_install(struct drm_i915_private *dev_priv);
2686 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2687
2688 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2689 {
2690         return dev_priv->gvt;
2691 }
2692
2693 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2694 {
2695         return dev_priv->vgpu.active;
2696 }
2697
2698 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2699                               enum pipe pipe);
2700 void
2701 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2702                      u32 status_mask);
2703
2704 void
2705 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2706                       u32 status_mask);
2707
2708 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2709 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2710 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2711                                    u32 mask,
2712                                    u32 bits);
2713 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2714                             u32 interrupt_mask,
2715                             u32 enabled_irq_mask);
2716 static inline void
2717 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2718 {
2719         ilk_update_display_irq(dev_priv, bits, bits);
2720 }
2721 static inline void
2722 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
2723 {
2724         ilk_update_display_irq(dev_priv, bits, 0);
2725 }
2726 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2727                          enum pipe pipe,
2728                          u32 interrupt_mask,
2729                          u32 enabled_irq_mask);
2730 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2731                                        enum pipe pipe, u32 bits)
2732 {
2733         bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2734 }
2735 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2736                                         enum pipe pipe, u32 bits)
2737 {
2738         bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2739 }
2740 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2741                                   u32 interrupt_mask,
2742                                   u32 enabled_irq_mask);
2743 static inline void
2744 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2745 {
2746         ibx_display_interrupt_update(dev_priv, bits, bits);
2747 }
2748 static inline void
2749 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
2750 {
2751         ibx_display_interrupt_update(dev_priv, bits, 0);
2752 }
2753
2754 /* i915_gem.c */
2755 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2756                           struct drm_file *file_priv);
2757 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2758                          struct drm_file *file_priv);
2759 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2760                           struct drm_file *file_priv);
2761 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2762                         struct drm_file *file_priv);
2763 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2764                         struct drm_file *file_priv);
2765 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2766                               struct drm_file *file_priv);
2767 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2768                              struct drm_file *file_priv);
2769 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2770                               struct drm_file *file_priv);
2771 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2772                                struct drm_file *file_priv);
2773 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2774                         struct drm_file *file_priv);
2775 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2776                                struct drm_file *file);
2777 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2778                                struct drm_file *file);
2779 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2780                             struct drm_file *file_priv);
2781 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2782                            struct drm_file *file_priv);
2783 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2784                               struct drm_file *file_priv);
2785 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2786                               struct drm_file *file_priv);
2787 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2788 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2789 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2790                            struct drm_file *file);
2791 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2792                                 struct drm_file *file_priv);
2793 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2794                         struct drm_file *file_priv);
2795 void i915_gem_sanitize(struct drm_i915_private *i915);
2796 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2797 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2798 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2799 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2800 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2801
2802 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2803 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2804 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2805                          const struct drm_i915_gem_object_ops *ops);
2806 struct drm_i915_gem_object *
2807 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2808 struct drm_i915_gem_object *
2809 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2810                                  const void *data, size_t size);
2811 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2812 void i915_gem_free_object(struct drm_gem_object *obj);
2813
2814 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2815 {
2816         if (!atomic_read(&i915->mm.free_count))
2817                 return;
2818
2819         /* A single pass should suffice to release all the freed objects (along
2820          * most call paths) , but be a little more paranoid in that freeing
2821          * the objects does take a little amount of time, during which the rcu
2822          * callbacks could have added new objects into the freed list, and
2823          * armed the work again.
2824          */
2825         do {
2826                 rcu_barrier();
2827         } while (flush_work(&i915->mm.free_work));
2828 }
2829
2830 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2831 {
2832         /*
2833          * Similar to objects above (see i915_gem_drain_freed-objects), in
2834          * general we have workers that are armed by RCU and then rearm
2835          * themselves in their callbacks. To be paranoid, we need to
2836          * drain the workqueue a second time after waiting for the RCU
2837          * grace period so that we catch work queued via RCU from the first
2838          * pass. As neither drain_workqueue() nor flush_workqueue() report
2839          * a result, we make an assumption that we only don't require more
2840          * than 2 passes to catch all recursive RCU delayed work.
2841          *
2842          */
2843         int pass = 2;
2844         do {
2845                 rcu_barrier();
2846                 drain_workqueue(i915->wq);
2847         } while (--pass);
2848 }
2849
2850 struct i915_vma * __must_check
2851 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2852                          const struct i915_ggtt_view *view,
2853                          u64 size,
2854                          u64 alignment,
2855                          u64 flags);
2856
2857 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2858 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2859
2860 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2861
2862 static inline int __sg_page_count(const struct scatterlist *sg)
2863 {
2864         return sg->length >> PAGE_SHIFT;
2865 }
2866
2867 struct scatterlist *
2868 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2869                        unsigned int n, unsigned int *offset);
2870
2871 struct page *
2872 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2873                          unsigned int n);
2874
2875 struct page *
2876 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2877                                unsigned int n);
2878
2879 dma_addr_t
2880 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2881                                 unsigned long n);
2882
2883 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2884                                  struct sg_table *pages,
2885                                  unsigned int sg_page_sizes);
2886 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2887
2888 static inline int __must_check
2889 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2890 {
2891         might_lock(&obj->mm.lock);
2892
2893         if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2894                 return 0;
2895
2896         return __i915_gem_object_get_pages(obj);
2897 }
2898
2899 static inline bool
2900 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2901 {
2902         return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2903 }
2904
2905 static inline void
2906 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2907 {
2908         GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2909
2910         atomic_inc(&obj->mm.pages_pin_count);
2911 }
2912
2913 static inline bool
2914 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
2915 {
2916         return atomic_read(&obj->mm.pages_pin_count);
2917 }
2918
2919 static inline void
2920 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2921 {
2922         GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2923         GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
2924
2925         atomic_dec(&obj->mm.pages_pin_count);
2926 }
2927
2928 static inline void
2929 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2930 {
2931         __i915_gem_object_unpin_pages(obj);
2932 }
2933
2934 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */
2935         I915_MM_NORMAL = 0,
2936         I915_MM_SHRINKER /* called "recursively" from direct-reclaim-esque */
2937 };
2938
2939 int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2940                                 enum i915_mm_subclass subclass);
2941 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
2942
2943 enum i915_map_type {
2944         I915_MAP_WB = 0,
2945         I915_MAP_WC,
2946 #define I915_MAP_OVERRIDE BIT(31)
2947         I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
2948         I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
2949 };
2950
2951 static inline enum i915_map_type
2952 i915_coherent_map_type(struct drm_i915_private *i915)
2953 {
2954         return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2955 }
2956
2957 /**
2958  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2959  * @obj: the object to map into kernel address space
2960  * @type: the type of mapping, used to select pgprot_t
2961  *
2962  * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
2963  * pages and then returns a contiguous mapping of the backing storage into
2964  * the kernel address space. Based on the @type of mapping, the PTE will be
2965  * set to either WriteBack or WriteCombine (via pgprot_t).
2966  *
2967  * The caller is responsible for calling i915_gem_object_unpin_map() when the
2968  * mapping is no longer required.
2969  *
2970  * Returns the pointer through which to access the mapped object, or an
2971  * ERR_PTR() on error.
2972  */
2973 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2974                                            enum i915_map_type type);
2975
2976 /**
2977  * i915_gem_object_unpin_map - releases an earlier mapping
2978  * @obj: the object to unmap
2979  *
2980  * After pinning the object and mapping its pages, once you are finished
2981  * with your access, call i915_gem_object_unpin_map() to release the pin
2982  * upon the mapping. Once the pin count reaches zero, that mapping may be
2983  * removed.
2984  */
2985 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
2986 {
2987         i915_gem_object_unpin_pages(obj);
2988 }
2989
2990 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2991                                     unsigned int *needs_clflush);
2992 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
2993                                      unsigned int *needs_clflush);
2994 #define CLFLUSH_BEFORE  BIT(0)
2995 #define CLFLUSH_AFTER   BIT(1)
2996 #define CLFLUSH_FLAGS   (CLFLUSH_BEFORE | CLFLUSH_AFTER)
2997
2998 static inline void
2999 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3000 {
3001         i915_gem_object_unpin_pages(obj);
3002 }
3003
3004 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3005 int i915_gem_dumb_create(struct drm_file *file_priv,
3006                          struct drm_device *dev,
3007                          struct drm_mode_create_dumb *args);
3008 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3009                       u32 handle, u64 *offset);
3010 int i915_gem_mmap_gtt_version(void);
3011
3012 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3013                        struct drm_i915_gem_object *new,
3014                        unsigned frontbuffer_bits);
3015
3016 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3017
3018 struct i915_request *
3019 i915_gem_find_active_request(struct intel_engine_cs *engine);
3020
3021 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3022 {
3023         return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3024 }
3025
3026 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3027 {
3028         return unlikely(test_bit(I915_WEDGED, &error->flags));
3029 }
3030
3031 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3032 {
3033         return i915_reset_backoff(error) | i915_terminally_wedged(error);
3034 }
3035
3036 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3037 {
3038         return READ_ONCE(error->reset_count);
3039 }
3040
3041 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3042                                           struct intel_engine_cs *engine)
3043 {
3044         return READ_ONCE(error->reset_engine_count[engine->id]);
3045 }
3046
3047 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3048 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3049
3050 void i915_gem_init_mmio(struct drm_i915_private *i915);
3051 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3052 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3053 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3054 void i915_gem_fini(struct drm_i915_private *dev_priv);
3055 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3056 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3057                            unsigned int flags, long timeout);
3058 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3059 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3060 void i915_gem_resume(struct drm_i915_private *dev_priv);
3061 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3062 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3063                          unsigned int flags,
3064                          long timeout,
3065                          struct intel_rps_client *rps);
3066 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3067                                   unsigned int flags,
3068                                   const struct i915_sched_attr *attr);
3069 #define I915_PRIORITY_DISPLAY I915_USER_PRIORITY(I915_PRIORITY_MAX)
3070
3071 int __must_check
3072 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3073 int __must_check
3074 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3075 int __must_check
3076 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3077 struct i915_vma * __must_check
3078 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3079                                      u32 alignment,
3080                                      const struct i915_ggtt_view *view,
3081                                      unsigned int flags);
3082 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3083 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3084                                 int align);
3085 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3086 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3087
3088 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3089                                     enum i915_cache_level cache_level);
3090
3091 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3092                                 struct dma_buf *dma_buf);
3093
3094 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3095                                 struct drm_gem_object *gem_obj, int flags);
3096
3097 static inline struct i915_hw_ppgtt *
3098 i915_vm_to_ppgtt(struct i915_address_space *vm)
3099 {
3100         return container_of(vm, struct i915_hw_ppgtt, vm);
3101 }
3102
3103 /* i915_gem_fence_reg.c */
3104 struct drm_i915_fence_reg *
3105 i915_reserve_fence(struct drm_i915_private *dev_priv);
3106 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3107
3108 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3109 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3110
3111 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3112 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3113                                        struct sg_table *pages);
3114 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3115                                          struct sg_table *pages);
3116
3117 static inline struct i915_gem_context *
3118 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3119 {
3120         return idr_find(&file_priv->context_idr, id);
3121 }
3122
3123 static inline struct i915_gem_context *
3124 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3125 {
3126         struct i915_gem_context *ctx;
3127
3128         rcu_read_lock();
3129         ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3130         if (ctx && !kref_get_unless_zero(&ctx->ref))
3131                 ctx = NULL;
3132         rcu_read_unlock();
3133
3134         return ctx;
3135 }
3136
3137 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3138                          struct drm_file *file);
3139 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3140                                struct drm_file *file);
3141 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3142                                   struct drm_file *file);
3143 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3144                             struct i915_gem_context *ctx,
3145                             u32 *reg_state);
3146
3147 /* i915_gem_evict.c */
3148 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3149                                           u64 min_size, u64 alignment,
3150                                           unsigned cache_level,
3151                                           u64 start, u64 end,
3152                                           unsigned flags);
3153 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3154                                          struct drm_mm_node *node,
3155                                          unsigned int flags);
3156 int i915_gem_evict_vm(struct i915_address_space *vm);
3157
3158 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3159
3160 /* belongs in i915_gem_gtt.h */
3161 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3162 {
3163         wmb();
3164         if (INTEL_GEN(dev_priv) < 6)
3165                 intel_gtt_chipset_flush();
3166 }
3167
3168 /* i915_gem_stolen.c */
3169 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3170                                 struct drm_mm_node *node, u64 size,
3171                                 unsigned alignment);
3172 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3173                                          struct drm_mm_node *node, u64 size,
3174                                          unsigned alignment, u64 start,
3175                                          u64 end);
3176 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3177                                  struct drm_mm_node *node);
3178 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3179 void i915_gem_cleanup_stolen(struct drm_i915_private *dev_priv);
3180 struct drm_i915_gem_object *
3181 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3182                               resource_size_t size);
3183 struct drm_i915_gem_object *
3184 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3185                                                resource_size_t stolen_offset,
3186                                                resource_size_t gtt_offset,
3187                                                resource_size_t size);
3188
3189 /* i915_gem_internal.c */
3190 struct drm_i915_gem_object *
3191 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3192                                 phys_addr_t size);
3193
3194 /* i915_gem_shrinker.c */
3195 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3196                               unsigned long target,
3197                               unsigned long *nr_scanned,
3198                               unsigned flags);
3199 #define I915_SHRINK_PURGEABLE 0x1
3200 #define I915_SHRINK_UNBOUND 0x2
3201 #define I915_SHRINK_BOUND 0x4
3202 #define I915_SHRINK_ACTIVE 0x8
3203 #define I915_SHRINK_VMAPS 0x10
3204 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3205 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3206 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3207 void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915,
3208                                     struct mutex *mutex);
3209
3210 /* i915_gem_tiling.c */