Merge tag 'pm-5.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42 #include <acpi/video.h>
43
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_irq.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
49
50 #include "i915_drv.h"
51 #include "i915_trace.h"
52 #include "i915_pmu.h"
53 #include "i915_reset.h"
54 #include "i915_query.h"
55 #include "i915_vgpu.h"
56 #include "intel_drv.h"
57 #include "intel_uc.h"
58 #include "intel_workarounds.h"
59
60 static struct drm_driver driver;
61
62 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
63 static unsigned int i915_load_fail_count;
64
65 bool __i915_inject_load_failure(const char *func, int line)
66 {
67         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
68                 return false;
69
70         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
71                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
72                          i915_modparams.inject_load_failure, func, line);
73                 i915_modparams.inject_load_failure = 0;
74                 return true;
75         }
76
77         return false;
78 }
79
80 bool i915_error_injected(void)
81 {
82         return i915_load_fail_count && !i915_modparams.inject_load_failure;
83 }
84
85 #endif
86
87 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
88 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
89                     "providing the dmesg log by booting with drm.debug=0xf"
90
91 void
92 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
93               const char *fmt, ...)
94 {
95         static bool shown_bug_once;
96         struct device *kdev = dev_priv->drm.dev;
97         bool is_error = level[1] <= KERN_ERR[1];
98         bool is_debug = level[1] == KERN_DEBUG[1];
99         struct va_format vaf;
100         va_list args;
101
102         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
103                 return;
104
105         va_start(args, fmt);
106
107         vaf.fmt = fmt;
108         vaf.va = &args;
109
110         if (is_error)
111                 dev_printk(level, kdev, "%pV", &vaf);
112         else
113                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
114                            __builtin_return_address(0), &vaf);
115
116         va_end(args);
117
118         if (is_error && !shown_bug_once) {
119                 /*
120                  * Ask the user to file a bug report for the error, except
121                  * if they may have caused the bug by fiddling with unsafe
122                  * module parameters.
123                  */
124                 if (!test_taint(TAINT_USER))
125                         dev_notice(kdev, "%s", FDO_BUG_MSG);
126                 shown_bug_once = true;
127         }
128 }
129
130 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
131 static enum intel_pch
132 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
133 {
134         switch (id) {
135         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
136                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
137                 WARN_ON(!IS_GEN(dev_priv, 5));
138                 return PCH_IBX;
139         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
140                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
141                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
142                 return PCH_CPT;
143         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
144                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
145                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
146                 /* PantherPoint is CPT compatible */
147                 return PCH_CPT;
148         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
149                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
150                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
151                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
152                 return PCH_LPT;
153         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
154                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
155                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
156                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
157                 return PCH_LPT;
158         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
159                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
160                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
161                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
162                 /* WildcatPoint is LPT compatible */
163                 return PCH_LPT;
164         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
165                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
166                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
167                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
168                 /* WildcatPoint is LPT compatible */
169                 return PCH_LPT;
170         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
171                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
173                 return PCH_SPT;
174         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
175                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
177                 return PCH_SPT;
178         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
179                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
180                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
181                         !IS_COFFEELAKE(dev_priv));
182                 return PCH_KBP;
183         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
184                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
186                 return PCH_CNP;
187         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
188                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
189                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
190                 return PCH_CNP;
191         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
192                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
193                 WARN_ON(!IS_ICELAKE(dev_priv));
194                 return PCH_ICP;
195         default:
196                 return PCH_NONE;
197         }
198 }
199
200 static bool intel_is_virt_pch(unsigned short id,
201                               unsigned short svendor, unsigned short sdevice)
202 {
203         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
204                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
205                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
206                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
207                  sdevice == PCI_SUBDEVICE_ID_QEMU));
208 }
209
210 static unsigned short
211 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
212 {
213         unsigned short id = 0;
214
215         /*
216          * In a virtualized passthrough environment we can be in a
217          * setup where the ISA bridge is not able to be passed through.
218          * In this case, a south bridge can be emulated and we have to
219          * make an educated guess as to which PCH is really there.
220          */
221
222         if (IS_GEN(dev_priv, 5))
223                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
224         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
225                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
226         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
227                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
228         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
229                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
230         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
231                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
232         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
233                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
234         else if (IS_ICELAKE(dev_priv))
235                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
236
237         if (id)
238                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
239         else
240                 DRM_DEBUG_KMS("Assuming no PCH\n");
241
242         return id;
243 }
244
245 static void intel_detect_pch(struct drm_i915_private *dev_priv)
246 {
247         struct pci_dev *pch = NULL;
248
249         /*
250          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
251          * make graphics device passthrough work easy for VMM, that only
252          * need to expose ISA bridge to let driver know the real hardware
253          * underneath. This is a requirement from virtualization team.
254          *
255          * In some virtualized environments (e.g. XEN), there is irrelevant
256          * ISA bridge in the system. To work reliably, we should scan trhough
257          * all the ISA bridge devices and check for the first match, instead
258          * of only checking the first one.
259          */
260         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
261                 unsigned short id;
262                 enum intel_pch pch_type;
263
264                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
265                         continue;
266
267                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
268
269                 pch_type = intel_pch_type(dev_priv, id);
270                 if (pch_type != PCH_NONE) {
271                         dev_priv->pch_type = pch_type;
272                         dev_priv->pch_id = id;
273                         break;
274                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
275                                          pch->subsystem_device)) {
276                         id = intel_virt_detect_pch(dev_priv);
277                         pch_type = intel_pch_type(dev_priv, id);
278
279                         /* Sanity check virtual PCH id */
280                         if (WARN_ON(id && pch_type == PCH_NONE))
281                                 id = 0;
282
283                         dev_priv->pch_type = pch_type;
284                         dev_priv->pch_id = id;
285                         break;
286                 }
287         }
288
289         /*
290          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
291          * display.
292          */
293         if (pch && !HAS_DISPLAY(dev_priv)) {
294                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
295                 dev_priv->pch_type = PCH_NOP;
296                 dev_priv->pch_id = 0;
297         }
298
299         if (!pch)
300                 DRM_DEBUG_KMS("No PCH found.\n");
301
302         pci_dev_put(pch);
303 }
304
305 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
306                                struct drm_file *file_priv)
307 {
308         struct drm_i915_private *dev_priv = to_i915(dev);
309         struct pci_dev *pdev = dev_priv->drm.pdev;
310         drm_i915_getparam_t *param = data;
311         int value;
312
313         switch (param->param) {
314         case I915_PARAM_IRQ_ACTIVE:
315         case I915_PARAM_ALLOW_BATCHBUFFER:
316         case I915_PARAM_LAST_DISPATCH:
317         case I915_PARAM_HAS_EXEC_CONSTANTS:
318                 /* Reject all old ums/dri params. */
319                 return -ENODEV;
320         case I915_PARAM_CHIPSET_ID:
321                 value = pdev->device;
322                 break;
323         case I915_PARAM_REVISION:
324                 value = pdev->revision;
325                 break;
326         case I915_PARAM_NUM_FENCES_AVAIL:
327                 value = dev_priv->num_fence_regs;
328                 break;
329         case I915_PARAM_HAS_OVERLAY:
330                 value = dev_priv->overlay ? 1 : 0;
331                 break;
332         case I915_PARAM_HAS_BSD:
333                 value = !!dev_priv->engine[VCS];
334                 break;
335         case I915_PARAM_HAS_BLT:
336                 value = !!dev_priv->engine[BCS];
337                 break;
338         case I915_PARAM_HAS_VEBOX:
339                 value = !!dev_priv->engine[VECS];
340                 break;
341         case I915_PARAM_HAS_BSD2:
342                 value = !!dev_priv->engine[VCS2];
343                 break;
344         case I915_PARAM_HAS_LLC:
345                 value = HAS_LLC(dev_priv);
346                 break;
347         case I915_PARAM_HAS_WT:
348                 value = HAS_WT(dev_priv);
349                 break;
350         case I915_PARAM_HAS_ALIASING_PPGTT:
351                 value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
352                 break;
353         case I915_PARAM_HAS_SEMAPHORES:
354                 value = 0;
355                 break;
356         case I915_PARAM_HAS_SECURE_BATCHES:
357                 value = capable(CAP_SYS_ADMIN);
358                 break;
359         case I915_PARAM_CMD_PARSER_VERSION:
360                 value = i915_cmd_parser_get_version(dev_priv);
361                 break;
362         case I915_PARAM_SUBSLICE_TOTAL:
363                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
364                 if (!value)
365                         return -ENODEV;
366                 break;
367         case I915_PARAM_EU_TOTAL:
368                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
369                 if (!value)
370                         return -ENODEV;
371                 break;
372         case I915_PARAM_HAS_GPU_RESET:
373                 value = i915_modparams.enable_hangcheck &&
374                         intel_has_gpu_reset(dev_priv);
375                 if (value && intel_has_reset_engine(dev_priv))
376                         value = 2;
377                 break;
378         case I915_PARAM_HAS_RESOURCE_STREAMER:
379                 value = 0;
380                 break;
381         case I915_PARAM_HAS_POOLED_EU:
382                 value = HAS_POOLED_EU(dev_priv);
383                 break;
384         case I915_PARAM_MIN_EU_IN_POOL:
385                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
386                 break;
387         case I915_PARAM_HUC_STATUS:
388                 value = intel_huc_check_status(&dev_priv->huc);
389                 if (value < 0)
390                         return value;
391                 break;
392         case I915_PARAM_MMAP_GTT_VERSION:
393                 /* Though we've started our numbering from 1, and so class all
394                  * earlier versions as 0, in effect their value is undefined as
395                  * the ioctl will report EINVAL for the unknown param!
396                  */
397                 value = i915_gem_mmap_gtt_version();
398                 break;
399         case I915_PARAM_HAS_SCHEDULER:
400                 value = dev_priv->caps.scheduler;
401                 break;
402
403         case I915_PARAM_MMAP_VERSION:
404                 /* Remember to bump this if the version changes! */
405         case I915_PARAM_HAS_GEM:
406         case I915_PARAM_HAS_PAGEFLIPPING:
407         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
408         case I915_PARAM_HAS_RELAXED_FENCING:
409         case I915_PARAM_HAS_COHERENT_RINGS:
410         case I915_PARAM_HAS_RELAXED_DELTA:
411         case I915_PARAM_HAS_GEN7_SOL_RESET:
412         case I915_PARAM_HAS_WAIT_TIMEOUT:
413         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
414         case I915_PARAM_HAS_PINNED_BATCHES:
415         case I915_PARAM_HAS_EXEC_NO_RELOC:
416         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
417         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
418         case I915_PARAM_HAS_EXEC_SOFTPIN:
419         case I915_PARAM_HAS_EXEC_ASYNC:
420         case I915_PARAM_HAS_EXEC_FENCE:
421         case I915_PARAM_HAS_EXEC_CAPTURE:
422         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
423         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
424                 /* For the time being all of these are always true;
425                  * if some supported hardware does not have one of these
426                  * features this value needs to be provided from
427                  * INTEL_INFO(), a feature macro, or similar.
428                  */
429                 value = 1;
430                 break;
431         case I915_PARAM_HAS_CONTEXT_ISOLATION:
432                 value = intel_engines_has_context_isolation(dev_priv);
433                 break;
434         case I915_PARAM_SLICE_MASK:
435                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
436                 if (!value)
437                         return -ENODEV;
438                 break;
439         case I915_PARAM_SUBSLICE_MASK:
440                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
441                 if (!value)
442                         return -ENODEV;
443                 break;
444         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
445                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
446                 break;
447         case I915_PARAM_MMAP_GTT_COHERENT:
448                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
449                 break;
450         default:
451                 DRM_DEBUG("Unknown parameter %d\n", param->param);
452                 return -EINVAL;
453         }
454
455         if (put_user(value, param->value))
456                 return -EFAULT;
457
458         return 0;
459 }
460
461 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
462 {
463         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
464
465         dev_priv->bridge_dev =
466                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
467         if (!dev_priv->bridge_dev) {
468                 DRM_ERROR("bridge device not found\n");
469                 return -1;
470         }
471         return 0;
472 }
473
474 /* Allocate space for the MCH regs if needed, return nonzero on error */
475 static int
476 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
477 {
478         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
479         u32 temp_lo, temp_hi = 0;
480         u64 mchbar_addr;
481         int ret;
482
483         if (INTEL_GEN(dev_priv) >= 4)
484                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
485         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
486         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
487
488         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
489 #ifdef CONFIG_PNP
490         if (mchbar_addr &&
491             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
492                 return 0;
493 #endif
494
495         /* Get some space for it */
496         dev_priv->mch_res.name = "i915 MCHBAR";
497         dev_priv->mch_res.flags = IORESOURCE_MEM;
498         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
499                                      &dev_priv->mch_res,
500                                      MCHBAR_SIZE, MCHBAR_SIZE,
501                                      PCIBIOS_MIN_MEM,
502                                      0, pcibios_align_resource,
503                                      dev_priv->bridge_dev);
504         if (ret) {
505                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
506                 dev_priv->mch_res.start = 0;
507                 return ret;
508         }
509
510         if (INTEL_GEN(dev_priv) >= 4)
511                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
512                                        upper_32_bits(dev_priv->mch_res.start));
513
514         pci_write_config_dword(dev_priv->bridge_dev, reg,
515                                lower_32_bits(dev_priv->mch_res.start));
516         return 0;
517 }
518
519 /* Setup MCHBAR if possible, return true if we should disable it again */
520 static void
521 intel_setup_mchbar(struct drm_i915_private *dev_priv)
522 {
523         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
524         u32 temp;
525         bool enabled;
526
527         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
528                 return;
529
530         dev_priv->mchbar_need_disable = false;
531
532         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
533                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
534                 enabled = !!(temp & DEVEN_MCHBAR_EN);
535         } else {
536                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
537                 enabled = temp & 1;
538         }
539
540         /* If it's already enabled, don't have to do anything */
541         if (enabled)
542                 return;
543
544         if (intel_alloc_mchbar_resource(dev_priv))
545                 return;
546
547         dev_priv->mchbar_need_disable = true;
548
549         /* Space is allocated or reserved, so enable it. */
550         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
551                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
552                                        temp | DEVEN_MCHBAR_EN);
553         } else {
554                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
555                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
556         }
557 }
558
559 static void
560 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
561 {
562         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
563
564         if (dev_priv->mchbar_need_disable) {
565                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
566                         u32 deven_val;
567
568                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
569                                               &deven_val);
570                         deven_val &= ~DEVEN_MCHBAR_EN;
571                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
572                                                deven_val);
573                 } else {
574                         u32 mchbar_val;
575
576                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
577                                               &mchbar_val);
578                         mchbar_val &= ~1;
579                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
580                                                mchbar_val);
581                 }
582         }
583
584         if (dev_priv->mch_res.start)
585                 release_resource(&dev_priv->mch_res);
586 }
587
588 /* true = enable decode, false = disable decoder */
589 static unsigned int i915_vga_set_decode(void *cookie, bool state)
590 {
591         struct drm_i915_private *dev_priv = cookie;
592
593         intel_modeset_vga_set_state(dev_priv, state);
594         if (state)
595                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
596                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
597         else
598                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
599 }
600
601 static int i915_resume_switcheroo(struct drm_device *dev);
602 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
603
604 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
605 {
606         struct drm_device *dev = pci_get_drvdata(pdev);
607         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
608
609         if (state == VGA_SWITCHEROO_ON) {
610                 pr_info("switched on\n");
611                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
612                 /* i915 resume handler doesn't set to D0 */
613                 pci_set_power_state(pdev, PCI_D0);
614                 i915_resume_switcheroo(dev);
615                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
616         } else {
617                 pr_info("switched off\n");
618                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
619                 i915_suspend_switcheroo(dev, pmm);
620                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
621         }
622 }
623
624 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
625 {
626         struct drm_device *dev = pci_get_drvdata(pdev);
627
628         /*
629          * FIXME: open_count is protected by drm_global_mutex but that would lead to
630          * locking inversion with the driver load path. And the access here is
631          * completely racy anyway. So don't bother with locking for now.
632          */
633         return dev->open_count == 0;
634 }
635
636 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
637         .set_gpu_state = i915_switcheroo_set_state,
638         .reprobe = NULL,
639         .can_switch = i915_switcheroo_can_switch,
640 };
641
642 static int i915_load_modeset_init(struct drm_device *dev)
643 {
644         struct drm_i915_private *dev_priv = to_i915(dev);
645         struct pci_dev *pdev = dev_priv->drm.pdev;
646         int ret;
647
648         if (i915_inject_load_failure())
649                 return -ENODEV;
650
651         if (HAS_DISPLAY(dev_priv)) {
652                 ret = drm_vblank_init(&dev_priv->drm,
653                                       INTEL_INFO(dev_priv)->num_pipes);
654                 if (ret)
655                         goto out;
656         }
657
658         intel_bios_init(dev_priv);
659
660         /* If we have > 1 VGA cards, then we need to arbitrate access
661          * to the common VGA resources.
662          *
663          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
664          * then we do not take part in VGA arbitration and the
665          * vga_client_register() fails with -ENODEV.
666          */
667         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
668         if (ret && ret != -ENODEV)
669                 goto out;
670
671         intel_register_dsm_handler();
672
673         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
674         if (ret)
675                 goto cleanup_vga_client;
676
677         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
678         intel_update_rawclk(dev_priv);
679
680         intel_power_domains_init_hw(dev_priv, false);
681
682         intel_csr_ucode_init(dev_priv);
683
684         ret = intel_irq_install(dev_priv);
685         if (ret)
686                 goto cleanup_csr;
687
688         intel_setup_gmbus(dev_priv);
689
690         /* Important: The output setup functions called by modeset_init need
691          * working irqs for e.g. gmbus and dp aux transfers. */
692         ret = intel_modeset_init(dev);
693         if (ret)
694                 goto cleanup_irq;
695
696         ret = i915_gem_init(dev_priv);
697         if (ret)
698                 goto cleanup_modeset;
699
700         intel_overlay_setup(dev_priv);
701
702         if (!HAS_DISPLAY(dev_priv))
703                 return 0;
704
705         ret = intel_fbdev_init(dev);
706         if (ret)
707                 goto cleanup_gem;
708
709         /* Only enable hotplug handling once the fbdev is fully set up. */
710         intel_hpd_init(dev_priv);
711
712         intel_init_ipc(dev_priv);
713
714         return 0;
715
716 cleanup_gem:
717         if (i915_gem_suspend(dev_priv))
718                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
719         i915_gem_fini(dev_priv);
720 cleanup_modeset:
721         intel_modeset_cleanup(dev);
722 cleanup_irq:
723         drm_irq_uninstall(dev);
724         intel_teardown_gmbus(dev_priv);
725 cleanup_csr:
726         intel_csr_ucode_fini(dev_priv);
727         intel_power_domains_fini_hw(dev_priv);
728         vga_switcheroo_unregister_client(pdev);
729 cleanup_vga_client:
730         vga_client_register(pdev, NULL, NULL, NULL);
731 out:
732         return ret;
733 }
734
735 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
736 {
737         struct apertures_struct *ap;
738         struct pci_dev *pdev = dev_priv->drm.pdev;
739         struct i915_ggtt *ggtt = &dev_priv->ggtt;
740         bool primary;
741         int ret;
742
743         ap = alloc_apertures(1);
744         if (!ap)
745                 return -ENOMEM;
746
747         ap->ranges[0].base = ggtt->gmadr.start;
748         ap->ranges[0].size = ggtt->mappable_end;
749
750         primary =
751                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
752
753         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
754
755         kfree(ap);
756
757         return ret;
758 }
759
760 #if !defined(CONFIG_VGA_CONSOLE)
761 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
762 {
763         return 0;
764 }
765 #elif !defined(CONFIG_DUMMY_CONSOLE)
766 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
767 {
768         return -ENODEV;
769 }
770 #else
771 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
772 {
773         int ret = 0;
774
775         DRM_INFO("Replacing VGA console driver\n");
776
777         console_lock();
778         if (con_is_bound(&vga_con))
779                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
780         if (ret == 0) {
781                 ret = do_unregister_con_driver(&vga_con);
782
783                 /* Ignore "already unregistered". */
784                 if (ret == -ENODEV)
785                         ret = 0;
786         }
787         console_unlock();
788
789         return ret;
790 }
791 #endif
792
793 static void intel_init_dpio(struct drm_i915_private *dev_priv)
794 {
795         /*
796          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
797          * CHV x1 PHY (DP/HDMI D)
798          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
799          */
800         if (IS_CHERRYVIEW(dev_priv)) {
801                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
802                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
803         } else if (IS_VALLEYVIEW(dev_priv)) {
804                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
805         }
806 }
807
808 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
809 {
810         /*
811          * The i915 workqueue is primarily used for batched retirement of
812          * requests (and thus managing bo) once the task has been completed
813          * by the GPU. i915_retire_requests() is called directly when we
814          * need high-priority retirement, such as waiting for an explicit
815          * bo.
816          *
817          * It is also used for periodic low-priority events, such as
818          * idle-timers and recording error state.
819          *
820          * All tasks on the workqueue are expected to acquire the dev mutex
821          * so there is no point in running more than one instance of the
822          * workqueue at any time.  Use an ordered one.
823          */
824         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
825         if (dev_priv->wq == NULL)
826                 goto out_err;
827
828         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
829         if (dev_priv->hotplug.dp_wq == NULL)
830                 goto out_free_wq;
831
832         return 0;
833
834 out_free_wq:
835         destroy_workqueue(dev_priv->wq);
836 out_err:
837         DRM_ERROR("Failed to allocate workqueues.\n");
838
839         return -ENOMEM;
840 }
841
842 static void i915_engines_cleanup(struct drm_i915_private *i915)
843 {
844         struct intel_engine_cs *engine;
845         enum intel_engine_id id;
846
847         for_each_engine(engine, i915, id)
848                 kfree(engine);
849 }
850
851 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
852 {
853         destroy_workqueue(dev_priv->hotplug.dp_wq);
854         destroy_workqueue(dev_priv->wq);
855 }
856
857 /*
858  * We don't keep the workarounds for pre-production hardware, so we expect our
859  * driver to fail on these machines in one way or another. A little warning on
860  * dmesg may help both the user and the bug triagers.
861  *
862  * Our policy for removing pre-production workarounds is to keep the
863  * current gen workarounds as a guide to the bring-up of the next gen
864  * (workarounds have a habit of persisting!). Anything older than that
865  * should be removed along with the complications they introduce.
866  */
867 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
868 {
869         bool pre = false;
870
871         pre |= IS_HSW_EARLY_SDV(dev_priv);
872         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
873         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
874         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
875
876         if (pre) {
877                 DRM_ERROR("This is a pre-production stepping. "
878                           "It may not be fully functional.\n");
879                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
880         }
881 }
882
883 /**
884  * i915_driver_init_early - setup state not requiring device access
885  * @dev_priv: device private
886  *
887  * Initialize everything that is a "SW-only" state, that is state not
888  * requiring accessing the device or exposing the driver via kernel internal
889  * or userspace interfaces. Example steps belonging here: lock initialization,
890  * system memory allocation, setting up device specific attributes and
891  * function hooks not requiring accessing the device.
892  */
893 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
894 {
895         int ret = 0;
896
897         if (i915_inject_load_failure())
898                 return -ENODEV;
899
900         spin_lock_init(&dev_priv->irq_lock);
901         spin_lock_init(&dev_priv->gpu_error.lock);
902         mutex_init(&dev_priv->backlight_lock);
903         spin_lock_init(&dev_priv->uncore.lock);
904
905         mutex_init(&dev_priv->sb_lock);
906         mutex_init(&dev_priv->av_mutex);
907         mutex_init(&dev_priv->wm.wm_mutex);
908         mutex_init(&dev_priv->pps_mutex);
909
910         i915_memcpy_init_early(dev_priv);
911         intel_runtime_pm_init_early(dev_priv);
912
913         ret = i915_workqueues_init(dev_priv);
914         if (ret < 0)
915                 goto err_engines;
916
917         ret = i915_gem_init_early(dev_priv);
918         if (ret < 0)
919                 goto err_workqueues;
920
921         /* This must be called before any calls to HAS_PCH_* */
922         intel_detect_pch(dev_priv);
923
924         intel_wopcm_init_early(&dev_priv->wopcm);
925         intel_uc_init_early(dev_priv);
926         intel_pm_setup(dev_priv);
927         intel_init_dpio(dev_priv);
928         ret = intel_power_domains_init(dev_priv);
929         if (ret < 0)
930                 goto err_uc;
931         intel_irq_init(dev_priv);
932         intel_hangcheck_init(dev_priv);
933         intel_init_display_hooks(dev_priv);
934         intel_init_clock_gating_hooks(dev_priv);
935         intel_init_audio_hooks(dev_priv);
936         intel_display_crc_init(dev_priv);
937
938         intel_detect_preproduction_hw(dev_priv);
939
940         return 0;
941
942 err_uc:
943         intel_uc_cleanup_early(dev_priv);
944         i915_gem_cleanup_early(dev_priv);
945 err_workqueues:
946         i915_workqueues_cleanup(dev_priv);
947 err_engines:
948         i915_engines_cleanup(dev_priv);
949         return ret;
950 }
951
952 /**
953  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
954  * @dev_priv: device private
955  */
956 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
957 {
958         intel_irq_fini(dev_priv);
959         intel_power_domains_cleanup(dev_priv);
960         intel_uc_cleanup_early(dev_priv);
961         i915_gem_cleanup_early(dev_priv);
962         i915_workqueues_cleanup(dev_priv);
963         i915_engines_cleanup(dev_priv);
964 }
965
966 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
967 {
968         struct pci_dev *pdev = dev_priv->drm.pdev;
969         int mmio_bar;
970         int mmio_size;
971
972         mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
973         /*
974          * Before gen4, the registers and the GTT are behind different BARs.
975          * However, from gen4 onwards, the registers and the GTT are shared
976          * in the same BAR, so we want to restrict this ioremap from
977          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
978          * the register BAR remains the same size for all the earlier
979          * generations up to Ironlake.
980          */
981         if (INTEL_GEN(dev_priv) < 5)
982                 mmio_size = 512 * 1024;
983         else
984                 mmio_size = 2 * 1024 * 1024;
985         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
986         if (dev_priv->regs == NULL) {
987                 DRM_ERROR("failed to map registers\n");
988
989                 return -EIO;
990         }
991
992         /* Try to make sure MCHBAR is enabled before poking at it */
993         intel_setup_mchbar(dev_priv);
994
995         return 0;
996 }
997
998 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
999 {
1000         struct pci_dev *pdev = dev_priv->drm.pdev;
1001
1002         intel_teardown_mchbar(dev_priv);
1003         pci_iounmap(pdev, dev_priv->regs);
1004 }
1005
1006 /**
1007  * i915_driver_init_mmio - setup device MMIO
1008  * @dev_priv: device private
1009  *
1010  * Setup minimal device state necessary for MMIO accesses later in the
1011  * initialization sequence. The setup here should avoid any other device-wide
1012  * side effects or exposing the driver via kernel internal or user space
1013  * interfaces.
1014  */
1015 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1016 {
1017         int ret;
1018
1019         if (i915_inject_load_failure())
1020                 return -ENODEV;
1021
1022         if (i915_get_bridge_dev(dev_priv))
1023                 return -EIO;
1024
1025         ret = i915_mmio_setup(dev_priv);
1026         if (ret < 0)
1027                 goto err_bridge;
1028
1029         intel_uncore_init(dev_priv);
1030
1031         intel_device_info_init_mmio(dev_priv);
1032
1033         intel_uncore_prune(dev_priv);
1034
1035         intel_uc_init_mmio(dev_priv);
1036
1037         ret = intel_engines_init_mmio(dev_priv);
1038         if (ret)
1039                 goto err_uncore;
1040
1041         i915_gem_init_mmio(dev_priv);
1042
1043         return 0;
1044
1045 err_uncore:
1046         intel_uncore_fini(dev_priv);
1047         i915_mmio_cleanup(dev_priv);
1048 err_bridge:
1049         pci_dev_put(dev_priv->bridge_dev);
1050
1051         return ret;
1052 }
1053
1054 /**
1055  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1056  * @dev_priv: device private
1057  */
1058 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1059 {
1060         intel_uncore_fini(dev_priv);
1061         i915_mmio_cleanup(dev_priv);
1062         pci_dev_put(dev_priv->bridge_dev);
1063 }
1064
1065 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1066 {
1067         intel_gvt_sanitize_options(dev_priv);
1068 }
1069
1070 static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1071 {
1072         if (size == 0)
1073                 return I915_DRAM_RANK_INVALID;
1074         if (rank == SKL_DRAM_RANK_SINGLE)
1075                 return I915_DRAM_RANK_SINGLE;
1076         else if (rank == SKL_DRAM_RANK_DUAL)
1077                 return I915_DRAM_RANK_DUAL;
1078
1079         return I915_DRAM_RANK_INVALID;
1080 }
1081
1082 static bool
1083 skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1084 {
1085         if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1086                 return true;
1087         else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1088                 return true;
1089         else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1090                 return true;
1091         else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1092                 return true;
1093
1094         return false;
1095 }
1096
1097 static int
1098 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1099 {
1100         u32 tmp_l, tmp_s;
1101         u32 s_val = val >> SKL_DRAM_S_SHIFT;
1102
1103         if (!val)
1104                 return -EINVAL;
1105
1106         tmp_l = val & SKL_DRAM_SIZE_MASK;
1107         tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1108
1109         if (tmp_l == 0 && tmp_s == 0)
1110                 return -EINVAL;
1111
1112         ch->l_info.size = tmp_l;
1113         ch->s_info.size = tmp_s;
1114
1115         tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1116         tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1117         ch->l_info.width = (1 << tmp_l) * 8;
1118         ch->s_info.width = (1 << tmp_s) * 8;
1119
1120         tmp_l = val & SKL_DRAM_RANK_MASK;
1121         tmp_s = s_val & SKL_DRAM_RANK_MASK;
1122         ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1123         ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1124
1125         if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1126             ch->s_info.rank == I915_DRAM_RANK_DUAL)
1127                 ch->rank = I915_DRAM_RANK_DUAL;
1128         else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1129                  ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1130                 ch->rank = I915_DRAM_RANK_DUAL;
1131         else
1132                 ch->rank = I915_DRAM_RANK_SINGLE;
1133
1134         ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1135                                             ch->l_info.width) ||
1136                            skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1137                                             ch->s_info.width);
1138
1139         DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1140                       ch->l_info.size, ch->l_info.width,
1141                       ch->l_info.rank ? "dual" : "single",
1142                       ch->s_info.size, ch->s_info.width,
1143                       ch->s_info.rank ? "dual" : "single");
1144
1145         return 0;
1146 }
1147
1148 static bool
1149 intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1150                         struct dram_channel_info *ch0)
1151 {
1152         return (val_ch0 == val_ch1 &&
1153                 (ch0->s_info.size == 0 ||
1154                  (ch0->l_info.size == ch0->s_info.size &&
1155                   ch0->l_info.width == ch0->s_info.width &&
1156                   ch0->l_info.rank == ch0->s_info.rank)));
1157 }
1158
1159 static int
1160 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1161 {
1162         struct dram_info *dram_info = &dev_priv->dram_info;
1163         struct dram_channel_info ch0, ch1;
1164         u32 val_ch0, val_ch1;
1165         int ret;
1166
1167         val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1168         ret = skl_dram_get_channel_info(&ch0, val_ch0);
1169         if (ret == 0)
1170                 dram_info->num_channels++;
1171
1172         val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1173         ret = skl_dram_get_channel_info(&ch1, val_ch1);
1174         if (ret == 0)
1175                 dram_info->num_channels++;
1176
1177         if (dram_info->num_channels == 0) {
1178                 DRM_INFO("Number of memory channels is zero\n");
1179                 return -EINVAL;
1180         }
1181
1182         /*
1183          * If any of the channel is single rank channel, worst case output
1184          * will be same as if single rank memory, so consider single rank
1185          * memory.
1186          */
1187         if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1188             ch1.rank == I915_DRAM_RANK_SINGLE)
1189                 dram_info->rank = I915_DRAM_RANK_SINGLE;
1190         else
1191                 dram_info->rank = max(ch0.rank, ch1.rank);
1192
1193         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1194                 DRM_INFO("couldn't get memory rank information\n");
1195                 return -EINVAL;
1196         }
1197
1198         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1199
1200         dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1201                                                                        val_ch1,
1202                                                                        &ch0);
1203
1204         DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1205                       dev_priv->dram_info.symmetric_memory ? "" : "not ");
1206         return 0;
1207 }
1208
1209 static int
1210 skl_get_dram_info(struct drm_i915_private *dev_priv)
1211 {
1212         struct dram_info *dram_info = &dev_priv->dram_info;
1213         u32 mem_freq_khz, val;
1214         int ret;
1215
1216         ret = skl_dram_get_channels_info(dev_priv);
1217         if (ret)
1218                 return ret;
1219
1220         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1221         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1222                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1223
1224         dram_info->bandwidth_kbps = dram_info->num_channels *
1225                                                         mem_freq_khz * 8;
1226
1227         if (dram_info->bandwidth_kbps == 0) {
1228                 DRM_INFO("Couldn't get system memory bandwidth\n");
1229                 return -EINVAL;
1230         }
1231
1232         dram_info->valid = true;
1233         return 0;
1234 }
1235
1236 static int
1237 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1238 {
1239         struct dram_info *dram_info = &dev_priv->dram_info;
1240         u32 dram_channels;
1241         u32 mem_freq_khz, val;
1242         u8 num_active_channels;
1243         int i;
1244
1245         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1246         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1247                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1248
1249         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1250         num_active_channels = hweight32(dram_channels);
1251
1252         /* Each active bit represents 4-byte channel */
1253         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1254
1255         if (dram_info->bandwidth_kbps == 0) {
1256                 DRM_INFO("Couldn't get system memory bandwidth\n");
1257                 return -EINVAL;
1258         }
1259
1260         /*
1261          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1262          */
1263         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1264                 u8 size, width;
1265                 enum dram_rank rank;
1266                 u32 tmp;
1267
1268                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1269                 if (val == 0xFFFFFFFF)
1270                         continue;
1271
1272                 dram_info->num_channels++;
1273                 tmp = val & BXT_DRAM_RANK_MASK;
1274
1275                 if (tmp == BXT_DRAM_RANK_SINGLE)
1276                         rank = I915_DRAM_RANK_SINGLE;
1277                 else if (tmp == BXT_DRAM_RANK_DUAL)
1278                         rank = I915_DRAM_RANK_DUAL;
1279                 else
1280                         rank = I915_DRAM_RANK_INVALID;
1281
1282                 tmp = val & BXT_DRAM_SIZE_MASK;
1283                 if (tmp == BXT_DRAM_SIZE_4GB)
1284                         size = 4;
1285                 else if (tmp == BXT_DRAM_SIZE_6GB)
1286                         size = 6;
1287                 else if (tmp == BXT_DRAM_SIZE_8GB)
1288                         size = 8;
1289                 else if (tmp == BXT_DRAM_SIZE_12GB)
1290                         size = 12;
1291                 else if (tmp == BXT_DRAM_SIZE_16GB)
1292                         size = 16;
1293                 else
1294                         size = 0;
1295
1296                 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1297                 width = (1 << tmp) * 8;
1298                 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1299                               width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1300                               rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1301
1302                 /*
1303                  * If any of the channel is single rank channel,
1304                  * worst case output will be same as if single rank
1305                  * memory, so consider single rank memory.
1306                  */
1307                 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1308                         dram_info->rank = rank;
1309                 else if (rank == I915_DRAM_RANK_SINGLE)
1310                         dram_info->rank = I915_DRAM_RANK_SINGLE;
1311         }
1312
1313         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1314                 DRM_INFO("couldn't get memory rank information\n");
1315                 return -EINVAL;
1316         }
1317
1318         dram_info->valid = true;
1319         return 0;
1320 }
1321
1322 static void
1323 intel_get_dram_info(struct drm_i915_private *dev_priv)
1324 {
1325         struct dram_info *dram_info = &dev_priv->dram_info;
1326         char bandwidth_str[32];
1327         int ret;
1328
1329         dram_info->valid = false;
1330         dram_info->rank = I915_DRAM_RANK_INVALID;
1331         dram_info->bandwidth_kbps = 0;
1332         dram_info->num_channels = 0;
1333
1334         /*
1335          * Assume 16Gb DIMMs are present until proven otherwise.
1336          * This is only used for the level 0 watermark latency
1337          * w/a which does not apply to bxt/glk.
1338          */
1339         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1340
1341         if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1342                 return;
1343
1344         /* Need to calculate bandwidth only for Gen9 */
1345         if (IS_BROXTON(dev_priv))
1346                 ret = bxt_get_dram_info(dev_priv);
1347         else if (IS_GEN(dev_priv, 9))
1348                 ret = skl_get_dram_info(dev_priv);
1349         else
1350                 ret = skl_dram_get_channels_info(dev_priv);
1351         if (ret)
1352                 return;
1353
1354         if (dram_info->bandwidth_kbps)
1355                 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1356         else
1357                 sprintf(bandwidth_str, "unknown");
1358         DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1359                       bandwidth_str, dram_info->num_channels);
1360         DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
1361                       (dram_info->rank == I915_DRAM_RANK_DUAL) ?
1362                       "dual" : "single", yesno(dram_info->is_16gb_dimm));
1363 }
1364
1365 /**
1366  * i915_driver_init_hw - setup state requiring device access
1367  * @dev_priv: device private
1368  *
1369  * Setup state that requires accessing the device, but doesn't require
1370  * exposing the driver via kernel internal or userspace interfaces.
1371  */
1372 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1373 {
1374         struct pci_dev *pdev = dev_priv->drm.pdev;
1375         int ret;
1376
1377         if (i915_inject_load_failure())
1378                 return -ENODEV;
1379
1380         intel_device_info_runtime_init(dev_priv);
1381
1382         if (HAS_PPGTT(dev_priv)) {
1383                 if (intel_vgpu_active(dev_priv) &&
1384                     !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
1385                         i915_report_error(dev_priv,
1386                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1387                         return -ENXIO;
1388                 }
1389         }
1390
1391         if (HAS_EXECLISTS(dev_priv)) {
1392                 /*
1393                  * Older GVT emulation depends upon intercepting CSB mmio,
1394                  * which we no longer use, preferring to use the HWSP cache
1395                  * instead.
1396                  */
1397                 if (intel_vgpu_active(dev_priv) &&
1398                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1399                         i915_report_error(dev_priv,
1400                                           "old vGPU host found, support for HWSP emulation required\n");
1401                         return -ENXIO;
1402                 }
1403         }
1404
1405         intel_sanitize_options(dev_priv);
1406
1407         i915_perf_init(dev_priv);
1408
1409         ret = i915_ggtt_probe_hw(dev_priv);
1410         if (ret)
1411                 goto err_perf;
1412
1413         /*
1414          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1415          * otherwise the vga fbdev driver falls over.
1416          */
1417         ret = i915_kick_out_firmware_fb(dev_priv);
1418         if (ret) {
1419                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1420                 goto err_ggtt;
1421         }
1422
1423         ret = i915_kick_out_vgacon(dev_priv);
1424         if (ret) {
1425                 DRM_ERROR("failed to remove conflicting VGA console\n");
1426                 goto err_ggtt;
1427         }
1428
1429         ret = i915_ggtt_init_hw(dev_priv);
1430         if (ret)
1431                 goto err_ggtt;
1432
1433         ret = i915_ggtt_enable_hw(dev_priv);
1434         if (ret) {
1435                 DRM_ERROR("failed to enable GGTT\n");
1436                 goto err_ggtt;
1437         }
1438
1439         pci_set_master(pdev);
1440
1441         /* overlay on gen2 is broken and can't address above 1G */
1442         if (IS_GEN(dev_priv, 2)) {
1443                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1444                 if (ret) {
1445                         DRM_ERROR("failed to set DMA mask\n");
1446
1447                         goto err_ggtt;
1448                 }
1449         }
1450
1451         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1452          * using 32bit addressing, overwriting memory if HWS is located
1453          * above 4GB.
1454          *
1455          * The documentation also mentions an issue with undefined
1456          * behaviour if any general state is accessed within a page above 4GB,
1457          * which also needs to be handled carefully.
1458          */
1459         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1460                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1461
1462                 if (ret) {
1463                         DRM_ERROR("failed to set DMA mask\n");
1464
1465                         goto err_ggtt;
1466                 }
1467         }
1468
1469         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1470                            PM_QOS_DEFAULT_VALUE);
1471
1472         intel_uncore_sanitize(dev_priv);
1473
1474         intel_gt_init_workarounds(dev_priv);
1475         i915_gem_load_init_fences(dev_priv);
1476
1477         /* On the 945G/GM, the chipset reports the MSI capability on the
1478          * integrated graphics even though the support isn't actually there
1479          * according to the published specs.  It doesn't appear to function
1480          * correctly in testing on 945G.
1481          * This may be a side effect of MSI having been made available for PEG
1482          * and the registers being closely associated.
1483          *
1484          * According to chipset errata, on the 965GM, MSI interrupts may
1485          * be lost or delayed, and was defeatured. MSI interrupts seem to
1486          * get lost on g4x as well, and interrupt delivery seems to stay
1487          * properly dead afterwards. So we'll just disable them for all
1488          * pre-gen5 chipsets.
1489          *
1490          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1491          * interrupts even when in MSI mode. This results in spurious
1492          * interrupt warnings if the legacy irq no. is shared with another
1493          * device. The kernel then disables that interrupt source and so
1494          * prevents the other device from working properly.
1495          */
1496         if (INTEL_GEN(dev_priv) >= 5) {
1497                 if (pci_enable_msi(pdev) < 0)
1498                         DRM_DEBUG_DRIVER("can't enable MSI");
1499         }
1500
1501         ret = intel_gvt_init(dev_priv);
1502         if (ret)
1503                 goto err_msi;
1504
1505         intel_opregion_setup(dev_priv);
1506         /*
1507          * Fill the dram structure to get the system raw bandwidth and
1508          * dram info. This will be used for memory latency calculation.
1509          */
1510         intel_get_dram_info(dev_priv);
1511
1512
1513         return 0;
1514
1515 err_msi:
1516         if (pdev->msi_enabled)
1517                 pci_disable_msi(pdev);
1518         pm_qos_remove_request(&dev_priv->pm_qos);
1519 err_ggtt:
1520         i915_ggtt_cleanup_hw(dev_priv);
1521 err_perf:
1522         i915_perf_fini(dev_priv);
1523         return ret;
1524 }
1525
1526 /**
1527  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1528  * @dev_priv: device private
1529  */
1530 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1531 {
1532         struct pci_dev *pdev = dev_priv->drm.pdev;
1533
1534         i915_perf_fini(dev_priv);
1535
1536         if (pdev->msi_enabled)
1537                 pci_disable_msi(pdev);
1538
1539         pm_qos_remove_request(&dev_priv->pm_qos);
1540         i915_ggtt_cleanup_hw(dev_priv);
1541 }
1542
1543 /**
1544  * i915_driver_register - register the driver with the rest of the system
1545  * @dev_priv: device private
1546  *
1547  * Perform any steps necessary to make the driver available via kernel
1548  * internal or userspace interfaces.
1549  */
1550 static void i915_driver_register(struct drm_i915_private *dev_priv)
1551 {
1552         struct drm_device *dev = &dev_priv->drm;
1553
1554         i915_gem_shrinker_register(dev_priv);
1555         i915_pmu_register(dev_priv);
1556
1557         /*
1558          * Notify a valid surface after modesetting,
1559          * when running inside a VM.
1560          */
1561         if (intel_vgpu_active(dev_priv))
1562                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1563
1564         /* Reveal our presence to userspace */
1565         if (drm_dev_register(dev, 0) == 0) {
1566                 i915_debugfs_register(dev_priv);
1567                 i915_setup_sysfs(dev_priv);
1568
1569                 /* Depends on sysfs having been initialized */
1570                 i915_perf_register(dev_priv);
1571         } else
1572                 DRM_ERROR("Failed to register driver for userspace access!\n");
1573
1574         if (HAS_DISPLAY(dev_priv)) {
1575                 /* Must be done after probing outputs */
1576                 intel_opregion_register(dev_priv);
1577                 acpi_video_register();
1578         }
1579
1580         if (IS_GEN(dev_priv, 5))
1581                 intel_gpu_ips_init(dev_priv);
1582
1583         intel_audio_init(dev_priv);
1584
1585         /*
1586          * Some ports require correctly set-up hpd registers for detection to
1587          * work properly (leading to ghost connected connector status), e.g. VGA
1588          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1589          * irqs are fully enabled. We do it last so that the async config
1590          * cannot run before the connectors are registered.
1591          */
1592         intel_fbdev_initial_config_async(dev);
1593
1594         /*
1595          * We need to coordinate the hotplugs with the asynchronous fbdev
1596          * configuration, for which we use the fbdev->async_cookie.
1597          */
1598         if (HAS_DISPLAY(dev_priv))
1599                 drm_kms_helper_poll_init(dev);
1600
1601         intel_power_domains_enable(dev_priv);
1602         intel_runtime_pm_enable(dev_priv);
1603 }
1604
1605 /**
1606  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1607  * @dev_priv: device private
1608  */
1609 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1610 {
1611         intel_runtime_pm_disable(dev_priv);
1612         intel_power_domains_disable(dev_priv);
1613
1614         intel_fbdev_unregister(dev_priv);
1615         intel_audio_deinit(dev_priv);
1616
1617         /*
1618          * After flushing the fbdev (incl. a late async config which will
1619          * have delayed queuing of a hotplug event), then flush the hotplug
1620          * events.
1621          */
1622         drm_kms_helper_poll_fini(&dev_priv->drm);
1623
1624         intel_gpu_ips_teardown();
1625         acpi_video_unregister();
1626         intel_opregion_unregister(dev_priv);
1627
1628         i915_perf_unregister(dev_priv);
1629         i915_pmu_unregister(dev_priv);
1630
1631         i915_teardown_sysfs(dev_priv);
1632         drm_dev_unregister(&dev_priv->drm);
1633
1634         i915_gem_shrinker_unregister(dev_priv);
1635 }
1636
1637 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1638 {
1639         if (drm_debug & DRM_UT_DRIVER) {
1640                 struct drm_printer p = drm_debug_printer("i915 device info:");
1641
1642                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1643                            INTEL_DEVID(dev_priv),
1644                            INTEL_REVID(dev_priv),
1645                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1646                            INTEL_GEN(dev_priv));
1647
1648                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1649                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1650         }
1651
1652         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1653                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1654         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1655                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1656         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1657                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1658 }
1659
1660 static struct drm_i915_private *
1661 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1662 {
1663         const struct intel_device_info *match_info =
1664                 (struct intel_device_info *)ent->driver_data;
1665         struct intel_device_info *device_info;
1666         struct drm_i915_private *i915;
1667         int err;
1668
1669         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1670         if (!i915)
1671                 return ERR_PTR(-ENOMEM);
1672
1673         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1674         if (err) {
1675                 kfree(i915);
1676                 return ERR_PTR(err);
1677         }
1678
1679         i915->drm.pdev = pdev;
1680         i915->drm.dev_private = i915;
1681         pci_set_drvdata(pdev, &i915->drm);
1682
1683         /* Setup the write-once "constant" device info */
1684         device_info = mkwrite_device_info(i915);
1685         memcpy(device_info, match_info, sizeof(*device_info));
1686         RUNTIME_INFO(i915)->device_id = pdev->device;
1687
1688         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1689                      BITS_PER_TYPE(device_info->platform_mask));
1690         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1691
1692         return i915;
1693 }
1694
1695 static void i915_driver_destroy(struct drm_i915_private *i915)
1696 {
1697         struct pci_dev *pdev = i915->drm.pdev;
1698
1699         drm_dev_fini(&i915->drm);
1700         kfree(i915);
1701
1702         /* And make sure we never chase our dangling pointer from pci_dev */
1703         pci_set_drvdata(pdev, NULL);
1704 }
1705
1706 /**
1707  * i915_driver_load - setup chip and create an initial config
1708  * @pdev: PCI device
1709  * @ent: matching PCI ID entry
1710  *
1711  * The driver load routine has to do several things:
1712  *   - drive output discovery via intel_modeset_init()
1713  *   - initialize the memory manager
1714  *   - allocate initial config memory
1715  *   - setup the DRM framebuffer with the allocated memory
1716  */
1717 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1718 {
1719         const struct intel_device_info *match_info =
1720                 (struct intel_device_info *)ent->driver_data;
1721         struct drm_i915_private *dev_priv;
1722         int ret;
1723
1724         dev_priv = i915_driver_create(pdev, ent);
1725         if (IS_ERR(dev_priv))
1726                 return PTR_ERR(dev_priv);
1727
1728         /* Disable nuclear pageflip by default on pre-ILK */
1729         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1730                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1731
1732         ret = pci_enable_device(pdev);
1733         if (ret)
1734                 goto out_fini;
1735
1736         ret = i915_driver_init_early(dev_priv);
1737         if (ret < 0)
1738                 goto out_pci_disable;
1739
1740         disable_rpm_wakeref_asserts(dev_priv);
1741
1742         ret = i915_driver_init_mmio(dev_priv);
1743         if (ret < 0)
1744                 goto out_runtime_pm_put;
1745
1746         ret = i915_driver_init_hw(dev_priv);
1747         if (ret < 0)
1748                 goto out_cleanup_mmio;
1749
1750         ret = i915_load_modeset_init(&dev_priv->drm);
1751         if (ret < 0)
1752                 goto out_cleanup_hw;
1753
1754         i915_driver_register(dev_priv);
1755
1756         enable_rpm_wakeref_asserts(dev_priv);
1757
1758         i915_welcome_messages(dev_priv);
1759
1760         return 0;
1761
1762 out_cleanup_hw:
1763         i915_driver_cleanup_hw(dev_priv);
1764 out_cleanup_mmio:
1765         i915_driver_cleanup_mmio(dev_priv);
1766 out_runtime_pm_put:
1767         enable_rpm_wakeref_asserts(dev_priv);
1768         i915_driver_cleanup_early(dev_priv);
1769 out_pci_disable:
1770         pci_disable_device(pdev);
1771 out_fini:
1772         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1773         i915_driver_destroy(dev_priv);
1774         return ret;
1775 }
1776
1777 void i915_driver_unload(struct drm_device *dev)
1778 {
1779         struct drm_i915_private *dev_priv = to_i915(dev);
1780         struct pci_dev *pdev = dev_priv->drm.pdev;
1781
1782         disable_rpm_wakeref_asserts(dev_priv);
1783
1784         i915_driver_unregister(dev_priv);
1785
1786         /* Flush any external code that still may be under the RCU lock */
1787         synchronize_rcu();
1788
1789         if (i915_gem_suspend(dev_priv))
1790                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1791
1792         drm_atomic_helper_shutdown(dev);
1793
1794         intel_gvt_cleanup(dev_priv);
1795
1796         intel_modeset_cleanup(dev);
1797
1798         intel_bios_cleanup(dev_priv);
1799
1800         vga_switcheroo_unregister_client(pdev);
1801         vga_client_register(pdev, NULL, NULL, NULL);
1802
1803         intel_csr_ucode_fini(dev_priv);
1804
1805         /* Free error state after interrupts are fully disabled. */
1806         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1807         i915_reset_error_state(dev_priv);
1808
1809         i915_gem_fini(dev_priv);
1810
1811         intel_power_domains_fini_hw(dev_priv);
1812
1813         i915_driver_cleanup_hw(dev_priv);
1814         i915_driver_cleanup_mmio(dev_priv);
1815
1816         enable_rpm_wakeref_asserts(dev_priv);
1817         intel_runtime_pm_cleanup(dev_priv);
1818 }
1819
1820 static void i915_driver_release(struct drm_device *dev)
1821 {
1822         struct drm_i915_private *dev_priv = to_i915(dev);
1823
1824         i915_driver_cleanup_early(dev_priv);
1825         i915_driver_destroy(dev_priv);
1826 }
1827
1828 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1829 {
1830         struct drm_i915_private *i915 = to_i915(dev);
1831         int ret;
1832
1833         ret = i915_gem_open(i915, file);
1834         if (ret)
1835                 return ret;
1836
1837         return 0;
1838 }
1839
1840 /**
1841  * i915_driver_lastclose - clean up after all DRM clients have exited
1842  * @dev: DRM device
1843  *
1844  * Take care of cleaning up after all DRM clients have exited.  In the
1845  * mode setting case, we want to restore the kernel's initial mode (just
1846  * in case the last client left us in a bad state).
1847  *
1848  * Additionally, in the non-mode setting case, we'll tear down the GTT
1849  * and DMA structures, since the kernel won't be using them, and clea
1850  * up any GEM state.
1851  */
1852 static void i915_driver_lastclose(struct drm_device *dev)
1853 {
1854         intel_fbdev_restore_mode(dev);
1855         vga_switcheroo_process_delayed_switch();
1856 }
1857
1858 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1859 {
1860         struct drm_i915_file_private *file_priv = file->driver_priv;
1861
1862         mutex_lock(&dev->struct_mutex);
1863         i915_gem_context_close(file);
1864         i915_gem_release(dev, file);
1865         mutex_unlock(&dev->struct_mutex);
1866
1867         kfree(file_priv);
1868 }
1869
1870 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1871 {
1872         struct drm_device *dev = &dev_priv->drm;
1873         struct intel_encoder *encoder;
1874
1875         drm_modeset_lock_all(dev);
1876         for_each_intel_encoder(dev, encoder)
1877                 if (encoder->suspend)
1878                         encoder->suspend(encoder);
1879         drm_modeset_unlock_all(dev);
1880 }
1881
1882 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1883                               bool rpm_resume);
1884 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1885
1886 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1887 {
1888 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1889         if (acpi_target_system_state() < ACPI_STATE_S3)
1890                 return true;
1891 #endif
1892         return false;
1893 }
1894
1895 static int i915_drm_prepare(struct drm_device *dev)
1896 {
1897         struct drm_i915_private *i915 = to_i915(dev);
1898         int err;
1899
1900         /*
1901          * NB intel_display_suspend() may issue new requests after we've
1902          * ostensibly marked the GPU as ready-to-sleep here. We need to
1903          * split out that work and pull it forward so that after point,
1904          * the GPU is not woken again.
1905          */
1906         err = i915_gem_suspend(i915);
1907         if (err)
1908                 dev_err(&i915->drm.pdev->dev,
1909                         "GEM idle failed, suspend/resume might fail\n");
1910
1911         return err;
1912 }
1913
1914 static int i915_drm_suspend(struct drm_device *dev)
1915 {
1916         struct drm_i915_private *dev_priv = to_i915(dev);
1917         struct pci_dev *pdev = dev_priv->drm.pdev;
1918         pci_power_t opregion_target_state;
1919
1920         disable_rpm_wakeref_asserts(dev_priv);
1921
1922         /* We do a lot of poking in a lot of registers, make sure they work
1923          * properly. */
1924         intel_power_domains_disable(dev_priv);
1925
1926         drm_kms_helper_poll_disable(dev);
1927
1928         pci_save_state(pdev);
1929
1930         intel_display_suspend(dev);
1931
1932         intel_dp_mst_suspend(dev_priv);
1933
1934         intel_runtime_pm_disable_interrupts(dev_priv);
1935         intel_hpd_cancel_work(dev_priv);
1936
1937         intel_suspend_encoders(dev_priv);
1938
1939         intel_suspend_hw(dev_priv);
1940
1941         i915_gem_suspend_gtt_mappings(dev_priv);
1942
1943         i915_save_state(dev_priv);
1944
1945         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1946         intel_opregion_suspend(dev_priv, opregion_target_state);
1947
1948         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1949
1950         dev_priv->suspend_count++;
1951
1952         intel_csr_ucode_suspend(dev_priv);
1953
1954         enable_rpm_wakeref_asserts(dev_priv);
1955
1956         return 0;
1957 }
1958
1959 static enum i915_drm_suspend_mode
1960 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1961 {
1962         if (hibernate)
1963                 return I915_DRM_SUSPEND_HIBERNATE;
1964
1965         if (suspend_to_idle(dev_priv))
1966                 return I915_DRM_SUSPEND_IDLE;
1967
1968         return I915_DRM_SUSPEND_MEM;
1969 }
1970
1971 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1972 {
1973         struct drm_i915_private *dev_priv = to_i915(dev);
1974         struct pci_dev *pdev = dev_priv->drm.pdev;
1975         int ret;
1976
1977         disable_rpm_wakeref_asserts(dev_priv);
1978
1979         i915_gem_suspend_late(dev_priv);
1980
1981         intel_uncore_suspend(dev_priv);
1982
1983         intel_power_domains_suspend(dev_priv,
1984                                     get_suspend_mode(dev_priv, hibernation));
1985
1986         ret = 0;
1987         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
1988                 bxt_enable_dc9(dev_priv);
1989         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1990                 hsw_enable_pc8(dev_priv);
1991         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1992                 ret = vlv_suspend_complete(dev_priv);
1993
1994         if (ret) {
1995                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1996                 intel_power_domains_resume(dev_priv);
1997
1998                 goto out;
1999         }
2000
2001         pci_disable_device(pdev);
2002         /*
2003          * During hibernation on some platforms the BIOS may try to access
2004          * the device even though it's already in D3 and hang the machine. So
2005          * leave the device in D0 on those platforms and hope the BIOS will
2006          * power down the device properly. The issue was seen on multiple old
2007          * GENs with different BIOS vendors, so having an explicit blacklist
2008          * is inpractical; apply the workaround on everything pre GEN6. The
2009          * platforms where the issue was seen:
2010          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2011          * Fujitsu FSC S7110
2012          * Acer Aspire 1830T
2013          */
2014         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2015                 pci_set_power_state(pdev, PCI_D3hot);
2016
2017 out:
2018         enable_rpm_wakeref_asserts(dev_priv);
2019         if (!dev_priv->uncore.user_forcewake.count)
2020                 intel_runtime_pm_cleanup(dev_priv);
2021
2022         return ret;
2023 }
2024
2025 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2026 {
2027         int error;
2028
2029         if (!dev) {
2030                 DRM_ERROR("dev: %p\n", dev);
2031                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2032                 return -ENODEV;
2033         }
2034
2035         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2036                          state.event != PM_EVENT_FREEZE))
2037                 return -EINVAL;
2038
2039         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2040                 return 0;
2041
2042         error = i915_drm_suspend(dev);
2043         if (error)
2044                 return error;
2045
2046         return i915_drm_suspend_late(dev, false);
2047 }
2048
2049 static int i915_drm_resume(struct drm_device *dev)
2050 {
2051         struct drm_i915_private *dev_priv = to_i915(dev);
2052         int ret;
2053
2054         disable_rpm_wakeref_asserts(dev_priv);
2055         intel_sanitize_gt_powersave(dev_priv);
2056
2057         i915_gem_sanitize(dev_priv);
2058
2059         ret = i915_ggtt_enable_hw(dev_priv);
2060         if (ret)
2061                 DRM_ERROR("failed to re-enable GGTT\n");
2062
2063         intel_csr_ucode_resume(dev_priv);
2064
2065         i915_restore_state(dev_priv);
2066         intel_pps_unlock_regs_wa(dev_priv);
2067
2068         intel_init_pch_refclk(dev_priv);
2069
2070         /*
2071          * Interrupts have to be enabled before any batches are run. If not the
2072          * GPU will hang. i915_gem_init_hw() will initiate batches to
2073          * update/restore the context.
2074          *
2075          * drm_mode_config_reset() needs AUX interrupts.
2076          *
2077          * Modeset enabling in intel_modeset_init_hw() also needs working
2078          * interrupts.
2079          */
2080         intel_runtime_pm_enable_interrupts(dev_priv);
2081
2082         drm_mode_config_reset(dev);
2083
2084         i915_gem_resume(dev_priv);
2085
2086         intel_modeset_init_hw(dev);
2087         intel_init_clock_gating(dev_priv);
2088
2089         spin_lock_irq(&dev_priv->irq_lock);
2090         if (dev_priv->display.hpd_irq_setup)
2091                 dev_priv->display.hpd_irq_setup(dev_priv);
2092         spin_unlock_irq(&dev_priv->irq_lock);
2093
2094         intel_dp_mst_resume(dev_priv);
2095
2096         intel_display_resume(dev);
2097
2098         drm_kms_helper_poll_enable(dev);
2099
2100         /*
2101          * ... but also need to make sure that hotplug processing
2102          * doesn't cause havoc. Like in the driver load code we don't
2103          * bother with the tiny race here where we might lose hotplug
2104          * notifications.
2105          * */
2106         intel_hpd_init(dev_priv);
2107
2108         intel_opregion_resume(dev_priv);
2109
2110         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2111
2112         intel_power_domains_enable(dev_priv);
2113
2114         enable_rpm_wakeref_asserts(dev_priv);
2115
2116         return 0;
2117 }
2118
2119 static int i915_drm_resume_early(struct drm_device *dev)
2120 {
2121         struct drm_i915_private *dev_priv = to_i915(dev);
2122         struct pci_dev *pdev = dev_priv->drm.pdev;
2123         int ret;
2124
2125         /*
2126          * We have a resume ordering issue with the snd-hda driver also
2127          * requiring our device to be power up. Due to the lack of a
2128          * parent/child relationship we currently solve this with an early
2129          * resume hook.
2130          *
2131          * FIXME: This should be solved with a special hdmi sink device or
2132          * similar so that power domains can be employed.
2133          */
2134
2135         /*
2136          * Note that we need to set the power state explicitly, since we
2137          * powered off the device during freeze and the PCI core won't power
2138          * it back up for us during thaw. Powering off the device during
2139          * freeze is not a hard requirement though, and during the
2140          * suspend/resume phases the PCI core makes sure we get here with the
2141          * device powered on. So in case we change our freeze logic and keep
2142          * the device powered we can also remove the following set power state
2143          * call.
2144          */
2145         ret = pci_set_power_state(pdev, PCI_D0);
2146         if (ret) {
2147                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2148                 return ret;
2149         }
2150
2151         /*
2152          * Note that pci_enable_device() first enables any parent bridge
2153          * device and only then sets the power state for this device. The
2154          * bridge enabling is a nop though, since bridge devices are resumed
2155          * first. The order of enabling power and enabling the device is
2156          * imposed by the PCI core as described above, so here we preserve the
2157          * same order for the freeze/thaw phases.
2158          *
2159          * TODO: eventually we should remove pci_disable_device() /
2160          * pci_enable_enable_device() from suspend/resume. Due to how they
2161          * depend on the device enable refcount we can't anyway depend on them
2162          * disabling/enabling the device.
2163          */
2164         if (pci_enable_device(pdev))
2165                 return -EIO;
2166
2167         pci_set_master(pdev);
2168
2169         disable_rpm_wakeref_asserts(dev_priv);
2170
2171         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2172                 ret = vlv_resume_prepare(dev_priv, false);
2173         if (ret)
2174                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2175                           ret);
2176
2177         intel_uncore_resume_early(dev_priv);
2178
2179         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2180                 gen9_sanitize_dc_state(dev_priv);
2181                 bxt_disable_dc9(dev_priv);
2182         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2183                 hsw_disable_pc8(dev_priv);
2184         }
2185
2186         intel_uncore_sanitize(dev_priv);
2187
2188         intel_power_domains_resume(dev_priv);
2189
2190         intel_engines_sanitize(dev_priv, true);
2191
2192         enable_rpm_wakeref_asserts(dev_priv);
2193
2194         return ret;
2195 }
2196
2197 static int i915_resume_switcheroo(struct drm_device *dev)
2198 {
2199         int ret;
2200
2201         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2202                 return 0;
2203
2204         ret = i915_drm_resume_early(dev);
2205         if (ret)
2206                 return ret;
2207
2208         return i915_drm_resume(dev);
2209 }
2210
2211 static int i915_pm_prepare(struct device *kdev)
2212 {
2213         struct pci_dev *pdev = to_pci_dev(kdev);
2214         struct drm_device *dev = pci_get_drvdata(pdev);
2215
2216         if (!dev) {
2217                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2218                 return -ENODEV;
2219         }
2220
2221         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2222                 return 0;
2223
2224         return i915_drm_prepare(dev);
2225 }
2226
2227 static int i915_pm_suspend(struct device *kdev)
2228 {
2229         struct pci_dev *pdev = to_pci_dev(kdev);
2230         struct drm_device *dev = pci_get_drvdata(pdev);
2231
2232         if (!dev) {
2233                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2234                 return -ENODEV;
2235         }
2236
2237         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2238                 return 0;
2239
2240         return i915_drm_suspend(dev);
2241 }
2242
2243 static int i915_pm_suspend_late(struct device *kdev)
2244 {
2245         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2246
2247         /*
2248          * We have a suspend ordering issue with the snd-hda driver also
2249          * requiring our device to be power up. Due to the lack of a
2250          * parent/child relationship we currently solve this with an late
2251          * suspend hook.
2252          *
2253          * FIXME: This should be solved with a special hdmi sink device or
2254          * similar so that power domains can be employed.
2255          */
2256         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2257                 return 0;
2258
2259         return i915_drm_suspend_late(dev, false);
2260 }
2261
2262 static int i915_pm_poweroff_late(struct device *kdev)
2263 {
2264         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2265
2266         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2267                 return 0;
2268
2269         return i915_drm_suspend_late(dev, true);
2270 }
2271
2272 static int i915_pm_resume_early(struct device *kdev)
2273 {
2274         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2275
2276         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2277                 return 0;
2278
2279         return i915_drm_resume_early(dev);
2280 }
2281
2282 static int i915_pm_resume(struct device *kdev)
2283 {
2284         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2285
2286         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2287                 return 0;
2288
2289         return i915_drm_resume(dev);
2290 }
2291
2292 /* freeze: before creating the hibernation_image */
2293 static int i915_pm_freeze(struct device *kdev)
2294 {
2295         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2296         int ret;
2297
2298         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2299                 ret = i915_drm_suspend(dev);
2300                 if (ret)
2301                         return ret;
2302         }
2303
2304         ret = i915_gem_freeze(kdev_to_i915(kdev));
2305         if (ret)
2306                 return ret;
2307
2308         return 0;
2309 }
2310
2311 static int i915_pm_freeze_late(struct device *kdev)
2312 {
2313         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2314         int ret;
2315
2316         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2317                 ret = i915_drm_suspend_late(dev, true);
2318                 if (ret)
2319                         return ret;
2320         }
2321
2322         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2323         if (ret)
2324                 return ret;
2325
2326         return 0;
2327 }
2328
2329 /* thaw: called after creating the hibernation image, but before turning off. */
2330 static int i915_pm_thaw_early(struct device *kdev)
2331 {
2332         return i915_pm_resume_early(kdev);
2333 }
2334
2335 static int i915_pm_thaw(struct device *kdev)
2336 {
2337         return i915_pm_resume(kdev);
2338 }
2339
2340 /* restore: called after loading the hibernation image. */
2341 static int i915_pm_restore_early(struct device *kdev)
2342 {
2343         return i915_pm_resume_early(kdev);
2344 }
2345
2346 static int i915_pm_restore(struct device *kdev)
2347 {
2348         return i915_pm_resume(kdev);
2349 }
2350
2351 /*
2352  * Save all Gunit registers that may be lost after a D3 and a subsequent
2353  * S0i[R123] transition. The list of registers needing a save/restore is
2354  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2355  * registers in the following way:
2356  * - Driver: saved/restored by the driver
2357  * - Punit : saved/restored by the Punit firmware
2358  * - No, w/o marking: no need to save/restore, since the register is R/O or
2359  *                    used internally by the HW in a way that doesn't depend
2360  *                    keeping the content across a suspend/resume.
2361  * - Debug : used for debugging
2362  *
2363  * We save/restore all registers marked with 'Driver', with the following
2364  * exceptions:
2365  * - Registers out of use, including also registers marked with 'Debug'.
2366  *   These have no effect on the driver's operation, so we don't save/restore
2367  *   them to reduce the overhead.
2368  * - Registers that are fully setup by an initialization function called from
2369  *   the resume path. For example many clock gating and RPS/RC6 registers.
2370  * - Registers that provide the right functionality with their reset defaults.
2371  *
2372  * TODO: Except for registers that based on the above 3 criteria can be safely
2373  * ignored, we save/restore all others, practically treating the HW context as
2374  * a black-box for the driver. Further investigation is needed to reduce the
2375  * saved/restored registers even further, by following the same 3 criteria.
2376  */
2377 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2378 {
2379         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2380         int i;
2381
2382         /* GAM 0x4000-0x4770 */
2383         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2384         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2385         s->arb_mode             = I915_READ(ARB_MODE);
2386         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2387         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2388
2389         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2390                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2391
2392         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2393         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2394
2395         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2396         s->ecochk               = I915_READ(GAM_ECOCHK);
2397         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2398         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2399
2400         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2401
2402         /* MBC 0x9024-0x91D0, 0x8500 */
2403         s->g3dctl               = I915_READ(VLV_G3DCTL);
2404         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2405         s->mbctl                = I915_READ(GEN6_MBCTL);
2406
2407         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2408         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2409         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2410         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2411         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2412         s->rstctl               = I915_READ(GEN6_RSTCTL);
2413         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2414
2415         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2416         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2417         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2418         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2419         s->ecobus               = I915_READ(ECOBUS);
2420         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2421         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2422         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2423         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2424         s->rcedata              = I915_READ(VLV_RCEDATA);
2425         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2426
2427         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2428         s->gt_imr               = I915_READ(GTIMR);
2429         s->gt_ier               = I915_READ(GTIER);
2430         s->pm_imr               = I915_READ(GEN6_PMIMR);
2431         s->pm_ier               = I915_READ(GEN6_PMIER);
2432
2433         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2434                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2435
2436         /* GT SA CZ domain, 0x100000-0x138124 */
2437         s->tilectl              = I915_READ(TILECTL);
2438         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2439         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2440         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2441         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2442
2443         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2444         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2445         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2446         s->pcbr                 = I915_READ(VLV_PCBR);
2447         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2448
2449         /*
2450          * Not saving any of:
2451          * DFT,         0x9800-0x9EC0
2452          * SARB,        0xB000-0xB1FC
2453          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2454          * PCI CFG
2455          */
2456 }
2457
2458 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2459 {
2460         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2461         u32 val;
2462         int i;
2463
2464         /* GAM 0x4000-0x4770 */
2465         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2466         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2467         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2468         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2469         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2470
2471         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2472                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2473
2474         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2475         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2476
2477         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2478         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2479         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2480         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2481
2482         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2483
2484         /* MBC 0x9024-0x91D0, 0x8500 */
2485         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2486         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2487         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2488
2489         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2490         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2491         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2492         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2493         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2494         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2495         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2496
2497         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2498         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2499         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2500         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2501         I915_WRITE(ECOBUS,              s->ecobus);
2502         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2503         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2504         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2505         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2506         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2507         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2508
2509         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2510         I915_WRITE(GTIMR,               s->gt_imr);
2511         I915_WRITE(GTIER,               s->gt_ier);
2512         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2513         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2514
2515         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2516                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2517
2518         /* GT SA CZ domain, 0x100000-0x138124 */
2519         I915_WRITE(TILECTL,                     s->tilectl);
2520         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2521         /*
2522          * Preserve the GT allow wake and GFX force clock bit, they are not
2523          * be restored, as they are used to control the s0ix suspend/resume
2524          * sequence by the caller.
2525          */
2526         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2527         val &= VLV_GTLC_ALLOWWAKEREQ;
2528         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2529         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2530
2531         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2532         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2533         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2534         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2535
2536         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2537
2538         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2539         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2540         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2541         I915_WRITE(VLV_PCBR,                    s->pcbr);
2542         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2543 }
2544
2545 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2546                                   u32 mask, u32 val)
2547 {
2548         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2549         u32 reg_value;
2550         int ret;
2551
2552         /* The HW does not like us polling for PW_STATUS frequently, so
2553          * use the sleeping loop rather than risk the busy spin within
2554          * intel_wait_for_register().
2555          *
2556          * Transitioning between RC6 states should be at most 2ms (see
2557          * valleyview_enable_rps) so use a 3ms timeout.
2558          */
2559         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2560
2561         /* just trace the final value */
2562         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2563
2564         return ret;
2565 }
2566
2567 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2568 {
2569         u32 val;
2570         int err;
2571
2572         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2573         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2574         if (force_on)
2575                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2576         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2577
2578         if (!force_on)
2579                 return 0;
2580
2581         err = intel_wait_for_register(dev_priv,
2582                                       VLV_GTLC_SURVIVABILITY_REG,
2583                                       VLV_GFX_CLK_STATUS_BIT,
2584                                       VLV_GFX_CLK_STATUS_BIT,
2585                                       20);
2586         if (err)
2587                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2588                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2589
2590         return err;
2591 }
2592
2593 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2594 {
2595         u32 mask;
2596         u32 val;
2597         int err;
2598
2599         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2600         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2601         if (allow)
2602                 val |= VLV_GTLC_ALLOWWAKEREQ;
2603         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2604         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2605
2606         mask = VLV_GTLC_ALLOWWAKEACK;
2607         val = allow ? mask : 0;
2608
2609         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2610         if (err)
2611                 DRM_ERROR("timeout disabling GT waking\n");
2612
2613         return err;
2614 }
2615
2616 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2617                                   bool wait_for_on)
2618 {
2619         u32 mask;
2620         u32 val;
2621
2622         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2623         val = wait_for_on ? mask : 0;
2624
2625         /*
2626          * RC6 transitioning can be delayed up to 2 msec (see
2627          * valleyview_enable_rps), use 3 msec for safety.
2628          *
2629          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2630          * reset and we are trying to force the machine to sleep.
2631          */
2632         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2633                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2634                                  onoff(wait_for_on));
2635 }
2636
2637 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2638 {
2639         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2640                 return;
2641
2642         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2643         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2644 }
2645
2646 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2647 {
2648         u32 mask;
2649         int err;
2650
2651         /*
2652          * Bspec defines the following GT well on flags as debug only, so
2653          * don't treat them as hard failures.
2654          */
2655         vlv_wait_for_gt_wells(dev_priv, false);
2656
2657         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2658         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2659
2660         vlv_check_no_gt_access(dev_priv);
2661
2662         err = vlv_force_gfx_clock(dev_priv, true);
2663         if (err)
2664                 goto err1;
2665
2666         err = vlv_allow_gt_wake(dev_priv, false);
2667         if (err)
2668                 goto err2;
2669
2670         if (!IS_CHERRYVIEW(dev_priv))
2671                 vlv_save_gunit_s0ix_state(dev_priv);
2672
2673         err = vlv_force_gfx_clock(dev_priv, false);
2674         if (err)
2675                 goto err2;
2676
2677         return 0;
2678
2679 err2:
2680         /* For safety always re-enable waking and disable gfx clock forcing */
2681         vlv_allow_gt_wake(dev_priv, true);
2682 err1:
2683         vlv_force_gfx_clock(dev_priv, false);
2684
2685         return err;
2686 }
2687
2688 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2689                                 bool rpm_resume)
2690 {
2691         int err;
2692         int ret;
2693
2694         /*
2695          * If any of the steps fail just try to continue, that's the best we
2696          * can do at this point. Return the first error code (which will also
2697          * leave RPM permanently disabled).
2698          */
2699         ret = vlv_force_gfx_clock(dev_priv, true);
2700
2701         if (!IS_CHERRYVIEW(dev_priv))
2702                 vlv_restore_gunit_s0ix_state(dev_priv);
2703
2704         err = vlv_allow_gt_wake(dev_priv, true);
2705         if (!ret)
2706                 ret = err;
2707
2708         err = vlv_force_gfx_clock(dev_priv, false);
2709         if (!ret)
2710                 ret = err;
2711
2712         vlv_check_no_gt_access(dev_priv);
2713
2714         if (rpm_resume)
2715                 intel_init_clock_gating(dev_priv);
2716
2717         return ret;
2718 }
2719
2720 static int intel_runtime_suspend(struct device *kdev)
2721 {
2722         struct pci_dev *pdev = to_pci_dev(kdev);
2723         struct drm_device *dev = pci_get_drvdata(pdev);
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         int ret;
2726
2727         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2728                 return -ENODEV;
2729
2730         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2731                 return -ENODEV;
2732
2733         DRM_DEBUG_KMS("Suspending device\n");
2734
2735         disable_rpm_wakeref_asserts(dev_priv);
2736
2737         /*
2738          * We are safe here against re-faults, since the fault handler takes
2739          * an RPM reference.
2740          */
2741         i915_gem_runtime_suspend(dev_priv);
2742
2743         intel_uc_suspend(dev_priv);
2744
2745         intel_runtime_pm_disable_interrupts(dev_priv);
2746
2747         intel_uncore_suspend(dev_priv);
2748
2749         ret = 0;
2750         if (INTEL_GEN(dev_priv) >= 11) {
2751                 icl_display_core_uninit(dev_priv);
2752                 bxt_enable_dc9(dev_priv);
2753         } else if (IS_GEN9_LP(dev_priv)) {
2754                 bxt_display_core_uninit(dev_priv);
2755                 bxt_enable_dc9(dev_priv);
2756         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2757                 hsw_enable_pc8(dev_priv);
2758         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2759                 ret = vlv_suspend_complete(dev_priv);
2760         }
2761
2762         if (ret) {
2763                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2764                 intel_uncore_runtime_resume(dev_priv);
2765
2766                 intel_runtime_pm_enable_interrupts(dev_priv);
2767
2768                 intel_uc_resume(dev_priv);
2769
2770                 i915_gem_init_swizzling(dev_priv);
2771                 i915_gem_restore_fences(dev_priv);
2772
2773                 enable_rpm_wakeref_asserts(dev_priv);
2774
2775                 return ret;
2776         }
2777
2778         enable_rpm_wakeref_asserts(dev_priv);
2779         intel_runtime_pm_cleanup(dev_priv);
2780
2781         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2782                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2783
2784         dev_priv->runtime_pm.suspended = true;
2785
2786         /*
2787          * FIXME: We really should find a document that references the arguments
2788          * used below!
2789          */
2790         if (IS_BROADWELL(dev_priv)) {
2791                 /*
2792                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2793                  * being detected, and the call we do at intel_runtime_resume()
2794                  * won't be able to restore them. Since PCI_D3hot matches the
2795                  * actual specification and appears to be working, use it.
2796                  */
2797                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2798         } else {
2799                 /*
2800                  * current versions of firmware which depend on this opregion
2801                  * notification have repurposed the D1 definition to mean
2802                  * "runtime suspended" vs. what you would normally expect (D3)
2803                  * to distinguish it from notifications that might be sent via
2804                  * the suspend path.
2805                  */
2806                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2807         }
2808
2809         assert_forcewakes_inactive(dev_priv);
2810
2811         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2812                 intel_hpd_poll_init(dev_priv);
2813
2814         DRM_DEBUG_KMS("Device suspended\n");
2815         return 0;
2816 }
2817
2818 static int intel_runtime_resume(struct device *kdev)
2819 {
2820         struct pci_dev *pdev = to_pci_dev(kdev);
2821         struct drm_device *dev = pci_get_drvdata(pdev);
2822         struct drm_i915_private *dev_priv = to_i915(dev);
2823         int ret = 0;
2824
2825         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2826                 return -ENODEV;
2827
2828         DRM_DEBUG_KMS("Resuming device\n");
2829
2830         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2831         disable_rpm_wakeref_asserts(dev_priv);
2832
2833         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2834         dev_priv->runtime_pm.suspended = false;
2835         if (intel_uncore_unclaimed_mmio(dev_priv))
2836                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2837
2838         if (INTEL_GEN(dev_priv) >= 11) {
2839                 bxt_disable_dc9(dev_priv);
2840                 icl_display_core_init(dev_priv, true);
2841                 if (dev_priv->csr.dmc_payload) {
2842                         if (dev_priv->csr.allowed_dc_mask &
2843                             DC_STATE_EN_UPTO_DC6)
2844                                 skl_enable_dc6(dev_priv);
2845                         else if (dev_priv->csr.allowed_dc_mask &
2846                                  DC_STATE_EN_UPTO_DC5)
2847                                 gen9_enable_dc5(dev_priv);
2848                 }
2849         } else if (IS_GEN9_LP(dev_priv)) {
2850                 bxt_disable_dc9(dev_priv);
2851                 bxt_display_core_init(dev_priv, true);
2852                 if (dev_priv->csr.dmc_payload &&
2853                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2854                         gen9_enable_dc5(dev_priv);
2855         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2856                 hsw_disable_pc8(dev_priv);
2857         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2858                 ret = vlv_resume_prepare(dev_priv, true);
2859         }
2860
2861         intel_uncore_runtime_resume(dev_priv);
2862
2863         intel_runtime_pm_enable_interrupts(dev_priv);
2864
2865         intel_uc_resume(dev_priv);
2866
2867         /*
2868          * No point of rolling back things in case of an error, as the best
2869          * we can do is to hope that things will still work (and disable RPM).
2870          */
2871         i915_gem_init_swizzling(dev_priv);
2872         i915_gem_restore_fences(dev_priv);
2873
2874         /*
2875          * On VLV/CHV display interrupts are part of the display
2876          * power well, so hpd is reinitialized from there. For
2877          * everyone else do it here.
2878          */
2879         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2880                 intel_hpd_init(dev_priv);
2881
2882         intel_enable_ipc(dev_priv);
2883
2884         enable_rpm_wakeref_asserts(dev_priv);
2885
2886         if (ret)
2887                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2888         else
2889                 DRM_DEBUG_KMS("Device resumed\n");
2890
2891         return ret;
2892 }
2893
2894 const struct dev_pm_ops i915_pm_ops = {
2895         /*
2896          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2897          * PMSG_RESUME]
2898          */
2899         .prepare = i915_pm_prepare,
2900         .suspend = i915_pm_suspend,
2901         .suspend_late = i915_pm_suspend_late,
2902         .resume_early = i915_pm_resume_early,
2903         .resume = i915_pm_resume,
2904
2905         /*
2906          * S4 event handlers
2907          * @freeze, @freeze_late    : called (1) before creating the
2908          *                            hibernation image [PMSG_FREEZE] and
2909          *                            (2) after rebooting, before restoring
2910          *                            the image [PMSG_QUIESCE]
2911          * @thaw, @thaw_early       : called (1) after creating the hibernation
2912          *                            image, before writing it [PMSG_THAW]
2913          *                            and (2) after failing to create or
2914          *                            restore the image [PMSG_RECOVER]
2915          * @poweroff, @poweroff_late: called after writing the hibernation
2916          *                            image, before rebooting [PMSG_HIBERNATE]
2917          * @restore, @restore_early : called after rebooting and restoring the
2918          *                            hibernation image [PMSG_RESTORE]
2919          */
2920         .freeze = i915_pm_freeze,
2921         .freeze_late = i915_pm_freeze_late,
2922         .thaw_early = i915_pm_thaw_early,
2923         .thaw = i915_pm_thaw,
2924         .poweroff = i915_pm_suspend,
2925         .poweroff_late = i915_pm_poweroff_late,
2926         .restore_early = i915_pm_restore_early,
2927         .restore = i915_pm_restore,
2928
2929         /* S0ix (via runtime suspend) event handlers */
2930         .runtime_suspend = intel_runtime_suspend,
2931         .runtime_resume = intel_runtime_resume,
2932 };
2933
2934 static const struct vm_operations_struct i915_gem_vm_ops = {
2935         .fault = i915_gem_fault,
2936         .open = drm_gem_vm_open,
2937         .close = drm_gem_vm_close,
2938 };
2939
2940 static const struct file_operations i915_driver_fops = {
2941         .owner = THIS_MODULE,
2942         .open = drm_open,
2943         .release = drm_release,
2944         .unlocked_ioctl = drm_ioctl,
2945         .mmap = drm_gem_mmap,
2946         .poll = drm_poll,
2947         .read = drm_read,
2948         .compat_ioctl = i915_compat_ioctl,
2949         .llseek = noop_llseek,
2950 };
2951
2952 static int
2953 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2954                           struct drm_file *file)
2955 {
2956         return -ENODEV;
2957 }
2958
2959 static const struct drm_ioctl_desc i915_ioctls[] = {
2960         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2961         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2962         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2963         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2964         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2965         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2966         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2967         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2968         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2969         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2970         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2971         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2972         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2973         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2974         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2975         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2976         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2977         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2978         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2979         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2980         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2981         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2982         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2983         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2984         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2985         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2986         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2987         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2988         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2989         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2990         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2991         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2992         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2993         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2994         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2995         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2996         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2997         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2998         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2999         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3000         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3001         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3002         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3003         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3004         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3005         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3006         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3007         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3008         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3009         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3010         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3011         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3012         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3013         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3014         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3015         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3016 };
3017
3018 static struct drm_driver driver = {
3019         /* Don't use MTRRs here; the Xserver or userspace app should
3020          * deal with them for Intel hardware.
3021          */
3022         .driver_features =
3023             DRIVER_GEM | DRIVER_PRIME |
3024             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3025         .release = i915_driver_release,
3026         .open = i915_driver_open,
3027         .lastclose = i915_driver_lastclose,
3028         .postclose = i915_driver_postclose,
3029
3030         .gem_close_object = i915_gem_close_object,
3031         .gem_free_object_unlocked = i915_gem_free_object,
3032         .gem_vm_ops = &i915_gem_vm_ops,
3033
3034         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3035         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3036         .gem_prime_export = i915_gem_prime_export,
3037         .gem_prime_import = i915_gem_prime_import,
3038
3039         .dumb_create = i915_gem_dumb_create,
3040         .dumb_map_offset = i915_gem_mmap_gtt,
3041         .ioctls = i915_ioctls,
3042         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3043         .fops = &i915_driver_fops,
3044         .name = DRIVER_NAME,
3045         .desc = DRIVER_DESC,
3046         .date = DRIVER_DATE,
3047         .major = DRIVER_MAJOR,
3048         .minor = DRIVER_MINOR,
3049         .patchlevel = DRIVER_PATCHLEVEL,
3050 };
3051
3052 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3053 #include "selftests/mock_drm.c"
3054 #endif