drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 return true;
  71         }
  72
  73         return false;
  74 }
  75 #endif
  76
  77 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  78 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  79                     "providing the dmesg log by booting with drm.debug=0xf"
  80
  81 void
  82 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  83               const char *fmt, ...)
  84 {
  85         static bool shown_bug_once;
  86         struct device *kdev = dev_priv->drm.dev;
  87         bool is_error = level[1] <= KERN_ERR[1];
  88         bool is_debug = level[1] == KERN_DEBUG[1];
  89         struct va_format vaf;
  90         va_list args;
  91
  92         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  93                 return;
  94
  95         va_start(args, fmt);
  96
  97         vaf.fmt = fmt;
  98         vaf.va = &args;
  99
 100         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 101                    __builtin_return_address(0), &vaf);
 102
 103         if (is_error && !shown_bug_once) {
 104                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 105                 shown_bug_once = true;
 106         }
 107
 108         va_end(args);
 109 }
 110
 111 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 112 {
 113 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 114         return i915_modparams.inject_load_failure &&
 115                i915_load_fail_count == i915_modparams.inject_load_failure;
 116 #else
 117         return false;
 118 #endif
 119 }
 120
 121 #define i915_load_error(dev_priv, fmt, ...)                                  \
 122         __i915_printk(dev_priv,                                              \
 123                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 124                       fmt, ##__VA_ARGS__)
 125
 126 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 127 static enum intel_pch
 128 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 129 {
 130         switch (id) {
 131         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 132                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 133                 WARN_ON(!IS_GEN5(dev_priv));
 134                 return PCH_IBX;
 135         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 136                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 137                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 138                 return PCH_CPT;
 139         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 140                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 141                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 142                 /* PantherPoint is CPT compatible */
 143                 return PCH_CPT;
 144         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 145                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 146                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 147                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 148                 return PCH_LPT;
 149         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 150                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 151                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 152                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 153                 return PCH_LPT;
 154         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 155                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 156                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 157                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 158                 /* WildcatPoint is LPT compatible */
 159                 return PCH_LPT;
 160         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 161                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 162                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 163                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 164                 /* WildcatPoint is LPT compatible */
 165                 return PCH_LPT;
 166         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 167                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 168                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 169                 return PCH_SPT;
 170         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 171                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 173                 return PCH_SPT;
 174         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 175                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 177                         !IS_COFFEELAKE(dev_priv));
 178                 return PCH_KBP;
 179         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 180                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 181                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 182                 return PCH_CNP;
 183         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 184                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 186                 return PCH_CNP;
 187         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 188                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 189                 WARN_ON(!IS_ICELAKE(dev_priv));
 190                 return PCH_ICP;
 191         default:
 192                 return PCH_NONE;
 193         }
 194 }
 195
 196 static bool intel_is_virt_pch(unsigned short id,
 197                               unsigned short svendor, unsigned short sdevice)
 198 {
 199         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 200                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 201                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 202                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 203                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 204 }
 205
 206 static unsigned short
 207 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 208 {
 209         unsigned short id = 0;
 210
 211         /*
 212          * In a virtualized passthrough environment we can be in a
 213          * setup where the ISA bridge is not able to be passed through.
 214          * In this case, a south bridge can be emulated and we have to
 215          * make an educated guess as to which PCH is really there.
 216          */
 217
 218         if (IS_GEN5(dev_priv))
 219                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 220         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 221                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 222         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 223                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 224         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 225                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 226         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 227                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 228         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 229                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 230
 231         if (id)
 232                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 233         else
 234                 DRM_DEBUG_KMS("Assuming no PCH\n");
 235
 236         return id;
 237 }
 238
 239 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 240 {
 241         struct pci_dev *pch = NULL;
 242
 243         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 244          * (which really amounts to a PCH but no South Display).
 245          */
 246         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 247                 dev_priv->pch_type = PCH_NOP;
 248                 return;
 249         }
 250
 251         /*
 252          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 253          * make graphics device passthrough work easy for VMM, that only
 254          * need to expose ISA bridge to let driver know the real hardware
 255          * underneath. This is a requirement from virtualization team.
 256          *
 257          * In some virtualized environments (e.g. XEN), there is irrelevant
 258          * ISA bridge in the system. To work reliably, we should scan trhough
 259          * all the ISA bridge devices and check for the first match, instead
 260          * of only checking the first one.
 261          */
 262         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 263                 unsigned short id;
 264                 enum intel_pch pch_type;
 265
 266                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 267                         continue;
 268
 269                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 270
 271                 pch_type = intel_pch_type(dev_priv, id);
 272                 if (pch_type != PCH_NONE) {
 273                         dev_priv->pch_type = pch_type;
 274                         dev_priv->pch_id = id;
 275                         break;
 276                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 277                                          pch->subsystem_device)) {
 278                         id = intel_virt_detect_pch(dev_priv);
 279                         if (id) {
 280                                 pch_type = intel_pch_type(dev_priv, id);
 281                                 if (WARN_ON(pch_type == PCH_NONE))
 282                                         pch_type = PCH_NOP;
 283                         } else {
 284                                 pch_type = PCH_NOP;
 285                         }
 286                         dev_priv->pch_type = pch_type;
 287                         dev_priv->pch_id = id;
 288                         break;
 289                 }
 290         }
 291         if (!pch)
 292                 DRM_DEBUG_KMS("No PCH found.\n");
 293
 294         pci_dev_put(pch);
 295 }
 296
 297 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 298                                struct drm_file *file_priv)
 299 {
 300         struct drm_i915_private *dev_priv = to_i915(dev);
 301         struct pci_dev *pdev = dev_priv->drm.pdev;
 302         drm_i915_getparam_t *param = data;
 303         int value;
 304
 305         switch (param->param) {
 306         case I915_PARAM_IRQ_ACTIVE:
 307         case I915_PARAM_ALLOW_BATCHBUFFER:
 308         case I915_PARAM_LAST_DISPATCH:
 309         case I915_PARAM_HAS_EXEC_CONSTANTS:
 310                 /* Reject all old ums/dri params. */
 311                 return -ENODEV;
 312         case I915_PARAM_CHIPSET_ID:
 313                 value = pdev->device;
 314                 break;
 315         case I915_PARAM_REVISION:
 316                 value = pdev->revision;
 317                 break;
 318         case I915_PARAM_NUM_FENCES_AVAIL:
 319                 value = dev_priv->num_fence_regs;
 320                 break;
 321         case I915_PARAM_HAS_OVERLAY:
 322                 value = dev_priv->overlay ? 1 : 0;
 323                 break;
 324         case I915_PARAM_HAS_BSD:
 325                 value = !!dev_priv->engine[VCS];
 326                 break;
 327         case I915_PARAM_HAS_BLT:
 328                 value = !!dev_priv->engine[BCS];
 329                 break;
 330         case I915_PARAM_HAS_VEBOX:
 331                 value = !!dev_priv->engine[VECS];
 332                 break;
 333         case I915_PARAM_HAS_BSD2:
 334                 value = !!dev_priv->engine[VCS2];
 335                 break;
 336         case I915_PARAM_HAS_LLC:
 337                 value = HAS_LLC(dev_priv);
 338                 break;
 339         case I915_PARAM_HAS_WT:
 340                 value = HAS_WT(dev_priv);
 341                 break;
 342         case I915_PARAM_HAS_ALIASING_PPGTT:
 343                 value = USES_PPGTT(dev_priv);
 344                 break;
 345         case I915_PARAM_HAS_SEMAPHORES:
 346                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 347                 break;
 348         case I915_PARAM_HAS_SECURE_BATCHES:
 349                 value = capable(CAP_SYS_ADMIN);
 350                 break;
 351         case I915_PARAM_CMD_PARSER_VERSION:
 352                 value = i915_cmd_parser_get_version(dev_priv);
 353                 break;
 354         case I915_PARAM_SUBSLICE_TOTAL:
 355                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 356                 if (!value)
 357                         return -ENODEV;
 358                 break;
 359         case I915_PARAM_EU_TOTAL:
 360                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_HAS_GPU_RESET:
 365                 value = i915_modparams.enable_hangcheck &&
 366                         intel_has_gpu_reset(dev_priv);
 367                 if (value && intel_has_reset_engine(dev_priv))
 368                         value = 2;
 369                 break;
 370         case I915_PARAM_HAS_RESOURCE_STREAMER:
 371                 value = HAS_RESOURCE_STREAMER(dev_priv);
 372                 break;
 373         case I915_PARAM_HAS_POOLED_EU:
 374                 value = HAS_POOLED_EU(dev_priv);
 375                 break;
 376         case I915_PARAM_MIN_EU_IN_POOL:
 377                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 378                 break;
 379         case I915_PARAM_HUC_STATUS:
 380                 intel_runtime_pm_get(dev_priv);
 381                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 382                 intel_runtime_pm_put(dev_priv);
 383                 break;
 384         case I915_PARAM_MMAP_GTT_VERSION:
 385                 /* Though we've started our numbering from 1, and so class all
 386                  * earlier versions as 0, in effect their value is undefined as
 387                  * the ioctl will report EINVAL for the unknown param!
 388                  */
 389                 value = i915_gem_mmap_gtt_version();
 390                 break;
 391         case I915_PARAM_HAS_SCHEDULER:
 392                 value = dev_priv->caps.scheduler;
 393                 break;
 394
 395         case I915_PARAM_MMAP_VERSION:
 396                 /* Remember to bump this if the version changes! */
 397         case I915_PARAM_HAS_GEM:
 398         case I915_PARAM_HAS_PAGEFLIPPING:
 399         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 400         case I915_PARAM_HAS_RELAXED_FENCING:
 401         case I915_PARAM_HAS_COHERENT_RINGS:
 402         case I915_PARAM_HAS_RELAXED_DELTA:
 403         case I915_PARAM_HAS_GEN7_SOL_RESET:
 404         case I915_PARAM_HAS_WAIT_TIMEOUT:
 405         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 406         case I915_PARAM_HAS_PINNED_BATCHES:
 407         case I915_PARAM_HAS_EXEC_NO_RELOC:
 408         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 409         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 410         case I915_PARAM_HAS_EXEC_SOFTPIN:
 411         case I915_PARAM_HAS_EXEC_ASYNC:
 412         case I915_PARAM_HAS_EXEC_FENCE:
 413         case I915_PARAM_HAS_EXEC_CAPTURE:
 414         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 415         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 416                 /* For the time being all of these are always true;
 417                  * if some supported hardware does not have one of these
 418                  * features this value needs to be provided from
 419                  * INTEL_INFO(), a feature macro, or similar.
 420                  */
 421                 value = 1;
 422                 break;
 423         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 424                 value = intel_engines_has_context_isolation(dev_priv);
 425                 break;
 426         case I915_PARAM_SLICE_MASK:
 427                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 428                 if (!value)
 429                         return -ENODEV;
 430                 break;
 431         case I915_PARAM_SUBSLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 437                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 438                 break;
 439         default:
 440                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 441                 return -EINVAL;
 442         }
 443
 444         if (put_user(value, param->value))
 445                 return -EFAULT;
 446
 447         return 0;
 448 }
 449
 450 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 451 {
 452         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 453
 454         dev_priv->bridge_dev =
 455                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 456         if (!dev_priv->bridge_dev) {
 457                 DRM_ERROR("bridge device not found\n");
 458                 return -1;
 459         }
 460         return 0;
 461 }
 462
 463 /* Allocate space for the MCH regs if needed, return nonzero on error */
 464 static int
 465 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 466 {
 467         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 468         u32 temp_lo, temp_hi = 0;
 469         u64 mchbar_addr;
 470         int ret;
 471
 472         if (INTEL_GEN(dev_priv) >= 4)
 473                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 474         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 475         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 476
 477         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 478 #ifdef CONFIG_PNP
 479         if (mchbar_addr &&
 480             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 481                 return 0;
 482 #endif
 483
 484         /* Get some space for it */
 485         dev_priv->mch_res.name = "i915 MCHBAR";
 486         dev_priv->mch_res.flags = IORESOURCE_MEM;
 487         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 488                                      &dev_priv->mch_res,
 489                                      MCHBAR_SIZE, MCHBAR_SIZE,
 490                                      PCIBIOS_MIN_MEM,
 491                                      0, pcibios_align_resource,
 492                                      dev_priv->bridge_dev);
 493         if (ret) {
 494                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 495                 dev_priv->mch_res.start = 0;
 496                 return ret;
 497         }
 498
 499         if (INTEL_GEN(dev_priv) >= 4)
 500                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 501                                        upper_32_bits(dev_priv->mch_res.start));
 502
 503         pci_write_config_dword(dev_priv->bridge_dev, reg,
 504                                lower_32_bits(dev_priv->mch_res.start));
 505         return 0;
 506 }
 507
 508 /* Setup MCHBAR if possible, return true if we should disable it again */
 509 static void
 510 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 511 {
 512         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 513         u32 temp;
 514         bool enabled;
 515
 516         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 517                 return;
 518
 519         dev_priv->mchbar_need_disable = false;
 520
 521         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 522                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 523                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 524         } else {
 525                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 526                 enabled = temp & 1;
 527         }
 528
 529         /* If it's already enabled, don't have to do anything */
 530         if (enabled)
 531                 return;
 532
 533         if (intel_alloc_mchbar_resource(dev_priv))
 534                 return;
 535
 536         dev_priv->mchbar_need_disable = true;
 537
 538         /* Space is allocated or reserved, so enable it. */
 539         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 540                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 541                                        temp | DEVEN_MCHBAR_EN);
 542         } else {
 543                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 544                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 545         }
 546 }
 547
 548 static void
 549 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 550 {
 551         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 552
 553         if (dev_priv->mchbar_need_disable) {
 554                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 555                         u32 deven_val;
 556
 557                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 558                                               &deven_val);
 559                         deven_val &= ~DEVEN_MCHBAR_EN;
 560                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 561                                                deven_val);
 562                 } else {
 563                         u32 mchbar_val;
 564
 565                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 566                                               &mchbar_val);
 567                         mchbar_val &= ~1;
 568                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 569                                                mchbar_val);
 570                 }
 571         }
 572
 573         if (dev_priv->mch_res.start)
 574                 release_resource(&dev_priv->mch_res);
 575 }
 576
 577 /* true = enable decode, false = disable decoder */
 578 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 579 {
 580         struct drm_i915_private *dev_priv = cookie;
 581
 582         intel_modeset_vga_set_state(dev_priv, state);
 583         if (state)
 584                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 585                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 586         else
 587                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 588 }
 589
 590 static int i915_resume_switcheroo(struct drm_device *dev);
 591 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 592
 593 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 594 {
 595         struct drm_device *dev = pci_get_drvdata(pdev);
 596         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 597
 598         if (state == VGA_SWITCHEROO_ON) {
 599                 pr_info("switched on\n");
 600                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 601                 /* i915 resume handler doesn't set to D0 */
 602                 pci_set_power_state(pdev, PCI_D0);
 603                 i915_resume_switcheroo(dev);
 604                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 605         } else {
 606                 pr_info("switched off\n");
 607                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 608                 i915_suspend_switcheroo(dev, pmm);
 609                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 610         }
 611 }
 612
 613 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 614 {
 615         struct drm_device *dev = pci_get_drvdata(pdev);
 616
 617         /*
 618          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 619          * locking inversion with the driver load path. And the access here is
 620          * completely racy anyway. So don't bother with locking for now.
 621          */
 622         return dev->open_count == 0;
 623 }
 624
 625 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 626         .set_gpu_state = i915_switcheroo_set_state,
 627         .reprobe = NULL,
 628         .can_switch = i915_switcheroo_can_switch,
 629 };
 630
 631 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 632 {
 633         /* Flush any outstanding unpin_work. */
 634         i915_gem_drain_workqueue(dev_priv);
 635
 636         mutex_lock(&dev_priv->drm.struct_mutex);
 637         intel_uc_fini_hw(dev_priv);
 638         intel_uc_fini(dev_priv);
 639         i915_gem_cleanup_engines(dev_priv);
 640         i915_gem_contexts_fini(dev_priv);
 641         mutex_unlock(&dev_priv->drm.struct_mutex);
 642
 643         intel_uc_fini_misc(dev_priv);
 644         i915_gem_cleanup_userptr(dev_priv);
 645
 646         i915_gem_drain_freed_objects(dev_priv);
 647
 648         WARN_ON(!list_empty(&dev_priv->contexts.list));
 649 }
 650
 651 static int i915_load_modeset_init(struct drm_device *dev)
 652 {
 653         struct drm_i915_private *dev_priv = to_i915(dev);
 654         struct pci_dev *pdev = dev_priv->drm.pdev;
 655         int ret;
 656
 657         if (i915_inject_load_failure())
 658                 return -ENODEV;
 659
 660         intel_bios_init(dev_priv);
 661
 662         /* If we have > 1 VGA cards, then we need to arbitrate access
 663          * to the common VGA resources.
 664          *
 665          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 666          * then we do not take part in VGA arbitration and the
 667          * vga_client_register() fails with -ENODEV.
 668          */
 669         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 670         if (ret && ret != -ENODEV)
 671                 goto out;
 672
 673         intel_register_dsm_handler();
 674
 675         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 676         if (ret)
 677                 goto cleanup_vga_client;
 678
 679         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 680         intel_update_rawclk(dev_priv);
 681
 682         intel_power_domains_init_hw(dev_priv, false);
 683
 684         intel_csr_ucode_init(dev_priv);
 685
 686         ret = intel_irq_install(dev_priv);
 687         if (ret)
 688                 goto cleanup_csr;
 689
 690         intel_setup_gmbus(dev_priv);
 691
 692         /* Important: The output setup functions called by modeset_init need
 693          * working irqs for e.g. gmbus and dp aux transfers. */
 694         ret = intel_modeset_init(dev);
 695         if (ret)
 696                 goto cleanup_irq;
 697
 698         intel_uc_init_fw(dev_priv);
 699
 700         ret = i915_gem_init(dev_priv);
 701         if (ret)
 702                 goto cleanup_uc;
 703
 704         intel_setup_overlay(dev_priv);
 705
 706         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 707                 return 0;
 708
 709         ret = intel_fbdev_init(dev);
 710         if (ret)
 711                 goto cleanup_gem;
 712
 713         /* Only enable hotplug handling once the fbdev is fully set up. */
 714         intel_hpd_init(dev_priv);
 715
 716         return 0;
 717
 718 cleanup_gem:
 719         if (i915_gem_suspend(dev_priv))
 720                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 721         i915_gem_fini(dev_priv);
 722 cleanup_uc:
 723         intel_uc_fini_fw(dev_priv);
 724 cleanup_irq:
 725         drm_irq_uninstall(dev);
 726         intel_teardown_gmbus(dev_priv);
 727 cleanup_csr:
 728         intel_csr_ucode_fini(dev_priv);
 729         intel_power_domains_fini(dev_priv);
 730         vga_switcheroo_unregister_client(pdev);
 731 cleanup_vga_client:
 732         vga_client_register(pdev, NULL, NULL, NULL);
 733 out:
 734         return ret;
 735 }
 736
 737 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 738 {
 739         struct apertures_struct *ap;
 740         struct pci_dev *pdev = dev_priv->drm.pdev;
 741         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 742         bool primary;
 743         int ret;
 744
 745         ap = alloc_apertures(1);
 746         if (!ap)
 747                 return -ENOMEM;
 748
 749         ap->ranges[0].base = ggtt->gmadr.start;
 750         ap->ranges[0].size = ggtt->mappable_end;
 751
 752         primary =
 753                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 754
 755         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 756
 757         kfree(ap);
 758
 759         return ret;
 760 }
 761
 762 #if !defined(CONFIG_VGA_CONSOLE)
 763 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 764 {
 765         return 0;
 766 }
 767 #elif !defined(CONFIG_DUMMY_CONSOLE)
 768 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 769 {
 770         return -ENODEV;
 771 }
 772 #else
 773 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 774 {
 775         int ret = 0;
 776
 777         DRM_INFO("Replacing VGA console driver\n");
 778
 779         console_lock();
 780         if (con_is_bound(&vga_con))
 781                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 782         if (ret == 0) {
 783                 ret = do_unregister_con_driver(&vga_con);
 784
 785                 /* Ignore "already unregistered". */
 786                 if (ret == -ENODEV)
 787                         ret = 0;
 788         }
 789         console_unlock();
 790
 791         return ret;
 792 }
 793 #endif
 794
 795 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 796 {
 797         /*
 798          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 799          * CHV x1 PHY (DP/HDMI D)
 800          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 801          */
 802         if (IS_CHERRYVIEW(dev_priv)) {
 803                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 804                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 805         } else if (IS_VALLEYVIEW(dev_priv)) {
 806                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 807         }
 808 }
 809
 810 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 811 {
 812         /*
 813          * The i915 workqueue is primarily used for batched retirement of
 814          * requests (and thus managing bo) once the task has been completed
 815          * by the GPU. i915_retire_requests() is called directly when we
 816          * need high-priority retirement, such as waiting for an explicit
 817          * bo.
 818          *
 819          * It is also used for periodic low-priority events, such as
 820          * idle-timers and recording error state.
 821          *
 822          * All tasks on the workqueue are expected to acquire the dev mutex
 823          * so there is no point in running more than one instance of the
 824          * workqueue at any time.  Use an ordered one.
 825          */
 826         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 827         if (dev_priv->wq == NULL)
 828                 goto out_err;
 829
 830         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 831         if (dev_priv->hotplug.dp_wq == NULL)
 832                 goto out_free_wq;
 833
 834         return 0;
 835
 836 out_free_wq:
 837         destroy_workqueue(dev_priv->wq);
 838 out_err:
 839         DRM_ERROR("Failed to allocate workqueues.\n");
 840
 841         return -ENOMEM;
 842 }
 843
 844 static void i915_engines_cleanup(struct drm_i915_private *i915)
 845 {
 846         struct intel_engine_cs *engine;
 847         enum intel_engine_id id;
 848
 849         for_each_engine(engine, i915, id)
 850                 kfree(engine);
 851 }
 852
 853 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 854 {
 855         destroy_workqueue(dev_priv->hotplug.dp_wq);
 856         destroy_workqueue(dev_priv->wq);
 857 }
 858
 859 /*
 860  * We don't keep the workarounds for pre-production hardware, so we expect our
 861  * driver to fail on these machines in one way or another. A little warning on
 862  * dmesg may help both the user and the bug triagers.
 863  *
 864  * Our policy for removing pre-production workarounds is to keep the
 865  * current gen workarounds as a guide to the bring-up of the next gen
 866  * (workarounds have a habit of persisting!). Anything older than that
 867  * should be removed along with the complications they introduce.
 868  */
 869 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 870 {
 871         bool pre = false;
 872
 873         pre |= IS_HSW_EARLY_SDV(dev_priv);
 874         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 875         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 876
 877         if (pre) {
 878                 DRM_ERROR("This is a pre-production stepping. "
 879                           "It may not be fully functional.\n");
 880                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 881         }
 882 }
 883
 884 /**
 885  * i915_driver_init_early - setup state not requiring device access
 886  * @dev_priv: device private
 887  * @ent: the matching pci_device_id
 888  *
 889  * Initialize everything that is a "SW-only" state, that is state not
 890  * requiring accessing the device or exposing the driver via kernel internal
 891  * or userspace interfaces. Example steps belonging here: lock initialization,
 892  * system memory allocation, setting up device specific attributes and
 893  * function hooks not requiring accessing the device.
 894  */
 895 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 896                                   const struct pci_device_id *ent)
 897 {
 898         const struct intel_device_info *match_info =
 899                 (struct intel_device_info *)ent->driver_data;
 900         struct intel_device_info *device_info;
 901         int ret = 0;
 902
 903         if (i915_inject_load_failure())
 904                 return -ENODEV;
 905
 906         /* Setup the write-once "constant" device info */
 907         device_info = mkwrite_device_info(dev_priv);
 908         memcpy(device_info, match_info, sizeof(*device_info));
 909         device_info->device_id = dev_priv->drm.pdev->device;
 910
 911         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 912                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 913         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 914         spin_lock_init(&dev_priv->irq_lock);
 915         spin_lock_init(&dev_priv->gpu_error.lock);
 916         mutex_init(&dev_priv->backlight_lock);
 917         spin_lock_init(&dev_priv->uncore.lock);
 918
 919         mutex_init(&dev_priv->sb_lock);
 920         mutex_init(&dev_priv->modeset_restore_lock);
 921         mutex_init(&dev_priv->av_mutex);
 922         mutex_init(&dev_priv->wm.wm_mutex);
 923         mutex_init(&dev_priv->pps_mutex);
 924
 925         intel_uc_init_early(dev_priv);
 926         i915_memcpy_init_early(dev_priv);
 927
 928         ret = i915_workqueues_init(dev_priv);
 929         if (ret < 0)
 930                 goto err_engines;
 931
 932         /* This must be called before any calls to HAS_PCH_* */
 933         intel_detect_pch(dev_priv);
 934
 935         intel_pm_setup(dev_priv);
 936         intel_init_dpio(dev_priv);
 937         intel_power_domains_init(dev_priv);
 938         intel_irq_init(dev_priv);
 939         intel_hangcheck_init(dev_priv);
 940         intel_init_display_hooks(dev_priv);
 941         intel_init_clock_gating_hooks(dev_priv);
 942         intel_init_audio_hooks(dev_priv);
 943         ret = i915_gem_load_init(dev_priv);
 944         if (ret < 0)
 945                 goto err_irq;
 946
 947         intel_display_crc_init(dev_priv);
 948
 949         intel_detect_preproduction_hw(dev_priv);
 950
 951         return 0;
 952
 953 err_irq:
 954         intel_irq_fini(dev_priv);
 955         i915_workqueues_cleanup(dev_priv);
 956 err_engines:
 957         i915_engines_cleanup(dev_priv);
 958         return ret;
 959 }
 960
 961 /**
 962  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 963  * @dev_priv: device private
 964  */
 965 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 966 {
 967         i915_gem_load_cleanup(dev_priv);
 968         intel_irq_fini(dev_priv);
 969         i915_workqueues_cleanup(dev_priv);
 970         i915_engines_cleanup(dev_priv);
 971 }
 972
 973 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 974 {
 975         struct pci_dev *pdev = dev_priv->drm.pdev;
 976         int mmio_bar;
 977         int mmio_size;
 978
 979         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 980         /*
 981          * Before gen4, the registers and the GTT are behind different BARs.
 982          * However, from gen4 onwards, the registers and the GTT are shared
 983          * in the same BAR, so we want to restrict this ioremap from
 984          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 985          * the register BAR remains the same size for all the earlier
 986          * generations up to Ironlake.
 987          */
 988         if (INTEL_GEN(dev_priv) < 5)
 989                 mmio_size = 512 * 1024;
 990         else
 991                 mmio_size = 2 * 1024 * 1024;
 992         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 993         if (dev_priv->regs == NULL) {
 994                 DRM_ERROR("failed to map registers\n");
 995
 996                 return -EIO;
 997         }
 998
 999         /* Try to make sure MCHBAR is enabled before poking at it */
1000         intel_setup_mchbar(dev_priv);
1001
1002         return 0;
1003 }
1004
1005 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1006 {
1007         struct pci_dev *pdev = dev_priv->drm.pdev;
1008
1009         intel_teardown_mchbar(dev_priv);
1010         pci_iounmap(pdev, dev_priv->regs);
1011 }
1012
1013 /**
1014  * i915_driver_init_mmio - setup device MMIO
1015  * @dev_priv: device private
1016  *
1017  * Setup minimal device state necessary for MMIO accesses later in the
1018  * initialization sequence. The setup here should avoid any other device-wide
1019  * side effects or exposing the driver via kernel internal or user space
1020  * interfaces.
1021  */
1022 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1023 {
1024         int ret;
1025
1026         if (i915_inject_load_failure())
1027                 return -ENODEV;
1028
1029         if (i915_get_bridge_dev(dev_priv))
1030                 return -EIO;
1031
1032         ret = i915_mmio_setup(dev_priv);
1033         if (ret < 0)
1034                 goto err_bridge;
1035
1036         intel_uncore_init(dev_priv);
1037
1038         intel_uc_init_mmio(dev_priv);
1039
1040         ret = intel_engines_init_mmio(dev_priv);
1041         if (ret)
1042                 goto err_uncore;
1043
1044         i915_gem_init_mmio(dev_priv);
1045
1046         return 0;
1047
1048 err_uncore:
1049         intel_uncore_fini(dev_priv);
1050 err_bridge:
1051         pci_dev_put(dev_priv->bridge_dev);
1052
1053         return ret;
1054 }
1055
1056 /**
1057  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1058  * @dev_priv: device private
1059  */
1060 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1061 {
1062         intel_uncore_fini(dev_priv);
1063         i915_mmio_cleanup(dev_priv);
1064         pci_dev_put(dev_priv->bridge_dev);
1065 }
1066
1067 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1068 {
1069         /*
1070          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1071          * user's requested state against the hardware/driver capabilities.  We
1072          * do this now so that we can print out any log messages once rather
1073          * than every time we check intel_enable_ppgtt().
1074          */
1075         i915_modparams.enable_ppgtt =
1076                 intel_sanitize_enable_ppgtt(dev_priv,
1077                                             i915_modparams.enable_ppgtt);
1078         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1079
1080         intel_uc_sanitize_options(dev_priv);
1081
1082         intel_gvt_sanitize_options(dev_priv);
1083 }
1084
1085 /**
1086  * i915_driver_init_hw - setup state requiring device access
1087  * @dev_priv: device private
1088  *
1089  * Setup state that requires accessing the device, but doesn't require
1090  * exposing the driver via kernel internal or userspace interfaces.
1091  */
1092 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1093 {
1094         struct pci_dev *pdev = dev_priv->drm.pdev;
1095         int ret;
1096
1097         if (i915_inject_load_failure())
1098                 return -ENODEV;
1099
1100         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1101
1102         intel_sanitize_options(dev_priv);
1103
1104         i915_perf_init(dev_priv);
1105
1106         ret = i915_ggtt_probe_hw(dev_priv);
1107         if (ret)
1108                 return ret;
1109
1110         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1111          * otherwise the vga fbdev driver falls over. */
1112         ret = i915_kick_out_firmware_fb(dev_priv);
1113         if (ret) {
1114                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1115                 goto out_ggtt;
1116         }
1117
1118         ret = i915_kick_out_vgacon(dev_priv);
1119         if (ret) {
1120                 DRM_ERROR("failed to remove conflicting VGA console\n");
1121                 goto out_ggtt;
1122         }
1123
1124         ret = i915_ggtt_init_hw(dev_priv);
1125         if (ret)
1126                 return ret;
1127
1128         ret = i915_ggtt_enable_hw(dev_priv);
1129         if (ret) {
1130                 DRM_ERROR("failed to enable GGTT\n");
1131                 goto out_ggtt;
1132         }
1133
1134         pci_set_master(pdev);
1135
1136         /* overlay on gen2 is broken and can't address above 1G */
1137         if (IS_GEN2(dev_priv)) {
1138                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1139                 if (ret) {
1140                         DRM_ERROR("failed to set DMA mask\n");
1141
1142                         goto out_ggtt;
1143                 }
1144         }
1145
1146         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1147          * using 32bit addressing, overwriting memory if HWS is located
1148          * above 4GB.
1149          *
1150          * The documentation also mentions an issue with undefined
1151          * behaviour if any general state is accessed within a page above 4GB,
1152          * which also needs to be handled carefully.
1153          */
1154         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1155                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1156
1157                 if (ret) {
1158                         DRM_ERROR("failed to set DMA mask\n");
1159
1160                         goto out_ggtt;
1161                 }
1162         }
1163
1164         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1165                            PM_QOS_DEFAULT_VALUE);
1166
1167         intel_uncore_sanitize(dev_priv);
1168
1169         intel_opregion_setup(dev_priv);
1170
1171         i915_gem_load_init_fences(dev_priv);
1172
1173         /* On the 945G/GM, the chipset reports the MSI capability on the
1174          * integrated graphics even though the support isn't actually there
1175          * according to the published specs.  It doesn't appear to function
1176          * correctly in testing on 945G.
1177          * This may be a side effect of MSI having been made available for PEG
1178          * and the registers being closely associated.
1179          *
1180          * According to chipset errata, on the 965GM, MSI interrupts may
1181          * be lost or delayed, and was defeatured. MSI interrupts seem to
1182          * get lost on g4x as well, and interrupt delivery seems to stay
1183          * properly dead afterwards. So we'll just disable them for all
1184          * pre-gen5 chipsets.
1185          */
1186         if (INTEL_GEN(dev_priv) >= 5) {
1187                 if (pci_enable_msi(pdev) < 0)
1188                         DRM_DEBUG_DRIVER("can't enable MSI");
1189         }
1190
1191         ret = intel_gvt_init(dev_priv);
1192         if (ret)
1193                 goto out_ggtt;
1194
1195         return 0;
1196
1197 out_ggtt:
1198         i915_ggtt_cleanup_hw(dev_priv);
1199
1200         return ret;
1201 }
1202
1203 /**
1204  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1205  * @dev_priv: device private
1206  */
1207 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1208 {
1209         struct pci_dev *pdev = dev_priv->drm.pdev;
1210
1211         i915_perf_fini(dev_priv);
1212
1213         if (pdev->msi_enabled)
1214                 pci_disable_msi(pdev);
1215
1216         pm_qos_remove_request(&dev_priv->pm_qos);
1217         i915_ggtt_cleanup_hw(dev_priv);
1218 }
1219
1220 /**
1221  * i915_driver_register - register the driver with the rest of the system
1222  * @dev_priv: device private
1223  *
1224  * Perform any steps necessary to make the driver available via kernel
1225  * internal or userspace interfaces.
1226  */
1227 static void i915_driver_register(struct drm_i915_private *dev_priv)
1228 {
1229         struct drm_device *dev = &dev_priv->drm;
1230
1231         i915_gem_shrinker_register(dev_priv);
1232         i915_pmu_register(dev_priv);
1233
1234         /*
1235          * Notify a valid surface after modesetting,
1236          * when running inside a VM.
1237          */
1238         if (intel_vgpu_active(dev_priv))
1239                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1240
1241         /* Reveal our presence to userspace */
1242         if (drm_dev_register(dev, 0) == 0) {
1243                 i915_debugfs_register(dev_priv);
1244                 i915_guc_log_register(dev_priv);
1245                 i915_setup_sysfs(dev_priv);
1246
1247                 /* Depends on sysfs having been initialized */
1248                 i915_perf_register(dev_priv);
1249         } else
1250                 DRM_ERROR("Failed to register driver for userspace access!\n");
1251
1252         if (INTEL_INFO(dev_priv)->num_pipes) {
1253                 /* Must be done after probing outputs */
1254                 intel_opregion_register(dev_priv);
1255                 acpi_video_register();
1256         }
1257
1258         if (IS_GEN5(dev_priv))
1259                 intel_gpu_ips_init(dev_priv);
1260
1261         intel_audio_init(dev_priv);
1262
1263         /*
1264          * Some ports require correctly set-up hpd registers for detection to
1265          * work properly (leading to ghost connected connector status), e.g. VGA
1266          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1267          * irqs are fully enabled. We do it last so that the async config
1268          * cannot run before the connectors are registered.
1269          */
1270         intel_fbdev_initial_config_async(dev);
1271
1272         /*
1273          * We need to coordinate the hotplugs with the asynchronous fbdev
1274          * configuration, for which we use the fbdev->async_cookie.
1275          */
1276         if (INTEL_INFO(dev_priv)->num_pipes)
1277                 drm_kms_helper_poll_init(dev);
1278 }
1279
1280 /**
1281  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1282  * @dev_priv: device private
1283  */
1284 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1285 {
1286         intel_fbdev_unregister(dev_priv);
1287         intel_audio_deinit(dev_priv);
1288
1289         /*
1290          * After flushing the fbdev (incl. a late async config which will
1291          * have delayed queuing of a hotplug event), then flush the hotplug
1292          * events.
1293          */
1294         drm_kms_helper_poll_fini(&dev_priv->drm);
1295
1296         intel_gpu_ips_teardown();
1297         acpi_video_unregister();
1298         intel_opregion_unregister(dev_priv);
1299
1300         i915_perf_unregister(dev_priv);
1301         i915_pmu_unregister(dev_priv);
1302
1303         i915_teardown_sysfs(dev_priv);
1304         i915_guc_log_unregister(dev_priv);
1305         drm_dev_unregister(&dev_priv->drm);
1306
1307         i915_gem_shrinker_unregister(dev_priv);
1308 }
1309
1310 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1311 {
1312         if (drm_debug & DRM_UT_DRIVER) {
1313                 struct drm_printer p = drm_debug_printer("i915 device info:");
1314
1315                 intel_device_info_dump(&dev_priv->info, &p);
1316                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1317         }
1318
1319         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1320                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1321         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1322                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1323 }
1324
1325 /**
1326  * i915_driver_load - setup chip and create an initial config
1327  * @pdev: PCI device
1328  * @ent: matching PCI ID entry
1329  *
1330  * The driver load routine has to do several things:
1331  *   - drive output discovery via intel_modeset_init()
1332  *   - initialize the memory manager
1333  *   - allocate initial config memory
1334  *   - setup the DRM framebuffer with the allocated memory
1335  */
1336 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1337 {
1338         const struct intel_device_info *match_info =
1339                 (struct intel_device_info *)ent->driver_data;
1340         struct drm_i915_private *dev_priv;
1341         int ret;
1342
1343         /* Enable nuclear pageflip on ILK+ */
1344         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1345                 driver.driver_features &= ~DRIVER_ATOMIC;
1346
1347         ret = -ENOMEM;
1348         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1349         if (dev_priv)
1350                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1351         if (ret) {
1352                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1353                 goto out_free;
1354         }
1355
1356         dev_priv->drm.pdev = pdev;
1357         dev_priv->drm.dev_private = dev_priv;
1358
1359         ret = pci_enable_device(pdev);
1360         if (ret)
1361                 goto out_fini;
1362
1363         pci_set_drvdata(pdev, &dev_priv->drm);
1364         /*
1365          * Disable the system suspend direct complete optimization, which can
1366          * leave the device suspended skipping the driver's suspend handlers
1367          * if the device was already runtime suspended. This is needed due to
1368          * the difference in our runtime and system suspend sequence and
1369          * becaue the HDA driver may require us to enable the audio power
1370          * domain during system suspend.
1371          */
1372         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1373
1374         ret = i915_driver_init_early(dev_priv, ent);
1375         if (ret < 0)
1376                 goto out_pci_disable;
1377
1378         intel_runtime_pm_get(dev_priv);
1379
1380         ret = i915_driver_init_mmio(dev_priv);
1381         if (ret < 0)
1382                 goto out_runtime_pm_put;
1383
1384         ret = i915_driver_init_hw(dev_priv);
1385         if (ret < 0)
1386                 goto out_cleanup_mmio;
1387
1388         /*
1389          * TODO: move the vblank init and parts of modeset init steps into one
1390          * of the i915_driver_init_/i915_driver_register functions according
1391          * to the role/effect of the given init step.
1392          */
1393         if (INTEL_INFO(dev_priv)->num_pipes) {
1394                 ret = drm_vblank_init(&dev_priv->drm,
1395                                       INTEL_INFO(dev_priv)->num_pipes);
1396                 if (ret)
1397                         goto out_cleanup_hw;
1398         }
1399
1400         ret = i915_load_modeset_init(&dev_priv->drm);
1401         if (ret < 0)
1402                 goto out_cleanup_hw;
1403
1404         i915_driver_register(dev_priv);
1405
1406         intel_runtime_pm_enable(dev_priv);
1407
1408         intel_init_ipc(dev_priv);
1409
1410         intel_runtime_pm_put(dev_priv);
1411
1412         i915_welcome_messages(dev_priv);
1413
1414         return 0;
1415
1416 out_cleanup_hw:
1417         i915_driver_cleanup_hw(dev_priv);
1418 out_cleanup_mmio:
1419         i915_driver_cleanup_mmio(dev_priv);
1420 out_runtime_pm_put:
1421         intel_runtime_pm_put(dev_priv);
1422         i915_driver_cleanup_early(dev_priv);
1423 out_pci_disable:
1424         pci_disable_device(pdev);
1425 out_fini:
1426         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1427         drm_dev_fini(&dev_priv->drm);
1428 out_free:
1429         kfree(dev_priv);
1430         return ret;
1431 }
1432
1433 void i915_driver_unload(struct drm_device *dev)
1434 {
1435         struct drm_i915_private *dev_priv = to_i915(dev);
1436         struct pci_dev *pdev = dev_priv->drm.pdev;
1437
1438         i915_driver_unregister(dev_priv);
1439
1440         if (i915_gem_suspend(dev_priv))
1441                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1442
1443         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1444
1445         drm_atomic_helper_shutdown(dev);
1446
1447         intel_gvt_cleanup(dev_priv);
1448
1449         intel_modeset_cleanup(dev);
1450
1451         intel_bios_cleanup(dev_priv);
1452
1453         vga_switcheroo_unregister_client(pdev);
1454         vga_client_register(pdev, NULL, NULL, NULL);
1455
1456         intel_csr_ucode_fini(dev_priv);
1457
1458         /* Free error state after interrupts are fully disabled. */
1459         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1460         i915_reset_error_state(dev_priv);
1461
1462         i915_gem_fini(dev_priv);
1463         intel_uc_fini_fw(dev_priv);
1464         intel_fbc_cleanup_cfb(dev_priv);
1465
1466         intel_power_domains_fini(dev_priv);
1467
1468         i915_driver_cleanup_hw(dev_priv);
1469         i915_driver_cleanup_mmio(dev_priv);
1470
1471         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1472 }
1473
1474 static void i915_driver_release(struct drm_device *dev)
1475 {
1476         struct drm_i915_private *dev_priv = to_i915(dev);
1477
1478         i915_driver_cleanup_early(dev_priv);
1479         drm_dev_fini(&dev_priv->drm);
1480
1481         kfree(dev_priv);
1482 }
1483
1484 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1485 {
1486         struct drm_i915_private *i915 = to_i915(dev);
1487         int ret;
1488
1489         ret = i915_gem_open(i915, file);
1490         if (ret)
1491                 return ret;
1492
1493         return 0;
1494 }
1495
1496 /**
1497  * i915_driver_lastclose - clean up after all DRM clients have exited
1498  * @dev: DRM device
1499  *
1500  * Take care of cleaning up after all DRM clients have exited.  In the
1501  * mode setting case, we want to restore the kernel's initial mode (just
1502  * in case the last client left us in a bad state).
1503  *
1504  * Additionally, in the non-mode setting case, we'll tear down the GTT
1505  * and DMA structures, since the kernel won't be using them, and clea
1506  * up any GEM state.
1507  */
1508 static void i915_driver_lastclose(struct drm_device *dev)
1509 {
1510         intel_fbdev_restore_mode(dev);
1511         vga_switcheroo_process_delayed_switch();
1512 }
1513
1514 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1515 {
1516         struct drm_i915_file_private *file_priv = file->driver_priv;
1517
1518         mutex_lock(&dev->struct_mutex);
1519         i915_gem_context_close(file);
1520         i915_gem_release(dev, file);
1521         mutex_unlock(&dev->struct_mutex);
1522
1523         kfree(file_priv);
1524 }
1525
1526 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1527 {
1528         struct drm_device *dev = &dev_priv->drm;
1529         struct intel_encoder *encoder;
1530
1531         drm_modeset_lock_all(dev);
1532         for_each_intel_encoder(dev, encoder)
1533                 if (encoder->suspend)
1534                         encoder->suspend(encoder);
1535         drm_modeset_unlock_all(dev);
1536 }
1537
1538 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1539                               bool rpm_resume);
1540 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1541
1542 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1543 {
1544 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1545         if (acpi_target_system_state() < ACPI_STATE_S3)
1546                 return true;
1547 #endif
1548         return false;
1549 }
1550
1551 static int i915_drm_suspend(struct drm_device *dev)
1552 {
1553         struct drm_i915_private *dev_priv = to_i915(dev);
1554         struct pci_dev *pdev = dev_priv->drm.pdev;
1555         pci_power_t opregion_target_state;
1556         int error;
1557
1558         /* ignore lid events during suspend */
1559         mutex_lock(&dev_priv->modeset_restore_lock);
1560         dev_priv->modeset_restore = MODESET_SUSPENDED;
1561         mutex_unlock(&dev_priv->modeset_restore_lock);
1562
1563         disable_rpm_wakeref_asserts(dev_priv);
1564
1565         /* We do a lot of poking in a lot of registers, make sure they work
1566          * properly. */
1567         intel_display_set_init_power(dev_priv, true);
1568
1569         drm_kms_helper_poll_disable(dev);
1570
1571         pci_save_state(pdev);
1572
1573         error = i915_gem_suspend(dev_priv);
1574         if (error) {
1575                 dev_err(&pdev->dev,
1576                         "GEM idle failed, resume might fail\n");
1577                 goto out;
1578         }
1579
1580         intel_display_suspend(dev);
1581
1582         intel_dp_mst_suspend(dev);
1583
1584         intel_runtime_pm_disable_interrupts(dev_priv);
1585         intel_hpd_cancel_work(dev_priv);
1586
1587         intel_suspend_encoders(dev_priv);
1588
1589         intel_suspend_hw(dev_priv);
1590
1591         i915_gem_suspend_gtt_mappings(dev_priv);
1592
1593         i915_save_state(dev_priv);
1594
1595         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1596         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1597
1598         intel_uncore_suspend(dev_priv);
1599         intel_opregion_unregister(dev_priv);
1600
1601         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1602
1603         dev_priv->suspend_count++;
1604
1605         intel_csr_ucode_suspend(dev_priv);
1606
1607 out:
1608         enable_rpm_wakeref_asserts(dev_priv);
1609
1610         return error;
1611 }
1612
1613 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1614 {
1615         struct drm_i915_private *dev_priv = to_i915(dev);
1616         struct pci_dev *pdev = dev_priv->drm.pdev;
1617         int ret;
1618
1619         disable_rpm_wakeref_asserts(dev_priv);
1620
1621         intel_display_set_init_power(dev_priv, false);
1622
1623         /*
1624          * In case of firmware assisted context save/restore don't manually
1625          * deinit the power domains. This also means the CSR/DMC firmware will
1626          * stay active, it will power down any HW resources as required and
1627          * also enable deeper system power states that would be blocked if the
1628          * firmware was inactive.
1629          */
1630         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1631             dev_priv->csr.dmc_payload == NULL) {
1632                 intel_power_domains_suspend(dev_priv);
1633                 dev_priv->power_domains_suspended = true;
1634         }
1635
1636         ret = 0;
1637         if (IS_GEN9_LP(dev_priv))
1638                 bxt_enable_dc9(dev_priv);
1639         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1640                 hsw_enable_pc8(dev_priv);
1641         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1642                 ret = vlv_suspend_complete(dev_priv);
1643
1644         if (ret) {
1645                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1646                 if (dev_priv->power_domains_suspended) {
1647                         intel_power_domains_init_hw(dev_priv, true);
1648                         dev_priv->power_domains_suspended = false;
1649                 }
1650
1651                 goto out;
1652         }
1653
1654         pci_disable_device(pdev);
1655         /*
1656          * During hibernation on some platforms the BIOS may try to access
1657          * the device even though it's already in D3 and hang the machine. So
1658          * leave the device in D0 on those platforms and hope the BIOS will
1659          * power down the device properly. The issue was seen on multiple old
1660          * GENs with different BIOS vendors, so having an explicit blacklist
1661          * is inpractical; apply the workaround on everything pre GEN6. The
1662          * platforms where the issue was seen:
1663          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1664          * Fujitsu FSC S7110
1665          * Acer Aspire 1830T
1666          */
1667         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1668                 pci_set_power_state(pdev, PCI_D3hot);
1669
1670 out:
1671         enable_rpm_wakeref_asserts(dev_priv);
1672
1673         return ret;
1674 }
1675
1676 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1677 {
1678         int error;
1679
1680         if (!dev) {
1681                 DRM_ERROR("dev: %p\n", dev);
1682                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1683                 return -ENODEV;
1684         }
1685
1686         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1687                          state.event != PM_EVENT_FREEZE))
1688                 return -EINVAL;
1689
1690         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1691                 return 0;
1692
1693         error = i915_drm_suspend(dev);
1694         if (error)
1695                 return error;
1696
1697         return i915_drm_suspend_late(dev, false);
1698 }
1699
1700 static int i915_drm_resume(struct drm_device *dev)
1701 {
1702         struct drm_i915_private *dev_priv = to_i915(dev);
1703         int ret;
1704
1705         disable_rpm_wakeref_asserts(dev_priv);
1706         intel_sanitize_gt_powersave(dev_priv);
1707
1708         ret = i915_ggtt_enable_hw(dev_priv);
1709         if (ret)
1710                 DRM_ERROR("failed to re-enable GGTT\n");
1711
1712         intel_csr_ucode_resume(dev_priv);
1713
1714         i915_restore_state(dev_priv);
1715         intel_pps_unlock_regs_wa(dev_priv);
1716         intel_opregion_setup(dev_priv);
1717
1718         intel_init_pch_refclk(dev_priv);
1719
1720         /*
1721          * Interrupts have to be enabled before any batches are run. If not the
1722          * GPU will hang. i915_gem_init_hw() will initiate batches to
1723          * update/restore the context.
1724          *
1725          * drm_mode_config_reset() needs AUX interrupts.
1726          *
1727          * Modeset enabling in intel_modeset_init_hw() also needs working
1728          * interrupts.
1729          */
1730         intel_runtime_pm_enable_interrupts(dev_priv);
1731
1732         drm_mode_config_reset(dev);
1733
1734         i915_gem_resume(dev_priv);
1735
1736         intel_modeset_init_hw(dev);
1737         intel_init_clock_gating(dev_priv);
1738
1739         spin_lock_irq(&dev_priv->irq_lock);
1740         if (dev_priv->display.hpd_irq_setup)
1741                 dev_priv->display.hpd_irq_setup(dev_priv);
1742         spin_unlock_irq(&dev_priv->irq_lock);
1743
1744         intel_dp_mst_resume(dev);
1745
1746         intel_display_resume(dev);
1747
1748         drm_kms_helper_poll_enable(dev);
1749
1750         /*
1751          * ... but also need to make sure that hotplug processing
1752          * doesn't cause havoc. Like in the driver load code we don't
1753          * bother with the tiny race here where we might loose hotplug
1754          * notifications.
1755          * */
1756         intel_hpd_init(dev_priv);
1757
1758         intel_opregion_register(dev_priv);
1759
1760         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1761
1762         mutex_lock(&dev_priv->modeset_restore_lock);
1763         dev_priv->modeset_restore = MODESET_DONE;
1764         mutex_unlock(&dev_priv->modeset_restore_lock);
1765
1766         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1767
1768         enable_rpm_wakeref_asserts(dev_priv);
1769
1770         return 0;
1771 }
1772
1773 static int i915_drm_resume_early(struct drm_device *dev)
1774 {
1775         struct drm_i915_private *dev_priv = to_i915(dev);
1776         struct pci_dev *pdev = dev_priv->drm.pdev;
1777         int ret;
1778
1779         /*
1780          * We have a resume ordering issue with the snd-hda driver also
1781          * requiring our device to be power up. Due to the lack of a
1782          * parent/child relationship we currently solve this with an early
1783          * resume hook.
1784          *
1785          * FIXME: This should be solved with a special hdmi sink device or
1786          * similar so that power domains can be employed.
1787          */
1788
1789         /*
1790          * Note that we need to set the power state explicitly, since we
1791          * powered off the device during freeze and the PCI core won't power
1792          * it back up for us during thaw. Powering off the device during
1793          * freeze is not a hard requirement though, and during the
1794          * suspend/resume phases the PCI core makes sure we get here with the
1795          * device powered on. So in case we change our freeze logic and keep
1796          * the device powered we can also remove the following set power state
1797          * call.
1798          */
1799         ret = pci_set_power_state(pdev, PCI_D0);
1800         if (ret) {
1801                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1802                 goto out;
1803         }
1804
1805         /*
1806          * Note that pci_enable_device() first enables any parent bridge
1807          * device and only then sets the power state for this device. The
1808          * bridge enabling is a nop though, since bridge devices are resumed
1809          * first. The order of enabling power and enabling the device is
1810          * imposed by the PCI core as described above, so here we preserve the
1811          * same order for the freeze/thaw phases.
1812          *
1813          * TODO: eventually we should remove pci_disable_device() /
1814          * pci_enable_enable_device() from suspend/resume. Due to how they
1815          * depend on the device enable refcount we can't anyway depend on them
1816          * disabling/enabling the device.
1817          */
1818         if (pci_enable_device(pdev)) {
1819                 ret = -EIO;
1820                 goto out;
1821         }
1822
1823         pci_set_master(pdev);
1824
1825         disable_rpm_wakeref_asserts(dev_priv);
1826
1827         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1828                 ret = vlv_resume_prepare(dev_priv, false);
1829         if (ret)
1830                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1831                           ret);
1832
1833         intel_uncore_resume_early(dev_priv);
1834
1835         if (IS_GEN9_LP(dev_priv)) {
1836                 gen9_sanitize_dc_state(dev_priv);
1837                 bxt_disable_dc9(dev_priv);
1838         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1839                 hsw_disable_pc8(dev_priv);
1840         }
1841
1842         intel_uncore_sanitize(dev_priv);
1843
1844         if (dev_priv->power_domains_suspended)
1845                 intel_power_domains_init_hw(dev_priv, true);
1846         else
1847                 intel_display_set_init_power(dev_priv, true);
1848
1849         i915_gem_sanitize(dev_priv);
1850
1851         enable_rpm_wakeref_asserts(dev_priv);
1852
1853 out:
1854         dev_priv->power_domains_suspended = false;
1855
1856         return ret;
1857 }
1858
1859 static int i915_resume_switcheroo(struct drm_device *dev)
1860 {
1861         int ret;
1862
1863         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1864                 return 0;
1865
1866         ret = i915_drm_resume_early(dev);
1867         if (ret)
1868                 return ret;
1869
1870         return i915_drm_resume(dev);
1871 }
1872
1873 /**
1874  * i915_reset - reset chip after a hang
1875  * @i915: #drm_i915_private to reset
1876  * @flags: Instructions
1877  *
1878  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1879  * on failure.
1880  *
1881  * Caller must hold the struct_mutex.
1882  *
1883  * Procedure is fairly simple:
1884  *   - reset the chip using the reset reg
1885  *   - re-init context state
1886  *   - re-init hardware status page
1887  *   - re-init ring buffer
1888  *   - re-init interrupt state
1889  *   - re-init display
1890  */
1891 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1892 {
1893         struct i915_gpu_error *error = &i915->gpu_error;
1894         int ret;
1895         int i;
1896
1897         might_sleep();
1898         lockdep_assert_held(&i915->drm.struct_mutex);
1899         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1900
1901         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1902                 return;
1903
1904         /* Clear any previous failed attempts at recovery. Time to try again. */
1905         if (!i915_gem_unset_wedged(i915))
1906                 goto wakeup;
1907
1908         if (!(flags & I915_RESET_QUIET))
1909                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1910         error->reset_count++;
1911
1912         disable_irq(i915->drm.irq);
1913         ret = i915_gem_reset_prepare(i915);
1914         if (ret) {
1915                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1916                 goto taint;
1917         }
1918
1919         if (!intel_has_gpu_reset(i915)) {
1920                 if (i915_modparams.reset)
1921                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1922                 else
1923                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1924                 goto error;
1925         }
1926
1927         for (i = 0; i < 3; i++) {
1928                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1929                 if (ret == 0)
1930                         break;
1931
1932                 msleep(100);
1933         }
1934         if (ret) {
1935                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1936                 goto taint;
1937         }
1938
1939         /* Ok, now get things going again... */
1940
1941         /*
1942          * Everything depends on having the GTT running, so we need to start
1943          * there.
1944          */
1945         ret = i915_ggtt_enable_hw(i915);
1946         if (ret) {
1947                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1948                           ret);
1949                 goto error;
1950         }
1951
1952         i915_gem_reset(i915);
1953         intel_overlay_reset(i915);
1954
1955         /*
1956          * Next we need to restore the context, but we don't use those
1957          * yet either...
1958          *
1959          * Ring buffer needs to be re-initialized in the KMS case, or if X
1960          * was running at the time of the reset (i.e. we weren't VT
1961          * switched away).
1962          */
1963         ret = i915_gem_init_hw(i915);
1964         if (ret) {
1965                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1966                           ret);
1967                 goto error;
1968         }
1969
1970         i915_queue_hangcheck(i915);
1971
1972 finish:
1973         i915_gem_reset_finish(i915);
1974         enable_irq(i915->drm.irq);
1975
1976 wakeup:
1977         clear_bit(I915_RESET_HANDOFF, &error->flags);
1978         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1979         return;
1980
1981 taint:
1982         /*
1983          * History tells us that if we cannot reset the GPU now, we
1984          * never will. This then impacts everything that is run
1985          * subsequently. On failing the reset, we mark the driver
1986          * as wedged, preventing further execution on the GPU.
1987          * We also want to go one step further and add a taint to the
1988          * kernel so that any subsequent faults can be traced back to
1989          * this failure. This is important for CI, where if the
1990          * GPU/driver fails we would like to reboot and restart testing
1991          * rather than continue on into oblivion. For everyone else,
1992          * the system should still plod along, but they have been warned!
1993          */
1994         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
1995 error:
1996         i915_gem_set_wedged(i915);
1997         i915_retire_requests(i915);
1998         intel_gpu_reset(i915, ALL_ENGINES);
1999         goto finish;
2000 }
2001
2002 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2003                                         struct intel_engine_cs *engine)
2004 {
2005         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2006 }
2007
2008 /**
2009  * i915_reset_engine - reset GPU engine to recover from a hang
2010  * @engine: engine to reset
2011  * @flags: options
2012  *
2013  * Reset a specific GPU engine. Useful if a hang is detected.
2014  * Returns zero on successful reset or otherwise an error code.
2015  *
2016  * Procedure is:
2017  *  - identifies the request that caused the hang and it is dropped
2018  *  - reset engine (which will force the engine to idle)
2019  *  - re-init/configure engine
2020  */
2021 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
2022 {
2023         struct i915_gpu_error *error = &engine->i915->gpu_error;
2024         struct i915_request *active_request;
2025         int ret;
2026
2027         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2028
2029         active_request = i915_gem_reset_prepare_engine(engine);
2030         if (IS_ERR_OR_NULL(active_request)) {
2031                 /* Either the previous reset failed, or we pardon the reset. */
2032                 ret = PTR_ERR(active_request);
2033                 goto out;
2034         }
2035
2036         if (!(flags & I915_RESET_QUIET)) {
2037                 dev_notice(engine->i915->drm.dev,
2038                            "Resetting %s after gpu hang\n", engine->name);
2039         }
2040         error->reset_engine_count[engine->id]++;
2041
2042         if (!engine->i915->guc.execbuf_client)
2043                 ret = intel_gt_reset_engine(engine->i915, engine);
2044         else
2045                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2046         if (ret) {
2047                 /* If we fail here, we expect to fallback to a global reset */
2048                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2049                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2050                                  engine->name, ret);
2051                 goto out;
2052         }
2053
2054         /*
2055          * The request that caused the hang is stuck on elsp, we know the
2056          * active request and can drop it, adjust head to skip the offending
2057          * request to resume executing remaining requests in the queue.
2058          */
2059         i915_gem_reset_engine(engine, active_request);
2060
2061         /*
2062          * The engine and its registers (and workarounds in case of render)
2063          * have been reset to their default values. Follow the init_ring
2064          * process to program RING_MODE, HWSP and re-enable submission.
2065          */
2066         ret = engine->init_hw(engine);
2067         if (ret)
2068                 goto out;
2069
2070 out:
2071         i915_gem_reset_finish_engine(engine);
2072         return ret;
2073 }
2074
2075 static int i915_pm_suspend(struct device *kdev)
2076 {
2077         struct pci_dev *pdev = to_pci_dev(kdev);
2078         struct drm_device *dev = pci_get_drvdata(pdev);
2079
2080         if (!dev) {
2081                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2082                 return -ENODEV;
2083         }
2084
2085         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2086                 return 0;
2087
2088         return i915_drm_suspend(dev);
2089 }
2090
2091 static int i915_pm_suspend_late(struct device *kdev)
2092 {
2093         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2094
2095         /*
2096          * We have a suspend ordering issue with the snd-hda driver also
2097          * requiring our device to be power up. Due to the lack of a
2098          * parent/child relationship we currently solve this with an late
2099          * suspend hook.
2100          *
2101          * FIXME: This should be solved with a special hdmi sink device or
2102          * similar so that power domains can be employed.
2103          */
2104         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2105                 return 0;
2106
2107         return i915_drm_suspend_late(dev, false);
2108 }
2109
2110 static int i915_pm_poweroff_late(struct device *kdev)
2111 {
2112         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2113
2114         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2115                 return 0;
2116
2117         return i915_drm_suspend_late(dev, true);
2118 }
2119
2120 static int i915_pm_resume_early(struct device *kdev)
2121 {
2122         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2123
2124         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2125                 return 0;
2126
2127         return i915_drm_resume_early(dev);
2128 }
2129
2130 static int i915_pm_resume(struct device *kdev)
2131 {
2132         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2133
2134         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2135                 return 0;
2136
2137         return i915_drm_resume(dev);
2138 }
2139
2140 /* freeze: before creating the hibernation_image */
2141 static int i915_pm_freeze(struct device *kdev)
2142 {
2143         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2144         int ret;
2145
2146         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2147                 ret = i915_drm_suspend(dev);
2148                 if (ret)
2149                         return ret;
2150         }
2151
2152         ret = i915_gem_freeze(kdev_to_i915(kdev));
2153         if (ret)
2154                 return ret;
2155
2156         return 0;
2157 }
2158
2159 static int i915_pm_freeze_late(struct device *kdev)
2160 {
2161         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2162         int ret;
2163
2164         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2165                 ret = i915_drm_suspend_late(dev, true);
2166                 if (ret)
2167                         return ret;
2168         }
2169
2170         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2171         if (ret)
2172                 return ret;
2173
2174         return 0;
2175 }
2176
2177 /* thaw: called after creating the hibernation image, but before turning off. */
2178 static int i915_pm_thaw_early(struct device *kdev)
2179 {
2180         return i915_pm_resume_early(kdev);
2181 }
2182
2183 static int i915_pm_thaw(struct device *kdev)
2184 {
2185         return i915_pm_resume(kdev);
2186 }
2187
2188 /* restore: called after loading the hibernation image. */
2189 static int i915_pm_restore_early(struct device *kdev)
2190 {
2191         return i915_pm_resume_early(kdev);
2192 }
2193
2194 static int i915_pm_restore(struct device *kdev)
2195 {
2196         return i915_pm_resume(kdev);
2197 }
2198
2199 /*
2200  * Save all Gunit registers that may be lost after a D3 and a subsequent
2201  * S0i[R123] transition. The list of registers needing a save/restore is
2202  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2203  * registers in the following way:
2204  * - Driver: saved/restored by the driver
2205  * - Punit : saved/restored by the Punit firmware
2206  * - No, w/o marking: no need to save/restore, since the register is R/O or
2207  *                    used internally by the HW in a way that doesn't depend
2208  *                    keeping the content across a suspend/resume.
2209  * - Debug : used for debugging
2210  *
2211  * We save/restore all registers marked with 'Driver', with the following
2212  * exceptions:
2213  * - Registers out of use, including also registers marked with 'Debug'.
2214  *   These have no effect on the driver's operation, so we don't save/restore
2215  *   them to reduce the overhead.
2216  * - Registers that are fully setup by an initialization function called from
2217  *   the resume path. For example many clock gating and RPS/RC6 registers.
2218  * - Registers that provide the right functionality with their reset defaults.
2219  *
2220  * TODO: Except for registers that based on the above 3 criteria can be safely
2221  * ignored, we save/restore all others, practically treating the HW context as
2222  * a black-box for the driver. Further investigation is needed to reduce the
2223  * saved/restored registers even further, by following the same 3 criteria.
2224  */
2225 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2226 {
2227         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2228         int i;
2229
2230         /* GAM 0x4000-0x4770 */
2231         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2232         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2233         s->arb_mode             = I915_READ(ARB_MODE);
2234         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2235         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2236
2237         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2238                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2239
2240         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2241         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2242
2243         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2244         s->ecochk               = I915_READ(GAM_ECOCHK);
2245         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2246         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2247
2248         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2249
2250         /* MBC 0x9024-0x91D0, 0x8500 */
2251         s->g3dctl               = I915_READ(VLV_G3DCTL);
2252         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2253         s->mbctl                = I915_READ(GEN6_MBCTL);
2254
2255         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2256         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2257         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2258         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2259         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2260         s->rstctl               = I915_READ(GEN6_RSTCTL);
2261         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2262
2263         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2264         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2265         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2266         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2267         s->ecobus               = I915_READ(ECOBUS);
2268         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2269         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2270         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2271         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2272         s->rcedata              = I915_READ(VLV_RCEDATA);
2273         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2274
2275         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2276         s->gt_imr               = I915_READ(GTIMR);
2277         s->gt_ier               = I915_READ(GTIER);
2278         s->pm_imr               = I915_READ(GEN6_PMIMR);
2279         s->pm_ier               = I915_READ(GEN6_PMIER);
2280
2281         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2282                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2283
2284         /* GT SA CZ domain, 0x100000-0x138124 */
2285         s->tilectl              = I915_READ(TILECTL);
2286         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2287         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2288         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2289         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2290
2291         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2292         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2293         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2294         s->pcbr                 = I915_READ(VLV_PCBR);
2295         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2296
2297         /*
2298          * Not saving any of:
2299          * DFT,         0x9800-0x9EC0
2300          * SARB,        0xB000-0xB1FC
2301          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2302          * PCI CFG
2303          */
2304 }
2305
2306 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2307 {
2308         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2309         u32 val;
2310         int i;
2311
2312         /* GAM 0x4000-0x4770 */
2313         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2314         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2315         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2316         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2317         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2318
2319         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2320                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2321
2322         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2323         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2324
2325         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2326         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2327         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2328         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2329
2330         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2331
2332         /* MBC 0x9024-0x91D0, 0x8500 */
2333         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2334         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2335         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2336
2337         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2338         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2339         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2340         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2341         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2342         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2343         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2344
2345         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2346         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2347         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2348         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2349         I915_WRITE(ECOBUS,              s->ecobus);
2350         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2351         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2352         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2353         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2354         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2355         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2356
2357         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2358         I915_WRITE(GTIMR,               s->gt_imr);
2359         I915_WRITE(GTIER,               s->gt_ier);
2360         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2361         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2362
2363         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2364                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2365
2366         /* GT SA CZ domain, 0x100000-0x138124 */
2367         I915_WRITE(TILECTL,                     s->tilectl);
2368         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2369         /*
2370          * Preserve the GT allow wake and GFX force clock bit, they are not
2371          * be restored, as they are used to control the s0ix suspend/resume
2372          * sequence by the caller.
2373          */
2374         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2375         val &= VLV_GTLC_ALLOWWAKEREQ;
2376         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2377         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2378
2379         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2380         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2381         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2382         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2383
2384         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2385
2386         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2387         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2388         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2389         I915_WRITE(VLV_PCBR,                    s->pcbr);
2390         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2391 }
2392
2393 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2394                                   u32 mask, u32 val)
2395 {
2396         /* The HW does not like us polling for PW_STATUS frequently, so
2397          * use the sleeping loop rather than risk the busy spin within
2398          * intel_wait_for_register().
2399          *
2400          * Transitioning between RC6 states should be at most 2ms (see
2401          * valleyview_enable_rps) so use a 3ms timeout.
2402          */
2403         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2404                         3);
2405 }
2406
2407 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2408 {
2409         u32 val;
2410         int err;
2411
2412         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2413         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2414         if (force_on)
2415                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2416         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2417
2418         if (!force_on)
2419                 return 0;
2420
2421         err = intel_wait_for_register(dev_priv,
2422                                       VLV_GTLC_SURVIVABILITY_REG,
2423                                       VLV_GFX_CLK_STATUS_BIT,
2424                                       VLV_GFX_CLK_STATUS_BIT,
2425                                       20);
2426         if (err)
2427                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2428                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2429
2430         return err;
2431 }
2432
2433 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2434 {
2435         u32 mask;
2436         u32 val;
2437         int err;
2438
2439         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2440         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2441         if (allow)
2442                 val |= VLV_GTLC_ALLOWWAKEREQ;
2443         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2444         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2445
2446         mask = VLV_GTLC_ALLOWWAKEACK;
2447         val = allow ? mask : 0;
2448
2449         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2450         if (err)
2451                 DRM_ERROR("timeout disabling GT waking\n");
2452
2453         return err;
2454 }
2455
2456 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2457                                   bool wait_for_on)
2458 {
2459         u32 mask;
2460         u32 val;
2461
2462         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2463         val = wait_for_on ? mask : 0;
2464
2465         /*
2466          * RC6 transitioning can be delayed up to 2 msec (see
2467          * valleyview_enable_rps), use 3 msec for safety.
2468          */
2469         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2470                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2471                           onoff(wait_for_on));
2472 }
2473
2474 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2475 {
2476         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2477                 return;
2478
2479         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2480         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2481 }
2482
2483 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2484 {
2485         u32 mask;
2486         int err;
2487
2488         /*
2489          * Bspec defines the following GT well on flags as debug only, so
2490          * don't treat them as hard failures.
2491          */
2492         vlv_wait_for_gt_wells(dev_priv, false);
2493
2494         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2495         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2496
2497         vlv_check_no_gt_access(dev_priv);
2498
2499         err = vlv_force_gfx_clock(dev_priv, true);
2500         if (err)
2501                 goto err1;
2502
2503         err = vlv_allow_gt_wake(dev_priv, false);
2504         if (err)
2505                 goto err2;
2506
2507         if (!IS_CHERRYVIEW(dev_priv))
2508                 vlv_save_gunit_s0ix_state(dev_priv);
2509
2510         err = vlv_force_gfx_clock(dev_priv, false);
2511         if (err)
2512                 goto err2;
2513
2514         return 0;
2515
2516 err2:
2517         /* For safety always re-enable waking and disable gfx clock forcing */
2518         vlv_allow_gt_wake(dev_priv, true);
2519 err1:
2520         vlv_force_gfx_clock(dev_priv, false);
2521
2522         return err;
2523 }
2524
2525 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2526                                 bool rpm_resume)
2527 {
2528         int err;
2529         int ret;
2530
2531         /*
2532          * If any of the steps fail just try to continue, that's the best we
2533          * can do at this point. Return the first error code (which will also
2534          * leave RPM permanently disabled).
2535          */
2536         ret = vlv_force_gfx_clock(dev_priv, true);
2537
2538         if (!IS_CHERRYVIEW(dev_priv))
2539                 vlv_restore_gunit_s0ix_state(dev_priv);
2540
2541         err = vlv_allow_gt_wake(dev_priv, true);
2542         if (!ret)
2543                 ret = err;
2544
2545         err = vlv_force_gfx_clock(dev_priv, false);
2546         if (!ret)
2547                 ret = err;
2548
2549         vlv_check_no_gt_access(dev_priv);
2550
2551         if (rpm_resume)
2552                 intel_init_clock_gating(dev_priv);
2553
2554         return ret;
2555 }
2556
2557 static int intel_runtime_suspend(struct device *kdev)
2558 {
2559         struct pci_dev *pdev = to_pci_dev(kdev);
2560         struct drm_device *dev = pci_get_drvdata(pdev);
2561         struct drm_i915_private *dev_priv = to_i915(dev);
2562         int ret;
2563
2564         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2565                 return -ENODEV;
2566
2567         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2568                 return -ENODEV;
2569
2570         DRM_DEBUG_KMS("Suspending device\n");
2571
2572         disable_rpm_wakeref_asserts(dev_priv);
2573
2574         /*
2575          * We are safe here against re-faults, since the fault handler takes
2576          * an RPM reference.
2577          */
2578         i915_gem_runtime_suspend(dev_priv);
2579
2580         intel_uc_suspend(dev_priv);
2581
2582         intel_runtime_pm_disable_interrupts(dev_priv);
2583
2584         intel_uncore_suspend(dev_priv);
2585
2586         ret = 0;
2587         if (IS_GEN9_LP(dev_priv)) {
2588                 bxt_display_core_uninit(dev_priv);
2589                 bxt_enable_dc9(dev_priv);
2590         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2591                 hsw_enable_pc8(dev_priv);
2592         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2593                 ret = vlv_suspend_complete(dev_priv);
2594         }
2595
2596         if (ret) {
2597                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2598                 intel_uncore_runtime_resume(dev_priv);
2599
2600                 intel_runtime_pm_enable_interrupts(dev_priv);
2601
2602                 intel_uc_resume(dev_priv);
2603
2604                 i915_gem_init_swizzling(dev_priv);
2605                 i915_gem_restore_fences(dev_priv);
2606
2607                 enable_rpm_wakeref_asserts(dev_priv);
2608
2609                 return ret;
2610         }
2611
2612         enable_rpm_wakeref_asserts(dev_priv);
2613         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2614
2615         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2616                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2617
2618         dev_priv->runtime_pm.suspended = true;
2619
2620         /*
2621          * FIXME: We really should find a document that references the arguments
2622          * used below!
2623          */
2624         if (IS_BROADWELL(dev_priv)) {
2625                 /*
2626                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2627                  * being detected, and the call we do at intel_runtime_resume()
2628                  * won't be able to restore them. Since PCI_D3hot matches the
2629                  * actual specification and appears to be working, use it.
2630                  */
2631                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2632         } else {
2633                 /*
2634                  * current versions of firmware which depend on this opregion
2635                  * notification have repurposed the D1 definition to mean
2636                  * "runtime suspended" vs. what you would normally expect (D3)
2637                  * to distinguish it from notifications that might be sent via
2638                  * the suspend path.
2639                  */
2640                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2641         }
2642
2643         assert_forcewakes_inactive(dev_priv);
2644
2645         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2646                 intel_hpd_poll_init(dev_priv);
2647
2648         DRM_DEBUG_KMS("Device suspended\n");
2649         return 0;
2650 }
2651
2652 static int intel_runtime_resume(struct device *kdev)
2653 {
2654         struct pci_dev *pdev = to_pci_dev(kdev);
2655         struct drm_device *dev = pci_get_drvdata(pdev);
2656         struct drm_i915_private *dev_priv = to_i915(dev);
2657         int ret = 0;
2658
2659         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2660                 return -ENODEV;
2661
2662         DRM_DEBUG_KMS("Resuming device\n");
2663
2664         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2665         disable_rpm_wakeref_asserts(dev_priv);
2666
2667         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2668         dev_priv->runtime_pm.suspended = false;
2669         if (intel_uncore_unclaimed_mmio(dev_priv))
2670                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2671
2672         if (IS_GEN9_LP(dev_priv)) {
2673                 bxt_disable_dc9(dev_priv);
2674                 bxt_display_core_init(dev_priv, true);
2675                 if (dev_priv->csr.dmc_payload &&
2676                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2677                         gen9_enable_dc5(dev_priv);
2678         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2679                 hsw_disable_pc8(dev_priv);
2680         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2681                 ret = vlv_resume_prepare(dev_priv, true);
2682         }
2683
2684         intel_uncore_runtime_resume(dev_priv);
2685
2686         intel_runtime_pm_enable_interrupts(dev_priv);
2687
2688         intel_uc_resume(dev_priv);
2689
2690         /*
2691          * No point of rolling back things in case of an error, as the best
2692          * we can do is to hope that things will still work (and disable RPM).
2693          */
2694         i915_gem_init_swizzling(dev_priv);
2695         i915_gem_restore_fences(dev_priv);
2696
2697         /*
2698          * On VLV/CHV display interrupts are part of the display
2699          * power well, so hpd is reinitialized from there. For
2700          * everyone else do it here.
2701          */
2702         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2703                 intel_hpd_init(dev_priv);
2704
2705         intel_enable_ipc(dev_priv);
2706
2707         enable_rpm_wakeref_asserts(dev_priv);
2708
2709         if (ret)
2710                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2711         else
2712                 DRM_DEBUG_KMS("Device resumed\n");
2713
2714         return ret;
2715 }
2716
2717 const struct dev_pm_ops i915_pm_ops = {
2718         /*
2719          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2720          * PMSG_RESUME]
2721          */
2722         .suspend = i915_pm_suspend,
2723         .suspend_late = i915_pm_suspend_late,
2724         .resume_early = i915_pm_resume_early,
2725         .resume = i915_pm_resume,
2726
2727         /*
2728          * S4 event handlers
2729          * @freeze, @freeze_late    : called (1) before creating the
2730          *                            hibernation image [PMSG_FREEZE] and
2731          *                            (2) after rebooting, before restoring
2732          *                            the image [PMSG_QUIESCE]
2733          * @thaw, @thaw_early       : called (1) after creating the hibernation
2734          *                            image, before writing it [PMSG_THAW]
2735          *                            and (2) after failing to create or
2736          *                            restore the image [PMSG_RECOVER]
2737          * @poweroff, @poweroff_late: called after writing the hibernation
2738          *                            image, before rebooting [PMSG_HIBERNATE]
2739          * @restore, @restore_early : called after rebooting and restoring the
2740          *                            hibernation image [PMSG_RESTORE]
2741          */
2742         .freeze = i915_pm_freeze,
2743         .freeze_late = i915_pm_freeze_late,
2744         .thaw_early = i915_pm_thaw_early,
2745         .thaw = i915_pm_thaw,
2746         .poweroff = i915_pm_suspend,
2747         .poweroff_late = i915_pm_poweroff_late,
2748         .restore_early = i915_pm_restore_early,
2749         .restore = i915_pm_restore,
2750
2751         /* S0ix (via runtime suspend) event handlers */
2752         .runtime_suspend = intel_runtime_suspend,
2753         .runtime_resume = intel_runtime_resume,
2754 };
2755
2756 static const struct vm_operations_struct i915_gem_vm_ops = {
2757         .fault = i915_gem_fault,
2758         .open = drm_gem_vm_open,
2759         .close = drm_gem_vm_close,
2760 };
2761
2762 static const struct file_operations i915_driver_fops = {
2763         .owner = THIS_MODULE,
2764         .open = drm_open,
2765         .release = drm_release,
2766         .unlocked_ioctl = drm_ioctl,
2767         .mmap = drm_gem_mmap,
2768         .poll = drm_poll,
2769         .read = drm_read,
2770         .compat_ioctl = i915_compat_ioctl,
2771         .llseek = noop_llseek,
2772 };
2773
2774 static int
2775 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2776                           struct drm_file *file)
2777 {
2778         return -ENODEV;
2779 }
2780
2781 static const struct drm_ioctl_desc i915_ioctls[] = {
2782         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2783         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2784         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2785         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2786         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2787         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2788         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2789         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2790         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2791         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2792         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2793         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2794         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2795         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2796         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2797         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2798         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2799         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2800         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2801         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2802         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2803         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2804         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2805         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2806         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2807         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2808         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2809         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2810         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2821         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2822         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2837         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2838 };
2839
2840 static struct drm_driver driver = {
2841         /* Don't use MTRRs here; the Xserver or userspace app should
2842          * deal with them for Intel hardware.
2843          */
2844         .driver_features =
2845             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2846             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2847         .release = i915_driver_release,
2848         .open = i915_driver_open,
2849         .lastclose = i915_driver_lastclose,
2850         .postclose = i915_driver_postclose,
2851
2852         .gem_close_object = i915_gem_close_object,
2853         .gem_free_object_unlocked = i915_gem_free_object,
2854         .gem_vm_ops = &i915_gem_vm_ops,
2855
2856         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2857         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2858         .gem_prime_export = i915_gem_prime_export,
2859         .gem_prime_import = i915_gem_prime_import,
2860
2861         .dumb_create = i915_gem_dumb_create,
2862         .dumb_map_offset = i915_gem_mmap_gtt,
2863         .ioctls = i915_ioctls,
2864         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2865         .fops = &i915_driver_fops,
2866         .name = DRIVER_NAME,
2867         .desc = DRIVER_DESC,
2868         .date = DRIVER_DATE,
2869         .major = DRIVER_MAJOR,
2870         .minor = DRIVER_MINOR,
2871         .patchlevel = DRIVER_PATCHLEVEL,
2872 };
2873
2874 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2875 #include "selftests/mock_drm.c"
2876 #endif