drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_vgpu.h"
  52 #include "intel_drv.h"
  53 #include "intel_uc.h"
  54
  55 static struct drm_driver driver;
  56
  57 static unsigned int i915_load_fail_count;
  58
  59 bool __i915_inject_load_failure(const char *func, int line)
  60 {
  61         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  62                 return false;
  63
  64         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  66                          i915_modparams.inject_load_failure, func, line);
  67                 return true;
  68         }
  69
  70         return false;
  71 }
  72
  73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  75                     "providing the dmesg log by booting with drm.debug=0xf"
  76
  77 void
  78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  79               const char *fmt, ...)
  80 {
  81         static bool shown_bug_once;
  82         struct device *kdev = dev_priv->drm.dev;
  83         bool is_error = level[1] <= KERN_ERR[1];
  84         bool is_debug = level[1] == KERN_DEBUG[1];
  85         struct va_format vaf;
  86         va_list args;
  87
  88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  89                 return;
  90
  91         va_start(args, fmt);
  92
  93         vaf.fmt = fmt;
  94         vaf.va = &args;
  95
  96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  97                    __builtin_return_address(0), &vaf);
  98
  99         if (is_error && !shown_bug_once) {
 100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
 101                 shown_bug_once = true;
 102         }
 103
 104         va_end(args);
 105 }
 106
 107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 108 {
 109         return i915_modparams.inject_load_failure &&
 110                i915_load_fail_count == i915_modparams.inject_load_failure;
 111 }
 112
 113 #define i915_load_error(dev_priv, fmt, ...)                                  \
 114         __i915_printk(dev_priv,                                              \
 115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 116                       fmt, ##__VA_ARGS__)
 117
 118
 119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 120 {
 121         enum intel_pch ret = PCH_NOP;
 122
 123         /*
 124          * In a virtualized passthrough environment we can be in a
 125          * setup where the ISA bridge is not able to be passed through.
 126          * In this case, a south bridge can be emulated and we have to
 127          * make an educated guess as to which PCH is really there.
 128          */
 129
 130         if (IS_GEN5(dev_priv)) {
 131                 ret = PCH_IBX;
 132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 134                 ret = PCH_CPT;
 135                 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
 136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 137                 ret = PCH_LPT;
 138                 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 139                         dev_priv->pch_id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 140                 else
 141                         dev_priv->pch_id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 142                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 143         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 144                 ret = PCH_SPT;
 145                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 146         } else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 147                 ret = PCH_CNP;
 148                 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
 149         }
 150
 151         return ret;
 152 }
 153
 154 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 155 {
 156         struct pci_dev *pch = NULL;
 157
 158         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 159          * (which really amounts to a PCH but no South Display).
 160          */
 161         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 162                 dev_priv->pch_type = PCH_NOP;
 163                 return;
 164         }
 165
 166         /*
 167          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 168          * make graphics device passthrough work easy for VMM, that only
 169          * need to expose ISA bridge to let driver know the real hardware
 170          * underneath. This is a requirement from virtualization team.
 171          *
 172          * In some virtualized environments (e.g. XEN), there is irrelevant
 173          * ISA bridge in the system. To work reliably, we should scan trhough
 174          * all the ISA bridge devices and check for the first match, instead
 175          * of only checking the first one.
 176          */
 177         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 178                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 179                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 180
 181                         dev_priv->pch_id = id;
 182
 183                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 184                                 dev_priv->pch_type = PCH_IBX;
 185                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 186                                 WARN_ON(!IS_GEN5(dev_priv));
 187                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_CPT;
 189                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 190                                 WARN_ON(!IS_GEN6(dev_priv) &&
 191                                         !IS_IVYBRIDGE(dev_priv));
 192                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 193                                 /* PantherPoint is CPT compatible */
 194                                 dev_priv->pch_type = PCH_CPT;
 195                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 196                                 WARN_ON(!IS_GEN6(dev_priv) &&
 197                                         !IS_IVYBRIDGE(dev_priv));
 198                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 199                                 dev_priv->pch_type = PCH_LPT;
 200                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 201                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 202                                         !IS_BROADWELL(dev_priv));
 203                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 204                                         IS_BDW_ULT(dev_priv));
 205                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 206                                 dev_priv->pch_type = PCH_LPT;
 207                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 208                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 209                                         !IS_BROADWELL(dev_priv));
 210                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 211                                         !IS_BDW_ULT(dev_priv));
 212                         } else if (id == INTEL_PCH_WPT_DEVICE_ID_TYPE) {
 213                                 /* WildcatPoint is LPT compatible */
 214                                 dev_priv->pch_type = PCH_LPT;
 215                                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 216                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 217                                         !IS_BROADWELL(dev_priv));
 218                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 219                                         IS_BDW_ULT(dev_priv));
 220                         } else if (id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) {
 221                                 /* WildcatPoint is LPT compatible */
 222                                 dev_priv->pch_type = PCH_LPT;
 223                                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 224                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 225                                         !IS_BROADWELL(dev_priv));
 226                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 227                                         !IS_BDW_ULT(dev_priv));
 228                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 229                                 dev_priv->pch_type = PCH_SPT;
 230                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 231                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 232                                         !IS_KABYLAKE(dev_priv));
 233                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 234                                 dev_priv->pch_type = PCH_SPT;
 235                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 236                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 237                                         !IS_KABYLAKE(dev_priv));
 238                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 239                                 dev_priv->pch_type = PCH_KBP;
 240                                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 241                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 242                                         !IS_KABYLAKE(dev_priv) &&
 243                                         !IS_COFFEELAKE(dev_priv));
 244                         } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) {
 245                                 dev_priv->pch_type = PCH_CNP;
 246                                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 247                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 248                                         !IS_COFFEELAKE(dev_priv));
 249                         } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) {
 250                                 dev_priv->pch_type = PCH_CNP;
 251                                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 252                                 WARN_ON(!IS_CANNONLAKE(dev_priv) &&
 253                                         !IS_COFFEELAKE(dev_priv));
 254                         } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 255                                    id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 256                                    (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 257                                     pch->subsystem_vendor ==
 258                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 259                                     pch->subsystem_device ==
 260                                             PCI_SUBDEVICE_ID_QEMU)) {
 261                                 dev_priv->pch_type =
 262                                         intel_virt_detect_pch(dev_priv);
 263                         } else
 264                                 continue;
 265
 266                         break;
 267                 }
 268         }
 269         if (!pch)
 270                 DRM_DEBUG_KMS("No PCH found.\n");
 271
 272         pci_dev_put(pch);
 273 }
 274
 275 static int i915_getparam(struct drm_device *dev, void *data,
 276                          struct drm_file *file_priv)
 277 {
 278         struct drm_i915_private *dev_priv = to_i915(dev);
 279         struct pci_dev *pdev = dev_priv->drm.pdev;
 280         drm_i915_getparam_t *param = data;
 281         int value;
 282
 283         switch (param->param) {
 284         case I915_PARAM_IRQ_ACTIVE:
 285         case I915_PARAM_ALLOW_BATCHBUFFER:
 286         case I915_PARAM_LAST_DISPATCH:
 287         case I915_PARAM_HAS_EXEC_CONSTANTS:
 288                 /* Reject all old ums/dri params. */
 289                 return -ENODEV;
 290         case I915_PARAM_CHIPSET_ID:
 291                 value = pdev->device;
 292                 break;
 293         case I915_PARAM_REVISION:
 294                 value = pdev->revision;
 295                 break;
 296         case I915_PARAM_NUM_FENCES_AVAIL:
 297                 value = dev_priv->num_fence_regs;
 298                 break;
 299         case I915_PARAM_HAS_OVERLAY:
 300                 value = dev_priv->overlay ? 1 : 0;
 301                 break;
 302         case I915_PARAM_HAS_BSD:
 303                 value = !!dev_priv->engine[VCS];
 304                 break;
 305         case I915_PARAM_HAS_BLT:
 306                 value = !!dev_priv->engine[BCS];
 307                 break;
 308         case I915_PARAM_HAS_VEBOX:
 309                 value = !!dev_priv->engine[VECS];
 310                 break;
 311         case I915_PARAM_HAS_BSD2:
 312                 value = !!dev_priv->engine[VCS2];
 313                 break;
 314         case I915_PARAM_HAS_LLC:
 315                 value = HAS_LLC(dev_priv);
 316                 break;
 317         case I915_PARAM_HAS_WT:
 318                 value = HAS_WT(dev_priv);
 319                 break;
 320         case I915_PARAM_HAS_ALIASING_PPGTT:
 321                 value = USES_PPGTT(dev_priv);
 322                 break;
 323         case I915_PARAM_HAS_SEMAPHORES:
 324                 value = i915_modparams.semaphores;
 325                 break;
 326         case I915_PARAM_HAS_SECURE_BATCHES:
 327                 value = capable(CAP_SYS_ADMIN);
 328                 break;
 329         case I915_PARAM_CMD_PARSER_VERSION:
 330                 value = i915_cmd_parser_get_version(dev_priv);
 331                 break;
 332         case I915_PARAM_SUBSLICE_TOTAL:
 333                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 334                 if (!value)
 335                         return -ENODEV;
 336                 break;
 337         case I915_PARAM_EU_TOTAL:
 338                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 339                 if (!value)
 340                         return -ENODEV;
 341                 break;
 342         case I915_PARAM_HAS_GPU_RESET:
 343                 value = i915_modparams.enable_hangcheck &&
 344                         intel_has_gpu_reset(dev_priv);
 345                 if (value && intel_has_reset_engine(dev_priv))
 346                         value = 2;
 347                 break;
 348         case I915_PARAM_HAS_RESOURCE_STREAMER:
 349                 value = HAS_RESOURCE_STREAMER(dev_priv);
 350                 break;
 351         case I915_PARAM_HAS_POOLED_EU:
 352                 value = HAS_POOLED_EU(dev_priv);
 353                 break;
 354         case I915_PARAM_MIN_EU_IN_POOL:
 355                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 356                 break;
 357         case I915_PARAM_HUC_STATUS:
 358                 intel_runtime_pm_get(dev_priv);
 359                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
 360                 intel_runtime_pm_put(dev_priv);
 361                 break;
 362         case I915_PARAM_MMAP_GTT_VERSION:
 363                 /* Though we've started our numbering from 1, and so class all
 364                  * earlier versions as 0, in effect their value is undefined as
 365                  * the ioctl will report EINVAL for the unknown param!
 366                  */
 367                 value = i915_gem_mmap_gtt_version();
 368                 break;
 369         case I915_PARAM_HAS_SCHEDULER:
 370                 value = 0;
 371                 if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
 372                         value |= I915_SCHEDULER_CAP_ENABLED;
 373                         value |= I915_SCHEDULER_CAP_PRIORITY;
 374
 375                         if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
 376                             i915_modparams.enable_execlists &&
 377                             !i915_modparams.enable_guc_submission)
 378                                 value |= I915_SCHEDULER_CAP_PREEMPTION;
 379                 }
 380                 break;
 381
 382         case I915_PARAM_MMAP_VERSION:
 383                 /* Remember to bump this if the version changes! */
 384         case I915_PARAM_HAS_GEM:
 385         case I915_PARAM_HAS_PAGEFLIPPING:
 386         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 387         case I915_PARAM_HAS_RELAXED_FENCING:
 388         case I915_PARAM_HAS_COHERENT_RINGS:
 389         case I915_PARAM_HAS_RELAXED_DELTA:
 390         case I915_PARAM_HAS_GEN7_SOL_RESET:
 391         case I915_PARAM_HAS_WAIT_TIMEOUT:
 392         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 393         case I915_PARAM_HAS_PINNED_BATCHES:
 394         case I915_PARAM_HAS_EXEC_NO_RELOC:
 395         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 396         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 397         case I915_PARAM_HAS_EXEC_SOFTPIN:
 398         case I915_PARAM_HAS_EXEC_ASYNC:
 399         case I915_PARAM_HAS_EXEC_FENCE:
 400         case I915_PARAM_HAS_EXEC_CAPTURE:
 401         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 402         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 403                 /* For the time being all of these are always true;
 404                  * if some supported hardware does not have one of these
 405                  * features this value needs to be provided from
 406                  * INTEL_INFO(), a feature macro, or similar.
 407                  */
 408                 value = 1;
 409                 break;
 410         case I915_PARAM_SLICE_MASK:
 411                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 412                 if (!value)
 413                         return -ENODEV;
 414                 break;
 415         case I915_PARAM_SUBSLICE_MASK:
 416                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 417                 if (!value)
 418                         return -ENODEV;
 419                 break;
 420         default:
 421                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 422                 return -EINVAL;
 423         }
 424
 425         if (put_user(value, param->value))
 426                 return -EFAULT;
 427
 428         return 0;
 429 }
 430
 431 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 432 {
 433         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 434         if (!dev_priv->bridge_dev) {
 435                 DRM_ERROR("bridge device not found\n");
 436                 return -1;
 437         }
 438         return 0;
 439 }
 440
 441 /* Allocate space for the MCH regs if needed, return nonzero on error */
 442 static int
 443 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 444 {
 445         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 446         u32 temp_lo, temp_hi = 0;
 447         u64 mchbar_addr;
 448         int ret;
 449
 450         if (INTEL_GEN(dev_priv) >= 4)
 451                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 452         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 453         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 454
 455         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 456 #ifdef CONFIG_PNP
 457         if (mchbar_addr &&
 458             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 459                 return 0;
 460 #endif
 461
 462         /* Get some space for it */
 463         dev_priv->mch_res.name = "i915 MCHBAR";
 464         dev_priv->mch_res.flags = IORESOURCE_MEM;
 465         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 466                                      &dev_priv->mch_res,
 467                                      MCHBAR_SIZE, MCHBAR_SIZE,
 468                                      PCIBIOS_MIN_MEM,
 469                                      0, pcibios_align_resource,
 470                                      dev_priv->bridge_dev);
 471         if (ret) {
 472                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 473                 dev_priv->mch_res.start = 0;
 474                 return ret;
 475         }
 476
 477         if (INTEL_GEN(dev_priv) >= 4)
 478                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 479                                        upper_32_bits(dev_priv->mch_res.start));
 480
 481         pci_write_config_dword(dev_priv->bridge_dev, reg,
 482                                lower_32_bits(dev_priv->mch_res.start));
 483         return 0;
 484 }
 485
 486 /* Setup MCHBAR if possible, return true if we should disable it again */
 487 static void
 488 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 489 {
 490         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 491         u32 temp;
 492         bool enabled;
 493
 494         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 495                 return;
 496
 497         dev_priv->mchbar_need_disable = false;
 498
 499         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 500                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 501                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 502         } else {
 503                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 504                 enabled = temp & 1;
 505         }
 506
 507         /* If it's already enabled, don't have to do anything */
 508         if (enabled)
 509                 return;
 510
 511         if (intel_alloc_mchbar_resource(dev_priv))
 512                 return;
 513
 514         dev_priv->mchbar_need_disable = true;
 515
 516         /* Space is allocated or reserved, so enable it. */
 517         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 518                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 519                                        temp | DEVEN_MCHBAR_EN);
 520         } else {
 521                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 522                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 523         }
 524 }
 525
 526 static void
 527 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 528 {
 529         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 530
 531         if (dev_priv->mchbar_need_disable) {
 532                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 533                         u32 deven_val;
 534
 535                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 536                                               &deven_val);
 537                         deven_val &= ~DEVEN_MCHBAR_EN;
 538                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 539                                                deven_val);
 540                 } else {
 541                         u32 mchbar_val;
 542
 543                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 544                                               &mchbar_val);
 545                         mchbar_val &= ~1;
 546                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 547                                                mchbar_val);
 548                 }
 549         }
 550
 551         if (dev_priv->mch_res.start)
 552                 release_resource(&dev_priv->mch_res);
 553 }
 554
 555 /* true = enable decode, false = disable decoder */
 556 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 557 {
 558         struct drm_i915_private *dev_priv = cookie;
 559
 560         intel_modeset_vga_set_state(dev_priv, state);
 561         if (state)
 562                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 563                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 564         else
 565                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 566 }
 567
 568 static int i915_resume_switcheroo(struct drm_device *dev);
 569 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 570
 571 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 572 {
 573         struct drm_device *dev = pci_get_drvdata(pdev);
 574         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 575
 576         if (state == VGA_SWITCHEROO_ON) {
 577                 pr_info("switched on\n");
 578                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 579                 /* i915 resume handler doesn't set to D0 */
 580                 pci_set_power_state(pdev, PCI_D0);
 581                 i915_resume_switcheroo(dev);
 582                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 583         } else {
 584                 pr_info("switched off\n");
 585                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 586                 i915_suspend_switcheroo(dev, pmm);
 587                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 588         }
 589 }
 590
 591 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 592 {
 593         struct drm_device *dev = pci_get_drvdata(pdev);
 594
 595         /*
 596          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 597          * locking inversion with the driver load path. And the access here is
 598          * completely racy anyway. So don't bother with locking for now.
 599          */
 600         return dev->open_count == 0;
 601 }
 602
 603 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 604         .set_gpu_state = i915_switcheroo_set_state,
 605         .reprobe = NULL,
 606         .can_switch = i915_switcheroo_can_switch,
 607 };
 608
 609 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 610 {
 611         /* Flush any outstanding unpin_work. */
 612         i915_gem_drain_workqueue(dev_priv);
 613
 614         mutex_lock(&dev_priv->drm.struct_mutex);
 615         intel_uc_fini_hw(dev_priv);
 616         i915_gem_cleanup_engines(dev_priv);
 617         i915_gem_contexts_fini(dev_priv);
 618         mutex_unlock(&dev_priv->drm.struct_mutex);
 619
 620         i915_gem_cleanup_userptr(dev_priv);
 621
 622         i915_gem_drain_freed_objects(dev_priv);
 623
 624         WARN_ON(!list_empty(&dev_priv->contexts.list));
 625 }
 626
 627 static int i915_load_modeset_init(struct drm_device *dev)
 628 {
 629         struct drm_i915_private *dev_priv = to_i915(dev);
 630         struct pci_dev *pdev = dev_priv->drm.pdev;
 631         int ret;
 632
 633         if (i915_inject_load_failure())
 634                 return -ENODEV;
 635
 636         intel_bios_init(dev_priv);
 637
 638         /* If we have > 1 VGA cards, then we need to arbitrate access
 639          * to the common VGA resources.
 640          *
 641          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 642          * then we do not take part in VGA arbitration and the
 643          * vga_client_register() fails with -ENODEV.
 644          */
 645         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 646         if (ret && ret != -ENODEV)
 647                 goto out;
 648
 649         intel_register_dsm_handler();
 650
 651         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 652         if (ret)
 653                 goto cleanup_vga_client;
 654
 655         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 656         intel_update_rawclk(dev_priv);
 657
 658         intel_power_domains_init_hw(dev_priv, false);
 659
 660         intel_csr_ucode_init(dev_priv);
 661
 662         ret = intel_irq_install(dev_priv);
 663         if (ret)
 664                 goto cleanup_csr;
 665
 666         intel_setup_gmbus(dev_priv);
 667
 668         /* Important: The output setup functions called by modeset_init need
 669          * working irqs for e.g. gmbus and dp aux transfers. */
 670         ret = intel_modeset_init(dev);
 671         if (ret)
 672                 goto cleanup_irq;
 673
 674         intel_uc_init_fw(dev_priv);
 675
 676         ret = i915_gem_init(dev_priv);
 677         if (ret)
 678                 goto cleanup_uc;
 679
 680         intel_modeset_gem_init(dev);
 681
 682         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 683                 return 0;
 684
 685         ret = intel_fbdev_init(dev);
 686         if (ret)
 687                 goto cleanup_gem;
 688
 689         /* Only enable hotplug handling once the fbdev is fully set up. */
 690         intel_hpd_init(dev_priv);
 691
 692         drm_kms_helper_poll_init(dev);
 693
 694         return 0;
 695
 696 cleanup_gem:
 697         if (i915_gem_suspend(dev_priv))
 698                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 699         i915_gem_fini(dev_priv);
 700 cleanup_uc:
 701         intel_uc_fini_fw(dev_priv);
 702 cleanup_irq:
 703         drm_irq_uninstall(dev);
 704         intel_teardown_gmbus(dev_priv);
 705 cleanup_csr:
 706         intel_csr_ucode_fini(dev_priv);
 707         intel_power_domains_fini(dev_priv);
 708         vga_switcheroo_unregister_client(pdev);
 709 cleanup_vga_client:
 710         vga_client_register(pdev, NULL, NULL, NULL);
 711 out:
 712         return ret;
 713 }
 714
 715 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 716 {
 717         struct apertures_struct *ap;
 718         struct pci_dev *pdev = dev_priv->drm.pdev;
 719         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 720         bool primary;
 721         int ret;
 722
 723         ap = alloc_apertures(1);
 724         if (!ap)
 725                 return -ENOMEM;
 726
 727         ap->ranges[0].base = ggtt->mappable_base;
 728         ap->ranges[0].size = ggtt->mappable_end;
 729
 730         primary =
 731                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 732
 733         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 734
 735         kfree(ap);
 736
 737         return ret;
 738 }
 739
 740 #if !defined(CONFIG_VGA_CONSOLE)
 741 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 742 {
 743         return 0;
 744 }
 745 #elif !defined(CONFIG_DUMMY_CONSOLE)
 746 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 747 {
 748         return -ENODEV;
 749 }
 750 #else
 751 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 752 {
 753         int ret = 0;
 754
 755         DRM_INFO("Replacing VGA console driver\n");
 756
 757         console_lock();
 758         if (con_is_bound(&vga_con))
 759                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 760         if (ret == 0) {
 761                 ret = do_unregister_con_driver(&vga_con);
 762
 763                 /* Ignore "already unregistered". */
 764                 if (ret == -ENODEV)
 765                         ret = 0;
 766         }
 767         console_unlock();
 768
 769         return ret;
 770 }
 771 #endif
 772
 773 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 774 {
 775         /*
 776          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 777          * CHV x1 PHY (DP/HDMI D)
 778          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 779          */
 780         if (IS_CHERRYVIEW(dev_priv)) {
 781                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 782                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 783         } else if (IS_VALLEYVIEW(dev_priv)) {
 784                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 785         }
 786 }
 787
 788 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 789 {
 790         /*
 791          * The i915 workqueue is primarily used for batched retirement of
 792          * requests (and thus managing bo) once the task has been completed
 793          * by the GPU. i915_gem_retire_requests() is called directly when we
 794          * need high-priority retirement, such as waiting for an explicit
 795          * bo.
 796          *
 797          * It is also used for periodic low-priority events, such as
 798          * idle-timers and recording error state.
 799          *
 800          * All tasks on the workqueue are expected to acquire the dev mutex
 801          * so there is no point in running more than one instance of the
 802          * workqueue at any time.  Use an ordered one.
 803          */
 804         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 805         if (dev_priv->wq == NULL)
 806                 goto out_err;
 807
 808         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 809         if (dev_priv->hotplug.dp_wq == NULL)
 810                 goto out_free_wq;
 811
 812         return 0;
 813
 814 out_free_wq:
 815         destroy_workqueue(dev_priv->wq);
 816 out_err:
 817         DRM_ERROR("Failed to allocate workqueues.\n");
 818
 819         return -ENOMEM;
 820 }
 821
 822 static void i915_engines_cleanup(struct drm_i915_private *i915)
 823 {
 824         struct intel_engine_cs *engine;
 825         enum intel_engine_id id;
 826
 827         for_each_engine(engine, i915, id)
 828                 kfree(engine);
 829 }
 830
 831 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 832 {
 833         destroy_workqueue(dev_priv->hotplug.dp_wq);
 834         destroy_workqueue(dev_priv->wq);
 835 }
 836
 837 /*
 838  * We don't keep the workarounds for pre-production hardware, so we expect our
 839  * driver to fail on these machines in one way or another. A little warning on
 840  * dmesg may help both the user and the bug triagers.
 841  */
 842 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 843 {
 844         bool pre = false;
 845
 846         pre |= IS_HSW_EARLY_SDV(dev_priv);
 847         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 848         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 849
 850         if (pre) {
 851                 DRM_ERROR("This is a pre-production stepping. "
 852                           "It may not be fully functional.\n");
 853                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 854         }
 855 }
 856
 857 /**
 858  * i915_driver_init_early - setup state not requiring device access
 859  * @dev_priv: device private
 860  *
 861  * Initialize everything that is a "SW-only" state, that is state not
 862  * requiring accessing the device or exposing the driver via kernel internal
 863  * or userspace interfaces. Example steps belonging here: lock initialization,
 864  * system memory allocation, setting up device specific attributes and
 865  * function hooks not requiring accessing the device.
 866  */
 867 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 868                                   const struct pci_device_id *ent)
 869 {
 870         const struct intel_device_info *match_info =
 871                 (struct intel_device_info *)ent->driver_data;
 872         struct intel_device_info *device_info;
 873         int ret = 0;
 874
 875         if (i915_inject_load_failure())
 876                 return -ENODEV;
 877
 878         /* Setup the write-once "constant" device info */
 879         device_info = mkwrite_device_info(dev_priv);
 880         memcpy(device_info, match_info, sizeof(*device_info));
 881         device_info->device_id = dev_priv->drm.pdev->device;
 882
 883         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 884                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 885         device_info->platform_mask = BIT(device_info->platform);
 886
 887         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 888         device_info->gen_mask = BIT(device_info->gen - 1);
 889
 890         spin_lock_init(&dev_priv->irq_lock);
 891         spin_lock_init(&dev_priv->gpu_error.lock);
 892         mutex_init(&dev_priv->backlight_lock);
 893         spin_lock_init(&dev_priv->uncore.lock);
 894
 895         spin_lock_init(&dev_priv->mm.object_stat_lock);
 896         mutex_init(&dev_priv->sb_lock);
 897         mutex_init(&dev_priv->modeset_restore_lock);
 898         mutex_init(&dev_priv->av_mutex);
 899         mutex_init(&dev_priv->wm.wm_mutex);
 900         mutex_init(&dev_priv->pps_mutex);
 901
 902         intel_uc_init_early(dev_priv);
 903         i915_memcpy_init_early(dev_priv);
 904
 905         ret = i915_workqueues_init(dev_priv);
 906         if (ret < 0)
 907                 goto err_engines;
 908
 909         /* This must be called before any calls to HAS_PCH_* */
 910         intel_detect_pch(dev_priv);
 911
 912         intel_pm_setup(dev_priv);
 913         intel_init_dpio(dev_priv);
 914         intel_power_domains_init(dev_priv);
 915         intel_irq_init(dev_priv);
 916         intel_hangcheck_init(dev_priv);
 917         intel_init_display_hooks(dev_priv);
 918         intel_init_clock_gating_hooks(dev_priv);
 919         intel_init_audio_hooks(dev_priv);
 920         ret = i915_gem_load_init(dev_priv);
 921         if (ret < 0)
 922                 goto err_irq;
 923
 924         intel_display_crc_init(dev_priv);
 925
 926         intel_device_info_dump(dev_priv);
 927
 928         intel_detect_preproduction_hw(dev_priv);
 929
 930         i915_perf_init(dev_priv);
 931
 932         return 0;
 933
 934 err_irq:
 935         intel_irq_fini(dev_priv);
 936         i915_workqueues_cleanup(dev_priv);
 937 err_engines:
 938         i915_engines_cleanup(dev_priv);
 939         return ret;
 940 }
 941
 942 /**
 943  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 944  * @dev_priv: device private
 945  */
 946 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 947 {
 948         i915_perf_fini(dev_priv);
 949         i915_gem_load_cleanup(dev_priv);
 950         intel_irq_fini(dev_priv);
 951         i915_workqueues_cleanup(dev_priv);
 952         i915_engines_cleanup(dev_priv);
 953 }
 954
 955 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 956 {
 957         struct pci_dev *pdev = dev_priv->drm.pdev;
 958         int mmio_bar;
 959         int mmio_size;
 960
 961         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 962         /*
 963          * Before gen4, the registers and the GTT are behind different BARs.
 964          * However, from gen4 onwards, the registers and the GTT are shared
 965          * in the same BAR, so we want to restrict this ioremap from
 966          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 967          * the register BAR remains the same size for all the earlier
 968          * generations up to Ironlake.
 969          */
 970         if (INTEL_GEN(dev_priv) < 5)
 971                 mmio_size = 512 * 1024;
 972         else
 973                 mmio_size = 2 * 1024 * 1024;
 974         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 975         if (dev_priv->regs == NULL) {
 976                 DRM_ERROR("failed to map registers\n");
 977
 978                 return -EIO;
 979         }
 980
 981         /* Try to make sure MCHBAR is enabled before poking at it */
 982         intel_setup_mchbar(dev_priv);
 983
 984         return 0;
 985 }
 986
 987 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 988 {
 989         struct pci_dev *pdev = dev_priv->drm.pdev;
 990
 991         intel_teardown_mchbar(dev_priv);
 992         pci_iounmap(pdev, dev_priv->regs);
 993 }
 994
 995 /**
 996  * i915_driver_init_mmio - setup device MMIO
 997  * @dev_priv: device private
 998  *
 999  * Setup minimal device state necessary for MMIO accesses later in the
1000  * initialization sequence. The setup here should avoid any other device-wide
1001  * side effects or exposing the driver via kernel internal or user space
1002  * interfaces.
1003  */
1004 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1005 {
1006         int ret;
1007
1008         if (i915_inject_load_failure())
1009                 return -ENODEV;
1010
1011         if (i915_get_bridge_dev(dev_priv))
1012                 return -EIO;
1013
1014         ret = i915_mmio_setup(dev_priv);
1015         if (ret < 0)
1016                 goto err_bridge;
1017
1018         intel_uncore_init(dev_priv);
1019
1020         intel_uc_init_mmio(dev_priv);
1021
1022         ret = intel_engines_init_mmio(dev_priv);
1023         if (ret)
1024                 goto err_uncore;
1025
1026         i915_gem_init_mmio(dev_priv);
1027
1028         return 0;
1029
1030 err_uncore:
1031         intel_uncore_fini(dev_priv);
1032 err_bridge:
1033         pci_dev_put(dev_priv->bridge_dev);
1034
1035         return ret;
1036 }
1037
1038 /**
1039  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1040  * @dev_priv: device private
1041  */
1042 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1043 {
1044         intel_uncore_fini(dev_priv);
1045         i915_mmio_cleanup(dev_priv);
1046         pci_dev_put(dev_priv->bridge_dev);
1047 }
1048
1049 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1050 {
1051         i915_modparams.enable_execlists =
1052                 intel_sanitize_enable_execlists(dev_priv,
1053                                                 i915_modparams.enable_execlists);
1054
1055         /*
1056          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1057          * user's requested state against the hardware/driver capabilities.  We
1058          * do this now so that we can print out any log messages once rather
1059          * than every time we check intel_enable_ppgtt().
1060          */
1061         i915_modparams.enable_ppgtt =
1062                 intel_sanitize_enable_ppgtt(dev_priv,
1063                                             i915_modparams.enable_ppgtt);
1064         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1065
1066         i915_modparams.semaphores =
1067                 intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
1068         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
1069                          yesno(i915_modparams.semaphores));
1070
1071         intel_uc_sanitize_options(dev_priv);
1072
1073         intel_gvt_sanitize_options(dev_priv);
1074 }
1075
1076 /**
1077  * i915_driver_init_hw - setup state requiring device access
1078  * @dev_priv: device private
1079  *
1080  * Setup state that requires accessing the device, but doesn't require
1081  * exposing the driver via kernel internal or userspace interfaces.
1082  */
1083 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1084 {
1085         struct pci_dev *pdev = dev_priv->drm.pdev;
1086         int ret;
1087
1088         if (i915_inject_load_failure())
1089                 return -ENODEV;
1090
1091         intel_device_info_runtime_init(dev_priv);
1092
1093         intel_sanitize_options(dev_priv);
1094
1095         ret = i915_ggtt_probe_hw(dev_priv);
1096         if (ret)
1097                 return ret;
1098
1099         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1100          * otherwise the vga fbdev driver falls over. */
1101         ret = i915_kick_out_firmware_fb(dev_priv);
1102         if (ret) {
1103                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1104                 goto out_ggtt;
1105         }
1106
1107         ret = i915_kick_out_vgacon(dev_priv);
1108         if (ret) {
1109                 DRM_ERROR("failed to remove conflicting VGA console\n");
1110                 goto out_ggtt;
1111         }
1112
1113         ret = i915_ggtt_init_hw(dev_priv);
1114         if (ret)
1115                 return ret;
1116
1117         ret = i915_ggtt_enable_hw(dev_priv);
1118         if (ret) {
1119                 DRM_ERROR("failed to enable GGTT\n");
1120                 goto out_ggtt;
1121         }
1122
1123         pci_set_master(pdev);
1124
1125         /* overlay on gen2 is broken and can't address above 1G */
1126         if (IS_GEN2(dev_priv)) {
1127                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1128                 if (ret) {
1129                         DRM_ERROR("failed to set DMA mask\n");
1130
1131                         goto out_ggtt;
1132                 }
1133         }
1134
1135         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1136          * using 32bit addressing, overwriting memory if HWS is located
1137          * above 4GB.
1138          *
1139          * The documentation also mentions an issue with undefined
1140          * behaviour if any general state is accessed within a page above 4GB,
1141          * which also needs to be handled carefully.
1142          */
1143         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1144                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1145
1146                 if (ret) {
1147                         DRM_ERROR("failed to set DMA mask\n");
1148
1149                         goto out_ggtt;
1150                 }
1151         }
1152
1153         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1154                            PM_QOS_DEFAULT_VALUE);
1155
1156         intel_uncore_sanitize(dev_priv);
1157
1158         intel_opregion_setup(dev_priv);
1159
1160         i915_gem_load_init_fences(dev_priv);
1161
1162         /* On the 945G/GM, the chipset reports the MSI capability on the
1163          * integrated graphics even though the support isn't actually there
1164          * according to the published specs.  It doesn't appear to function
1165          * correctly in testing on 945G.
1166          * This may be a side effect of MSI having been made available for PEG
1167          * and the registers being closely associated.
1168          *
1169          * According to chipset errata, on the 965GM, MSI interrupts may
1170          * be lost or delayed, and was defeatured. MSI interrupts seem to
1171          * get lost on g4x as well, and interrupt delivery seems to stay
1172          * properly dead afterwards. So we'll just disable them for all
1173          * pre-gen5 chipsets.
1174          */
1175         if (INTEL_GEN(dev_priv) >= 5) {
1176                 if (pci_enable_msi(pdev) < 0)
1177                         DRM_DEBUG_DRIVER("can't enable MSI");
1178         }
1179
1180         ret = intel_gvt_init(dev_priv);
1181         if (ret)
1182                 goto out_ggtt;
1183
1184         return 0;
1185
1186 out_ggtt:
1187         i915_ggtt_cleanup_hw(dev_priv);
1188
1189         return ret;
1190 }
1191
1192 /**
1193  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1194  * @dev_priv: device private
1195  */
1196 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1197 {
1198         struct pci_dev *pdev = dev_priv->drm.pdev;
1199
1200         if (pdev->msi_enabled)
1201                 pci_disable_msi(pdev);
1202
1203         pm_qos_remove_request(&dev_priv->pm_qos);
1204         i915_ggtt_cleanup_hw(dev_priv);
1205 }
1206
1207 /**
1208  * i915_driver_register - register the driver with the rest of the system
1209  * @dev_priv: device private
1210  *
1211  * Perform any steps necessary to make the driver available via kernel
1212  * internal or userspace interfaces.
1213  */
1214 static void i915_driver_register(struct drm_i915_private *dev_priv)
1215 {
1216         struct drm_device *dev = &dev_priv->drm;
1217
1218         i915_gem_shrinker_init(dev_priv);
1219
1220         /*
1221          * Notify a valid surface after modesetting,
1222          * when running inside a VM.
1223          */
1224         if (intel_vgpu_active(dev_priv))
1225                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1226
1227         /* Reveal our presence to userspace */
1228         if (drm_dev_register(dev, 0) == 0) {
1229                 i915_debugfs_register(dev_priv);
1230                 i915_guc_log_register(dev_priv);
1231                 i915_setup_sysfs(dev_priv);
1232
1233                 /* Depends on sysfs having been initialized */
1234                 i915_perf_register(dev_priv);
1235         } else
1236                 DRM_ERROR("Failed to register driver for userspace access!\n");
1237
1238         if (INTEL_INFO(dev_priv)->num_pipes) {
1239                 /* Must be done after probing outputs */
1240                 intel_opregion_register(dev_priv);
1241                 acpi_video_register();
1242         }
1243
1244         if (IS_GEN5(dev_priv))
1245                 intel_gpu_ips_init(dev_priv);
1246
1247         intel_audio_init(dev_priv);
1248
1249         /*
1250          * Some ports require correctly set-up hpd registers for detection to
1251          * work properly (leading to ghost connected connector status), e.g. VGA
1252          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1253          * irqs are fully enabled. We do it last so that the async config
1254          * cannot run before the connectors are registered.
1255          */
1256         intel_fbdev_initial_config_async(dev);
1257 }
1258
1259 /**
1260  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1261  * @dev_priv: device private
1262  */
1263 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1264 {
1265         intel_fbdev_unregister(dev_priv);
1266         intel_audio_deinit(dev_priv);
1267
1268         intel_gpu_ips_teardown();
1269         acpi_video_unregister();
1270         intel_opregion_unregister(dev_priv);
1271
1272         i915_perf_unregister(dev_priv);
1273
1274         i915_teardown_sysfs(dev_priv);
1275         i915_guc_log_unregister(dev_priv);
1276         drm_dev_unregister(&dev_priv->drm);
1277
1278         i915_gem_shrinker_cleanup(dev_priv);
1279 }
1280
1281 /**
1282  * i915_driver_load - setup chip and create an initial config
1283  * @pdev: PCI device
1284  * @ent: matching PCI ID entry
1285  *
1286  * The driver load routine has to do several things:
1287  *   - drive output discovery via intel_modeset_init()
1288  *   - initialize the memory manager
1289  *   - allocate initial config memory
1290  *   - setup the DRM framebuffer with the allocated memory
1291  */
1292 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1293 {
1294         const struct intel_device_info *match_info =
1295                 (struct intel_device_info *)ent->driver_data;
1296         struct drm_i915_private *dev_priv;
1297         int ret;
1298
1299         /* Enable nuclear pageflip on ILK+ */
1300         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1301                 driver.driver_features &= ~DRIVER_ATOMIC;
1302
1303         ret = -ENOMEM;
1304         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1305         if (dev_priv)
1306                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1307         if (ret) {
1308                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1309                 goto out_free;
1310         }
1311
1312         dev_priv->drm.pdev = pdev;
1313         dev_priv->drm.dev_private = dev_priv;
1314
1315         ret = pci_enable_device(pdev);
1316         if (ret)
1317                 goto out_fini;
1318
1319         pci_set_drvdata(pdev, &dev_priv->drm);
1320         /*
1321          * Disable the system suspend direct complete optimization, which can
1322          * leave the device suspended skipping the driver's suspend handlers
1323          * if the device was already runtime suspended. This is needed due to
1324          * the difference in our runtime and system suspend sequence and
1325          * becaue the HDA driver may require us to enable the audio power
1326          * domain during system suspend.
1327          */
1328         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1329
1330         ret = i915_driver_init_early(dev_priv, ent);
1331         if (ret < 0)
1332                 goto out_pci_disable;
1333
1334         intel_runtime_pm_get(dev_priv);
1335
1336         ret = i915_driver_init_mmio(dev_priv);
1337         if (ret < 0)
1338                 goto out_runtime_pm_put;
1339
1340         ret = i915_driver_init_hw(dev_priv);
1341         if (ret < 0)
1342                 goto out_cleanup_mmio;
1343
1344         /*
1345          * TODO: move the vblank init and parts of modeset init steps into one
1346          * of the i915_driver_init_/i915_driver_register functions according
1347          * to the role/effect of the given init step.
1348          */
1349         if (INTEL_INFO(dev_priv)->num_pipes) {
1350                 ret = drm_vblank_init(&dev_priv->drm,
1351                                       INTEL_INFO(dev_priv)->num_pipes);
1352                 if (ret)
1353                         goto out_cleanup_hw;
1354         }
1355
1356         ret = i915_load_modeset_init(&dev_priv->drm);
1357         if (ret < 0)
1358                 goto out_cleanup_hw;
1359
1360         i915_driver_register(dev_priv);
1361
1362         intel_runtime_pm_enable(dev_priv);
1363
1364         intel_init_ipc(dev_priv);
1365
1366         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1367                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1368         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1369                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1370
1371         intel_runtime_pm_put(dev_priv);
1372
1373         return 0;
1374
1375 out_cleanup_hw:
1376         i915_driver_cleanup_hw(dev_priv);
1377 out_cleanup_mmio:
1378         i915_driver_cleanup_mmio(dev_priv);
1379 out_runtime_pm_put:
1380         intel_runtime_pm_put(dev_priv);
1381         i915_driver_cleanup_early(dev_priv);
1382 out_pci_disable:
1383         pci_disable_device(pdev);
1384 out_fini:
1385         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1386         drm_dev_fini(&dev_priv->drm);
1387 out_free:
1388         kfree(dev_priv);
1389         return ret;
1390 }
1391
1392 void i915_driver_unload(struct drm_device *dev)
1393 {
1394         struct drm_i915_private *dev_priv = to_i915(dev);
1395         struct pci_dev *pdev = dev_priv->drm.pdev;
1396
1397         i915_driver_unregister(dev_priv);
1398
1399         if (i915_gem_suspend(dev_priv))
1400                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1401
1402         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1403
1404         drm_atomic_helper_shutdown(dev);
1405
1406         intel_gvt_cleanup(dev_priv);
1407
1408         intel_modeset_cleanup(dev);
1409
1410         /*
1411          * free the memory space allocated for the child device
1412          * config parsed from VBT
1413          */
1414         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1415                 kfree(dev_priv->vbt.child_dev);
1416                 dev_priv->vbt.child_dev = NULL;
1417                 dev_priv->vbt.child_dev_num = 0;
1418         }
1419         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1420         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1421         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1422         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1423
1424         vga_switcheroo_unregister_client(pdev);
1425         vga_client_register(pdev, NULL, NULL, NULL);
1426
1427         intel_csr_ucode_fini(dev_priv);
1428
1429         /* Free error state after interrupts are fully disabled. */
1430         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1431         i915_reset_error_state(dev_priv);
1432
1433         i915_gem_fini(dev_priv);
1434         intel_uc_fini_fw(dev_priv);
1435         intel_fbc_cleanup_cfb(dev_priv);
1436
1437         intel_power_domains_fini(dev_priv);
1438
1439         i915_driver_cleanup_hw(dev_priv);
1440         i915_driver_cleanup_mmio(dev_priv);
1441
1442         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1443 }
1444
1445 static void i915_driver_release(struct drm_device *dev)
1446 {
1447         struct drm_i915_private *dev_priv = to_i915(dev);
1448
1449         i915_driver_cleanup_early(dev_priv);
1450         drm_dev_fini(&dev_priv->drm);
1451
1452         kfree(dev_priv);
1453 }
1454
1455 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1456 {
1457         struct drm_i915_private *i915 = to_i915(dev);
1458         int ret;
1459
1460         ret = i915_gem_open(i915, file);
1461         if (ret)
1462                 return ret;
1463
1464         return 0;
1465 }
1466
1467 /**
1468  * i915_driver_lastclose - clean up after all DRM clients have exited
1469  * @dev: DRM device
1470  *
1471  * Take care of cleaning up after all DRM clients have exited.  In the
1472  * mode setting case, we want to restore the kernel's initial mode (just
1473  * in case the last client left us in a bad state).
1474  *
1475  * Additionally, in the non-mode setting case, we'll tear down the GTT
1476  * and DMA structures, since the kernel won't be using them, and clea
1477  * up any GEM state.
1478  */
1479 static void i915_driver_lastclose(struct drm_device *dev)
1480 {
1481         intel_fbdev_restore_mode(dev);
1482         vga_switcheroo_process_delayed_switch();
1483 }
1484
1485 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1486 {
1487         struct drm_i915_file_private *file_priv = file->driver_priv;
1488
1489         mutex_lock(&dev->struct_mutex);
1490         i915_gem_context_close(file);
1491         i915_gem_release(dev, file);
1492         mutex_unlock(&dev->struct_mutex);
1493
1494         kfree(file_priv);
1495 }
1496
1497 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1498 {
1499         struct drm_device *dev = &dev_priv->drm;
1500         struct intel_encoder *encoder;
1501
1502         drm_modeset_lock_all(dev);
1503         for_each_intel_encoder(dev, encoder)
1504                 if (encoder->suspend)
1505                         encoder->suspend(encoder);
1506         drm_modeset_unlock_all(dev);
1507 }
1508
1509 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1510                               bool rpm_resume);
1511 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1512
1513 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1514 {
1515 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1516         if (acpi_target_system_state() < ACPI_STATE_S3)
1517                 return true;
1518 #endif
1519         return false;
1520 }
1521
1522 static int i915_drm_suspend(struct drm_device *dev)
1523 {
1524         struct drm_i915_private *dev_priv = to_i915(dev);
1525         struct pci_dev *pdev = dev_priv->drm.pdev;
1526         pci_power_t opregion_target_state;
1527         int error;
1528
1529         /* ignore lid events during suspend */
1530         mutex_lock(&dev_priv->modeset_restore_lock);
1531         dev_priv->modeset_restore = MODESET_SUSPENDED;
1532         mutex_unlock(&dev_priv->modeset_restore_lock);
1533
1534         disable_rpm_wakeref_asserts(dev_priv);
1535
1536         /* We do a lot of poking in a lot of registers, make sure they work
1537          * properly. */
1538         intel_display_set_init_power(dev_priv, true);
1539
1540         drm_kms_helper_poll_disable(dev);
1541
1542         pci_save_state(pdev);
1543
1544         error = i915_gem_suspend(dev_priv);
1545         if (error) {
1546                 dev_err(&pdev->dev,
1547                         "GEM idle failed, resume might fail\n");
1548                 goto out;
1549         }
1550
1551         intel_display_suspend(dev);
1552
1553         intel_dp_mst_suspend(dev);
1554
1555         intel_runtime_pm_disable_interrupts(dev_priv);
1556         intel_hpd_cancel_work(dev_priv);
1557
1558         intel_suspend_encoders(dev_priv);
1559
1560         intel_suspend_hw(dev_priv);
1561
1562         i915_gem_suspend_gtt_mappings(dev_priv);
1563
1564         i915_save_state(dev_priv);
1565
1566         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1567         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1568
1569         intel_uncore_suspend(dev_priv);
1570         intel_opregion_unregister(dev_priv);
1571
1572         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1573
1574         dev_priv->suspend_count++;
1575
1576         intel_csr_ucode_suspend(dev_priv);
1577
1578 out:
1579         enable_rpm_wakeref_asserts(dev_priv);
1580
1581         return error;
1582 }
1583
1584 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1585 {
1586         struct drm_i915_private *dev_priv = to_i915(dev);
1587         struct pci_dev *pdev = dev_priv->drm.pdev;
1588         bool fw_csr;
1589         int ret;
1590
1591         disable_rpm_wakeref_asserts(dev_priv);
1592
1593         intel_display_set_init_power(dev_priv, false);
1594
1595         fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
1596                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1597         /*
1598          * In case of firmware assisted context save/restore don't manually
1599          * deinit the power domains. This also means the CSR/DMC firmware will
1600          * stay active, it will power down any HW resources as required and
1601          * also enable deeper system power states that would be blocked if the
1602          * firmware was inactive.
1603          */
1604         if (!fw_csr)
1605                 intel_power_domains_suspend(dev_priv);
1606
1607         ret = 0;
1608         if (IS_GEN9_LP(dev_priv))
1609                 bxt_enable_dc9(dev_priv);
1610         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1611                 hsw_enable_pc8(dev_priv);
1612         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1613                 ret = vlv_suspend_complete(dev_priv);
1614
1615         if (ret) {
1616                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1617                 if (!fw_csr)
1618                         intel_power_domains_init_hw(dev_priv, true);
1619
1620                 goto out;
1621         }
1622
1623         pci_disable_device(pdev);
1624         /*
1625          * During hibernation on some platforms the BIOS may try to access
1626          * the device even though it's already in D3 and hang the machine. So
1627          * leave the device in D0 on those platforms and hope the BIOS will
1628          * power down the device properly. The issue was seen on multiple old
1629          * GENs with different BIOS vendors, so having an explicit blacklist
1630          * is inpractical; apply the workaround on everything pre GEN6. The
1631          * platforms where the issue was seen:
1632          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1633          * Fujitsu FSC S7110
1634          * Acer Aspire 1830T
1635          */
1636         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1637                 pci_set_power_state(pdev, PCI_D3hot);
1638
1639         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1640
1641 out:
1642         enable_rpm_wakeref_asserts(dev_priv);
1643
1644         return ret;
1645 }
1646
1647 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1648 {
1649         int error;
1650
1651         if (!dev) {
1652                 DRM_ERROR("dev: %p\n", dev);
1653                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1654                 return -ENODEV;
1655         }
1656
1657         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1658                          state.event != PM_EVENT_FREEZE))
1659                 return -EINVAL;
1660
1661         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1662                 return 0;
1663
1664         error = i915_drm_suspend(dev);
1665         if (error)
1666                 return error;
1667
1668         return i915_drm_suspend_late(dev, false);
1669 }
1670
1671 static int i915_drm_resume(struct drm_device *dev)
1672 {
1673         struct drm_i915_private *dev_priv = to_i915(dev);
1674         int ret;
1675
1676         disable_rpm_wakeref_asserts(dev_priv);
1677         intel_sanitize_gt_powersave(dev_priv);
1678
1679         ret = i915_ggtt_enable_hw(dev_priv);
1680         if (ret)
1681                 DRM_ERROR("failed to re-enable GGTT\n");
1682
1683         intel_csr_ucode_resume(dev_priv);
1684
1685         i915_gem_resume(dev_priv);
1686
1687         i915_restore_state(dev_priv);
1688         intel_pps_unlock_regs_wa(dev_priv);
1689         intel_opregion_setup(dev_priv);
1690
1691         intel_init_pch_refclk(dev_priv);
1692
1693         /*
1694          * Interrupts have to be enabled before any batches are run. If not the
1695          * GPU will hang. i915_gem_init_hw() will initiate batches to
1696          * update/restore the context.
1697          *
1698          * drm_mode_config_reset() needs AUX interrupts.
1699          *
1700          * Modeset enabling in intel_modeset_init_hw() also needs working
1701          * interrupts.
1702          */
1703         intel_runtime_pm_enable_interrupts(dev_priv);
1704
1705         drm_mode_config_reset(dev);
1706
1707         mutex_lock(&dev->struct_mutex);
1708         if (i915_gem_init_hw(dev_priv)) {
1709                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1710                 i915_gem_set_wedged(dev_priv);
1711         }
1712         mutex_unlock(&dev->struct_mutex);
1713
1714         intel_guc_resume(dev_priv);
1715
1716         intel_modeset_init_hw(dev);
1717
1718         spin_lock_irq(&dev_priv->irq_lock);
1719         if (dev_priv->display.hpd_irq_setup)
1720                 dev_priv->display.hpd_irq_setup(dev_priv);
1721         spin_unlock_irq(&dev_priv->irq_lock);
1722
1723         intel_dp_mst_resume(dev);
1724
1725         intel_display_resume(dev);
1726
1727         drm_kms_helper_poll_enable(dev);
1728
1729         /*
1730          * ... but also need to make sure that hotplug processing
1731          * doesn't cause havoc. Like in the driver load code we don't
1732          * bother with the tiny race here where we might loose hotplug
1733          * notifications.
1734          * */
1735         intel_hpd_init(dev_priv);
1736
1737         intel_opregion_register(dev_priv);
1738
1739         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1740
1741         mutex_lock(&dev_priv->modeset_restore_lock);
1742         dev_priv->modeset_restore = MODESET_DONE;
1743         mutex_unlock(&dev_priv->modeset_restore_lock);
1744
1745         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1746
1747         intel_autoenable_gt_powersave(dev_priv);
1748
1749         enable_rpm_wakeref_asserts(dev_priv);
1750
1751         return 0;
1752 }
1753
1754 static int i915_drm_resume_early(struct drm_device *dev)
1755 {
1756         struct drm_i915_private *dev_priv = to_i915(dev);
1757         struct pci_dev *pdev = dev_priv->drm.pdev;
1758         int ret;
1759
1760         /*
1761          * We have a resume ordering issue with the snd-hda driver also
1762          * requiring our device to be power up. Due to the lack of a
1763          * parent/child relationship we currently solve this with an early
1764          * resume hook.
1765          *
1766          * FIXME: This should be solved with a special hdmi sink device or
1767          * similar so that power domains can be employed.
1768          */
1769
1770         /*
1771          * Note that we need to set the power state explicitly, since we
1772          * powered off the device during freeze and the PCI core won't power
1773          * it back up for us during thaw. Powering off the device during
1774          * freeze is not a hard requirement though, and during the
1775          * suspend/resume phases the PCI core makes sure we get here with the
1776          * device powered on. So in case we change our freeze logic and keep
1777          * the device powered we can also remove the following set power state
1778          * call.
1779          */
1780         ret = pci_set_power_state(pdev, PCI_D0);
1781         if (ret) {
1782                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1783                 goto out;
1784         }
1785
1786         /*
1787          * Note that pci_enable_device() first enables any parent bridge
1788          * device and only then sets the power state for this device. The
1789          * bridge enabling is a nop though, since bridge devices are resumed
1790          * first. The order of enabling power and enabling the device is
1791          * imposed by the PCI core as described above, so here we preserve the
1792          * same order for the freeze/thaw phases.
1793          *
1794          * TODO: eventually we should remove pci_disable_device() /
1795          * pci_enable_enable_device() from suspend/resume. Due to how they
1796          * depend on the device enable refcount we can't anyway depend on them
1797          * disabling/enabling the device.
1798          */
1799         if (pci_enable_device(pdev)) {
1800                 ret = -EIO;
1801                 goto out;
1802         }
1803
1804         pci_set_master(pdev);
1805
1806         disable_rpm_wakeref_asserts(dev_priv);
1807
1808         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1809                 ret = vlv_resume_prepare(dev_priv, false);
1810         if (ret)
1811                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1812                           ret);
1813
1814         intel_uncore_resume_early(dev_priv);
1815
1816         if (IS_GEN9_LP(dev_priv)) {
1817                 if (!dev_priv->suspended_to_idle)
1818                         gen9_sanitize_dc_state(dev_priv);
1819                 bxt_disable_dc9(dev_priv);
1820         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1821                 hsw_disable_pc8(dev_priv);
1822         }
1823
1824         intel_uncore_sanitize(dev_priv);
1825
1826         if (IS_GEN9_LP(dev_priv) ||
1827             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1828                 intel_power_domains_init_hw(dev_priv, true);
1829
1830         i915_gem_sanitize(dev_priv);
1831
1832         enable_rpm_wakeref_asserts(dev_priv);
1833
1834 out:
1835         dev_priv->suspended_to_idle = false;
1836
1837         return ret;
1838 }
1839
1840 static int i915_resume_switcheroo(struct drm_device *dev)
1841 {
1842         int ret;
1843
1844         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1845                 return 0;
1846
1847         ret = i915_drm_resume_early(dev);
1848         if (ret)
1849                 return ret;
1850
1851         return i915_drm_resume(dev);
1852 }
1853
1854 /**
1855  * i915_reset - reset chip after a hang
1856  * @i915: #drm_i915_private to reset
1857  * @flags: Instructions
1858  *
1859  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1860  * on failure.
1861  *
1862  * Caller must hold the struct_mutex.
1863  *
1864  * Procedure is fairly simple:
1865  *   - reset the chip using the reset reg
1866  *   - re-init context state
1867  *   - re-init hardware status page
1868  *   - re-init ring buffer
1869  *   - re-init interrupt state
1870  *   - re-init display
1871  */
1872 void i915_reset(struct drm_i915_private *i915, unsigned int flags)
1873 {
1874         struct i915_gpu_error *error = &i915->gpu_error;
1875         int ret;
1876
1877         lockdep_assert_held(&i915->drm.struct_mutex);
1878         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1879
1880         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1881                 return;
1882
1883         /* Clear any previous failed attempts at recovery. Time to try again. */
1884         if (!i915_gem_unset_wedged(i915))
1885                 goto wakeup;
1886
1887         if (!(flags & I915_RESET_QUIET))
1888                 dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n");
1889         error->reset_count++;
1890
1891         disable_irq(i915->drm.irq);
1892         ret = i915_gem_reset_prepare(i915);
1893         if (ret) {
1894                 DRM_ERROR("GPU recovery failed\n");
1895                 intel_gpu_reset(i915, ALL_ENGINES);
1896                 goto error;
1897         }
1898
1899         ret = intel_gpu_reset(i915, ALL_ENGINES);
1900         if (ret) {
1901                 if (ret != -ENODEV)
1902                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1903                 else
1904                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1905                 goto error;
1906         }
1907
1908         i915_gem_reset(i915);
1909         intel_overlay_reset(i915);
1910
1911         /* Ok, now get things going again... */
1912
1913         /*
1914          * Everything depends on having the GTT running, so we need to start
1915          * there.
1916          */
1917         ret = i915_ggtt_enable_hw(i915);
1918         if (ret) {
1919                 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);
1920                 goto error;
1921         }
1922
1923         /*
1924          * Next we need to restore the context, but we don't use those
1925          * yet either...
1926          *
1927          * Ring buffer needs to be re-initialized in the KMS case, or if X
1928          * was running at the time of the reset (i.e. we weren't VT
1929          * switched away).
1930          */
1931         ret = i915_gem_init_hw(i915);
1932         if (ret) {
1933                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1934                 goto error;
1935         }
1936
1937         i915_queue_hangcheck(i915);
1938
1939 finish:
1940         i915_gem_reset_finish(i915);
1941         enable_irq(i915->drm.irq);
1942
1943 wakeup:
1944         clear_bit(I915_RESET_HANDOFF, &error->flags);
1945         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1946         return;
1947
1948 error:
1949         i915_gem_set_wedged(i915);
1950         i915_gem_retire_requests(i915);
1951         goto finish;
1952 }
1953
1954 /**
1955  * i915_reset_engine - reset GPU engine to recover from a hang
1956  * @engine: engine to reset
1957  * @flags: options
1958  *
1959  * Reset a specific GPU engine. Useful if a hang is detected.
1960  * Returns zero on successful reset or otherwise an error code.
1961  *
1962  * Procedure is:
1963  *  - identifies the request that caused the hang and it is dropped
1964  *  - reset engine (which will force the engine to idle)
1965  *  - re-init/configure engine
1966  */
1967 int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags)
1968 {
1969         struct i915_gpu_error *error = &engine->i915->gpu_error;
1970         struct drm_i915_gem_request *active_request;
1971         int ret;
1972
1973         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1974
1975         if (!(flags & I915_RESET_QUIET)) {
1976                 dev_notice(engine->i915->drm.dev,
1977                            "Resetting %s after gpu hang\n", engine->name);
1978         }
1979         error->reset_engine_count[engine->id]++;
1980
1981         active_request = i915_gem_reset_prepare_engine(engine);
1982         if (IS_ERR(active_request)) {
1983                 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1984                 ret = PTR_ERR(active_request);
1985                 goto out;
1986         }
1987
1988         ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine));
1989         if (ret) {
1990                 /* If we fail here, we expect to fallback to a global reset */
1991                 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1992                                  engine->name, ret);
1993                 goto out;
1994         }
1995
1996         /*
1997          * The request that caused the hang is stuck on elsp, we know the
1998          * active request and can drop it, adjust head to skip the offending
1999          * request to resume executing remaining requests in the queue.
2000          */
2001         i915_gem_reset_engine(engine, active_request);
2002
2003         /*
2004          * The engine and its registers (and workarounds in case of render)
2005          * have been reset to their default values. Follow the init_ring
2006          * process to program RING_MODE, HWSP and re-enable submission.
2007          */
2008         ret = engine->init_hw(engine);
2009         if (ret)
2010                 goto out;
2011
2012 out:
2013         i915_gem_reset_finish_engine(engine);
2014         return ret;
2015 }
2016
2017 static int i915_pm_suspend(struct device *kdev)
2018 {
2019         struct pci_dev *pdev = to_pci_dev(kdev);
2020         struct drm_device *dev = pci_get_drvdata(pdev);
2021
2022         if (!dev) {
2023                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2024                 return -ENODEV;
2025         }
2026
2027         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2028                 return 0;
2029
2030         return i915_drm_suspend(dev);
2031 }
2032
2033 static int i915_pm_suspend_late(struct device *kdev)
2034 {
2035         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2036
2037         /*
2038          * We have a suspend ordering issue with the snd-hda driver also
2039          * requiring our device to be power up. Due to the lack of a
2040          * parent/child relationship we currently solve this with an late
2041          * suspend hook.
2042          *
2043          * FIXME: This should be solved with a special hdmi sink device or
2044          * similar so that power domains can be employed.
2045          */
2046         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2047                 return 0;
2048
2049         return i915_drm_suspend_late(dev, false);
2050 }
2051
2052 static int i915_pm_poweroff_late(struct device *kdev)
2053 {
2054         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2055
2056         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2057                 return 0;
2058
2059         return i915_drm_suspend_late(dev, true);
2060 }
2061
2062 static int i915_pm_resume_early(struct device *kdev)
2063 {
2064         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2065
2066         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2067                 return 0;
2068
2069         return i915_drm_resume_early(dev);
2070 }
2071
2072 static int i915_pm_resume(struct device *kdev)
2073 {
2074         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2075
2076         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2077                 return 0;
2078
2079         return i915_drm_resume(dev);
2080 }
2081
2082 /* freeze: before creating the hibernation_image */
2083 static int i915_pm_freeze(struct device *kdev)
2084 {
2085         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2086         int ret;
2087
2088         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2089                 ret = i915_drm_suspend(dev);
2090                 if (ret)
2091                         return ret;
2092         }
2093
2094         ret = i915_gem_freeze(kdev_to_i915(kdev));
2095         if (ret)
2096                 return ret;
2097
2098         return 0;
2099 }
2100
2101 static int i915_pm_freeze_late(struct device *kdev)
2102 {
2103         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2104         int ret;
2105
2106         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2107                 ret = i915_drm_suspend_late(dev, true);
2108                 if (ret)
2109                         return ret;
2110         }
2111
2112         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2113         if (ret)
2114                 return ret;
2115
2116         return 0;
2117 }
2118
2119 /* thaw: called after creating the hibernation image, but before turning off. */
2120 static int i915_pm_thaw_early(struct device *kdev)
2121 {
2122         return i915_pm_resume_early(kdev);
2123 }
2124
2125 static int i915_pm_thaw(struct device *kdev)
2126 {
2127         return i915_pm_resume(kdev);
2128 }
2129
2130 /* restore: called after loading the hibernation image. */
2131 static int i915_pm_restore_early(struct device *kdev)
2132 {
2133         return i915_pm_resume_early(kdev);
2134 }
2135
2136 static int i915_pm_restore(struct device *kdev)
2137 {
2138         return i915_pm_resume(kdev);
2139 }
2140
2141 /*
2142  * Save all Gunit registers that may be lost after a D3 and a subsequent
2143  * S0i[R123] transition. The list of registers needing a save/restore is
2144  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2145  * registers in the following way:
2146  * - Driver: saved/restored by the driver
2147  * - Punit : saved/restored by the Punit firmware
2148  * - No, w/o marking: no need to save/restore, since the register is R/O or
2149  *                    used internally by the HW in a way that doesn't depend
2150  *                    keeping the content across a suspend/resume.
2151  * - Debug : used for debugging
2152  *
2153  * We save/restore all registers marked with 'Driver', with the following
2154  * exceptions:
2155  * - Registers out of use, including also registers marked with 'Debug'.
2156  *   These have no effect on the driver's operation, so we don't save/restore
2157  *   them to reduce the overhead.
2158  * - Registers that are fully setup by an initialization function called from
2159  *   the resume path. For example many clock gating and RPS/RC6 registers.
2160  * - Registers that provide the right functionality with their reset defaults.
2161  *
2162  * TODO: Except for registers that based on the above 3 criteria can be safely
2163  * ignored, we save/restore all others, practically treating the HW context as
2164  * a black-box for the driver. Further investigation is needed to reduce the
2165  * saved/restored registers even further, by following the same 3 criteria.
2166  */
2167 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2168 {
2169         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2170         int i;
2171
2172         /* GAM 0x4000-0x4770 */
2173         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2174         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2175         s->arb_mode             = I915_READ(ARB_MODE);
2176         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2177         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2178
2179         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2180                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2181
2182         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2183         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2184
2185         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2186         s->ecochk               = I915_READ(GAM_ECOCHK);
2187         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2188         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2189
2190         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2191
2192         /* MBC 0x9024-0x91D0, 0x8500 */
2193         s->g3dctl               = I915_READ(VLV_G3DCTL);
2194         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2195         s->mbctl                = I915_READ(GEN6_MBCTL);
2196
2197         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2198         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2199         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2200         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2201         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2202         s->rstctl               = I915_READ(GEN6_RSTCTL);
2203         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2204
2205         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2206         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2207         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2208         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2209         s->ecobus               = I915_READ(ECOBUS);
2210         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2211         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2212         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2213         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2214         s->rcedata              = I915_READ(VLV_RCEDATA);
2215         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2216
2217         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2218         s->gt_imr               = I915_READ(GTIMR);
2219         s->gt_ier               = I915_READ(GTIER);
2220         s->pm_imr               = I915_READ(GEN6_PMIMR);
2221         s->pm_ier               = I915_READ(GEN6_PMIER);
2222
2223         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2224                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2225
2226         /* GT SA CZ domain, 0x100000-0x138124 */
2227         s->tilectl              = I915_READ(TILECTL);
2228         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2229         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2230         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2231         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2232
2233         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2234         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2235         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2236         s->pcbr                 = I915_READ(VLV_PCBR);
2237         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2238
2239         /*
2240          * Not saving any of:
2241          * DFT,         0x9800-0x9EC0
2242          * SARB,        0xB000-0xB1FC
2243          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2244          * PCI CFG
2245          */
2246 }
2247
2248 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2249 {
2250         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2251         u32 val;
2252         int i;
2253
2254         /* GAM 0x4000-0x4770 */
2255         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2256         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2257         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2258         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2259         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2260
2261         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2262                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2263
2264         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2265         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2266
2267         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2268         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2269         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2270         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2271
2272         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2273
2274         /* MBC 0x9024-0x91D0, 0x8500 */
2275         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2276         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2277         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2278
2279         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2280         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2281         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2282         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2283         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2284         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2285         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2286
2287         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2288         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2289         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2290         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2291         I915_WRITE(ECOBUS,              s->ecobus);
2292         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2293         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2294         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2295         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2296         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2297         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2298
2299         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2300         I915_WRITE(GTIMR,               s->gt_imr);
2301         I915_WRITE(GTIER,               s->gt_ier);
2302         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2303         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2304
2305         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2306                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2307
2308         /* GT SA CZ domain, 0x100000-0x138124 */
2309         I915_WRITE(TILECTL,                     s->tilectl);
2310         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2311         /*
2312          * Preserve the GT allow wake and GFX force clock bit, they are not
2313          * be restored, as they are used to control the s0ix suspend/resume
2314          * sequence by the caller.
2315          */
2316         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2317         val &= VLV_GTLC_ALLOWWAKEREQ;
2318         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2319         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2320
2321         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2322         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2323         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2324         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2325
2326         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2327
2328         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2329         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2330         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2331         I915_WRITE(VLV_PCBR,                    s->pcbr);
2332         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2333 }
2334
2335 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2336                                   u32 mask, u32 val)
2337 {
2338         /* The HW does not like us polling for PW_STATUS frequently, so
2339          * use the sleeping loop rather than risk the busy spin within
2340          * intel_wait_for_register().
2341          *
2342          * Transitioning between RC6 states should be at most 2ms (see
2343          * valleyview_enable_rps) so use a 3ms timeout.
2344          */
2345         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2346                         3);
2347 }
2348
2349 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2350 {
2351         u32 val;
2352         int err;
2353
2354         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2355         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2356         if (force_on)
2357                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2358         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2359
2360         if (!force_on)
2361                 return 0;
2362
2363         err = intel_wait_for_register(dev_priv,
2364                                       VLV_GTLC_SURVIVABILITY_REG,
2365                                       VLV_GFX_CLK_STATUS_BIT,
2366                                       VLV_GFX_CLK_STATUS_BIT,
2367                                       20);
2368         if (err)
2369                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2370                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2371
2372         return err;
2373 }
2374
2375 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2376 {
2377         u32 mask;
2378         u32 val;
2379         int err;
2380
2381         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2382         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2383         if (allow)
2384                 val |= VLV_GTLC_ALLOWWAKEREQ;
2385         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2386         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2387
2388         mask = VLV_GTLC_ALLOWWAKEACK;
2389         val = allow ? mask : 0;
2390
2391         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2392         if (err)
2393                 DRM_ERROR("timeout disabling GT waking\n");
2394
2395         return err;
2396 }
2397
2398 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2399                                   bool wait_for_on)
2400 {
2401         u32 mask;
2402         u32 val;
2403
2404         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2405         val = wait_for_on ? mask : 0;
2406
2407         /*
2408          * RC6 transitioning can be delayed up to 2 msec (see
2409          * valleyview_enable_rps), use 3 msec for safety.
2410          */
2411         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2412                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2413                           onoff(wait_for_on));
2414 }
2415
2416 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2417 {
2418         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2419                 return;
2420
2421         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2422         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2423 }
2424
2425 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2426 {
2427         u32 mask;
2428         int err;
2429
2430         /*
2431          * Bspec defines the following GT well on flags as debug only, so
2432          * don't treat them as hard failures.
2433          */
2434         vlv_wait_for_gt_wells(dev_priv, false);
2435
2436         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2437         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2438
2439         vlv_check_no_gt_access(dev_priv);
2440
2441         err = vlv_force_gfx_clock(dev_priv, true);
2442         if (err)
2443                 goto err1;
2444
2445         err = vlv_allow_gt_wake(dev_priv, false);
2446         if (err)
2447                 goto err2;
2448
2449         if (!IS_CHERRYVIEW(dev_priv))
2450                 vlv_save_gunit_s0ix_state(dev_priv);
2451
2452         err = vlv_force_gfx_clock(dev_priv, false);
2453         if (err)
2454                 goto err2;
2455
2456         return 0;
2457
2458 err2:
2459         /* For safety always re-enable waking and disable gfx clock forcing */
2460         vlv_allow_gt_wake(dev_priv, true);
2461 err1:
2462         vlv_force_gfx_clock(dev_priv, false);
2463
2464         return err;
2465 }
2466
2467 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2468                                 bool rpm_resume)
2469 {
2470         int err;
2471         int ret;
2472
2473         /*
2474          * If any of the steps fail just try to continue, that's the best we
2475          * can do at this point. Return the first error code (which will also
2476          * leave RPM permanently disabled).
2477          */
2478         ret = vlv_force_gfx_clock(dev_priv, true);
2479
2480         if (!IS_CHERRYVIEW(dev_priv))
2481                 vlv_restore_gunit_s0ix_state(dev_priv);
2482
2483         err = vlv_allow_gt_wake(dev_priv, true);
2484         if (!ret)
2485                 ret = err;
2486
2487         err = vlv_force_gfx_clock(dev_priv, false);
2488         if (!ret)
2489                 ret = err;
2490
2491         vlv_check_no_gt_access(dev_priv);
2492
2493         if (rpm_resume)
2494                 intel_init_clock_gating(dev_priv);
2495
2496         return ret;
2497 }
2498
2499 static int intel_runtime_suspend(struct device *kdev)
2500 {
2501         struct pci_dev *pdev = to_pci_dev(kdev);
2502         struct drm_device *dev = pci_get_drvdata(pdev);
2503         struct drm_i915_private *dev_priv = to_i915(dev);
2504         int ret;
2505
2506         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && intel_rc6_enabled())))
2507                 return -ENODEV;
2508
2509         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2510                 return -ENODEV;
2511
2512         DRM_DEBUG_KMS("Suspending device\n");
2513
2514         disable_rpm_wakeref_asserts(dev_priv);
2515
2516         /*
2517          * We are safe here against re-faults, since the fault handler takes
2518          * an RPM reference.
2519          */
2520         i915_gem_runtime_suspend(dev_priv);
2521
2522         intel_guc_suspend(dev_priv);
2523
2524         intel_runtime_pm_disable_interrupts(dev_priv);
2525
2526         ret = 0;
2527         if (IS_GEN9_LP(dev_priv)) {
2528                 bxt_display_core_uninit(dev_priv);
2529                 bxt_enable_dc9(dev_priv);
2530         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2531                 hsw_enable_pc8(dev_priv);
2532         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2533                 ret = vlv_suspend_complete(dev_priv);
2534         }
2535
2536         if (ret) {
2537                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2538                 intel_runtime_pm_enable_interrupts(dev_priv);
2539
2540                 enable_rpm_wakeref_asserts(dev_priv);
2541
2542                 return ret;
2543         }
2544
2545         intel_uncore_suspend(dev_priv);
2546
2547         enable_rpm_wakeref_asserts(dev_priv);
2548         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2549
2550         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2551                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2552
2553         dev_priv->runtime_pm.suspended = true;
2554
2555         /*
2556          * FIXME: We really should find a document that references the arguments
2557          * used below!
2558          */
2559         if (IS_BROADWELL(dev_priv)) {
2560                 /*
2561                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2562                  * being detected, and the call we do at intel_runtime_resume()
2563                  * won't be able to restore them. Since PCI_D3hot matches the
2564                  * actual specification and appears to be working, use it.
2565                  */
2566                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2567         } else {
2568                 /*
2569                  * current versions of firmware which depend on this opregion
2570                  * notification have repurposed the D1 definition to mean
2571                  * "runtime suspended" vs. what you would normally expect (D3)
2572                  * to distinguish it from notifications that might be sent via
2573                  * the suspend path.
2574                  */
2575                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2576         }
2577
2578         assert_forcewakes_inactive(dev_priv);
2579
2580         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2581                 intel_hpd_poll_init(dev_priv);
2582
2583         DRM_DEBUG_KMS("Device suspended\n");
2584         return 0;
2585 }
2586
2587 static int intel_runtime_resume(struct device *kdev)
2588 {
2589         struct pci_dev *pdev = to_pci_dev(kdev);
2590         struct drm_device *dev = pci_get_drvdata(pdev);
2591         struct drm_i915_private *dev_priv = to_i915(dev);
2592         int ret = 0;
2593
2594         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2595                 return -ENODEV;
2596
2597         DRM_DEBUG_KMS("Resuming device\n");
2598
2599         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2600         disable_rpm_wakeref_asserts(dev_priv);
2601
2602         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2603         dev_priv->runtime_pm.suspended = false;
2604         if (intel_uncore_unclaimed_mmio(dev_priv))
2605                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2606
2607         intel_guc_resume(dev_priv);
2608
2609         if (IS_GEN9_LP(dev_priv)) {
2610                 bxt_disable_dc9(dev_priv);
2611                 bxt_display_core_init(dev_priv, true);
2612                 if (dev_priv->csr.dmc_payload &&
2613                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2614                         gen9_enable_dc5(dev_priv);
2615         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2616                 hsw_disable_pc8(dev_priv);
2617         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2618                 ret = vlv_resume_prepare(dev_priv, true);
2619         }
2620
2621         /*
2622          * No point of rolling back things in case of an error, as the best
2623          * we can do is to hope that things will still work (and disable RPM).
2624          */
2625         i915_gem_init_swizzling(dev_priv);
2626         i915_gem_restore_fences(dev_priv);
2627
2628         intel_runtime_pm_enable_interrupts(dev_priv);
2629
2630         /*
2631          * On VLV/CHV display interrupts are part of the display
2632          * power well, so hpd is reinitialized from there. For
2633          * everyone else do it here.
2634          */
2635         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2636                 intel_hpd_init(dev_priv);
2637
2638         intel_enable_ipc(dev_priv);
2639
2640         enable_rpm_wakeref_asserts(dev_priv);
2641
2642         if (ret)
2643                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2644         else
2645                 DRM_DEBUG_KMS("Device resumed\n");
2646
2647         return ret;
2648 }
2649
2650 const struct dev_pm_ops i915_pm_ops = {
2651         /*
2652          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2653          * PMSG_RESUME]
2654          */
2655         .suspend = i915_pm_suspend,
2656         .suspend_late = i915_pm_suspend_late,
2657         .resume_early = i915_pm_resume_early,
2658         .resume = i915_pm_resume,
2659
2660         /*
2661          * S4 event handlers
2662          * @freeze, @freeze_late    : called (1) before creating the
2663          *                            hibernation image [PMSG_FREEZE] and
2664          *                            (2) after rebooting, before restoring
2665          *                            the image [PMSG_QUIESCE]
2666          * @thaw, @thaw_early       : called (1) after creating the hibernation
2667          *                            image, before writing it [PMSG_THAW]
2668          *                            and (2) after failing to create or
2669          *                            restore the image [PMSG_RECOVER]
2670          * @poweroff, @poweroff_late: called after writing the hibernation
2671          *                            image, before rebooting [PMSG_HIBERNATE]
2672          * @restore, @restore_early : called after rebooting and restoring the
2673          *                            hibernation image [PMSG_RESTORE]
2674          */
2675         .freeze = i915_pm_freeze,
2676         .freeze_late = i915_pm_freeze_late,
2677         .thaw_early = i915_pm_thaw_early,
2678         .thaw = i915_pm_thaw,
2679         .poweroff = i915_pm_suspend,
2680         .poweroff_late = i915_pm_poweroff_late,
2681         .restore_early = i915_pm_restore_early,
2682         .restore = i915_pm_restore,
2683
2684         /* S0ix (via runtime suspend) event handlers */
2685         .runtime_suspend = intel_runtime_suspend,
2686         .runtime_resume = intel_runtime_resume,
2687 };
2688
2689 static const struct vm_operations_struct i915_gem_vm_ops = {
2690         .fault = i915_gem_fault,
2691         .open = drm_gem_vm_open,
2692         .close = drm_gem_vm_close,
2693 };
2694
2695 static const struct file_operations i915_driver_fops = {
2696         .owner = THIS_MODULE,
2697         .open = drm_open,
2698         .release = drm_release,
2699         .unlocked_ioctl = drm_ioctl,
2700         .mmap = drm_gem_mmap,
2701         .poll = drm_poll,
2702         .read = drm_read,
2703         .compat_ioctl = i915_compat_ioctl,
2704         .llseek = noop_llseek,
2705 };
2706
2707 static int
2708 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2709                           struct drm_file *file)
2710 {
2711         return -ENODEV;
2712 }
2713
2714 static const struct drm_ioctl_desc i915_ioctls[] = {
2715         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2716         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2717         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2718         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2719         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2720         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2721         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2722         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2723         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2724         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2725         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2726         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2727         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2728         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2729         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2730         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2731         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2732         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2733         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2734         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2735         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2736         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2737         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2738         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2739         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2740         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2741         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2742         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2743         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2744         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2745         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2746         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2747         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2748         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2749         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2750         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2751         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2752         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2753         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2754         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2755         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2756         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2757         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2758         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2759         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2760         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2761         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2762         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2763         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2764         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2765         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2766         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2767         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2768         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2769         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2770 };
2771
2772 static struct drm_driver driver = {
2773         /* Don't use MTRRs here; the Xserver or userspace app should
2774          * deal with them for Intel hardware.
2775          */
2776         .driver_features =
2777             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2778             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2779         .release = i915_driver_release,
2780         .open = i915_driver_open,
2781         .lastclose = i915_driver_lastclose,
2782         .postclose = i915_driver_postclose,
2783
2784         .gem_close_object = i915_gem_close_object,
2785         .gem_free_object_unlocked = i915_gem_free_object,
2786         .gem_vm_ops = &i915_gem_vm_ops,
2787
2788         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2789         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2790         .gem_prime_export = i915_gem_prime_export,
2791         .gem_prime_import = i915_gem_prime_import,
2792
2793         .dumb_create = i915_gem_dumb_create,
2794         .dumb_map_offset = i915_gem_mmap_gtt,
2795         .ioctls = i915_ioctls,
2796         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2797         .fops = &i915_driver_fops,
2798         .name = DRIVER_NAME,
2799         .desc = DRIVER_DESC,
2800         .date = DRIVER_DATE,
2801         .major = DRIVER_MAJOR,
2802         .minor = DRIVER_MINOR,
2803         .patchlevel = DRIVER_PATCHLEVEL,
2804 };
2805
2806 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2807 #include "selftests/mock_drm.c"
2808 #endif