drm/i915: move regs pointer inside the uncore structure
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42 #include <acpi/video.h>
43
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_irq.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
49
50 #include "i915_drv.h"
51 #include "i915_trace.h"
52 #include "i915_pmu.h"
53 #include "i915_reset.h"
54 #include "i915_query.h"
55 #include "i915_vgpu.h"
56 #include "intel_drv.h"
57 #include "intel_uc.h"
58 #include "intel_workarounds.h"
59
60 static struct drm_driver driver;
61
62 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
63 static unsigned int i915_load_fail_count;
64
65 bool __i915_inject_load_failure(const char *func, int line)
66 {
67         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
68                 return false;
69
70         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
71                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
72                          i915_modparams.inject_load_failure, func, line);
73                 i915_modparams.inject_load_failure = 0;
74                 return true;
75         }
76
77         return false;
78 }
79
80 bool i915_error_injected(void)
81 {
82         return i915_load_fail_count && !i915_modparams.inject_load_failure;
83 }
84
85 #endif
86
87 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
88 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
89                     "providing the dmesg log by booting with drm.debug=0xf"
90
91 void
92 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
93               const char *fmt, ...)
94 {
95         static bool shown_bug_once;
96         struct device *kdev = dev_priv->drm.dev;
97         bool is_error = level[1] <= KERN_ERR[1];
98         bool is_debug = level[1] == KERN_DEBUG[1];
99         struct va_format vaf;
100         va_list args;
101
102         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
103                 return;
104
105         va_start(args, fmt);
106
107         vaf.fmt = fmt;
108         vaf.va = &args;
109
110         if (is_error)
111                 dev_printk(level, kdev, "%pV", &vaf);
112         else
113                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
114                            __builtin_return_address(0), &vaf);
115
116         va_end(args);
117
118         if (is_error && !shown_bug_once) {
119                 /*
120                  * Ask the user to file a bug report for the error, except
121                  * if they may have caused the bug by fiddling with unsafe
122                  * module parameters.
123                  */
124                 if (!test_taint(TAINT_USER))
125                         dev_notice(kdev, "%s", FDO_BUG_MSG);
126                 shown_bug_once = true;
127         }
128 }
129
130 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
131 static enum intel_pch
132 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
133 {
134         switch (id) {
135         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
136                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
137                 WARN_ON(!IS_GEN(dev_priv, 5));
138                 return PCH_IBX;
139         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
140                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
141                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
142                 return PCH_CPT;
143         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
144                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
145                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
146                 /* PantherPoint is CPT compatible */
147                 return PCH_CPT;
148         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
149                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
150                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
151                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
152                 return PCH_LPT;
153         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
154                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
155                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
156                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
157                 return PCH_LPT;
158         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
159                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
160                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
161                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
162                 /* WildcatPoint is LPT compatible */
163                 return PCH_LPT;
164         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
165                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
166                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
167                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
168                 /* WildcatPoint is LPT compatible */
169                 return PCH_LPT;
170         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
171                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
173                 return PCH_SPT;
174         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
175                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
177                 return PCH_SPT;
178         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
179                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
180                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
181                         !IS_COFFEELAKE(dev_priv));
182                 return PCH_KBP;
183         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
184                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
186                 return PCH_CNP;
187         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
188                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
189                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
190                 return PCH_CNP;
191         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
192                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
193                 WARN_ON(!IS_COFFEELAKE(dev_priv));
194                 /* CometPoint is CNP Compatible */
195                 return PCH_CNP;
196         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
197                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
198                 WARN_ON(!IS_ICELAKE(dev_priv));
199                 return PCH_ICP;
200         default:
201                 return PCH_NONE;
202         }
203 }
204
205 static bool intel_is_virt_pch(unsigned short id,
206                               unsigned short svendor, unsigned short sdevice)
207 {
208         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
209                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
210                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
211                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
212                  sdevice == PCI_SUBDEVICE_ID_QEMU));
213 }
214
215 static unsigned short
216 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
217 {
218         unsigned short id = 0;
219
220         /*
221          * In a virtualized passthrough environment we can be in a
222          * setup where the ISA bridge is not able to be passed through.
223          * In this case, a south bridge can be emulated and we have to
224          * make an educated guess as to which PCH is really there.
225          */
226
227         if (IS_ICELAKE(dev_priv))
228                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
229         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
231         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
232                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
233         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
234                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
235         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
236                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
237         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
238                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
239         else if (IS_GEN(dev_priv, 5))
240                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
241
242         if (id)
243                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
244         else
245                 DRM_DEBUG_KMS("Assuming no PCH\n");
246
247         return id;
248 }
249
250 static void intel_detect_pch(struct drm_i915_private *dev_priv)
251 {
252         struct pci_dev *pch = NULL;
253
254         /*
255          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
256          * make graphics device passthrough work easy for VMM, that only
257          * need to expose ISA bridge to let driver know the real hardware
258          * underneath. This is a requirement from virtualization team.
259          *
260          * In some virtualized environments (e.g. XEN), there is irrelevant
261          * ISA bridge in the system. To work reliably, we should scan trhough
262          * all the ISA bridge devices and check for the first match, instead
263          * of only checking the first one.
264          */
265         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
266                 unsigned short id;
267                 enum intel_pch pch_type;
268
269                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
270                         continue;
271
272                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
273
274                 pch_type = intel_pch_type(dev_priv, id);
275                 if (pch_type != PCH_NONE) {
276                         dev_priv->pch_type = pch_type;
277                         dev_priv->pch_id = id;
278                         break;
279                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
280                                          pch->subsystem_device)) {
281                         id = intel_virt_detect_pch(dev_priv);
282                         pch_type = intel_pch_type(dev_priv, id);
283
284                         /* Sanity check virtual PCH id */
285                         if (WARN_ON(id && pch_type == PCH_NONE))
286                                 id = 0;
287
288                         dev_priv->pch_type = pch_type;
289                         dev_priv->pch_id = id;
290                         break;
291                 }
292         }
293
294         /*
295          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
296          * display.
297          */
298         if (pch && !HAS_DISPLAY(dev_priv)) {
299                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
300                 dev_priv->pch_type = PCH_NOP;
301                 dev_priv->pch_id = 0;
302         }
303
304         if (!pch)
305                 DRM_DEBUG_KMS("No PCH found.\n");
306
307         pci_dev_put(pch);
308 }
309
310 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
311                                struct drm_file *file_priv)
312 {
313         struct drm_i915_private *dev_priv = to_i915(dev);
314         struct pci_dev *pdev = dev_priv->drm.pdev;
315         drm_i915_getparam_t *param = data;
316         int value;
317
318         switch (param->param) {
319         case I915_PARAM_IRQ_ACTIVE:
320         case I915_PARAM_ALLOW_BATCHBUFFER:
321         case I915_PARAM_LAST_DISPATCH:
322         case I915_PARAM_HAS_EXEC_CONSTANTS:
323                 /* Reject all old ums/dri params. */
324                 return -ENODEV;
325         case I915_PARAM_CHIPSET_ID:
326                 value = pdev->device;
327                 break;
328         case I915_PARAM_REVISION:
329                 value = pdev->revision;
330                 break;
331         case I915_PARAM_NUM_FENCES_AVAIL:
332                 value = dev_priv->num_fence_regs;
333                 break;
334         case I915_PARAM_HAS_OVERLAY:
335                 value = dev_priv->overlay ? 1 : 0;
336                 break;
337         case I915_PARAM_HAS_BSD:
338                 value = !!dev_priv->engine[VCS0];
339                 break;
340         case I915_PARAM_HAS_BLT:
341                 value = !!dev_priv->engine[BCS0];
342                 break;
343         case I915_PARAM_HAS_VEBOX:
344                 value = !!dev_priv->engine[VECS0];
345                 break;
346         case I915_PARAM_HAS_BSD2:
347                 value = !!dev_priv->engine[VCS1];
348                 break;
349         case I915_PARAM_HAS_LLC:
350                 value = HAS_LLC(dev_priv);
351                 break;
352         case I915_PARAM_HAS_WT:
353                 value = HAS_WT(dev_priv);
354                 break;
355         case I915_PARAM_HAS_ALIASING_PPGTT:
356                 value = INTEL_PPGTT(dev_priv);
357                 break;
358         case I915_PARAM_HAS_SEMAPHORES:
359                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
360                 break;
361         case I915_PARAM_HAS_SECURE_BATCHES:
362                 value = capable(CAP_SYS_ADMIN);
363                 break;
364         case I915_PARAM_CMD_PARSER_VERSION:
365                 value = i915_cmd_parser_get_version(dev_priv);
366                 break;
367         case I915_PARAM_SUBSLICE_TOTAL:
368                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
369                 if (!value)
370                         return -ENODEV;
371                 break;
372         case I915_PARAM_EU_TOTAL:
373                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
374                 if (!value)
375                         return -ENODEV;
376                 break;
377         case I915_PARAM_HAS_GPU_RESET:
378                 value = i915_modparams.enable_hangcheck &&
379                         intel_has_gpu_reset(dev_priv);
380                 if (value && intel_has_reset_engine(dev_priv))
381                         value = 2;
382                 break;
383         case I915_PARAM_HAS_RESOURCE_STREAMER:
384                 value = 0;
385                 break;
386         case I915_PARAM_HAS_POOLED_EU:
387                 value = HAS_POOLED_EU(dev_priv);
388                 break;
389         case I915_PARAM_MIN_EU_IN_POOL:
390                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
391                 break;
392         case I915_PARAM_HUC_STATUS:
393                 value = intel_huc_check_status(&dev_priv->huc);
394                 if (value < 0)
395                         return value;
396                 break;
397         case I915_PARAM_MMAP_GTT_VERSION:
398                 /* Though we've started our numbering from 1, and so class all
399                  * earlier versions as 0, in effect their value is undefined as
400                  * the ioctl will report EINVAL for the unknown param!
401                  */
402                 value = i915_gem_mmap_gtt_version();
403                 break;
404         case I915_PARAM_HAS_SCHEDULER:
405                 value = dev_priv->caps.scheduler;
406                 break;
407
408         case I915_PARAM_MMAP_VERSION:
409                 /* Remember to bump this if the version changes! */
410         case I915_PARAM_HAS_GEM:
411         case I915_PARAM_HAS_PAGEFLIPPING:
412         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
413         case I915_PARAM_HAS_RELAXED_FENCING:
414         case I915_PARAM_HAS_COHERENT_RINGS:
415         case I915_PARAM_HAS_RELAXED_DELTA:
416         case I915_PARAM_HAS_GEN7_SOL_RESET:
417         case I915_PARAM_HAS_WAIT_TIMEOUT:
418         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
419         case I915_PARAM_HAS_PINNED_BATCHES:
420         case I915_PARAM_HAS_EXEC_NO_RELOC:
421         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
422         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
423         case I915_PARAM_HAS_EXEC_SOFTPIN:
424         case I915_PARAM_HAS_EXEC_ASYNC:
425         case I915_PARAM_HAS_EXEC_FENCE:
426         case I915_PARAM_HAS_EXEC_CAPTURE:
427         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
428         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
429                 /* For the time being all of these are always true;
430                  * if some supported hardware does not have one of these
431                  * features this value needs to be provided from
432                  * INTEL_INFO(), a feature macro, or similar.
433                  */
434                 value = 1;
435                 break;
436         case I915_PARAM_HAS_CONTEXT_ISOLATION:
437                 value = intel_engines_has_context_isolation(dev_priv);
438                 break;
439         case I915_PARAM_SLICE_MASK:
440                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
441                 if (!value)
442                         return -ENODEV;
443                 break;
444         case I915_PARAM_SUBSLICE_MASK:
445                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
446                 if (!value)
447                         return -ENODEV;
448                 break;
449         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
450                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
451                 break;
452         case I915_PARAM_MMAP_GTT_COHERENT:
453                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
454                 break;
455         default:
456                 DRM_DEBUG("Unknown parameter %d\n", param->param);
457                 return -EINVAL;
458         }
459
460         if (put_user(value, param->value))
461                 return -EFAULT;
462
463         return 0;
464 }
465
466 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
467 {
468         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
469
470         dev_priv->bridge_dev =
471                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
472         if (!dev_priv->bridge_dev) {
473                 DRM_ERROR("bridge device not found\n");
474                 return -1;
475         }
476         return 0;
477 }
478
479 /* Allocate space for the MCH regs if needed, return nonzero on error */
480 static int
481 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
482 {
483         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
484         u32 temp_lo, temp_hi = 0;
485         u64 mchbar_addr;
486         int ret;
487
488         if (INTEL_GEN(dev_priv) >= 4)
489                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
490         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
491         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
492
493         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
494 #ifdef CONFIG_PNP
495         if (mchbar_addr &&
496             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
497                 return 0;
498 #endif
499
500         /* Get some space for it */
501         dev_priv->mch_res.name = "i915 MCHBAR";
502         dev_priv->mch_res.flags = IORESOURCE_MEM;
503         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
504                                      &dev_priv->mch_res,
505                                      MCHBAR_SIZE, MCHBAR_SIZE,
506                                      PCIBIOS_MIN_MEM,
507                                      0, pcibios_align_resource,
508                                      dev_priv->bridge_dev);
509         if (ret) {
510                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
511                 dev_priv->mch_res.start = 0;
512                 return ret;
513         }
514
515         if (INTEL_GEN(dev_priv) >= 4)
516                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
517                                        upper_32_bits(dev_priv->mch_res.start));
518
519         pci_write_config_dword(dev_priv->bridge_dev, reg,
520                                lower_32_bits(dev_priv->mch_res.start));
521         return 0;
522 }
523
524 /* Setup MCHBAR if possible, return true if we should disable it again */
525 static void
526 intel_setup_mchbar(struct drm_i915_private *dev_priv)
527 {
528         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
529         u32 temp;
530         bool enabled;
531
532         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
533                 return;
534
535         dev_priv->mchbar_need_disable = false;
536
537         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
538                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
539                 enabled = !!(temp & DEVEN_MCHBAR_EN);
540         } else {
541                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
542                 enabled = temp & 1;
543         }
544
545         /* If it's already enabled, don't have to do anything */
546         if (enabled)
547                 return;
548
549         if (intel_alloc_mchbar_resource(dev_priv))
550                 return;
551
552         dev_priv->mchbar_need_disable = true;
553
554         /* Space is allocated or reserved, so enable it. */
555         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
556                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
557                                        temp | DEVEN_MCHBAR_EN);
558         } else {
559                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
560                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
561         }
562 }
563
564 static void
565 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
566 {
567         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
568
569         if (dev_priv->mchbar_need_disable) {
570                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
571                         u32 deven_val;
572
573                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
574                                               &deven_val);
575                         deven_val &= ~DEVEN_MCHBAR_EN;
576                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
577                                                deven_val);
578                 } else {
579                         u32 mchbar_val;
580
581                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
582                                               &mchbar_val);
583                         mchbar_val &= ~1;
584                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
585                                                mchbar_val);
586                 }
587         }
588
589         if (dev_priv->mch_res.start)
590                 release_resource(&dev_priv->mch_res);
591 }
592
593 /* true = enable decode, false = disable decoder */
594 static unsigned int i915_vga_set_decode(void *cookie, bool state)
595 {
596         struct drm_i915_private *dev_priv = cookie;
597
598         intel_modeset_vga_set_state(dev_priv, state);
599         if (state)
600                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
601                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
602         else
603                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
604 }
605
606 static int i915_resume_switcheroo(struct drm_device *dev);
607 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
608
609 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
610 {
611         struct drm_device *dev = pci_get_drvdata(pdev);
612         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
613
614         if (state == VGA_SWITCHEROO_ON) {
615                 pr_info("switched on\n");
616                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
617                 /* i915 resume handler doesn't set to D0 */
618                 pci_set_power_state(pdev, PCI_D0);
619                 i915_resume_switcheroo(dev);
620                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
621         } else {
622                 pr_info("switched off\n");
623                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
624                 i915_suspend_switcheroo(dev, pmm);
625                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
626         }
627 }
628
629 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
630 {
631         struct drm_device *dev = pci_get_drvdata(pdev);
632
633         /*
634          * FIXME: open_count is protected by drm_global_mutex but that would lead to
635          * locking inversion with the driver load path. And the access here is
636          * completely racy anyway. So don't bother with locking for now.
637          */
638         return dev->open_count == 0;
639 }
640
641 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
642         .set_gpu_state = i915_switcheroo_set_state,
643         .reprobe = NULL,
644         .can_switch = i915_switcheroo_can_switch,
645 };
646
647 static int i915_load_modeset_init(struct drm_device *dev)
648 {
649         struct drm_i915_private *dev_priv = to_i915(dev);
650         struct pci_dev *pdev = dev_priv->drm.pdev;
651         int ret;
652
653         if (i915_inject_load_failure())
654                 return -ENODEV;
655
656         if (HAS_DISPLAY(dev_priv)) {
657                 ret = drm_vblank_init(&dev_priv->drm,
658                                       INTEL_INFO(dev_priv)->num_pipes);
659                 if (ret)
660                         goto out;
661         }
662
663         intel_bios_init(dev_priv);
664
665         /* If we have > 1 VGA cards, then we need to arbitrate access
666          * to the common VGA resources.
667          *
668          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
669          * then we do not take part in VGA arbitration and the
670          * vga_client_register() fails with -ENODEV.
671          */
672         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
673         if (ret && ret != -ENODEV)
674                 goto out;
675
676         intel_register_dsm_handler();
677
678         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
679         if (ret)
680                 goto cleanup_vga_client;
681
682         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
683         intel_update_rawclk(dev_priv);
684
685         intel_power_domains_init_hw(dev_priv, false);
686
687         intel_csr_ucode_init(dev_priv);
688
689         ret = intel_irq_install(dev_priv);
690         if (ret)
691                 goto cleanup_csr;
692
693         intel_setup_gmbus(dev_priv);
694
695         /* Important: The output setup functions called by modeset_init need
696          * working irqs for e.g. gmbus and dp aux transfers. */
697         ret = intel_modeset_init(dev);
698         if (ret)
699                 goto cleanup_irq;
700
701         ret = i915_gem_init(dev_priv);
702         if (ret)
703                 goto cleanup_modeset;
704
705         intel_overlay_setup(dev_priv);
706
707         if (!HAS_DISPLAY(dev_priv))
708                 return 0;
709
710         ret = intel_fbdev_init(dev);
711         if (ret)
712                 goto cleanup_gem;
713
714         /* Only enable hotplug handling once the fbdev is fully set up. */
715         intel_hpd_init(dev_priv);
716
717         intel_init_ipc(dev_priv);
718
719         return 0;
720
721 cleanup_gem:
722         i915_gem_suspend(dev_priv);
723         i915_gem_fini(dev_priv);
724 cleanup_modeset:
725         intel_modeset_cleanup(dev);
726 cleanup_irq:
727         drm_irq_uninstall(dev);
728         intel_teardown_gmbus(dev_priv);
729 cleanup_csr:
730         intel_csr_ucode_fini(dev_priv);
731         intel_power_domains_fini_hw(dev_priv);
732         vga_switcheroo_unregister_client(pdev);
733 cleanup_vga_client:
734         vga_client_register(pdev, NULL, NULL, NULL);
735 out:
736         return ret;
737 }
738
739 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
740 {
741         struct apertures_struct *ap;
742         struct pci_dev *pdev = dev_priv->drm.pdev;
743         struct i915_ggtt *ggtt = &dev_priv->ggtt;
744         bool primary;
745         int ret;
746
747         ap = alloc_apertures(1);
748         if (!ap)
749                 return -ENOMEM;
750
751         ap->ranges[0].base = ggtt->gmadr.start;
752         ap->ranges[0].size = ggtt->mappable_end;
753
754         primary =
755                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
756
757         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
758
759         kfree(ap);
760
761         return ret;
762 }
763
764 #if !defined(CONFIG_VGA_CONSOLE)
765 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
766 {
767         return 0;
768 }
769 #elif !defined(CONFIG_DUMMY_CONSOLE)
770 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
771 {
772         return -ENODEV;
773 }
774 #else
775 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
776 {
777         int ret = 0;
778
779         DRM_INFO("Replacing VGA console driver\n");
780
781         console_lock();
782         if (con_is_bound(&vga_con))
783                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
784         if (ret == 0) {
785                 ret = do_unregister_con_driver(&vga_con);
786
787                 /* Ignore "already unregistered". */
788                 if (ret == -ENODEV)
789                         ret = 0;
790         }
791         console_unlock();
792
793         return ret;
794 }
795 #endif
796
797 static void intel_init_dpio(struct drm_i915_private *dev_priv)
798 {
799         /*
800          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
801          * CHV x1 PHY (DP/HDMI D)
802          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
803          */
804         if (IS_CHERRYVIEW(dev_priv)) {
805                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
806                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
807         } else if (IS_VALLEYVIEW(dev_priv)) {
808                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
809         }
810 }
811
812 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
813 {
814         /*
815          * The i915 workqueue is primarily used for batched retirement of
816          * requests (and thus managing bo) once the task has been completed
817          * by the GPU. i915_retire_requests() is called directly when we
818          * need high-priority retirement, such as waiting for an explicit
819          * bo.
820          *
821          * It is also used for periodic low-priority events, such as
822          * idle-timers and recording error state.
823          *
824          * All tasks on the workqueue are expected to acquire the dev mutex
825          * so there is no point in running more than one instance of the
826          * workqueue at any time.  Use an ordered one.
827          */
828         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
829         if (dev_priv->wq == NULL)
830                 goto out_err;
831
832         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
833         if (dev_priv->hotplug.dp_wq == NULL)
834                 goto out_free_wq;
835
836         return 0;
837
838 out_free_wq:
839         destroy_workqueue(dev_priv->wq);
840 out_err:
841         DRM_ERROR("Failed to allocate workqueues.\n");
842
843         return -ENOMEM;
844 }
845
846 static void i915_engines_cleanup(struct drm_i915_private *i915)
847 {
848         struct intel_engine_cs *engine;
849         enum intel_engine_id id;
850
851         for_each_engine(engine, i915, id)
852                 kfree(engine);
853 }
854
855 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
856 {
857         destroy_workqueue(dev_priv->hotplug.dp_wq);
858         destroy_workqueue(dev_priv->wq);
859 }
860
861 /*
862  * We don't keep the workarounds for pre-production hardware, so we expect our
863  * driver to fail on these machines in one way or another. A little warning on
864  * dmesg may help both the user and the bug triagers.
865  *
866  * Our policy for removing pre-production workarounds is to keep the
867  * current gen workarounds as a guide to the bring-up of the next gen
868  * (workarounds have a habit of persisting!). Anything older than that
869  * should be removed along with the complications they introduce.
870  */
871 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
872 {
873         bool pre = false;
874
875         pre |= IS_HSW_EARLY_SDV(dev_priv);
876         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
877         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
878         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
879
880         if (pre) {
881                 DRM_ERROR("This is a pre-production stepping. "
882                           "It may not be fully functional.\n");
883                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
884         }
885 }
886
887 /**
888  * i915_driver_init_early - setup state not requiring device access
889  * @dev_priv: device private
890  *
891  * Initialize everything that is a "SW-only" state, that is state not
892  * requiring accessing the device or exposing the driver via kernel internal
893  * or userspace interfaces. Example steps belonging here: lock initialization,
894  * system memory allocation, setting up device specific attributes and
895  * function hooks not requiring accessing the device.
896  */
897 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
898 {
899         int ret = 0;
900
901         if (i915_inject_load_failure())
902                 return -ENODEV;
903
904         spin_lock_init(&dev_priv->irq_lock);
905         spin_lock_init(&dev_priv->gpu_error.lock);
906         mutex_init(&dev_priv->backlight_lock);
907         spin_lock_init(&dev_priv->uncore.lock);
908
909         mutex_init(&dev_priv->sb_lock);
910         mutex_init(&dev_priv->av_mutex);
911         mutex_init(&dev_priv->wm.wm_mutex);
912         mutex_init(&dev_priv->pps_mutex);
913         mutex_init(&dev_priv->hdcp_comp_mutex);
914
915         i915_memcpy_init_early(dev_priv);
916         intel_runtime_pm_init_early(dev_priv);
917
918         ret = i915_workqueues_init(dev_priv);
919         if (ret < 0)
920                 goto err_engines;
921
922         ret = i915_gem_init_early(dev_priv);
923         if (ret < 0)
924                 goto err_workqueues;
925
926         /* This must be called before any calls to HAS_PCH_* */
927         intel_detect_pch(dev_priv);
928
929         intel_wopcm_init_early(&dev_priv->wopcm);
930         intel_uc_init_early(dev_priv);
931         intel_pm_setup(dev_priv);
932         intel_init_dpio(dev_priv);
933         ret = intel_power_domains_init(dev_priv);
934         if (ret < 0)
935                 goto err_uc;
936         intel_irq_init(dev_priv);
937         intel_hangcheck_init(dev_priv);
938         intel_init_display_hooks(dev_priv);
939         intel_init_clock_gating_hooks(dev_priv);
940         intel_init_audio_hooks(dev_priv);
941         intel_display_crc_init(dev_priv);
942
943         intel_detect_preproduction_hw(dev_priv);
944
945         return 0;
946
947 err_uc:
948         intel_uc_cleanup_early(dev_priv);
949         i915_gem_cleanup_early(dev_priv);
950 err_workqueues:
951         i915_workqueues_cleanup(dev_priv);
952 err_engines:
953         i915_engines_cleanup(dev_priv);
954         return ret;
955 }
956
957 /**
958  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
959  * @dev_priv: device private
960  */
961 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
962 {
963         intel_irq_fini(dev_priv);
964         intel_power_domains_cleanup(dev_priv);
965         intel_uc_cleanup_early(dev_priv);
966         i915_gem_cleanup_early(dev_priv);
967         i915_workqueues_cleanup(dev_priv);
968         i915_engines_cleanup(dev_priv);
969 }
970
971 /**
972  * i915_driver_init_mmio - setup device MMIO
973  * @dev_priv: device private
974  *
975  * Setup minimal device state necessary for MMIO accesses later in the
976  * initialization sequence. The setup here should avoid any other device-wide
977  * side effects or exposing the driver via kernel internal or user space
978  * interfaces.
979  */
980 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
981 {
982         int ret;
983
984         if (i915_inject_load_failure())
985                 return -ENODEV;
986
987         if (i915_get_bridge_dev(dev_priv))
988                 return -EIO;
989
990         ret = intel_uncore_init(&dev_priv->uncore);
991         if (ret < 0)
992                 goto err_bridge;
993
994         /* Try to make sure MCHBAR is enabled before poking at it */
995         intel_setup_mchbar(dev_priv);
996
997         intel_device_info_init_mmio(dev_priv);
998
999         intel_uncore_prune(&dev_priv->uncore);
1000
1001         intel_uc_init_mmio(dev_priv);
1002
1003         ret = intel_engines_init_mmio(dev_priv);
1004         if (ret)
1005                 goto err_uncore;
1006
1007         i915_gem_init_mmio(dev_priv);
1008
1009         return 0;
1010
1011 err_uncore:
1012         intel_teardown_mchbar(dev_priv);
1013         intel_uncore_fini(&dev_priv->uncore);
1014 err_bridge:
1015         pci_dev_put(dev_priv->bridge_dev);
1016
1017         return ret;
1018 }
1019
1020 /**
1021  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1022  * @dev_priv: device private
1023  */
1024 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1025 {
1026         intel_teardown_mchbar(dev_priv);
1027         intel_uncore_fini(&dev_priv->uncore);
1028         pci_dev_put(dev_priv->bridge_dev);
1029 }
1030
1031 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1032 {
1033         intel_gvt_sanitize_options(dev_priv);
1034 }
1035
1036 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1037
1038 static const char *intel_dram_type_str(enum intel_dram_type type)
1039 {
1040         static const char * const str[] = {
1041                 DRAM_TYPE_STR(UNKNOWN),
1042                 DRAM_TYPE_STR(DDR3),
1043                 DRAM_TYPE_STR(DDR4),
1044                 DRAM_TYPE_STR(LPDDR3),
1045                 DRAM_TYPE_STR(LPDDR4),
1046         };
1047
1048         if (type >= ARRAY_SIZE(str))
1049                 type = INTEL_DRAM_UNKNOWN;
1050
1051         return str[type];
1052 }
1053
1054 #undef DRAM_TYPE_STR
1055
1056 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1057 {
1058         return dimm->ranks * 64 / (dimm->width ?: 1);
1059 }
1060
1061 /* Returns total GB for the whole DIMM */
1062 static int skl_get_dimm_size(u16 val)
1063 {
1064         return val & SKL_DRAM_SIZE_MASK;
1065 }
1066
1067 static int skl_get_dimm_width(u16 val)
1068 {
1069         if (skl_get_dimm_size(val) == 0)
1070                 return 0;
1071
1072         switch (val & SKL_DRAM_WIDTH_MASK) {
1073         case SKL_DRAM_WIDTH_X8:
1074         case SKL_DRAM_WIDTH_X16:
1075         case SKL_DRAM_WIDTH_X32:
1076                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1077                 return 8 << val;
1078         default:
1079                 MISSING_CASE(val);
1080                 return 0;
1081         }
1082 }
1083
1084 static int skl_get_dimm_ranks(u16 val)
1085 {
1086         if (skl_get_dimm_size(val) == 0)
1087                 return 0;
1088
1089         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1090
1091         return val + 1;
1092 }
1093
1094 /* Returns total GB for the whole DIMM */
1095 static int cnl_get_dimm_size(u16 val)
1096 {
1097         return (val & CNL_DRAM_SIZE_MASK) / 2;
1098 }
1099
1100 static int cnl_get_dimm_width(u16 val)
1101 {
1102         if (cnl_get_dimm_size(val) == 0)
1103                 return 0;
1104
1105         switch (val & CNL_DRAM_WIDTH_MASK) {
1106         case CNL_DRAM_WIDTH_X8:
1107         case CNL_DRAM_WIDTH_X16:
1108         case CNL_DRAM_WIDTH_X32:
1109                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1110                 return 8 << val;
1111         default:
1112                 MISSING_CASE(val);
1113                 return 0;
1114         }
1115 }
1116
1117 static int cnl_get_dimm_ranks(u16 val)
1118 {
1119         if (cnl_get_dimm_size(val) == 0)
1120                 return 0;
1121
1122         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1123
1124         return val + 1;
1125 }
1126
1127 static bool
1128 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1129 {
1130         /* Convert total GB to Gb per DRAM device */
1131         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1132 }
1133
1134 static void
1135 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1136                        struct dram_dimm_info *dimm,
1137                        int channel, char dimm_name, u16 val)
1138 {
1139         if (INTEL_GEN(dev_priv) >= 10) {
1140                 dimm->size = cnl_get_dimm_size(val);
1141                 dimm->width = cnl_get_dimm_width(val);
1142                 dimm->ranks = cnl_get_dimm_ranks(val);
1143         } else {
1144                 dimm->size = skl_get_dimm_size(val);
1145                 dimm->width = skl_get_dimm_width(val);
1146                 dimm->ranks = skl_get_dimm_ranks(val);
1147         }
1148
1149         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1150                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1151                       yesno(skl_is_16gb_dimm(dimm)));
1152 }
1153
1154 static int
1155 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1156                           struct dram_channel_info *ch,
1157                           int channel, u32 val)
1158 {
1159         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1160                                channel, 'L', val & 0xffff);
1161         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1162                                channel, 'S', val >> 16);
1163
1164         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1165                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1166                 return -EINVAL;
1167         }
1168
1169         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1170                 ch->ranks = 2;
1171         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1172                 ch->ranks = 2;
1173         else
1174                 ch->ranks = 1;
1175
1176         ch->is_16gb_dimm =
1177                 skl_is_16gb_dimm(&ch->dimm_l) ||
1178                 skl_is_16gb_dimm(&ch->dimm_s);
1179
1180         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1181                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1182
1183         return 0;
1184 }
1185
1186 static bool
1187 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1188                         const struct dram_channel_info *ch1)
1189 {
1190         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1191                 (ch0->dimm_s.size == 0 ||
1192                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1193 }
1194
1195 static int
1196 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1197 {
1198         struct dram_info *dram_info = &dev_priv->dram_info;
1199         struct dram_channel_info ch0 = {}, ch1 = {};
1200         u32 val;
1201         int ret;
1202
1203         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1204         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1205         if (ret == 0)
1206                 dram_info->num_channels++;
1207
1208         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1209         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1210         if (ret == 0)
1211                 dram_info->num_channels++;
1212
1213         if (dram_info->num_channels == 0) {
1214                 DRM_INFO("Number of memory channels is zero\n");
1215                 return -EINVAL;
1216         }
1217
1218         /*
1219          * If any of the channel is single rank channel, worst case output
1220          * will be same as if single rank memory, so consider single rank
1221          * memory.
1222          */
1223         if (ch0.ranks == 1 || ch1.ranks == 1)
1224                 dram_info->ranks = 1;
1225         else
1226                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1227
1228         if (dram_info->ranks == 0) {
1229                 DRM_INFO("couldn't get memory rank information\n");
1230                 return -EINVAL;
1231         }
1232
1233         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1234
1235         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1236
1237         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1238                       yesno(dram_info->symmetric_memory));
1239         return 0;
1240 }
1241
1242 static enum intel_dram_type
1243 skl_get_dram_type(struct drm_i915_private *dev_priv)
1244 {
1245         u32 val;
1246
1247         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1248
1249         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1250         case SKL_DRAM_DDR_TYPE_DDR3:
1251                 return INTEL_DRAM_DDR3;
1252         case SKL_DRAM_DDR_TYPE_DDR4:
1253                 return INTEL_DRAM_DDR4;
1254         case SKL_DRAM_DDR_TYPE_LPDDR3:
1255                 return INTEL_DRAM_LPDDR3;
1256         case SKL_DRAM_DDR_TYPE_LPDDR4:
1257                 return INTEL_DRAM_LPDDR4;
1258         default:
1259                 MISSING_CASE(val);
1260                 return INTEL_DRAM_UNKNOWN;
1261         }
1262 }
1263
1264 static int
1265 skl_get_dram_info(struct drm_i915_private *dev_priv)
1266 {
1267         struct dram_info *dram_info = &dev_priv->dram_info;
1268         u32 mem_freq_khz, val;
1269         int ret;
1270
1271         dram_info->type = skl_get_dram_type(dev_priv);
1272         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1273
1274         ret = skl_dram_get_channels_info(dev_priv);
1275         if (ret)
1276                 return ret;
1277
1278         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1279         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1280                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1281
1282         dram_info->bandwidth_kbps = dram_info->num_channels *
1283                                                         mem_freq_khz * 8;
1284
1285         if (dram_info->bandwidth_kbps == 0) {
1286                 DRM_INFO("Couldn't get system memory bandwidth\n");
1287                 return -EINVAL;
1288         }
1289
1290         dram_info->valid = true;
1291         return 0;
1292 }
1293
1294 /* Returns Gb per DRAM device */
1295 static int bxt_get_dimm_size(u32 val)
1296 {
1297         switch (val & BXT_DRAM_SIZE_MASK) {
1298         case BXT_DRAM_SIZE_4GBIT:
1299                 return 4;
1300         case BXT_DRAM_SIZE_6GBIT:
1301                 return 6;
1302         case BXT_DRAM_SIZE_8GBIT:
1303                 return 8;
1304         case BXT_DRAM_SIZE_12GBIT:
1305                 return 12;
1306         case BXT_DRAM_SIZE_16GBIT:
1307                 return 16;
1308         default:
1309                 MISSING_CASE(val);
1310                 return 0;
1311         }
1312 }
1313
1314 static int bxt_get_dimm_width(u32 val)
1315 {
1316         if (!bxt_get_dimm_size(val))
1317                 return 0;
1318
1319         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1320
1321         return 8 << val;
1322 }
1323
1324 static int bxt_get_dimm_ranks(u32 val)
1325 {
1326         if (!bxt_get_dimm_size(val))
1327                 return 0;
1328
1329         switch (val & BXT_DRAM_RANK_MASK) {
1330         case BXT_DRAM_RANK_SINGLE:
1331                 return 1;
1332         case BXT_DRAM_RANK_DUAL:
1333                 return 2;
1334         default:
1335                 MISSING_CASE(val);
1336                 return 0;
1337         }
1338 }
1339
1340 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1341 {
1342         if (!bxt_get_dimm_size(val))
1343                 return INTEL_DRAM_UNKNOWN;
1344
1345         switch (val & BXT_DRAM_TYPE_MASK) {
1346         case BXT_DRAM_TYPE_DDR3:
1347                 return INTEL_DRAM_DDR3;
1348         case BXT_DRAM_TYPE_LPDDR3:
1349                 return INTEL_DRAM_LPDDR3;
1350         case BXT_DRAM_TYPE_DDR4:
1351                 return INTEL_DRAM_DDR4;
1352         case BXT_DRAM_TYPE_LPDDR4:
1353                 return INTEL_DRAM_LPDDR4;
1354         default:
1355                 MISSING_CASE(val);
1356                 return INTEL_DRAM_UNKNOWN;
1357         }
1358 }
1359
1360 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1361                               u32 val)
1362 {
1363         dimm->width = bxt_get_dimm_width(val);
1364         dimm->ranks = bxt_get_dimm_ranks(val);
1365
1366         /*
1367          * Size in register is Gb per DRAM device. Convert to total
1368          * GB to match the way we report this for non-LP platforms.
1369          */
1370         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1371 }
1372
1373 static int
1374 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1375 {
1376         struct dram_info *dram_info = &dev_priv->dram_info;
1377         u32 dram_channels;
1378         u32 mem_freq_khz, val;
1379         u8 num_active_channels;
1380         int i;
1381
1382         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1383         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1384                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1385
1386         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1387         num_active_channels = hweight32(dram_channels);
1388
1389         /* Each active bit represents 4-byte channel */
1390         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1391
1392         if (dram_info->bandwidth_kbps == 0) {
1393                 DRM_INFO("Couldn't get system memory bandwidth\n");
1394                 return -EINVAL;
1395         }
1396
1397         /*
1398          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1399          */
1400         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1401                 struct dram_dimm_info dimm;
1402                 enum intel_dram_type type;
1403
1404                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1405                 if (val == 0xFFFFFFFF)
1406                         continue;
1407
1408                 dram_info->num_channels++;
1409
1410                 bxt_get_dimm_info(&dimm, val);
1411                 type = bxt_get_dimm_type(val);
1412
1413                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1414                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1415                         dram_info->type != type);
1416
1417                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1418                               i - BXT_D_CR_DRP0_DUNIT_START,
1419                               dimm.size, dimm.width, dimm.ranks,
1420                               intel_dram_type_str(type));
1421
1422                 /*
1423                  * If any of the channel is single rank channel,
1424                  * worst case output will be same as if single rank
1425                  * memory, so consider single rank memory.
1426                  */
1427                 if (dram_info->ranks == 0)
1428                         dram_info->ranks = dimm.ranks;
1429                 else if (dimm.ranks == 1)
1430                         dram_info->ranks = 1;
1431
1432                 if (type != INTEL_DRAM_UNKNOWN)
1433                         dram_info->type = type;
1434         }
1435
1436         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1437             dram_info->ranks == 0) {
1438                 DRM_INFO("couldn't get memory information\n");
1439                 return -EINVAL;
1440         }
1441
1442         dram_info->valid = true;
1443         return 0;
1444 }
1445
1446 static void
1447 intel_get_dram_info(struct drm_i915_private *dev_priv)
1448 {
1449         struct dram_info *dram_info = &dev_priv->dram_info;
1450         int ret;
1451
1452         /*
1453          * Assume 16Gb DIMMs are present until proven otherwise.
1454          * This is only used for the level 0 watermark latency
1455          * w/a which does not apply to bxt/glk.
1456          */
1457         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1458
1459         if (INTEL_GEN(dev_priv) < 9)
1460                 return;
1461
1462         if (IS_GEN9_LP(dev_priv))
1463                 ret = bxt_get_dram_info(dev_priv);
1464         else
1465                 ret = skl_get_dram_info(dev_priv);
1466         if (ret)
1467                 return;
1468
1469         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1470                       dram_info->bandwidth_kbps,
1471                       dram_info->num_channels);
1472
1473         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1474                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1475 }
1476
1477 /**
1478  * i915_driver_init_hw - setup state requiring device access
1479  * @dev_priv: device private
1480  *
1481  * Setup state that requires accessing the device, but doesn't require
1482  * exposing the driver via kernel internal or userspace interfaces.
1483  */
1484 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1485 {
1486         struct pci_dev *pdev = dev_priv->drm.pdev;
1487         int ret;
1488
1489         if (i915_inject_load_failure())
1490                 return -ENODEV;
1491
1492         intel_device_info_runtime_init(dev_priv);
1493
1494         if (HAS_PPGTT(dev_priv)) {
1495                 if (intel_vgpu_active(dev_priv) &&
1496                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1497                         i915_report_error(dev_priv,
1498                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1499                         return -ENXIO;
1500                 }
1501         }
1502
1503         if (HAS_EXECLISTS(dev_priv)) {
1504                 /*
1505                  * Older GVT emulation depends upon intercepting CSB mmio,
1506                  * which we no longer use, preferring to use the HWSP cache
1507                  * instead.
1508                  */
1509                 if (intel_vgpu_active(dev_priv) &&
1510                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1511                         i915_report_error(dev_priv,
1512                                           "old vGPU host found, support for HWSP emulation required\n");
1513                         return -ENXIO;
1514                 }
1515         }
1516
1517         intel_sanitize_options(dev_priv);
1518
1519         i915_perf_init(dev_priv);
1520
1521         ret = i915_ggtt_probe_hw(dev_priv);
1522         if (ret)
1523                 goto err_perf;
1524
1525         /*
1526          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1527          * otherwise the vga fbdev driver falls over.
1528          */
1529         ret = i915_kick_out_firmware_fb(dev_priv);
1530         if (ret) {
1531                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1532                 goto err_ggtt;
1533         }
1534
1535         ret = i915_kick_out_vgacon(dev_priv);
1536         if (ret) {
1537                 DRM_ERROR("failed to remove conflicting VGA console\n");
1538                 goto err_ggtt;
1539         }
1540
1541         ret = i915_ggtt_init_hw(dev_priv);
1542         if (ret)
1543                 goto err_ggtt;
1544
1545         ret = i915_ggtt_enable_hw(dev_priv);
1546         if (ret) {
1547                 DRM_ERROR("failed to enable GGTT\n");
1548                 goto err_ggtt;
1549         }
1550
1551         pci_set_master(pdev);
1552
1553         /* overlay on gen2 is broken and can't address above 1G */
1554         if (IS_GEN(dev_priv, 2)) {
1555                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1556                 if (ret) {
1557                         DRM_ERROR("failed to set DMA mask\n");
1558
1559                         goto err_ggtt;
1560                 }
1561         }
1562
1563         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1564          * using 32bit addressing, overwriting memory if HWS is located
1565          * above 4GB.
1566          *
1567          * The documentation also mentions an issue with undefined
1568          * behaviour if any general state is accessed within a page above 4GB,
1569          * which also needs to be handled carefully.
1570          */
1571         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1572                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1573
1574                 if (ret) {
1575                         DRM_ERROR("failed to set DMA mask\n");
1576
1577                         goto err_ggtt;
1578                 }
1579         }
1580
1581         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1582                            PM_QOS_DEFAULT_VALUE);
1583
1584         intel_uncore_sanitize(dev_priv);
1585
1586         intel_gt_init_workarounds(dev_priv);
1587         i915_gem_load_init_fences(dev_priv);
1588
1589         /* On the 945G/GM, the chipset reports the MSI capability on the
1590          * integrated graphics even though the support isn't actually there
1591          * according to the published specs.  It doesn't appear to function
1592          * correctly in testing on 945G.
1593          * This may be a side effect of MSI having been made available for PEG
1594          * and the registers being closely associated.
1595          *
1596          * According to chipset errata, on the 965GM, MSI interrupts may
1597          * be lost or delayed, and was defeatured. MSI interrupts seem to
1598          * get lost on g4x as well, and interrupt delivery seems to stay
1599          * properly dead afterwards. So we'll just disable them for all
1600          * pre-gen5 chipsets.
1601          *
1602          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1603          * interrupts even when in MSI mode. This results in spurious
1604          * interrupt warnings if the legacy irq no. is shared with another
1605          * device. The kernel then disables that interrupt source and so
1606          * prevents the other device from working properly.
1607          */
1608         if (INTEL_GEN(dev_priv) >= 5) {
1609                 if (pci_enable_msi(pdev) < 0)
1610                         DRM_DEBUG_DRIVER("can't enable MSI");
1611         }
1612
1613         ret = intel_gvt_init(dev_priv);
1614         if (ret)
1615                 goto err_msi;
1616
1617         intel_opregion_setup(dev_priv);
1618         /*
1619          * Fill the dram structure to get the system raw bandwidth and
1620          * dram info. This will be used for memory latency calculation.
1621          */
1622         intel_get_dram_info(dev_priv);
1623
1624
1625         return 0;
1626
1627 err_msi:
1628         if (pdev->msi_enabled)
1629                 pci_disable_msi(pdev);
1630         pm_qos_remove_request(&dev_priv->pm_qos);
1631 err_ggtt:
1632         i915_ggtt_cleanup_hw(dev_priv);
1633 err_perf:
1634         i915_perf_fini(dev_priv);
1635         return ret;
1636 }
1637
1638 /**
1639  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1640  * @dev_priv: device private
1641  */
1642 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1643 {
1644         struct pci_dev *pdev = dev_priv->drm.pdev;
1645
1646         i915_perf_fini(dev_priv);
1647
1648         if (pdev->msi_enabled)
1649                 pci_disable_msi(pdev);
1650
1651         pm_qos_remove_request(&dev_priv->pm_qos);
1652         i915_ggtt_cleanup_hw(dev_priv);
1653 }
1654
1655 /**
1656  * i915_driver_register - register the driver with the rest of the system
1657  * @dev_priv: device private
1658  *
1659  * Perform any steps necessary to make the driver available via kernel
1660  * internal or userspace interfaces.
1661  */
1662 static void i915_driver_register(struct drm_i915_private *dev_priv)
1663 {
1664         struct drm_device *dev = &dev_priv->drm;
1665
1666         i915_gem_shrinker_register(dev_priv);
1667         i915_pmu_register(dev_priv);
1668
1669         /*
1670          * Notify a valid surface after modesetting,
1671          * when running inside a VM.
1672          */
1673         if (intel_vgpu_active(dev_priv))
1674                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1675
1676         /* Reveal our presence to userspace */
1677         if (drm_dev_register(dev, 0) == 0) {
1678                 i915_debugfs_register(dev_priv);
1679                 i915_setup_sysfs(dev_priv);
1680
1681                 /* Depends on sysfs having been initialized */
1682                 i915_perf_register(dev_priv);
1683         } else
1684                 DRM_ERROR("Failed to register driver for userspace access!\n");
1685
1686         if (HAS_DISPLAY(dev_priv)) {
1687                 /* Must be done after probing outputs */
1688                 intel_opregion_register(dev_priv);
1689                 acpi_video_register();
1690         }
1691
1692         if (IS_GEN(dev_priv, 5))
1693                 intel_gpu_ips_init(dev_priv);
1694
1695         intel_audio_init(dev_priv);
1696
1697         /*
1698          * Some ports require correctly set-up hpd registers for detection to
1699          * work properly (leading to ghost connected connector status), e.g. VGA
1700          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1701          * irqs are fully enabled. We do it last so that the async config
1702          * cannot run before the connectors are registered.
1703          */
1704         intel_fbdev_initial_config_async(dev);
1705
1706         /*
1707          * We need to coordinate the hotplugs with the asynchronous fbdev
1708          * configuration, for which we use the fbdev->async_cookie.
1709          */
1710         if (HAS_DISPLAY(dev_priv))
1711                 drm_kms_helper_poll_init(dev);
1712
1713         intel_power_domains_enable(dev_priv);
1714         intel_runtime_pm_enable(dev_priv);
1715 }
1716
1717 /**
1718  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1719  * @dev_priv: device private
1720  */
1721 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1722 {
1723         intel_runtime_pm_disable(dev_priv);
1724         intel_power_domains_disable(dev_priv);
1725
1726         intel_fbdev_unregister(dev_priv);
1727         intel_audio_deinit(dev_priv);
1728
1729         /*
1730          * After flushing the fbdev (incl. a late async config which will
1731          * have delayed queuing of a hotplug event), then flush the hotplug
1732          * events.
1733          */
1734         drm_kms_helper_poll_fini(&dev_priv->drm);
1735
1736         intel_gpu_ips_teardown();
1737         acpi_video_unregister();
1738         intel_opregion_unregister(dev_priv);
1739
1740         i915_perf_unregister(dev_priv);
1741         i915_pmu_unregister(dev_priv);
1742
1743         i915_teardown_sysfs(dev_priv);
1744         drm_dev_unregister(&dev_priv->drm);
1745
1746         i915_gem_shrinker_unregister(dev_priv);
1747 }
1748
1749 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1750 {
1751         if (drm_debug & DRM_UT_DRIVER) {
1752                 struct drm_printer p = drm_debug_printer("i915 device info:");
1753
1754                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1755                            INTEL_DEVID(dev_priv),
1756                            INTEL_REVID(dev_priv),
1757                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1758                            INTEL_GEN(dev_priv));
1759
1760                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1761                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1762         }
1763
1764         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1765                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1766         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1767                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1768         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1769                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1770 }
1771
1772 static struct drm_i915_private *
1773 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1774 {
1775         const struct intel_device_info *match_info =
1776                 (struct intel_device_info *)ent->driver_data;
1777         struct intel_device_info *device_info;
1778         struct drm_i915_private *i915;
1779         int err;
1780
1781         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1782         if (!i915)
1783                 return ERR_PTR(-ENOMEM);
1784
1785         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1786         if (err) {
1787                 kfree(i915);
1788                 return ERR_PTR(err);
1789         }
1790
1791         i915->drm.pdev = pdev;
1792         i915->drm.dev_private = i915;
1793         pci_set_drvdata(pdev, &i915->drm);
1794
1795         /* Setup the write-once "constant" device info */
1796         device_info = mkwrite_device_info(i915);
1797         memcpy(device_info, match_info, sizeof(*device_info));
1798         RUNTIME_INFO(i915)->device_id = pdev->device;
1799
1800         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1801                      BITS_PER_TYPE(device_info->platform_mask));
1802         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1803
1804         return i915;
1805 }
1806
1807 static void i915_driver_destroy(struct drm_i915_private *i915)
1808 {
1809         struct pci_dev *pdev = i915->drm.pdev;
1810
1811         drm_dev_fini(&i915->drm);
1812         kfree(i915);
1813
1814         /* And make sure we never chase our dangling pointer from pci_dev */
1815         pci_set_drvdata(pdev, NULL);
1816 }
1817
1818 /**
1819  * i915_driver_load - setup chip and create an initial config
1820  * @pdev: PCI device
1821  * @ent: matching PCI ID entry
1822  *
1823  * The driver load routine has to do several things:
1824  *   - drive output discovery via intel_modeset_init()
1825  *   - initialize the memory manager
1826  *   - allocate initial config memory
1827  *   - setup the DRM framebuffer with the allocated memory
1828  */
1829 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1830 {
1831         const struct intel_device_info *match_info =
1832                 (struct intel_device_info *)ent->driver_data;
1833         struct drm_i915_private *dev_priv;
1834         int ret;
1835
1836         dev_priv = i915_driver_create(pdev, ent);
1837         if (IS_ERR(dev_priv))
1838                 return PTR_ERR(dev_priv);
1839
1840         /* Disable nuclear pageflip by default on pre-ILK */
1841         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1842                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1843
1844         ret = pci_enable_device(pdev);
1845         if (ret)
1846                 goto out_fini;
1847
1848         ret = i915_driver_init_early(dev_priv);
1849         if (ret < 0)
1850                 goto out_pci_disable;
1851
1852         disable_rpm_wakeref_asserts(dev_priv);
1853
1854         ret = i915_driver_init_mmio(dev_priv);
1855         if (ret < 0)
1856                 goto out_runtime_pm_put;
1857
1858         ret = i915_driver_init_hw(dev_priv);
1859         if (ret < 0)
1860                 goto out_cleanup_mmio;
1861
1862         ret = i915_load_modeset_init(&dev_priv->drm);
1863         if (ret < 0)
1864                 goto out_cleanup_hw;
1865
1866         i915_driver_register(dev_priv);
1867
1868         enable_rpm_wakeref_asserts(dev_priv);
1869
1870         i915_welcome_messages(dev_priv);
1871
1872         return 0;
1873
1874 out_cleanup_hw:
1875         i915_driver_cleanup_hw(dev_priv);
1876 out_cleanup_mmio:
1877         i915_driver_cleanup_mmio(dev_priv);
1878 out_runtime_pm_put:
1879         enable_rpm_wakeref_asserts(dev_priv);
1880         i915_driver_cleanup_early(dev_priv);
1881 out_pci_disable:
1882         pci_disable_device(pdev);
1883 out_fini:
1884         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1885         i915_driver_destroy(dev_priv);
1886         return ret;
1887 }
1888
1889 void i915_driver_unload(struct drm_device *dev)
1890 {
1891         struct drm_i915_private *dev_priv = to_i915(dev);
1892         struct pci_dev *pdev = dev_priv->drm.pdev;
1893
1894         disable_rpm_wakeref_asserts(dev_priv);
1895
1896         i915_driver_unregister(dev_priv);
1897
1898         /* Flush any external code that still may be under the RCU lock */
1899         synchronize_rcu();
1900
1901         i915_gem_suspend(dev_priv);
1902
1903         drm_atomic_helper_shutdown(dev);
1904
1905         intel_gvt_cleanup(dev_priv);
1906
1907         intel_modeset_cleanup(dev);
1908
1909         intel_bios_cleanup(dev_priv);
1910
1911         vga_switcheroo_unregister_client(pdev);
1912         vga_client_register(pdev, NULL, NULL, NULL);
1913
1914         intel_csr_ucode_fini(dev_priv);
1915
1916         /* Free error state after interrupts are fully disabled. */
1917         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1918         i915_reset_error_state(dev_priv);
1919
1920         i915_gem_fini(dev_priv);
1921
1922         intel_power_domains_fini_hw(dev_priv);
1923
1924         i915_driver_cleanup_hw(dev_priv);
1925         i915_driver_cleanup_mmio(dev_priv);
1926
1927         enable_rpm_wakeref_asserts(dev_priv);
1928         intel_runtime_pm_cleanup(dev_priv);
1929 }
1930
1931 static void i915_driver_release(struct drm_device *dev)
1932 {
1933         struct drm_i915_private *dev_priv = to_i915(dev);
1934
1935         i915_driver_cleanup_early(dev_priv);
1936         i915_driver_destroy(dev_priv);
1937 }
1938
1939 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1940 {
1941         struct drm_i915_private *i915 = to_i915(dev);
1942         int ret;
1943
1944         ret = i915_gem_open(i915, file);
1945         if (ret)
1946                 return ret;
1947
1948         return 0;
1949 }
1950
1951 /**
1952  * i915_driver_lastclose - clean up after all DRM clients have exited
1953  * @dev: DRM device
1954  *
1955  * Take care of cleaning up after all DRM clients have exited.  In the
1956  * mode setting case, we want to restore the kernel's initial mode (just
1957  * in case the last client left us in a bad state).
1958  *
1959  * Additionally, in the non-mode setting case, we'll tear down the GTT
1960  * and DMA structures, since the kernel won't be using them, and clea
1961  * up any GEM state.
1962  */
1963 static void i915_driver_lastclose(struct drm_device *dev)
1964 {
1965         intel_fbdev_restore_mode(dev);
1966         vga_switcheroo_process_delayed_switch();
1967 }
1968
1969 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1970 {
1971         struct drm_i915_file_private *file_priv = file->driver_priv;
1972
1973         mutex_lock(&dev->struct_mutex);
1974         i915_gem_context_close(file);
1975         i915_gem_release(dev, file);
1976         mutex_unlock(&dev->struct_mutex);
1977
1978         kfree(file_priv);
1979 }
1980
1981 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1982 {
1983         struct drm_device *dev = &dev_priv->drm;
1984         struct intel_encoder *encoder;
1985
1986         drm_modeset_lock_all(dev);
1987         for_each_intel_encoder(dev, encoder)
1988                 if (encoder->suspend)
1989                         encoder->suspend(encoder);
1990         drm_modeset_unlock_all(dev);
1991 }
1992
1993 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1994                               bool rpm_resume);
1995 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1996
1997 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1998 {
1999 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2000         if (acpi_target_system_state() < ACPI_STATE_S3)
2001                 return true;
2002 #endif
2003         return false;
2004 }
2005
2006 static int i915_drm_prepare(struct drm_device *dev)
2007 {
2008         struct drm_i915_private *i915 = to_i915(dev);
2009
2010         /*
2011          * NB intel_display_suspend() may issue new requests after we've
2012          * ostensibly marked the GPU as ready-to-sleep here. We need to
2013          * split out that work and pull it forward so that after point,
2014          * the GPU is not woken again.
2015          */
2016         i915_gem_suspend(i915);
2017
2018         return 0;
2019 }
2020
2021 static int i915_drm_suspend(struct drm_device *dev)
2022 {
2023         struct drm_i915_private *dev_priv = to_i915(dev);
2024         struct pci_dev *pdev = dev_priv->drm.pdev;
2025         pci_power_t opregion_target_state;
2026
2027         disable_rpm_wakeref_asserts(dev_priv);
2028
2029         /* We do a lot of poking in a lot of registers, make sure they work
2030          * properly. */
2031         intel_power_domains_disable(dev_priv);
2032
2033         drm_kms_helper_poll_disable(dev);
2034
2035         pci_save_state(pdev);
2036
2037         intel_display_suspend(dev);
2038
2039         intel_dp_mst_suspend(dev_priv);
2040
2041         intel_runtime_pm_disable_interrupts(dev_priv);
2042         intel_hpd_cancel_work(dev_priv);
2043
2044         intel_suspend_encoders(dev_priv);
2045
2046         intel_suspend_hw(dev_priv);
2047
2048         i915_gem_suspend_gtt_mappings(dev_priv);
2049
2050         i915_save_state(dev_priv);
2051
2052         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2053         intel_opregion_suspend(dev_priv, opregion_target_state);
2054
2055         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2056
2057         dev_priv->suspend_count++;
2058
2059         intel_csr_ucode_suspend(dev_priv);
2060
2061         enable_rpm_wakeref_asserts(dev_priv);
2062
2063         return 0;
2064 }
2065
2066 static enum i915_drm_suspend_mode
2067 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2068 {
2069         if (hibernate)
2070                 return I915_DRM_SUSPEND_HIBERNATE;
2071
2072         if (suspend_to_idle(dev_priv))
2073                 return I915_DRM_SUSPEND_IDLE;
2074
2075         return I915_DRM_SUSPEND_MEM;
2076 }
2077
2078 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2079 {
2080         struct drm_i915_private *dev_priv = to_i915(dev);
2081         struct pci_dev *pdev = dev_priv->drm.pdev;
2082         int ret;
2083
2084         disable_rpm_wakeref_asserts(dev_priv);
2085
2086         i915_gem_suspend_late(dev_priv);
2087
2088         intel_uncore_suspend(&dev_priv->uncore);
2089
2090         intel_power_domains_suspend(dev_priv,
2091                                     get_suspend_mode(dev_priv, hibernation));
2092
2093         ret = 0;
2094         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2095                 bxt_enable_dc9(dev_priv);
2096         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2097                 hsw_enable_pc8(dev_priv);
2098         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2099                 ret = vlv_suspend_complete(dev_priv);
2100
2101         if (ret) {
2102                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2103                 intel_power_domains_resume(dev_priv);
2104
2105                 goto out;
2106         }
2107
2108         pci_disable_device(pdev);
2109         /*
2110          * During hibernation on some platforms the BIOS may try to access
2111          * the device even though it's already in D3 and hang the machine. So
2112          * leave the device in D0 on those platforms and hope the BIOS will
2113          * power down the device properly. The issue was seen on multiple old
2114          * GENs with different BIOS vendors, so having an explicit blacklist
2115          * is inpractical; apply the workaround on everything pre GEN6. The
2116          * platforms where the issue was seen:
2117          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2118          * Fujitsu FSC S7110
2119          * Acer Aspire 1830T
2120          */
2121         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2122                 pci_set_power_state(pdev, PCI_D3hot);
2123
2124 out:
2125         enable_rpm_wakeref_asserts(dev_priv);
2126         if (!dev_priv->uncore.user_forcewake.count)
2127                 intel_runtime_pm_cleanup(dev_priv);
2128
2129         return ret;
2130 }
2131
2132 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2133 {
2134         int error;
2135
2136         if (!dev) {
2137                 DRM_ERROR("dev: %p\n", dev);
2138                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2139                 return -ENODEV;
2140         }
2141
2142         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2143                          state.event != PM_EVENT_FREEZE))
2144                 return -EINVAL;
2145
2146         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2147                 return 0;
2148
2149         error = i915_drm_suspend(dev);
2150         if (error)
2151                 return error;
2152
2153         return i915_drm_suspend_late(dev, false);
2154 }
2155
2156 static int i915_drm_resume(struct drm_device *dev)
2157 {
2158         struct drm_i915_private *dev_priv = to_i915(dev);
2159         int ret;
2160
2161         disable_rpm_wakeref_asserts(dev_priv);
2162         intel_sanitize_gt_powersave(dev_priv);
2163
2164         i915_gem_sanitize(dev_priv);
2165
2166         ret = i915_ggtt_enable_hw(dev_priv);
2167         if (ret)
2168                 DRM_ERROR("failed to re-enable GGTT\n");
2169
2170         intel_csr_ucode_resume(dev_priv);
2171
2172         i915_restore_state(dev_priv);
2173         intel_pps_unlock_regs_wa(dev_priv);
2174
2175         intel_init_pch_refclk(dev_priv);
2176
2177         /*
2178          * Interrupts have to be enabled before any batches are run. If not the
2179          * GPU will hang. i915_gem_init_hw() will initiate batches to
2180          * update/restore the context.
2181          *
2182          * drm_mode_config_reset() needs AUX interrupts.
2183          *
2184          * Modeset enabling in intel_modeset_init_hw() also needs working
2185          * interrupts.
2186          */
2187         intel_runtime_pm_enable_interrupts(dev_priv);
2188
2189         drm_mode_config_reset(dev);
2190
2191         i915_gem_resume(dev_priv);
2192
2193         intel_modeset_init_hw(dev);
2194         intel_init_clock_gating(dev_priv);
2195
2196         spin_lock_irq(&dev_priv->irq_lock);
2197         if (dev_priv->display.hpd_irq_setup)
2198                 dev_priv->display.hpd_irq_setup(dev_priv);
2199         spin_unlock_irq(&dev_priv->irq_lock);
2200
2201         intel_dp_mst_resume(dev_priv);
2202
2203         intel_display_resume(dev);
2204
2205         drm_kms_helper_poll_enable(dev);
2206
2207         /*
2208          * ... but also need to make sure that hotplug processing
2209          * doesn't cause havoc. Like in the driver load code we don't
2210          * bother with the tiny race here where we might lose hotplug
2211          * notifications.
2212          * */
2213         intel_hpd_init(dev_priv);
2214
2215         intel_opregion_resume(dev_priv);
2216
2217         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2218
2219         intel_power_domains_enable(dev_priv);
2220
2221         enable_rpm_wakeref_asserts(dev_priv);
2222
2223         return 0;
2224 }
2225
2226 static int i915_drm_resume_early(struct drm_device *dev)
2227 {
2228         struct drm_i915_private *dev_priv = to_i915(dev);
2229         struct pci_dev *pdev = dev_priv->drm.pdev;
2230         int ret;
2231
2232         /*
2233          * We have a resume ordering issue with the snd-hda driver also
2234          * requiring our device to be power up. Due to the lack of a
2235          * parent/child relationship we currently solve this with an early
2236          * resume hook.
2237          *
2238          * FIXME: This should be solved with a special hdmi sink device or
2239          * similar so that power domains can be employed.
2240          */
2241
2242         /*
2243          * Note that we need to set the power state explicitly, since we
2244          * powered off the device during freeze and the PCI core won't power
2245          * it back up for us during thaw. Powering off the device during
2246          * freeze is not a hard requirement though, and during the
2247          * suspend/resume phases the PCI core makes sure we get here with the
2248          * device powered on. So in case we change our freeze logic and keep
2249          * the device powered we can also remove the following set power state
2250          * call.
2251          */
2252         ret = pci_set_power_state(pdev, PCI_D0);
2253         if (ret) {
2254                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2255                 return ret;
2256         }
2257
2258         /*
2259          * Note that pci_enable_device() first enables any parent bridge
2260          * device and only then sets the power state for this device. The
2261          * bridge enabling is a nop though, since bridge devices are resumed
2262          * first. The order of enabling power and enabling the device is
2263          * imposed by the PCI core as described above, so here we preserve the
2264          * same order for the freeze/thaw phases.
2265          *
2266          * TODO: eventually we should remove pci_disable_device() /
2267          * pci_enable_enable_device() from suspend/resume. Due to how they
2268          * depend on the device enable refcount we can't anyway depend on them
2269          * disabling/enabling the device.
2270          */
2271         if (pci_enable_device(pdev))
2272                 return -EIO;
2273
2274         pci_set_master(pdev);
2275
2276         disable_rpm_wakeref_asserts(dev_priv);
2277
2278         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2279                 ret = vlv_resume_prepare(dev_priv, false);
2280         if (ret)
2281                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2282                           ret);
2283
2284         intel_uncore_resume_early(&dev_priv->uncore);
2285
2286         i915_check_and_clear_faults(dev_priv);
2287
2288         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2289                 gen9_sanitize_dc_state(dev_priv);
2290                 bxt_disable_dc9(dev_priv);
2291         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2292                 hsw_disable_pc8(dev_priv);
2293         }
2294
2295         intel_uncore_sanitize(dev_priv);
2296
2297         intel_power_domains_resume(dev_priv);
2298
2299         intel_engines_sanitize(dev_priv, true);
2300
2301         enable_rpm_wakeref_asserts(dev_priv);
2302
2303         return ret;
2304 }
2305
2306 static int i915_resume_switcheroo(struct drm_device *dev)
2307 {
2308         int ret;
2309
2310         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2311                 return 0;
2312
2313         ret = i915_drm_resume_early(dev);
2314         if (ret)
2315                 return ret;
2316
2317         return i915_drm_resume(dev);
2318 }
2319
2320 static int i915_pm_prepare(struct device *kdev)
2321 {
2322         struct pci_dev *pdev = to_pci_dev(kdev);
2323         struct drm_device *dev = pci_get_drvdata(pdev);
2324
2325         if (!dev) {
2326                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2327                 return -ENODEV;
2328         }
2329
2330         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2331                 return 0;
2332
2333         return i915_drm_prepare(dev);
2334 }
2335
2336 static int i915_pm_suspend(struct device *kdev)
2337 {
2338         struct pci_dev *pdev = to_pci_dev(kdev);
2339         struct drm_device *dev = pci_get_drvdata(pdev);
2340
2341         if (!dev) {
2342                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2343                 return -ENODEV;
2344         }
2345
2346         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2347                 return 0;
2348
2349         return i915_drm_suspend(dev);
2350 }
2351
2352 static int i915_pm_suspend_late(struct device *kdev)
2353 {
2354         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2355
2356         /*
2357          * We have a suspend ordering issue with the snd-hda driver also
2358          * requiring our device to be power up. Due to the lack of a
2359          * parent/child relationship we currently solve this with an late
2360          * suspend hook.
2361          *
2362          * FIXME: This should be solved with a special hdmi sink device or
2363          * similar so that power domains can be employed.
2364          */
2365         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2366                 return 0;
2367
2368         return i915_drm_suspend_late(dev, false);
2369 }
2370
2371 static int i915_pm_poweroff_late(struct device *kdev)
2372 {
2373         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2374
2375         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2376                 return 0;
2377
2378         return i915_drm_suspend_late(dev, true);
2379 }
2380
2381 static int i915_pm_resume_early(struct device *kdev)
2382 {
2383         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2384
2385         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2386                 return 0;
2387
2388         return i915_drm_resume_early(dev);
2389 }
2390
2391 static int i915_pm_resume(struct device *kdev)
2392 {
2393         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2394
2395         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2396                 return 0;
2397
2398         return i915_drm_resume(dev);
2399 }
2400
2401 /* freeze: before creating the hibernation_image */
2402 static int i915_pm_freeze(struct device *kdev)
2403 {
2404         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2405         int ret;
2406
2407         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2408                 ret = i915_drm_suspend(dev);
2409                 if (ret)
2410                         return ret;
2411         }
2412
2413         ret = i915_gem_freeze(kdev_to_i915(kdev));
2414         if (ret)
2415                 return ret;
2416
2417         return 0;
2418 }
2419
2420 static int i915_pm_freeze_late(struct device *kdev)
2421 {
2422         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2423         int ret;
2424
2425         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2426                 ret = i915_drm_suspend_late(dev, true);
2427                 if (ret)
2428                         return ret;
2429         }
2430
2431         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2432         if (ret)
2433                 return ret;
2434
2435         return 0;
2436 }
2437
2438 /* thaw: called after creating the hibernation image, but before turning off. */
2439 static int i915_pm_thaw_early(struct device *kdev)
2440 {
2441         return i915_pm_resume_early(kdev);
2442 }
2443
2444 static int i915_pm_thaw(struct device *kdev)
2445 {
2446         return i915_pm_resume(kdev);
2447 }
2448
2449 /* restore: called after loading the hibernation image. */
2450 static int i915_pm_restore_early(struct device *kdev)
2451 {
2452         return i915_pm_resume_early(kdev);
2453 }
2454
2455 static int i915_pm_restore(struct device *kdev)
2456 {
2457         return i915_pm_resume(kdev);
2458 }
2459
2460 /*
2461  * Save all Gunit registers that may be lost after a D3 and a subsequent
2462  * S0i[R123] transition. The list of registers needing a save/restore is
2463  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2464  * registers in the following way:
2465  * - Driver: saved/restored by the driver
2466  * - Punit : saved/restored by the Punit firmware
2467  * - No, w/o marking: no need to save/restore, since the register is R/O or
2468  *                    used internally by the HW in a way that doesn't depend
2469  *                    keeping the content across a suspend/resume.
2470  * - Debug : used for debugging
2471  *
2472  * We save/restore all registers marked with 'Driver', with the following
2473  * exceptions:
2474  * - Registers out of use, including also registers marked with 'Debug'.
2475  *   These have no effect on the driver's operation, so we don't save/restore
2476  *   them to reduce the overhead.
2477  * - Registers that are fully setup by an initialization function called from
2478  *   the resume path. For example many clock gating and RPS/RC6 registers.
2479  * - Registers that provide the right functionality with their reset defaults.
2480  *
2481  * TODO: Except for registers that based on the above 3 criteria can be safely
2482  * ignored, we save/restore all others, practically treating the HW context as
2483  * a black-box for the driver. Further investigation is needed to reduce the
2484  * saved/restored registers even further, by following the same 3 criteria.
2485  */
2486 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2487 {
2488         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2489         int i;
2490
2491         /* GAM 0x4000-0x4770 */
2492         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2493         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2494         s->arb_mode             = I915_READ(ARB_MODE);
2495         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2496         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2497
2498         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2499                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2500
2501         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2502         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2503
2504         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2505         s->ecochk               = I915_READ(GAM_ECOCHK);
2506         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2507         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2508
2509         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2510
2511         /* MBC 0x9024-0x91D0, 0x8500 */
2512         s->g3dctl               = I915_READ(VLV_G3DCTL);
2513         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2514         s->mbctl                = I915_READ(GEN6_MBCTL);
2515
2516         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2517         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2518         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2519         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2520         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2521         s->rstctl               = I915_READ(GEN6_RSTCTL);
2522         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2523
2524         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2525         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2526         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2527         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2528         s->ecobus               = I915_READ(ECOBUS);
2529         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2530         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2531         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2532         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2533         s->rcedata              = I915_READ(VLV_RCEDATA);
2534         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2535
2536         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2537         s->gt_imr               = I915_READ(GTIMR);
2538         s->gt_ier               = I915_READ(GTIER);
2539         s->pm_imr               = I915_READ(GEN6_PMIMR);
2540         s->pm_ier               = I915_READ(GEN6_PMIER);
2541
2542         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2543                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2544
2545         /* GT SA CZ domain, 0x100000-0x138124 */
2546         s->tilectl              = I915_READ(TILECTL);
2547         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2548         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2549         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2550         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2551
2552         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2553         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2554         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2555         s->pcbr                 = I915_READ(VLV_PCBR);
2556         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2557
2558         /*
2559          * Not saving any of:
2560          * DFT,         0x9800-0x9EC0
2561          * SARB,        0xB000-0xB1FC
2562          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2563          * PCI CFG
2564          */
2565 }
2566
2567 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2568 {
2569         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2570         u32 val;
2571         int i;
2572
2573         /* GAM 0x4000-0x4770 */
2574         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2575         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2576         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2577         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2578         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2579
2580         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2581                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2582
2583         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2584         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2585
2586         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2587         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2588         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2589         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2590
2591         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2592
2593         /* MBC 0x9024-0x91D0, 0x8500 */
2594         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2595         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2596         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2597
2598         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2599         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2600         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2601         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2602         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2603         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2604         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2605
2606         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2607         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2608         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2609         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2610         I915_WRITE(ECOBUS,              s->ecobus);
2611         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2612         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2613         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2614         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2615         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2616         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2617
2618         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2619         I915_WRITE(GTIMR,               s->gt_imr);
2620         I915_WRITE(GTIER,               s->gt_ier);
2621         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2622         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2623
2624         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2625                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2626
2627         /* GT SA CZ domain, 0x100000-0x138124 */
2628         I915_WRITE(TILECTL,                     s->tilectl);
2629         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2630         /*
2631          * Preserve the GT allow wake and GFX force clock bit, they are not
2632          * be restored, as they are used to control the s0ix suspend/resume
2633          * sequence by the caller.
2634          */
2635         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2636         val &= VLV_GTLC_ALLOWWAKEREQ;
2637         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2638         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2639
2640         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2641         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2642         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2643         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2644
2645         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2646
2647         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2648         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2649         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2650         I915_WRITE(VLV_PCBR,                    s->pcbr);
2651         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2652 }
2653
2654 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2655                                   u32 mask, u32 val)
2656 {
2657         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2658         u32 reg_value;
2659         int ret;
2660
2661         /* The HW does not like us polling for PW_STATUS frequently, so
2662          * use the sleeping loop rather than risk the busy spin within
2663          * intel_wait_for_register().
2664          *
2665          * Transitioning between RC6 states should be at most 2ms (see
2666          * valleyview_enable_rps) so use a 3ms timeout.
2667          */
2668         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2669
2670         /* just trace the final value */
2671         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2672
2673         return ret;
2674 }
2675
2676 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2677 {
2678         u32 val;
2679         int err;
2680
2681         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2682         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2683         if (force_on)
2684                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2685         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2686
2687         if (!force_on)
2688                 return 0;
2689
2690         err = intel_wait_for_register(dev_priv,
2691                                       VLV_GTLC_SURVIVABILITY_REG,
2692                                       VLV_GFX_CLK_STATUS_BIT,
2693                                       VLV_GFX_CLK_STATUS_BIT,
2694                                       20);
2695         if (err)
2696                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2697                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2698
2699         return err;
2700 }
2701
2702 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2703 {
2704         u32 mask;
2705         u32 val;
2706         int err;
2707
2708         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2709         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2710         if (allow)
2711                 val |= VLV_GTLC_ALLOWWAKEREQ;
2712         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2713         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2714
2715         mask = VLV_GTLC_ALLOWWAKEACK;
2716         val = allow ? mask : 0;
2717
2718         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2719         if (err)
2720                 DRM_ERROR("timeout disabling GT waking\n");
2721
2722         return err;
2723 }
2724
2725 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2726                                   bool wait_for_on)
2727 {
2728         u32 mask;
2729         u32 val;
2730
2731         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2732         val = wait_for_on ? mask : 0;
2733
2734         /*
2735          * RC6 transitioning can be delayed up to 2 msec (see
2736          * valleyview_enable_rps), use 3 msec for safety.
2737          *
2738          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2739          * reset and we are trying to force the machine to sleep.
2740          */
2741         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2742                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2743                                  onoff(wait_for_on));
2744 }
2745
2746 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2747 {
2748         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2749                 return;
2750
2751         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2752         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2753 }
2754
2755 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2756 {
2757         u32 mask;
2758         int err;
2759
2760         /*
2761          * Bspec defines the following GT well on flags as debug only, so
2762          * don't treat them as hard failures.
2763          */
2764         vlv_wait_for_gt_wells(dev_priv, false);
2765
2766         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2767         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2768
2769         vlv_check_no_gt_access(dev_priv);
2770
2771         err = vlv_force_gfx_clock(dev_priv, true);
2772         if (err)
2773                 goto err1;
2774
2775         err = vlv_allow_gt_wake(dev_priv, false);
2776         if (err)
2777                 goto err2;
2778
2779         if (!IS_CHERRYVIEW(dev_priv))
2780                 vlv_save_gunit_s0ix_state(dev_priv);
2781
2782         err = vlv_force_gfx_clock(dev_priv, false);
2783         if (err)
2784                 goto err2;
2785
2786         return 0;
2787
2788 err2:
2789         /* For safety always re-enable waking and disable gfx clock forcing */
2790         vlv_allow_gt_wake(dev_priv, true);
2791 err1:
2792         vlv_force_gfx_clock(dev_priv, false);
2793
2794         return err;
2795 }
2796
2797 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2798                                 bool rpm_resume)
2799 {
2800         int err;
2801         int ret;
2802
2803         /*
2804          * If any of the steps fail just try to continue, that's the best we
2805          * can do at this point. Return the first error code (which will also
2806          * leave RPM permanently disabled).
2807          */
2808         ret = vlv_force_gfx_clock(dev_priv, true);
2809
2810         if (!IS_CHERRYVIEW(dev_priv))
2811                 vlv_restore_gunit_s0ix_state(dev_priv);
2812
2813         err = vlv_allow_gt_wake(dev_priv, true);
2814         if (!ret)
2815                 ret = err;
2816
2817         err = vlv_force_gfx_clock(dev_priv, false);
2818         if (!ret)
2819                 ret = err;
2820
2821         vlv_check_no_gt_access(dev_priv);
2822
2823         if (rpm_resume)
2824                 intel_init_clock_gating(dev_priv);
2825
2826         return ret;
2827 }
2828
2829 static int intel_runtime_suspend(struct device *kdev)
2830 {
2831         struct pci_dev *pdev = to_pci_dev(kdev);
2832         struct drm_device *dev = pci_get_drvdata(pdev);
2833         struct drm_i915_private *dev_priv = to_i915(dev);
2834         int ret;
2835
2836         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2837                 return -ENODEV;
2838
2839         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2840                 return -ENODEV;
2841
2842         DRM_DEBUG_KMS("Suspending device\n");
2843
2844         disable_rpm_wakeref_asserts(dev_priv);
2845
2846         /*
2847          * We are safe here against re-faults, since the fault handler takes
2848          * an RPM reference.
2849          */
2850         i915_gem_runtime_suspend(dev_priv);
2851
2852         intel_uc_suspend(dev_priv);
2853
2854         intel_runtime_pm_disable_interrupts(dev_priv);
2855
2856         intel_uncore_suspend(&dev_priv->uncore);
2857
2858         ret = 0;
2859         if (INTEL_GEN(dev_priv) >= 11) {
2860                 icl_display_core_uninit(dev_priv);
2861                 bxt_enable_dc9(dev_priv);
2862         } else if (IS_GEN9_LP(dev_priv)) {
2863                 bxt_display_core_uninit(dev_priv);
2864                 bxt_enable_dc9(dev_priv);
2865         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2866                 hsw_enable_pc8(dev_priv);
2867         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2868                 ret = vlv_suspend_complete(dev_priv);
2869         }
2870
2871         if (ret) {
2872                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2873                 intel_uncore_runtime_resume(&dev_priv->uncore);
2874
2875                 intel_runtime_pm_enable_interrupts(dev_priv);
2876
2877                 intel_uc_resume(dev_priv);
2878
2879                 i915_gem_init_swizzling(dev_priv);
2880                 i915_gem_restore_fences(dev_priv);
2881
2882                 enable_rpm_wakeref_asserts(dev_priv);
2883
2884                 return ret;
2885         }
2886
2887         enable_rpm_wakeref_asserts(dev_priv);
2888         intel_runtime_pm_cleanup(dev_priv);
2889
2890         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2891                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2892
2893         dev_priv->runtime_pm.suspended = true;
2894
2895         /*
2896          * FIXME: We really should find a document that references the arguments
2897          * used below!
2898          */
2899         if (IS_BROADWELL(dev_priv)) {
2900                 /*
2901                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2902                  * being detected, and the call we do at intel_runtime_resume()
2903                  * won't be able to restore them. Since PCI_D3hot matches the
2904                  * actual specification and appears to be working, use it.
2905                  */
2906                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2907         } else {
2908                 /*
2909                  * current versions of firmware which depend on this opregion
2910                  * notification have repurposed the D1 definition to mean
2911                  * "runtime suspended" vs. what you would normally expect (D3)
2912                  * to distinguish it from notifications that might be sent via
2913                  * the suspend path.
2914                  */
2915                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2916         }
2917
2918         assert_forcewakes_inactive(&dev_priv->uncore);
2919
2920         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2921                 intel_hpd_poll_init(dev_priv);
2922
2923         DRM_DEBUG_KMS("Device suspended\n");
2924         return 0;
2925 }
2926
2927 static int intel_runtime_resume(struct device *kdev)
2928 {
2929         struct pci_dev *pdev = to_pci_dev(kdev);
2930         struct drm_device *dev = pci_get_drvdata(pdev);
2931         struct drm_i915_private *dev_priv = to_i915(dev);
2932         int ret = 0;
2933
2934         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2935                 return -ENODEV;
2936
2937         DRM_DEBUG_KMS("Resuming device\n");
2938
2939         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2940         disable_rpm_wakeref_asserts(dev_priv);
2941
2942         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2943         dev_priv->runtime_pm.suspended = false;
2944         if (intel_uncore_unclaimed_mmio(dev_priv))
2945                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2946
2947         if (INTEL_GEN(dev_priv) >= 11) {
2948                 bxt_disable_dc9(dev_priv);
2949                 icl_display_core_init(dev_priv, true);
2950                 if (dev_priv->csr.dmc_payload) {
2951                         if (dev_priv->csr.allowed_dc_mask &
2952                             DC_STATE_EN_UPTO_DC6)
2953                                 skl_enable_dc6(dev_priv);
2954                         else if (dev_priv->csr.allowed_dc_mask &
2955                                  DC_STATE_EN_UPTO_DC5)
2956                                 gen9_enable_dc5(dev_priv);
2957                 }
2958         } else if (IS_GEN9_LP(dev_priv)) {
2959                 bxt_disable_dc9(dev_priv);
2960                 bxt_display_core_init(dev_priv, true);
2961                 if (dev_priv->csr.dmc_payload &&
2962                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2963                         gen9_enable_dc5(dev_priv);
2964         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2965                 hsw_disable_pc8(dev_priv);
2966         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2967                 ret = vlv_resume_prepare(dev_priv, true);
2968         }
2969
2970         intel_uncore_runtime_resume(&dev_priv->uncore);
2971
2972         intel_runtime_pm_enable_interrupts(dev_priv);
2973
2974         intel_uc_resume(dev_priv);
2975
2976         /*
2977          * No point of rolling back things in case of an error, as the best
2978          * we can do is to hope that things will still work (and disable RPM).
2979          */
2980         i915_gem_init_swizzling(dev_priv);
2981         i915_gem_restore_fences(dev_priv);
2982
2983         /*
2984          * On VLV/CHV display interrupts are part of the display
2985          * power well, so hpd is reinitialized from there. For
2986          * everyone else do it here.
2987          */
2988         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2989                 intel_hpd_init(dev_priv);
2990
2991         intel_enable_ipc(dev_priv);
2992
2993         enable_rpm_wakeref_asserts(dev_priv);
2994
2995         if (ret)
2996                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2997         else
2998                 DRM_DEBUG_KMS("Device resumed\n");
2999
3000         return ret;
3001 }
3002
3003 const struct dev_pm_ops i915_pm_ops = {
3004         /*
3005          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3006          * PMSG_RESUME]
3007          */
3008         .prepare = i915_pm_prepare,
3009         .suspend = i915_pm_suspend,
3010         .suspend_late = i915_pm_suspend_late,
3011         .resume_early = i915_pm_resume_early,
3012         .resume = i915_pm_resume,
3013
3014         /*
3015          * S4 event handlers
3016          * @freeze, @freeze_late    : called (1) before creating the
3017          *                            hibernation image [PMSG_FREEZE] and
3018          *                            (2) after rebooting, before restoring
3019          *                            the image [PMSG_QUIESCE]
3020          * @thaw, @thaw_early       : called (1) after creating the hibernation
3021          *                            image, before writing it [PMSG_THAW]
3022          *                            and (2) after failing to create or
3023          *                            restore the image [PMSG_RECOVER]
3024          * @poweroff, @poweroff_late: called after writing the hibernation
3025          *                            image, before rebooting [PMSG_HIBERNATE]
3026          * @restore, @restore_early : called after rebooting and restoring the
3027          *                            hibernation image [PMSG_RESTORE]
3028          */
3029         .freeze = i915_pm_freeze,
3030         .freeze_late = i915_pm_freeze_late,
3031         .thaw_early = i915_pm_thaw_early,
3032         .thaw = i915_pm_thaw,
3033         .poweroff = i915_pm_suspend,
3034         .poweroff_late = i915_pm_poweroff_late,
3035         .restore_early = i915_pm_restore_early,
3036         .restore = i915_pm_restore,
3037
3038         /* S0ix (via runtime suspend) event handlers */
3039         .runtime_suspend = intel_runtime_suspend,
3040         .runtime_resume = intel_runtime_resume,
3041 };
3042
3043 static const struct vm_operations_struct i915_gem_vm_ops = {
3044         .fault = i915_gem_fault,
3045         .open = drm_gem_vm_open,
3046         .close = drm_gem_vm_close,
3047 };
3048
3049 static const struct file_operations i915_driver_fops = {
3050         .owner = THIS_MODULE,
3051         .open = drm_open,
3052         .release = drm_release,
3053         .unlocked_ioctl = drm_ioctl,
3054         .mmap = drm_gem_mmap,
3055         .poll = drm_poll,
3056         .read = drm_read,
3057         .compat_ioctl = i915_compat_ioctl,
3058         .llseek = noop_llseek,
3059 };
3060
3061 static int
3062 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3063                           struct drm_file *file)
3064 {
3065         return -ENODEV;
3066 }
3067
3068 static const struct drm_ioctl_desc i915_ioctls[] = {
3069         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3070         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3071         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3072         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3073         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3074         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3075         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3076         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3077         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3078         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3079         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3080         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3081         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3082         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3083         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3084         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3085         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3086         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3087         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3088         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3089         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3090         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3091         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3092         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3093         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3094         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3095         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3096         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3097         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3098         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3099         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3100         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3101         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3102         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3103         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3104         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3105         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3106         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3107         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3108         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3109         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3110         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3111         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3112         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3113         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3114         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3115         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3116         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3117         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3118         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3119         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3120         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3121         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3122         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3123         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3124         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3125 };
3126
3127 static struct drm_driver driver = {
3128         /* Don't use MTRRs here; the Xserver or userspace app should
3129          * deal with them for Intel hardware.
3130          */
3131         .driver_features =
3132             DRIVER_GEM | DRIVER_PRIME |
3133             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3134         .release = i915_driver_release,
3135         .open = i915_driver_open,
3136         .lastclose = i915_driver_lastclose,
3137         .postclose = i915_driver_postclose,
3138
3139         .gem_close_object = i915_gem_close_object,
3140         .gem_free_object_unlocked = i915_gem_free_object,
3141         .gem_vm_ops = &i915_gem_vm_ops,
3142
3143         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3144         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3145         .gem_prime_export = i915_gem_prime_export,
3146         .gem_prime_import = i915_gem_prime_import,
3147
3148         .dumb_create = i915_gem_dumb_create,
3149         .dumb_map_offset = i915_gem_mmap_gtt,
3150         .ioctls = i915_ioctls,
3151         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3152         .fops = &i915_driver_fops,
3153         .name = DRIVER_NAME,
3154         .desc = DRIVER_DESC,
3155         .date = DRIVER_DATE,
3156         .major = DRIVER_MAJOR,
3157         .minor = DRIVER_MINOR,
3158         .patchlevel = DRIVER_PATCHLEVEL,
3159 };
3160
3161 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3162 #include "selftests/mock_drm.c"
3163 #endif