drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 i915_modparams.inject_load_failure = 0;
  71                 return true;
  72         }
  73
  74         return false;
  75 }
  76
  77 bool i915_error_injected(void)
  78 {
  79         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  80 }
  81
  82 #endif
  83
  84 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  85 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  86                     "providing the dmesg log by booting with drm.debug=0xf"
  87
  88 void
  89 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  90               const char *fmt, ...)
  91 {
  92         static bool shown_bug_once;
  93         struct device *kdev = dev_priv->drm.dev;
  94         bool is_error = level[1] <= KERN_ERR[1];
  95         bool is_debug = level[1] == KERN_DEBUG[1];
  96         struct va_format vaf;
  97         va_list args;
  98
  99         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 100                 return;
 101
 102         va_start(args, fmt);
 103
 104         vaf.fmt = fmt;
 105         vaf.va = &args;
 106
 107         if (is_error)
 108                 dev_printk(level, kdev, "%pV", &vaf);
 109         else
 110                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 111                            __builtin_return_address(0), &vaf);
 112
 113         va_end(args);
 114
 115         if (is_error && !shown_bug_once) {
 116                 /*
 117                  * Ask the user to file a bug report for the error, except
 118                  * if they may have caused the bug by fiddling with unsafe
 119                  * module parameters.
 120                  */
 121                 if (!test_taint(TAINT_USER))
 122                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 123                 shown_bug_once = true;
 124         }
 125 }
 126
 127 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 128 static enum intel_pch
 129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 130 {
 131         switch (id) {
 132         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 133                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 134                 WARN_ON(!IS_GEN5(dev_priv));
 135                 return PCH_IBX;
 136         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 137                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 138                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 139                 return PCH_CPT;
 140         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 141                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 142                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 143                 /* PantherPoint is CPT compatible */
 144                 return PCH_CPT;
 145         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 147                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 148                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 149                 return PCH_LPT;
 150         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 159                 /* WildcatPoint is LPT compatible */
 160                 return PCH_LPT;
 161         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 162                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 163                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 164                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 165                 /* WildcatPoint is LPT compatible */
 166                 return PCH_LPT;
 167         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 168                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 169                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 170                 return PCH_SPT;
 171         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 173                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 174                 return PCH_SPT;
 175         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 176                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 177                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 178                         !IS_COFFEELAKE(dev_priv));
 179                 return PCH_KBP;
 180         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 182                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 183                 return PCH_CNP;
 184         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 185                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 186                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 187                 return PCH_CNP;
 188         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 189                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 190                 WARN_ON(!IS_ICELAKE(dev_priv));
 191                 return PCH_ICP;
 192         default:
 193                 return PCH_NONE;
 194         }
 195 }
 196
 197 static bool intel_is_virt_pch(unsigned short id,
 198                               unsigned short svendor, unsigned short sdevice)
 199 {
 200         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 201                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 202                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 203                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 204                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 205 }
 206
 207 static unsigned short
 208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 209 {
 210         unsigned short id = 0;
 211
 212         /*
 213          * In a virtualized passthrough environment we can be in a
 214          * setup where the ISA bridge is not able to be passed through.
 215          * In this case, a south bridge can be emulated and we have to
 216          * make an educated guess as to which PCH is really there.
 217          */
 218
 219         if (IS_GEN5(dev_priv))
 220                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 221         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 222                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 223         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 224                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 225         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 226                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 227         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 228                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 229         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 231         else if (IS_ICELAKE(dev_priv))
 232                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 233
 234         if (id)
 235                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 236         else
 237                 DRM_DEBUG_KMS("Assuming no PCH\n");
 238
 239         return id;
 240 }
 241
 242 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 243 {
 244         struct pci_dev *pch = NULL;
 245
 246         /*
 247          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 248          * make graphics device passthrough work easy for VMM, that only
 249          * need to expose ISA bridge to let driver know the real hardware
 250          * underneath. This is a requirement from virtualization team.
 251          *
 252          * In some virtualized environments (e.g. XEN), there is irrelevant
 253          * ISA bridge in the system. To work reliably, we should scan trhough
 254          * all the ISA bridge devices and check for the first match, instead
 255          * of only checking the first one.
 256          */
 257         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 258                 unsigned short id;
 259                 enum intel_pch pch_type;
 260
 261                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 262                         continue;
 263
 264                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 265
 266                 pch_type = intel_pch_type(dev_priv, id);
 267                 if (pch_type != PCH_NONE) {
 268                         dev_priv->pch_type = pch_type;
 269                         dev_priv->pch_id = id;
 270                         break;
 271                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 272                                          pch->subsystem_device)) {
 273                         id = intel_virt_detect_pch(dev_priv);
 274                         pch_type = intel_pch_type(dev_priv, id);
 275
 276                         /* Sanity check virtual PCH id */
 277                         if (WARN_ON(id && pch_type == PCH_NONE))
 278                                 id = 0;
 279
 280                         dev_priv->pch_type = pch_type;
 281                         dev_priv->pch_id = id;
 282                         break;
 283                 }
 284         }
 285
 286         /*
 287          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 288          * display.
 289          */
 290         if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
 291                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 292                 dev_priv->pch_type = PCH_NOP;
 293                 dev_priv->pch_id = 0;
 294         }
 295
 296         if (!pch)
 297                 DRM_DEBUG_KMS("No PCH found.\n");
 298
 299         pci_dev_put(pch);
 300 }
 301
 302 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 303                                struct drm_file *file_priv)
 304 {
 305         struct drm_i915_private *dev_priv = to_i915(dev);
 306         struct pci_dev *pdev = dev_priv->drm.pdev;
 307         drm_i915_getparam_t *param = data;
 308         int value;
 309
 310         switch (param->param) {
 311         case I915_PARAM_IRQ_ACTIVE:
 312         case I915_PARAM_ALLOW_BATCHBUFFER:
 313         case I915_PARAM_LAST_DISPATCH:
 314         case I915_PARAM_HAS_EXEC_CONSTANTS:
 315                 /* Reject all old ums/dri params. */
 316                 return -ENODEV;
 317         case I915_PARAM_CHIPSET_ID:
 318                 value = pdev->device;
 319                 break;
 320         case I915_PARAM_REVISION:
 321                 value = pdev->revision;
 322                 break;
 323         case I915_PARAM_NUM_FENCES_AVAIL:
 324                 value = dev_priv->num_fence_regs;
 325                 break;
 326         case I915_PARAM_HAS_OVERLAY:
 327                 value = dev_priv->overlay ? 1 : 0;
 328                 break;
 329         case I915_PARAM_HAS_BSD:
 330                 value = !!dev_priv->engine[VCS];
 331                 break;
 332         case I915_PARAM_HAS_BLT:
 333                 value = !!dev_priv->engine[BCS];
 334                 break;
 335         case I915_PARAM_HAS_VEBOX:
 336                 value = !!dev_priv->engine[VECS];
 337                 break;
 338         case I915_PARAM_HAS_BSD2:
 339                 value = !!dev_priv->engine[VCS2];
 340                 break;
 341         case I915_PARAM_HAS_LLC:
 342                 value = HAS_LLC(dev_priv);
 343                 break;
 344         case I915_PARAM_HAS_WT:
 345                 value = HAS_WT(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_ALIASING_PPGTT:
 348                 value = USES_PPGTT(dev_priv);
 349                 break;
 350         case I915_PARAM_HAS_SEMAPHORES:
 351                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 352                 break;
 353         case I915_PARAM_HAS_SECURE_BATCHES:
 354                 value = capable(CAP_SYS_ADMIN);
 355                 break;
 356         case I915_PARAM_CMD_PARSER_VERSION:
 357                 value = i915_cmd_parser_get_version(dev_priv);
 358                 break;
 359         case I915_PARAM_SUBSLICE_TOTAL:
 360                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_EU_TOTAL:
 365                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 366                 if (!value)
 367                         return -ENODEV;
 368                 break;
 369         case I915_PARAM_HAS_GPU_RESET:
 370                 value = i915_modparams.enable_hangcheck &&
 371                         intel_has_gpu_reset(dev_priv);
 372                 if (value && intel_has_reset_engine(dev_priv))
 373                         value = 2;
 374                 break;
 375         case I915_PARAM_HAS_RESOURCE_STREAMER:
 376                 value = 0;
 377                 break;
 378         case I915_PARAM_HAS_POOLED_EU:
 379                 value = HAS_POOLED_EU(dev_priv);
 380                 break;
 381         case I915_PARAM_MIN_EU_IN_POOL:
 382                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 383                 break;
 384         case I915_PARAM_HUC_STATUS:
 385                 value = intel_huc_check_status(&dev_priv->huc);
 386                 if (value < 0)
 387                         return value;
 388                 break;
 389         case I915_PARAM_MMAP_GTT_VERSION:
 390                 /* Though we've started our numbering from 1, and so class all
 391                  * earlier versions as 0, in effect their value is undefined as
 392                  * the ioctl will report EINVAL for the unknown param!
 393                  */
 394                 value = i915_gem_mmap_gtt_version();
 395                 break;
 396         case I915_PARAM_HAS_SCHEDULER:
 397                 value = dev_priv->caps.scheduler;
 398                 break;
 399
 400         case I915_PARAM_MMAP_VERSION:
 401                 /* Remember to bump this if the version changes! */
 402         case I915_PARAM_HAS_GEM:
 403         case I915_PARAM_HAS_PAGEFLIPPING:
 404         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 405         case I915_PARAM_HAS_RELAXED_FENCING:
 406         case I915_PARAM_HAS_COHERENT_RINGS:
 407         case I915_PARAM_HAS_RELAXED_DELTA:
 408         case I915_PARAM_HAS_GEN7_SOL_RESET:
 409         case I915_PARAM_HAS_WAIT_TIMEOUT:
 410         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 411         case I915_PARAM_HAS_PINNED_BATCHES:
 412         case I915_PARAM_HAS_EXEC_NO_RELOC:
 413         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 414         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 415         case I915_PARAM_HAS_EXEC_SOFTPIN:
 416         case I915_PARAM_HAS_EXEC_ASYNC:
 417         case I915_PARAM_HAS_EXEC_FENCE:
 418         case I915_PARAM_HAS_EXEC_CAPTURE:
 419         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 420         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 421                 /* For the time being all of these are always true;
 422                  * if some supported hardware does not have one of these
 423                  * features this value needs to be provided from
 424                  * INTEL_INFO(), a feature macro, or similar.
 425                  */
 426                 value = 1;
 427                 break;
 428         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 429                 value = intel_engines_has_context_isolation(dev_priv);
 430                 break;
 431         case I915_PARAM_SLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_SUBSLICE_MASK:
 437                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 438                 if (!value)
 439                         return -ENODEV;
 440                 break;
 441         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 442                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 443                 break;
 444         case I915_PARAM_MMAP_GTT_COHERENT:
 445                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 446                 break;
 447         default:
 448                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 449                 return -EINVAL;
 450         }
 451
 452         if (put_user(value, param->value))
 453                 return -EFAULT;
 454
 455         return 0;
 456 }
 457
 458 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 459 {
 460         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 461
 462         dev_priv->bridge_dev =
 463                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 464         if (!dev_priv->bridge_dev) {
 465                 DRM_ERROR("bridge device not found\n");
 466                 return -1;
 467         }
 468         return 0;
 469 }
 470
 471 /* Allocate space for the MCH regs if needed, return nonzero on error */
 472 static int
 473 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 474 {
 475         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 476         u32 temp_lo, temp_hi = 0;
 477         u64 mchbar_addr;
 478         int ret;
 479
 480         if (INTEL_GEN(dev_priv) >= 4)
 481                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 482         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 483         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 484
 485         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 486 #ifdef CONFIG_PNP
 487         if (mchbar_addr &&
 488             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 489                 return 0;
 490 #endif
 491
 492         /* Get some space for it */
 493         dev_priv->mch_res.name = "i915 MCHBAR";
 494         dev_priv->mch_res.flags = IORESOURCE_MEM;
 495         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 496                                      &dev_priv->mch_res,
 497                                      MCHBAR_SIZE, MCHBAR_SIZE,
 498                                      PCIBIOS_MIN_MEM,
 499                                      0, pcibios_align_resource,
 500                                      dev_priv->bridge_dev);
 501         if (ret) {
 502                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 503                 dev_priv->mch_res.start = 0;
 504                 return ret;
 505         }
 506
 507         if (INTEL_GEN(dev_priv) >= 4)
 508                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 509                                        upper_32_bits(dev_priv->mch_res.start));
 510
 511         pci_write_config_dword(dev_priv->bridge_dev, reg,
 512                                lower_32_bits(dev_priv->mch_res.start));
 513         return 0;
 514 }
 515
 516 /* Setup MCHBAR if possible, return true if we should disable it again */
 517 static void
 518 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 519 {
 520         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 521         u32 temp;
 522         bool enabled;
 523
 524         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 525                 return;
 526
 527         dev_priv->mchbar_need_disable = false;
 528
 529         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 530                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 531                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 532         } else {
 533                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 534                 enabled = temp & 1;
 535         }
 536
 537         /* If it's already enabled, don't have to do anything */
 538         if (enabled)
 539                 return;
 540
 541         if (intel_alloc_mchbar_resource(dev_priv))
 542                 return;
 543
 544         dev_priv->mchbar_need_disable = true;
 545
 546         /* Space is allocated or reserved, so enable it. */
 547         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 548                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 549                                        temp | DEVEN_MCHBAR_EN);
 550         } else {
 551                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 552                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 553         }
 554 }
 555
 556 static void
 557 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 558 {
 559         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 560
 561         if (dev_priv->mchbar_need_disable) {
 562                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 563                         u32 deven_val;
 564
 565                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 566                                               &deven_val);
 567                         deven_val &= ~DEVEN_MCHBAR_EN;
 568                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 569                                                deven_val);
 570                 } else {
 571                         u32 mchbar_val;
 572
 573                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 574                                               &mchbar_val);
 575                         mchbar_val &= ~1;
 576                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 577                                                mchbar_val);
 578                 }
 579         }
 580
 581         if (dev_priv->mch_res.start)
 582                 release_resource(&dev_priv->mch_res);
 583 }
 584
 585 /* true = enable decode, false = disable decoder */
 586 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 587 {
 588         struct drm_i915_private *dev_priv = cookie;
 589
 590         intel_modeset_vga_set_state(dev_priv, state);
 591         if (state)
 592                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 593                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 594         else
 595                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 596 }
 597
 598 static int i915_resume_switcheroo(struct drm_device *dev);
 599 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 600
 601 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 602 {
 603         struct drm_device *dev = pci_get_drvdata(pdev);
 604         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 605
 606         if (state == VGA_SWITCHEROO_ON) {
 607                 pr_info("switched on\n");
 608                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 609                 /* i915 resume handler doesn't set to D0 */
 610                 pci_set_power_state(pdev, PCI_D0);
 611                 i915_resume_switcheroo(dev);
 612                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 613         } else {
 614                 pr_info("switched off\n");
 615                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 616                 i915_suspend_switcheroo(dev, pmm);
 617                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 618         }
 619 }
 620
 621 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 622 {
 623         struct drm_device *dev = pci_get_drvdata(pdev);
 624
 625         /*
 626          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 627          * locking inversion with the driver load path. And the access here is
 628          * completely racy anyway. So don't bother with locking for now.
 629          */
 630         return dev->open_count == 0;
 631 }
 632
 633 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 634         .set_gpu_state = i915_switcheroo_set_state,
 635         .reprobe = NULL,
 636         .can_switch = i915_switcheroo_can_switch,
 637 };
 638
 639 static int i915_load_modeset_init(struct drm_device *dev)
 640 {
 641         struct drm_i915_private *dev_priv = to_i915(dev);
 642         struct pci_dev *pdev = dev_priv->drm.pdev;
 643         int ret;
 644
 645         if (i915_inject_load_failure())
 646                 return -ENODEV;
 647
 648         intel_bios_init(dev_priv);
 649
 650         /* If we have > 1 VGA cards, then we need to arbitrate access
 651          * to the common VGA resources.
 652          *
 653          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 654          * then we do not take part in VGA arbitration and the
 655          * vga_client_register() fails with -ENODEV.
 656          */
 657         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 658         if (ret && ret != -ENODEV)
 659                 goto out;
 660
 661         intel_register_dsm_handler();
 662
 663         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 664         if (ret)
 665                 goto cleanup_vga_client;
 666
 667         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 668         intel_update_rawclk(dev_priv);
 669
 670         intel_power_domains_init_hw(dev_priv, false);
 671
 672         intel_csr_ucode_init(dev_priv);
 673
 674         ret = intel_irq_install(dev_priv);
 675         if (ret)
 676                 goto cleanup_csr;
 677
 678         intel_setup_gmbus(dev_priv);
 679
 680         /* Important: The output setup functions called by modeset_init need
 681          * working irqs for e.g. gmbus and dp aux transfers. */
 682         ret = intel_modeset_init(dev);
 683         if (ret)
 684                 goto cleanup_irq;
 685
 686         ret = i915_gem_init(dev_priv);
 687         if (ret)
 688                 goto cleanup_modeset;
 689
 690         intel_setup_overlay(dev_priv);
 691
 692         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 693                 return 0;
 694
 695         ret = intel_fbdev_init(dev);
 696         if (ret)
 697                 goto cleanup_gem;
 698
 699         /* Only enable hotplug handling once the fbdev is fully set up. */
 700         intel_hpd_init(dev_priv);
 701
 702         return 0;
 703
 704 cleanup_gem:
 705         if (i915_gem_suspend(dev_priv))
 706                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 707         i915_gem_fini(dev_priv);
 708 cleanup_modeset:
 709         intel_modeset_cleanup(dev);
 710 cleanup_irq:
 711         drm_irq_uninstall(dev);
 712         intel_teardown_gmbus(dev_priv);
 713 cleanup_csr:
 714         intel_csr_ucode_fini(dev_priv);
 715         intel_power_domains_fini_hw(dev_priv);
 716         vga_switcheroo_unregister_client(pdev);
 717 cleanup_vga_client:
 718         vga_client_register(pdev, NULL, NULL, NULL);
 719 out:
 720         return ret;
 721 }
 722
 723 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 724 {
 725         struct apertures_struct *ap;
 726         struct pci_dev *pdev = dev_priv->drm.pdev;
 727         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 728         bool primary;
 729         int ret;
 730
 731         ap = alloc_apertures(1);
 732         if (!ap)
 733                 return -ENOMEM;
 734
 735         ap->ranges[0].base = ggtt->gmadr.start;
 736         ap->ranges[0].size = ggtt->mappable_end;
 737
 738         primary =
 739                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 740
 741         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 742
 743         kfree(ap);
 744
 745         return ret;
 746 }
 747
 748 #if !defined(CONFIG_VGA_CONSOLE)
 749 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 750 {
 751         return 0;
 752 }
 753 #elif !defined(CONFIG_DUMMY_CONSOLE)
 754 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 755 {
 756         return -ENODEV;
 757 }
 758 #else
 759 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 760 {
 761         int ret = 0;
 762
 763         DRM_INFO("Replacing VGA console driver\n");
 764
 765         console_lock();
 766         if (con_is_bound(&vga_con))
 767                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 768         if (ret == 0) {
 769                 ret = do_unregister_con_driver(&vga_con);
 770
 771                 /* Ignore "already unregistered". */
 772                 if (ret == -ENODEV)
 773                         ret = 0;
 774         }
 775         console_unlock();
 776
 777         return ret;
 778 }
 779 #endif
 780
 781 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 782 {
 783         /*
 784          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 785          * CHV x1 PHY (DP/HDMI D)
 786          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 787          */
 788         if (IS_CHERRYVIEW(dev_priv)) {
 789                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 790                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 791         } else if (IS_VALLEYVIEW(dev_priv)) {
 792                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 793         }
 794 }
 795
 796 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 797 {
 798         /*
 799          * The i915 workqueue is primarily used for batched retirement of
 800          * requests (and thus managing bo) once the task has been completed
 801          * by the GPU. i915_retire_requests() is called directly when we
 802          * need high-priority retirement, such as waiting for an explicit
 803          * bo.
 804          *
 805          * It is also used for periodic low-priority events, such as
 806          * idle-timers and recording error state.
 807          *
 808          * All tasks on the workqueue are expected to acquire the dev mutex
 809          * so there is no point in running more than one instance of the
 810          * workqueue at any time.  Use an ordered one.
 811          */
 812         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 813         if (dev_priv->wq == NULL)
 814                 goto out_err;
 815
 816         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 817         if (dev_priv->hotplug.dp_wq == NULL)
 818                 goto out_free_wq;
 819
 820         return 0;
 821
 822 out_free_wq:
 823         destroy_workqueue(dev_priv->wq);
 824 out_err:
 825         DRM_ERROR("Failed to allocate workqueues.\n");
 826
 827         return -ENOMEM;
 828 }
 829
 830 static void i915_engines_cleanup(struct drm_i915_private *i915)
 831 {
 832         struct intel_engine_cs *engine;
 833         enum intel_engine_id id;
 834
 835         for_each_engine(engine, i915, id)
 836                 kfree(engine);
 837 }
 838
 839 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 840 {
 841         destroy_workqueue(dev_priv->hotplug.dp_wq);
 842         destroy_workqueue(dev_priv->wq);
 843 }
 844
 845 /*
 846  * We don't keep the workarounds for pre-production hardware, so we expect our
 847  * driver to fail on these machines in one way or another. A little warning on
 848  * dmesg may help both the user and the bug triagers.
 849  *
 850  * Our policy for removing pre-production workarounds is to keep the
 851  * current gen workarounds as a guide to the bring-up of the next gen
 852  * (workarounds have a habit of persisting!). Anything older than that
 853  * should be removed along with the complications they introduce.
 854  */
 855 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 856 {
 857         bool pre = false;
 858
 859         pre |= IS_HSW_EARLY_SDV(dev_priv);
 860         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 861         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 862
 863         if (pre) {
 864                 DRM_ERROR("This is a pre-production stepping. "
 865                           "It may not be fully functional.\n");
 866                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 867         }
 868 }
 869
 870 /**
 871  * i915_driver_init_early - setup state not requiring device access
 872  * @dev_priv: device private
 873  *
 874  * Initialize everything that is a "SW-only" state, that is state not
 875  * requiring accessing the device or exposing the driver via kernel internal
 876  * or userspace interfaces. Example steps belonging here: lock initialization,
 877  * system memory allocation, setting up device specific attributes and
 878  * function hooks not requiring accessing the device.
 879  */
 880 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 881 {
 882         int ret = 0;
 883
 884         if (i915_inject_load_failure())
 885                 return -ENODEV;
 886
 887         spin_lock_init(&dev_priv->irq_lock);
 888         spin_lock_init(&dev_priv->gpu_error.lock);
 889         mutex_init(&dev_priv->backlight_lock);
 890         spin_lock_init(&dev_priv->uncore.lock);
 891
 892         mutex_init(&dev_priv->sb_lock);
 893         mutex_init(&dev_priv->av_mutex);
 894         mutex_init(&dev_priv->wm.wm_mutex);
 895         mutex_init(&dev_priv->pps_mutex);
 896
 897         i915_memcpy_init_early(dev_priv);
 898
 899         ret = i915_workqueues_init(dev_priv);
 900         if (ret < 0)
 901                 goto err_engines;
 902
 903         ret = i915_gem_init_early(dev_priv);
 904         if (ret < 0)
 905                 goto err_workqueues;
 906
 907         /* This must be called before any calls to HAS_PCH_* */
 908         intel_detect_pch(dev_priv);
 909
 910         intel_wopcm_init_early(&dev_priv->wopcm);
 911         intel_uc_init_early(dev_priv);
 912         intel_pm_setup(dev_priv);
 913         intel_init_dpio(dev_priv);
 914         ret = intel_power_domains_init(dev_priv);
 915         if (ret < 0)
 916                 goto err_uc;
 917         intel_irq_init(dev_priv);
 918         intel_hangcheck_init(dev_priv);
 919         intel_init_display_hooks(dev_priv);
 920         intel_init_clock_gating_hooks(dev_priv);
 921         intel_init_audio_hooks(dev_priv);
 922         intel_display_crc_init(dev_priv);
 923
 924         intel_detect_preproduction_hw(dev_priv);
 925
 926         return 0;
 927
 928 err_uc:
 929         intel_uc_cleanup_early(dev_priv);
 930         i915_gem_cleanup_early(dev_priv);
 931 err_workqueues:
 932         i915_workqueues_cleanup(dev_priv);
 933 err_engines:
 934         i915_engines_cleanup(dev_priv);
 935         return ret;
 936 }
 937
 938 /**
 939  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 940  * @dev_priv: device private
 941  */
 942 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 943 {
 944         intel_irq_fini(dev_priv);
 945         intel_power_domains_cleanup(dev_priv);
 946         intel_uc_cleanup_early(dev_priv);
 947         i915_gem_cleanup_early(dev_priv);
 948         i915_workqueues_cleanup(dev_priv);
 949         i915_engines_cleanup(dev_priv);
 950 }
 951
 952 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 953 {
 954         struct pci_dev *pdev = dev_priv->drm.pdev;
 955         int mmio_bar;
 956         int mmio_size;
 957
 958         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 959         /*
 960          * Before gen4, the registers and the GTT are behind different BARs.
 961          * However, from gen4 onwards, the registers and the GTT are shared
 962          * in the same BAR, so we want to restrict this ioremap from
 963          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 964          * the register BAR remains the same size for all the earlier
 965          * generations up to Ironlake.
 966          */
 967         if (INTEL_GEN(dev_priv) < 5)
 968                 mmio_size = 512 * 1024;
 969         else
 970                 mmio_size = 2 * 1024 * 1024;
 971         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 972         if (dev_priv->regs == NULL) {
 973                 DRM_ERROR("failed to map registers\n");
 974
 975                 return -EIO;
 976         }
 977
 978         /* Try to make sure MCHBAR is enabled before poking at it */
 979         intel_setup_mchbar(dev_priv);
 980
 981         return 0;
 982 }
 983
 984 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 985 {
 986         struct pci_dev *pdev = dev_priv->drm.pdev;
 987
 988         intel_teardown_mchbar(dev_priv);
 989         pci_iounmap(pdev, dev_priv->regs);
 990 }
 991
 992 /**
 993  * i915_driver_init_mmio - setup device MMIO
 994  * @dev_priv: device private
 995  *
 996  * Setup minimal device state necessary for MMIO accesses later in the
 997  * initialization sequence. The setup here should avoid any other device-wide
 998  * side effects or exposing the driver via kernel internal or user space
 999  * interfaces.
1000  */
1001 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1002 {
1003         int ret;
1004
1005         if (i915_inject_load_failure())
1006                 return -ENODEV;
1007
1008         if (i915_get_bridge_dev(dev_priv))
1009                 return -EIO;
1010
1011         ret = i915_mmio_setup(dev_priv);
1012         if (ret < 0)
1013                 goto err_bridge;
1014
1015         intel_uncore_init(dev_priv);
1016
1017         intel_device_info_init_mmio(dev_priv);
1018
1019         intel_uncore_prune(dev_priv);
1020
1021         intel_uc_init_mmio(dev_priv);
1022
1023         ret = intel_engines_init_mmio(dev_priv);
1024         if (ret)
1025                 goto err_uncore;
1026
1027         i915_gem_init_mmio(dev_priv);
1028
1029         return 0;
1030
1031 err_uncore:
1032         intel_uncore_fini(dev_priv);
1033 err_bridge:
1034         pci_dev_put(dev_priv->bridge_dev);
1035
1036         return ret;
1037 }
1038
1039 /**
1040  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1041  * @dev_priv: device private
1042  */
1043 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1044 {
1045         intel_uncore_fini(dev_priv);
1046         i915_mmio_cleanup(dev_priv);
1047         pci_dev_put(dev_priv->bridge_dev);
1048 }
1049
1050 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1051 {
1052         /*
1053          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1054          * user's requested state against the hardware/driver capabilities.  We
1055          * do this now so that we can print out any log messages once rather
1056          * than every time we check intel_enable_ppgtt().
1057          */
1058         i915_modparams.enable_ppgtt =
1059                 intel_sanitize_enable_ppgtt(dev_priv,
1060                                             i915_modparams.enable_ppgtt);
1061         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1062
1063         intel_gvt_sanitize_options(dev_priv);
1064 }
1065
1066 static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1067 {
1068         if (size == 0)
1069                 return I915_DRAM_RANK_INVALID;
1070         if (rank == SKL_DRAM_RANK_SINGLE)
1071                 return I915_DRAM_RANK_SINGLE;
1072         else if (rank == SKL_DRAM_RANK_DUAL)
1073                 return I915_DRAM_RANK_DUAL;
1074
1075         return I915_DRAM_RANK_INVALID;
1076 }
1077
1078 static bool
1079 skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1080 {
1081         if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1082                 return true;
1083         else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1084                 return true;
1085         else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1086                 return true;
1087         else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1088                 return true;
1089
1090         return false;
1091 }
1092
1093 static int
1094 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1095 {
1096         u32 tmp_l, tmp_s;
1097         u32 s_val = val >> SKL_DRAM_S_SHIFT;
1098
1099         if (!val)
1100                 return -EINVAL;
1101
1102         tmp_l = val & SKL_DRAM_SIZE_MASK;
1103         tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1104
1105         if (tmp_l == 0 && tmp_s == 0)
1106                 return -EINVAL;
1107
1108         ch->l_info.size = tmp_l;
1109         ch->s_info.size = tmp_s;
1110
1111         tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1112         tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1113         ch->l_info.width = (1 << tmp_l) * 8;
1114         ch->s_info.width = (1 << tmp_s) * 8;
1115
1116         tmp_l = val & SKL_DRAM_RANK_MASK;
1117         tmp_s = s_val & SKL_DRAM_RANK_MASK;
1118         ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1119         ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1120
1121         if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1122             ch->s_info.rank == I915_DRAM_RANK_DUAL)
1123                 ch->rank = I915_DRAM_RANK_DUAL;
1124         else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1125                  ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1126                 ch->rank = I915_DRAM_RANK_DUAL;
1127         else
1128                 ch->rank = I915_DRAM_RANK_SINGLE;
1129
1130         ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1131                                             ch->l_info.width) ||
1132                            skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1133                                             ch->s_info.width);
1134
1135         DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1136                       ch->l_info.size, ch->l_info.width,
1137                       ch->l_info.rank ? "dual" : "single",
1138                       ch->s_info.size, ch->s_info.width,
1139                       ch->s_info.rank ? "dual" : "single");
1140
1141         return 0;
1142 }
1143
1144 static bool
1145 intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1146                         struct dram_channel_info *ch0)
1147 {
1148         return (val_ch0 == val_ch1 &&
1149                 (ch0->s_info.size == 0 ||
1150                  (ch0->l_info.size == ch0->s_info.size &&
1151                   ch0->l_info.width == ch0->s_info.width &&
1152                   ch0->l_info.rank == ch0->s_info.rank)));
1153 }
1154
1155 static int
1156 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1157 {
1158         struct dram_info *dram_info = &dev_priv->dram_info;
1159         struct dram_channel_info ch0, ch1;
1160         u32 val_ch0, val_ch1;
1161         int ret;
1162
1163         val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1164         ret = skl_dram_get_channel_info(&ch0, val_ch0);
1165         if (ret == 0)
1166                 dram_info->num_channels++;
1167
1168         val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1169         ret = skl_dram_get_channel_info(&ch1, val_ch1);
1170         if (ret == 0)
1171                 dram_info->num_channels++;
1172
1173         if (dram_info->num_channels == 0) {
1174                 DRM_INFO("Number of memory channels is zero\n");
1175                 return -EINVAL;
1176         }
1177
1178         /*
1179          * If any of the channel is single rank channel, worst case output
1180          * will be same as if single rank memory, so consider single rank
1181          * memory.
1182          */
1183         if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1184             ch1.rank == I915_DRAM_RANK_SINGLE)
1185                 dram_info->rank = I915_DRAM_RANK_SINGLE;
1186         else
1187                 dram_info->rank = max(ch0.rank, ch1.rank);
1188
1189         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1190                 DRM_INFO("couldn't get memory rank information\n");
1191                 return -EINVAL;
1192         }
1193
1194         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1195
1196         dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1197                                                                        val_ch1,
1198                                                                        &ch0);
1199
1200         DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1201                       dev_priv->dram_info.symmetric_memory ? "" : "not ");
1202         return 0;
1203 }
1204
1205 static int
1206 skl_get_dram_info(struct drm_i915_private *dev_priv)
1207 {
1208         struct dram_info *dram_info = &dev_priv->dram_info;
1209         u32 mem_freq_khz, val;
1210         int ret;
1211
1212         ret = skl_dram_get_channels_info(dev_priv);
1213         if (ret)
1214                 return ret;
1215
1216         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1217         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1218                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1219
1220         dram_info->bandwidth_kbps = dram_info->num_channels *
1221                                                         mem_freq_khz * 8;
1222
1223         if (dram_info->bandwidth_kbps == 0) {
1224                 DRM_INFO("Couldn't get system memory bandwidth\n");
1225                 return -EINVAL;
1226         }
1227
1228         dram_info->valid = true;
1229         return 0;
1230 }
1231
1232 static int
1233 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1234 {
1235         struct dram_info *dram_info = &dev_priv->dram_info;
1236         u32 dram_channels;
1237         u32 mem_freq_khz, val;
1238         u8 num_active_channels;
1239         int i;
1240
1241         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1242         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1243                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1244
1245         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1246         num_active_channels = hweight32(dram_channels);
1247
1248         /* Each active bit represents 4-byte channel */
1249         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1250
1251         if (dram_info->bandwidth_kbps == 0) {
1252                 DRM_INFO("Couldn't get system memory bandwidth\n");
1253                 return -EINVAL;
1254         }
1255
1256         /*
1257          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1258          */
1259         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1260                 u8 size, width;
1261                 enum dram_rank rank;
1262                 u32 tmp;
1263
1264                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1265                 if (val == 0xFFFFFFFF)
1266                         continue;
1267
1268                 dram_info->num_channels++;
1269                 tmp = val & BXT_DRAM_RANK_MASK;
1270
1271                 if (tmp == BXT_DRAM_RANK_SINGLE)
1272                         rank = I915_DRAM_RANK_SINGLE;
1273                 else if (tmp == BXT_DRAM_RANK_DUAL)
1274                         rank = I915_DRAM_RANK_DUAL;
1275                 else
1276                         rank = I915_DRAM_RANK_INVALID;
1277
1278                 tmp = val & BXT_DRAM_SIZE_MASK;
1279                 if (tmp == BXT_DRAM_SIZE_4GB)
1280                         size = 4;
1281                 else if (tmp == BXT_DRAM_SIZE_6GB)
1282                         size = 6;
1283                 else if (tmp == BXT_DRAM_SIZE_8GB)
1284                         size = 8;
1285                 else if (tmp == BXT_DRAM_SIZE_12GB)
1286                         size = 12;
1287                 else if (tmp == BXT_DRAM_SIZE_16GB)
1288                         size = 16;
1289                 else
1290                         size = 0;
1291
1292                 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1293                 width = (1 << tmp) * 8;
1294                 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1295                               width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1296                               rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1297
1298                 /*
1299                  * If any of the channel is single rank channel,
1300                  * worst case output will be same as if single rank
1301                  * memory, so consider single rank memory.
1302                  */
1303                 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1304                         dram_info->rank = rank;
1305                 else if (rank == I915_DRAM_RANK_SINGLE)
1306                         dram_info->rank = I915_DRAM_RANK_SINGLE;
1307         }
1308
1309         if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1310                 DRM_INFO("couldn't get memory rank information\n");
1311                 return -EINVAL;
1312         }
1313
1314         dram_info->valid = true;
1315         return 0;
1316 }
1317
1318 static void
1319 intel_get_dram_info(struct drm_i915_private *dev_priv)
1320 {
1321         struct dram_info *dram_info = &dev_priv->dram_info;
1322         char bandwidth_str[32];
1323         int ret;
1324
1325         dram_info->valid = false;
1326         dram_info->rank = I915_DRAM_RANK_INVALID;
1327         dram_info->bandwidth_kbps = 0;
1328         dram_info->num_channels = 0;
1329
1330         /*
1331          * Assume 16Gb DIMMs are present until proven otherwise.
1332          * This is only used for the level 0 watermark latency
1333          * w/a which does not apply to bxt/glk.
1334          */
1335         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1336
1337         if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1338                 return;
1339
1340         /* Need to calculate bandwidth only for Gen9 */
1341         if (IS_BROXTON(dev_priv))
1342                 ret = bxt_get_dram_info(dev_priv);
1343         else if (INTEL_GEN(dev_priv) == 9)
1344                 ret = skl_get_dram_info(dev_priv);
1345         else
1346                 ret = skl_dram_get_channels_info(dev_priv);
1347         if (ret)
1348                 return;
1349
1350         if (dram_info->bandwidth_kbps)
1351                 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1352         else
1353                 sprintf(bandwidth_str, "unknown");
1354         DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1355                       bandwidth_str, dram_info->num_channels);
1356         DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
1357                       (dram_info->rank == I915_DRAM_RANK_DUAL) ?
1358                       "dual" : "single", yesno(dram_info->is_16gb_dimm));
1359 }
1360
1361 /**
1362  * i915_driver_init_hw - setup state requiring device access
1363  * @dev_priv: device private
1364  *
1365  * Setup state that requires accessing the device, but doesn't require
1366  * exposing the driver via kernel internal or userspace interfaces.
1367  */
1368 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1369 {
1370         struct pci_dev *pdev = dev_priv->drm.pdev;
1371         int ret;
1372
1373         if (i915_inject_load_failure())
1374                 return -ENODEV;
1375
1376         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1377
1378         intel_sanitize_options(dev_priv);
1379
1380         i915_perf_init(dev_priv);
1381
1382         ret = i915_ggtt_probe_hw(dev_priv);
1383         if (ret)
1384                 goto err_perf;
1385
1386         /*
1387          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1388          * otherwise the vga fbdev driver falls over.
1389          */
1390         ret = i915_kick_out_firmware_fb(dev_priv);
1391         if (ret) {
1392                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1393                 goto err_ggtt;
1394         }
1395
1396         ret = i915_kick_out_vgacon(dev_priv);
1397         if (ret) {
1398                 DRM_ERROR("failed to remove conflicting VGA console\n");
1399                 goto err_ggtt;
1400         }
1401
1402         ret = i915_ggtt_init_hw(dev_priv);
1403         if (ret)
1404                 goto err_ggtt;
1405
1406         ret = i915_ggtt_enable_hw(dev_priv);
1407         if (ret) {
1408                 DRM_ERROR("failed to enable GGTT\n");
1409                 goto err_ggtt;
1410         }
1411
1412         pci_set_master(pdev);
1413
1414         /* overlay on gen2 is broken and can't address above 1G */
1415         if (IS_GEN2(dev_priv)) {
1416                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1417                 if (ret) {
1418                         DRM_ERROR("failed to set DMA mask\n");
1419
1420                         goto err_ggtt;
1421                 }
1422         }
1423
1424         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1425          * using 32bit addressing, overwriting memory if HWS is located
1426          * above 4GB.
1427          *
1428          * The documentation also mentions an issue with undefined
1429          * behaviour if any general state is accessed within a page above 4GB,
1430          * which also needs to be handled carefully.
1431          */
1432         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1433                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1434
1435                 if (ret) {
1436                         DRM_ERROR("failed to set DMA mask\n");
1437
1438                         goto err_ggtt;
1439                 }
1440         }
1441
1442         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1443                            PM_QOS_DEFAULT_VALUE);
1444
1445         intel_uncore_sanitize(dev_priv);
1446
1447         i915_gem_load_init_fences(dev_priv);
1448
1449         /* On the 945G/GM, the chipset reports the MSI capability on the
1450          * integrated graphics even though the support isn't actually there
1451          * according to the published specs.  It doesn't appear to function
1452          * correctly in testing on 945G.
1453          * This may be a side effect of MSI having been made available for PEG
1454          * and the registers being closely associated.
1455          *
1456          * According to chipset errata, on the 965GM, MSI interrupts may
1457          * be lost or delayed, and was defeatured. MSI interrupts seem to
1458          * get lost on g4x as well, and interrupt delivery seems to stay
1459          * properly dead afterwards. So we'll just disable them for all
1460          * pre-gen5 chipsets.
1461          *
1462          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1463          * interrupts even when in MSI mode. This results in spurious
1464          * interrupt warnings if the legacy irq no. is shared with another
1465          * device. The kernel then disables that interrupt source and so
1466          * prevents the other device from working properly.
1467          */
1468         if (INTEL_GEN(dev_priv) >= 5) {
1469                 if (pci_enable_msi(pdev) < 0)
1470                         DRM_DEBUG_DRIVER("can't enable MSI");
1471         }
1472
1473         ret = intel_gvt_init(dev_priv);
1474         if (ret)
1475                 goto err_msi;
1476
1477         intel_opregion_setup(dev_priv);
1478         /*
1479          * Fill the dram structure to get the system raw bandwidth and
1480          * dram info. This will be used for memory latency calculation.
1481          */
1482         intel_get_dram_info(dev_priv);
1483
1484
1485         return 0;
1486
1487 err_msi:
1488         if (pdev->msi_enabled)
1489                 pci_disable_msi(pdev);
1490         pm_qos_remove_request(&dev_priv->pm_qos);
1491 err_ggtt:
1492         i915_ggtt_cleanup_hw(dev_priv);
1493 err_perf:
1494         i915_perf_fini(dev_priv);
1495         return ret;
1496 }
1497
1498 /**
1499  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1500  * @dev_priv: device private
1501  */
1502 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1503 {
1504         struct pci_dev *pdev = dev_priv->drm.pdev;
1505
1506         i915_perf_fini(dev_priv);
1507
1508         if (pdev->msi_enabled)
1509                 pci_disable_msi(pdev);
1510
1511         pm_qos_remove_request(&dev_priv->pm_qos);
1512         i915_ggtt_cleanup_hw(dev_priv);
1513 }
1514
1515 /**
1516  * i915_driver_register - register the driver with the rest of the system
1517  * @dev_priv: device private
1518  *
1519  * Perform any steps necessary to make the driver available via kernel
1520  * internal or userspace interfaces.
1521  */
1522 static void i915_driver_register(struct drm_i915_private *dev_priv)
1523 {
1524         struct drm_device *dev = &dev_priv->drm;
1525
1526         i915_gem_shrinker_register(dev_priv);
1527         i915_pmu_register(dev_priv);
1528
1529         /*
1530          * Notify a valid surface after modesetting,
1531          * when running inside a VM.
1532          */
1533         if (intel_vgpu_active(dev_priv))
1534                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1535
1536         /* Reveal our presence to userspace */
1537         if (drm_dev_register(dev, 0) == 0) {
1538                 i915_debugfs_register(dev_priv);
1539                 i915_setup_sysfs(dev_priv);
1540
1541                 /* Depends on sysfs having been initialized */
1542                 i915_perf_register(dev_priv);
1543         } else
1544                 DRM_ERROR("Failed to register driver for userspace access!\n");
1545
1546         if (INTEL_INFO(dev_priv)->num_pipes) {
1547                 /* Must be done after probing outputs */
1548                 intel_opregion_register(dev_priv);
1549                 acpi_video_register();
1550         }
1551
1552         if (IS_GEN5(dev_priv))
1553                 intel_gpu_ips_init(dev_priv);
1554
1555         intel_audio_init(dev_priv);
1556
1557         /*
1558          * Some ports require correctly set-up hpd registers for detection to
1559          * work properly (leading to ghost connected connector status), e.g. VGA
1560          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1561          * irqs are fully enabled. We do it last so that the async config
1562          * cannot run before the connectors are registered.
1563          */
1564         intel_fbdev_initial_config_async(dev);
1565
1566         /*
1567          * We need to coordinate the hotplugs with the asynchronous fbdev
1568          * configuration, for which we use the fbdev->async_cookie.
1569          */
1570         if (INTEL_INFO(dev_priv)->num_pipes)
1571                 drm_kms_helper_poll_init(dev);
1572
1573         intel_power_domains_enable(dev_priv);
1574         intel_runtime_pm_enable(dev_priv);
1575 }
1576
1577 /**
1578  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1579  * @dev_priv: device private
1580  */
1581 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1582 {
1583         intel_runtime_pm_disable(dev_priv);
1584         intel_power_domains_disable(dev_priv);
1585
1586         intel_fbdev_unregister(dev_priv);
1587         intel_audio_deinit(dev_priv);
1588
1589         /*
1590          * After flushing the fbdev (incl. a late async config which will
1591          * have delayed queuing of a hotplug event), then flush the hotplug
1592          * events.
1593          */
1594         drm_kms_helper_poll_fini(&dev_priv->drm);
1595
1596         intel_gpu_ips_teardown();
1597         acpi_video_unregister();
1598         intel_opregion_unregister(dev_priv);
1599
1600         i915_perf_unregister(dev_priv);
1601         i915_pmu_unregister(dev_priv);
1602
1603         i915_teardown_sysfs(dev_priv);
1604         drm_dev_unregister(&dev_priv->drm);
1605
1606         i915_gem_shrinker_unregister(dev_priv);
1607 }
1608
1609 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1610 {
1611         if (drm_debug & DRM_UT_DRIVER) {
1612                 struct drm_printer p = drm_debug_printer("i915 device info:");
1613
1614                 intel_device_info_dump(&dev_priv->info, &p);
1615                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1616         }
1617
1618         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1619                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1620         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1621                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1622         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1623                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1624 }
1625
1626 static struct drm_i915_private *
1627 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1628 {
1629         const struct intel_device_info *match_info =
1630                 (struct intel_device_info *)ent->driver_data;
1631         struct intel_device_info *device_info;
1632         struct drm_i915_private *i915;
1633
1634         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1635         if (!i915)
1636                 return NULL;
1637
1638         if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
1639                 kfree(i915);
1640                 return NULL;
1641         }
1642
1643         i915->drm.pdev = pdev;
1644         i915->drm.dev_private = i915;
1645         pci_set_drvdata(pdev, &i915->drm);
1646
1647         /* Setup the write-once "constant" device info */
1648         device_info = mkwrite_device_info(i915);
1649         memcpy(device_info, match_info, sizeof(*device_info));
1650         device_info->device_id = pdev->device;
1651
1652         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1653                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
1654         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1655
1656         return i915;
1657 }
1658
1659 static void i915_driver_destroy(struct drm_i915_private *i915)
1660 {
1661         struct pci_dev *pdev = i915->drm.pdev;
1662
1663         drm_dev_fini(&i915->drm);
1664         kfree(i915);
1665
1666         /* And make sure we never chase our dangling pointer from pci_dev */
1667         pci_set_drvdata(pdev, NULL);
1668 }
1669
1670 /**
1671  * i915_driver_load - setup chip and create an initial config
1672  * @pdev: PCI device
1673  * @ent: matching PCI ID entry
1674  *
1675  * The driver load routine has to do several things:
1676  *   - drive output discovery via intel_modeset_init()
1677  *   - initialize the memory manager
1678  *   - allocate initial config memory
1679  *   - setup the DRM framebuffer with the allocated memory
1680  */
1681 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1682 {
1683         const struct intel_device_info *match_info =
1684                 (struct intel_device_info *)ent->driver_data;
1685         struct drm_i915_private *dev_priv;
1686         int ret;
1687
1688         dev_priv = i915_driver_create(pdev, ent);
1689         if (!dev_priv)
1690                 return -ENOMEM;
1691
1692         /* Disable nuclear pageflip by default on pre-ILK */
1693         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1694                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1695
1696         ret = pci_enable_device(pdev);
1697         if (ret)
1698                 goto out_fini;
1699
1700         ret = i915_driver_init_early(dev_priv);
1701         if (ret < 0)
1702                 goto out_pci_disable;
1703
1704         disable_rpm_wakeref_asserts(dev_priv);
1705
1706         ret = i915_driver_init_mmio(dev_priv);
1707         if (ret < 0)
1708                 goto out_runtime_pm_put;
1709
1710         ret = i915_driver_init_hw(dev_priv);
1711         if (ret < 0)
1712                 goto out_cleanup_mmio;
1713
1714         /*
1715          * TODO: move the vblank init and parts of modeset init steps into one
1716          * of the i915_driver_init_/i915_driver_register functions according
1717          * to the role/effect of the given init step.
1718          */
1719         if (INTEL_INFO(dev_priv)->num_pipes) {
1720                 ret = drm_vblank_init(&dev_priv->drm,
1721                                       INTEL_INFO(dev_priv)->num_pipes);
1722                 if (ret)
1723                         goto out_cleanup_hw;
1724         }
1725
1726         ret = i915_load_modeset_init(&dev_priv->drm);
1727         if (ret < 0)
1728                 goto out_cleanup_hw;
1729
1730         i915_driver_register(dev_priv);
1731
1732         intel_init_ipc(dev_priv);
1733
1734         enable_rpm_wakeref_asserts(dev_priv);
1735
1736         i915_welcome_messages(dev_priv);
1737
1738         return 0;
1739
1740 out_cleanup_hw:
1741         i915_driver_cleanup_hw(dev_priv);
1742 out_cleanup_mmio:
1743         i915_driver_cleanup_mmio(dev_priv);
1744 out_runtime_pm_put:
1745         enable_rpm_wakeref_asserts(dev_priv);
1746         i915_driver_cleanup_early(dev_priv);
1747 out_pci_disable:
1748         pci_disable_device(pdev);
1749 out_fini:
1750         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1751         i915_driver_destroy(dev_priv);
1752         return ret;
1753 }
1754
1755 void i915_driver_unload(struct drm_device *dev)
1756 {
1757         struct drm_i915_private *dev_priv = to_i915(dev);
1758         struct pci_dev *pdev = dev_priv->drm.pdev;
1759
1760         disable_rpm_wakeref_asserts(dev_priv);
1761
1762         i915_driver_unregister(dev_priv);
1763
1764         if (i915_gem_suspend(dev_priv))
1765                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1766
1767         drm_atomic_helper_shutdown(dev);
1768
1769         intel_gvt_cleanup(dev_priv);
1770
1771         intel_modeset_cleanup(dev);
1772
1773         intel_bios_cleanup(dev_priv);
1774
1775         vga_switcheroo_unregister_client(pdev);
1776         vga_client_register(pdev, NULL, NULL, NULL);
1777
1778         intel_csr_ucode_fini(dev_priv);
1779
1780         /* Free error state after interrupts are fully disabled. */
1781         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1782         i915_reset_error_state(dev_priv);
1783
1784         i915_gem_fini(dev_priv);
1785         intel_fbc_cleanup_cfb(dev_priv);
1786
1787         intel_power_domains_fini_hw(dev_priv);
1788
1789         i915_driver_cleanup_hw(dev_priv);
1790         i915_driver_cleanup_mmio(dev_priv);
1791
1792         enable_rpm_wakeref_asserts(dev_priv);
1793
1794         WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1795 }
1796
1797 static void i915_driver_release(struct drm_device *dev)
1798 {
1799         struct drm_i915_private *dev_priv = to_i915(dev);
1800
1801         i915_driver_cleanup_early(dev_priv);
1802         i915_driver_destroy(dev_priv);
1803 }
1804
1805 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1806 {
1807         struct drm_i915_private *i915 = to_i915(dev);
1808         int ret;
1809
1810         ret = i915_gem_open(i915, file);
1811         if (ret)
1812                 return ret;
1813
1814         return 0;
1815 }
1816
1817 /**
1818  * i915_driver_lastclose - clean up after all DRM clients have exited
1819  * @dev: DRM device
1820  *
1821  * Take care of cleaning up after all DRM clients have exited.  In the
1822  * mode setting case, we want to restore the kernel's initial mode (just
1823  * in case the last client left us in a bad state).
1824  *
1825  * Additionally, in the non-mode setting case, we'll tear down the GTT
1826  * and DMA structures, since the kernel won't be using them, and clea
1827  * up any GEM state.
1828  */
1829 static void i915_driver_lastclose(struct drm_device *dev)
1830 {
1831         intel_fbdev_restore_mode(dev);
1832         vga_switcheroo_process_delayed_switch();
1833 }
1834
1835 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1836 {
1837         struct drm_i915_file_private *file_priv = file->driver_priv;
1838
1839         mutex_lock(&dev->struct_mutex);
1840         i915_gem_context_close(file);
1841         i915_gem_release(dev, file);
1842         mutex_unlock(&dev->struct_mutex);
1843
1844         kfree(file_priv);
1845 }
1846
1847 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1848 {
1849         struct drm_device *dev = &dev_priv->drm;
1850         struct intel_encoder *encoder;
1851
1852         drm_modeset_lock_all(dev);
1853         for_each_intel_encoder(dev, encoder)
1854                 if (encoder->suspend)
1855                         encoder->suspend(encoder);
1856         drm_modeset_unlock_all(dev);
1857 }
1858
1859 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1860                               bool rpm_resume);
1861 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1862
1863 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1864 {
1865 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1866         if (acpi_target_system_state() < ACPI_STATE_S3)
1867                 return true;
1868 #endif
1869         return false;
1870 }
1871
1872 static int i915_drm_prepare(struct drm_device *dev)
1873 {
1874         struct drm_i915_private *i915 = to_i915(dev);
1875         int err;
1876
1877         /*
1878          * NB intel_display_suspend() may issue new requests after we've
1879          * ostensibly marked the GPU as ready-to-sleep here. We need to
1880          * split out that work and pull it forward so that after point,
1881          * the GPU is not woken again.
1882          */
1883         err = i915_gem_suspend(i915);
1884         if (err)
1885                 dev_err(&i915->drm.pdev->dev,
1886                         "GEM idle failed, suspend/resume might fail\n");
1887
1888         return err;
1889 }
1890
1891 static int i915_drm_suspend(struct drm_device *dev)
1892 {
1893         struct drm_i915_private *dev_priv = to_i915(dev);
1894         struct pci_dev *pdev = dev_priv->drm.pdev;
1895         pci_power_t opregion_target_state;
1896
1897         disable_rpm_wakeref_asserts(dev_priv);
1898
1899         /* We do a lot of poking in a lot of registers, make sure they work
1900          * properly. */
1901         intel_power_domains_disable(dev_priv);
1902
1903         drm_kms_helper_poll_disable(dev);
1904
1905         pci_save_state(pdev);
1906
1907         intel_display_suspend(dev);
1908
1909         intel_dp_mst_suspend(dev_priv);
1910
1911         intel_runtime_pm_disable_interrupts(dev_priv);
1912         intel_hpd_cancel_work(dev_priv);
1913
1914         intel_suspend_encoders(dev_priv);
1915
1916         intel_suspend_hw(dev_priv);
1917
1918         i915_gem_suspend_gtt_mappings(dev_priv);
1919
1920         i915_save_state(dev_priv);
1921
1922         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1923         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1924
1925         intel_opregion_unregister(dev_priv);
1926
1927         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1928
1929         dev_priv->suspend_count++;
1930
1931         intel_csr_ucode_suspend(dev_priv);
1932
1933         enable_rpm_wakeref_asserts(dev_priv);
1934
1935         return 0;
1936 }
1937
1938 static enum i915_drm_suspend_mode
1939 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1940 {
1941         if (hibernate)
1942                 return I915_DRM_SUSPEND_HIBERNATE;
1943
1944         if (suspend_to_idle(dev_priv))
1945                 return I915_DRM_SUSPEND_IDLE;
1946
1947         return I915_DRM_SUSPEND_MEM;
1948 }
1949
1950 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1951 {
1952         struct drm_i915_private *dev_priv = to_i915(dev);
1953         struct pci_dev *pdev = dev_priv->drm.pdev;
1954         int ret;
1955
1956         disable_rpm_wakeref_asserts(dev_priv);
1957
1958         i915_gem_suspend_late(dev_priv);
1959
1960         intel_uncore_suspend(dev_priv);
1961
1962         intel_power_domains_suspend(dev_priv,
1963                                     get_suspend_mode(dev_priv, hibernation));
1964
1965         ret = 0;
1966         if (IS_GEN9_LP(dev_priv))
1967                 bxt_enable_dc9(dev_priv);
1968         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1969                 hsw_enable_pc8(dev_priv);
1970         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1971                 ret = vlv_suspend_complete(dev_priv);
1972
1973         if (ret) {
1974                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1975                 intel_power_domains_resume(dev_priv);
1976
1977                 goto out;
1978         }
1979
1980         pci_disable_device(pdev);
1981         /*
1982          * During hibernation on some platforms the BIOS may try to access
1983          * the device even though it's already in D3 and hang the machine. So
1984          * leave the device in D0 on those platforms and hope the BIOS will
1985          * power down the device properly. The issue was seen on multiple old
1986          * GENs with different BIOS vendors, so having an explicit blacklist
1987          * is inpractical; apply the workaround on everything pre GEN6. The
1988          * platforms where the issue was seen:
1989          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1990          * Fujitsu FSC S7110
1991          * Acer Aspire 1830T
1992          */
1993         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1994                 pci_set_power_state(pdev, PCI_D3hot);
1995
1996 out:
1997         enable_rpm_wakeref_asserts(dev_priv);
1998
1999         return ret;
2000 }
2001
2002 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2003 {
2004         int error;
2005
2006         if (!dev) {
2007                 DRM_ERROR("dev: %p\n", dev);
2008                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2009                 return -ENODEV;
2010         }
2011
2012         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2013                          state.event != PM_EVENT_FREEZE))
2014                 return -EINVAL;
2015
2016         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2017                 return 0;
2018
2019         error = i915_drm_suspend(dev);
2020         if (error)
2021                 return error;
2022
2023         return i915_drm_suspend_late(dev, false);
2024 }
2025
2026 static int i915_drm_resume(struct drm_device *dev)
2027 {
2028         struct drm_i915_private *dev_priv = to_i915(dev);
2029         int ret;
2030
2031         disable_rpm_wakeref_asserts(dev_priv);
2032         intel_sanitize_gt_powersave(dev_priv);
2033
2034         i915_gem_sanitize(dev_priv);
2035
2036         ret = i915_ggtt_enable_hw(dev_priv);
2037         if (ret)
2038                 DRM_ERROR("failed to re-enable GGTT\n");
2039
2040         intel_csr_ucode_resume(dev_priv);
2041
2042         i915_restore_state(dev_priv);
2043         intel_pps_unlock_regs_wa(dev_priv);
2044         intel_opregion_setup(dev_priv);
2045
2046         intel_init_pch_refclk(dev_priv);
2047
2048         /*
2049          * Interrupts have to be enabled before any batches are run. If not the
2050          * GPU will hang. i915_gem_init_hw() will initiate batches to
2051          * update/restore the context.
2052          *
2053          * drm_mode_config_reset() needs AUX interrupts.
2054          *
2055          * Modeset enabling in intel_modeset_init_hw() also needs working
2056          * interrupts.
2057          */
2058         intel_runtime_pm_enable_interrupts(dev_priv);
2059
2060         drm_mode_config_reset(dev);
2061
2062         i915_gem_resume(dev_priv);
2063
2064         intel_modeset_init_hw(dev);
2065         intel_init_clock_gating(dev_priv);
2066
2067         spin_lock_irq(&dev_priv->irq_lock);
2068         if (dev_priv->display.hpd_irq_setup)
2069                 dev_priv->display.hpd_irq_setup(dev_priv);
2070         spin_unlock_irq(&dev_priv->irq_lock);
2071
2072         intel_dp_mst_resume(dev_priv);
2073
2074         intel_display_resume(dev);
2075
2076         drm_kms_helper_poll_enable(dev);
2077
2078         /*
2079          * ... but also need to make sure that hotplug processing
2080          * doesn't cause havoc. Like in the driver load code we don't
2081          * bother with the tiny race here where we might lose hotplug
2082          * notifications.
2083          * */
2084         intel_hpd_init(dev_priv);
2085
2086         intel_opregion_register(dev_priv);
2087
2088         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2089
2090         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2091
2092         intel_power_domains_enable(dev_priv);
2093
2094         enable_rpm_wakeref_asserts(dev_priv);
2095
2096         return 0;
2097 }
2098
2099 static int i915_drm_resume_early(struct drm_device *dev)
2100 {
2101         struct drm_i915_private *dev_priv = to_i915(dev);
2102         struct pci_dev *pdev = dev_priv->drm.pdev;
2103         int ret;
2104
2105         /*
2106          * We have a resume ordering issue with the snd-hda driver also
2107          * requiring our device to be power up. Due to the lack of a
2108          * parent/child relationship we currently solve this with an early
2109          * resume hook.
2110          *
2111          * FIXME: This should be solved with a special hdmi sink device or
2112          * similar so that power domains can be employed.
2113          */
2114
2115         /*
2116          * Note that we need to set the power state explicitly, since we
2117          * powered off the device during freeze and the PCI core won't power
2118          * it back up for us during thaw. Powering off the device during
2119          * freeze is not a hard requirement though, and during the
2120          * suspend/resume phases the PCI core makes sure we get here with the
2121          * device powered on. So in case we change our freeze logic and keep
2122          * the device powered we can also remove the following set power state
2123          * call.
2124          */
2125         ret = pci_set_power_state(pdev, PCI_D0);
2126         if (ret) {
2127                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2128                 return ret;
2129         }
2130
2131         /*
2132          * Note that pci_enable_device() first enables any parent bridge
2133          * device and only then sets the power state for this device. The
2134          * bridge enabling is a nop though, since bridge devices are resumed
2135          * first. The order of enabling power and enabling the device is
2136          * imposed by the PCI core as described above, so here we preserve the
2137          * same order for the freeze/thaw phases.
2138          *
2139          * TODO: eventually we should remove pci_disable_device() /
2140          * pci_enable_enable_device() from suspend/resume. Due to how they
2141          * depend on the device enable refcount we can't anyway depend on them
2142          * disabling/enabling the device.
2143          */
2144         if (pci_enable_device(pdev))
2145                 return -EIO;
2146
2147         pci_set_master(pdev);
2148
2149         disable_rpm_wakeref_asserts(dev_priv);
2150
2151         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2152                 ret = vlv_resume_prepare(dev_priv, false);
2153         if (ret)
2154                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2155                           ret);
2156
2157         intel_uncore_resume_early(dev_priv);
2158
2159         if (IS_GEN9_LP(dev_priv)) {
2160                 gen9_sanitize_dc_state(dev_priv);
2161                 bxt_disable_dc9(dev_priv);
2162         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2163                 hsw_disable_pc8(dev_priv);
2164         }
2165
2166         intel_uncore_sanitize(dev_priv);
2167
2168         intel_power_domains_resume(dev_priv);
2169
2170         intel_engines_sanitize(dev_priv);
2171
2172         enable_rpm_wakeref_asserts(dev_priv);
2173
2174         return ret;
2175 }
2176
2177 static int i915_resume_switcheroo(struct drm_device *dev)
2178 {
2179         int ret;
2180
2181         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2182                 return 0;
2183
2184         ret = i915_drm_resume_early(dev);
2185         if (ret)
2186                 return ret;
2187
2188         return i915_drm_resume(dev);
2189 }
2190
2191 /**
2192  * i915_reset - reset chip after a hang
2193  * @i915: #drm_i915_private to reset
2194  * @stalled_mask: mask of the stalled engines with the guilty requests
2195  * @reason: user error message for why we are resetting
2196  *
2197  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
2198  * on failure.
2199  *
2200  * Caller must hold the struct_mutex.
2201  *
2202  * Procedure is fairly simple:
2203  *   - reset the chip using the reset reg
2204  *   - re-init context state
2205  *   - re-init hardware status page
2206  *   - re-init ring buffer
2207  *   - re-init interrupt state
2208  *   - re-init display
2209  */
2210 void i915_reset(struct drm_i915_private *i915,
2211                 unsigned int stalled_mask,
2212                 const char *reason)
2213 {
2214         struct i915_gpu_error *error = &i915->gpu_error;
2215         int ret;
2216         int i;
2217
2218         GEM_TRACE("flags=%lx\n", error->flags);
2219
2220         might_sleep();
2221         lockdep_assert_held(&i915->drm.struct_mutex);
2222         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
2223
2224         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
2225                 return;
2226
2227         /* Clear any previous failed attempts at recovery. Time to try again. */
2228         if (!i915_gem_unset_wedged(i915))
2229                 goto wakeup;
2230
2231         if (reason)
2232                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
2233         error->reset_count++;
2234
2235         ret = i915_gem_reset_prepare(i915);
2236         if (ret) {
2237                 dev_err(i915->drm.dev, "GPU recovery failed\n");
2238                 goto taint;
2239         }
2240
2241         if (!intel_has_gpu_reset(i915)) {
2242                 if (i915_modparams.reset)
2243                         dev_err(i915->drm.dev, "GPU reset not supported\n");
2244                 else
2245                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
2246                 goto error;
2247         }
2248
2249         for (i = 0; i < 3; i++) {
2250                 ret = intel_gpu_reset(i915, ALL_ENGINES);
2251                 if (ret == 0)
2252                         break;
2253
2254                 msleep(100);
2255         }
2256         if (ret) {
2257                 dev_err(i915->drm.dev, "Failed to reset chip\n");
2258                 goto taint;
2259         }
2260
2261         /* Ok, now get things going again... */
2262
2263         /*
2264          * Everything depends on having the GTT running, so we need to start
2265          * there.
2266          */
2267         ret = i915_ggtt_enable_hw(i915);
2268         if (ret) {
2269                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
2270                           ret);
2271                 goto error;
2272         }
2273
2274         i915_gem_reset(i915, stalled_mask);
2275         intel_overlay_reset(i915);
2276
2277         /*
2278          * Next we need to restore the context, but we don't use those
2279          * yet either...
2280          *
2281          * Ring buffer needs to be re-initialized in the KMS case, or if X
2282          * was running at the time of the reset (i.e. we weren't VT
2283          * switched away).
2284          */
2285         ret = i915_gem_init_hw(i915);
2286         if (ret) {
2287                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
2288                           ret);
2289                 goto error;
2290         }
2291
2292         i915_queue_hangcheck(i915);
2293
2294 finish:
2295         i915_gem_reset_finish(i915);
2296 wakeup:
2297         clear_bit(I915_RESET_HANDOFF, &error->flags);
2298         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
2299         return;
2300
2301 taint:
2302         /*
2303          * History tells us that if we cannot reset the GPU now, we
2304          * never will. This then impacts everything that is run
2305          * subsequently. On failing the reset, we mark the driver
2306          * as wedged, preventing further execution on the GPU.
2307          * We also want to go one step further and add a taint to the
2308          * kernel so that any subsequent faults can be traced back to
2309          * this failure. This is important for CI, where if the
2310          * GPU/driver fails we would like to reboot and restart testing
2311          * rather than continue on into oblivion. For everyone else,
2312          * the system should still plod along, but they have been warned!
2313          */
2314         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2315 error:
2316         i915_gem_set_wedged(i915);
2317         i915_retire_requests(i915);
2318         goto finish;
2319 }
2320
2321 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2322                                         struct intel_engine_cs *engine)
2323 {
2324         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2325 }
2326
2327 /**
2328  * i915_reset_engine - reset GPU engine to recover from a hang
2329  * @engine: engine to reset
2330  * @msg: reason for GPU reset; or NULL for no dev_notice()
2331  *
2332  * Reset a specific GPU engine. Useful if a hang is detected.
2333  * Returns zero on successful reset or otherwise an error code.
2334  *
2335  * Procedure is:
2336  *  - identifies the request that caused the hang and it is dropped
2337  *  - reset engine (which will force the engine to idle)
2338  *  - re-init/configure engine
2339  */
2340 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2341 {
2342         struct i915_gpu_error *error = &engine->i915->gpu_error;
2343         struct i915_request *active_request;
2344         int ret;
2345
2346         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2347         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2348
2349         active_request = i915_gem_reset_prepare_engine(engine);
2350         if (IS_ERR_OR_NULL(active_request)) {
2351                 /* Either the previous reset failed, or we pardon the reset. */
2352                 ret = PTR_ERR(active_request);
2353                 goto out;
2354         }
2355
2356         if (msg)
2357                 dev_notice(engine->i915->drm.dev,
2358                            "Resetting %s for %s\n", engine->name, msg);
2359         error->reset_engine_count[engine->id]++;
2360
2361         if (!engine->i915->guc.execbuf_client)
2362                 ret = intel_gt_reset_engine(engine->i915, engine);
2363         else
2364                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2365         if (ret) {
2366                 /* If we fail here, we expect to fallback to a global reset */
2367                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2368                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2369                                  engine->name, ret);
2370                 goto out;
2371         }
2372
2373         /*
2374          * The request that caused the hang is stuck on elsp, we know the
2375          * active request and can drop it, adjust head to skip the offending
2376          * request to resume executing remaining requests in the queue.
2377          */
2378         i915_gem_reset_engine(engine, active_request, true);
2379
2380         /*
2381          * The engine and its registers (and workarounds in case of render)
2382          * have been reset to their default values. Follow the init_ring
2383          * process to program RING_MODE, HWSP and re-enable submission.
2384          */
2385         ret = engine->init_hw(engine);
2386         if (ret)
2387                 goto out;
2388
2389 out:
2390         intel_engine_cancel_stop_cs(engine);
2391         i915_gem_reset_finish_engine(engine);
2392         return ret;
2393 }
2394
2395 static int i915_pm_prepare(struct device *kdev)
2396 {
2397         struct pci_dev *pdev = to_pci_dev(kdev);
2398         struct drm_device *dev = pci_get_drvdata(pdev);
2399
2400         if (!dev) {
2401                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2402                 return -ENODEV;
2403         }
2404
2405         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2406                 return 0;
2407
2408         return i915_drm_prepare(dev);
2409 }
2410
2411 static int i915_pm_suspend(struct device *kdev)
2412 {
2413         struct pci_dev *pdev = to_pci_dev(kdev);
2414         struct drm_device *dev = pci_get_drvdata(pdev);
2415
2416         if (!dev) {
2417                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2418                 return -ENODEV;
2419         }
2420
2421         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2422                 return 0;
2423
2424         return i915_drm_suspend(dev);
2425 }
2426
2427 static int i915_pm_suspend_late(struct device *kdev)
2428 {
2429         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2430
2431         /*
2432          * We have a suspend ordering issue with the snd-hda driver also
2433          * requiring our device to be power up. Due to the lack of a
2434          * parent/child relationship we currently solve this with an late
2435          * suspend hook.
2436          *
2437          * FIXME: This should be solved with a special hdmi sink device or
2438          * similar so that power domains can be employed.
2439          */
2440         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2441                 return 0;
2442
2443         return i915_drm_suspend_late(dev, false);
2444 }
2445
2446 static int i915_pm_poweroff_late(struct device *kdev)
2447 {
2448         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2449
2450         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2451                 return 0;
2452
2453         return i915_drm_suspend_late(dev, true);
2454 }
2455
2456 static int i915_pm_resume_early(struct device *kdev)
2457 {
2458         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2459
2460         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2461                 return 0;
2462
2463         return i915_drm_resume_early(dev);
2464 }
2465
2466 static int i915_pm_resume(struct device *kdev)
2467 {
2468         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2469
2470         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2471                 return 0;
2472
2473         return i915_drm_resume(dev);
2474 }
2475
2476 /* freeze: before creating the hibernation_image */
2477 static int i915_pm_freeze(struct device *kdev)
2478 {
2479         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2480         int ret;
2481
2482         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2483                 ret = i915_drm_suspend(dev);
2484                 if (ret)
2485                         return ret;
2486         }
2487
2488         ret = i915_gem_freeze(kdev_to_i915(kdev));
2489         if (ret)
2490                 return ret;
2491
2492         return 0;
2493 }
2494
2495 static int i915_pm_freeze_late(struct device *kdev)
2496 {
2497         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2498         int ret;
2499
2500         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2501                 ret = i915_drm_suspend_late(dev, true);
2502                 if (ret)
2503                         return ret;
2504         }
2505
2506         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2507         if (ret)
2508                 return ret;
2509
2510         return 0;
2511 }
2512
2513 /* thaw: called after creating the hibernation image, but before turning off. */
2514 static int i915_pm_thaw_early(struct device *kdev)
2515 {
2516         return i915_pm_resume_early(kdev);
2517 }
2518
2519 static int i915_pm_thaw(struct device *kdev)
2520 {
2521         return i915_pm_resume(kdev);
2522 }
2523
2524 /* restore: called after loading the hibernation image. */
2525 static int i915_pm_restore_early(struct device *kdev)
2526 {
2527         return i915_pm_resume_early(kdev);
2528 }
2529
2530 static int i915_pm_restore(struct device *kdev)
2531 {
2532         return i915_pm_resume(kdev);
2533 }
2534
2535 /*
2536  * Save all Gunit registers that may be lost after a D3 and a subsequent
2537  * S0i[R123] transition. The list of registers needing a save/restore is
2538  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2539  * registers in the following way:
2540  * - Driver: saved/restored by the driver
2541  * - Punit : saved/restored by the Punit firmware
2542  * - No, w/o marking: no need to save/restore, since the register is R/O or
2543  *                    used internally by the HW in a way that doesn't depend
2544  *                    keeping the content across a suspend/resume.
2545  * - Debug : used for debugging
2546  *
2547  * We save/restore all registers marked with 'Driver', with the following
2548  * exceptions:
2549  * - Registers out of use, including also registers marked with 'Debug'.
2550  *   These have no effect on the driver's operation, so we don't save/restore
2551  *   them to reduce the overhead.
2552  * - Registers that are fully setup by an initialization function called from
2553  *   the resume path. For example many clock gating and RPS/RC6 registers.
2554  * - Registers that provide the right functionality with their reset defaults.
2555  *
2556  * TODO: Except for registers that based on the above 3 criteria can be safely
2557  * ignored, we save/restore all others, practically treating the HW context as
2558  * a black-box for the driver. Further investigation is needed to reduce the
2559  * saved/restored registers even further, by following the same 3 criteria.
2560  */
2561 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2562 {
2563         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2564         int i;
2565
2566         /* GAM 0x4000-0x4770 */
2567         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2568         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2569         s->arb_mode             = I915_READ(ARB_MODE);
2570         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2571         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2572
2573         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2574                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2575
2576         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2577         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2578
2579         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2580         s->ecochk               = I915_READ(GAM_ECOCHK);
2581         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2582         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2583
2584         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2585
2586         /* MBC 0x9024-0x91D0, 0x8500 */
2587         s->g3dctl               = I915_READ(VLV_G3DCTL);
2588         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2589         s->mbctl                = I915_READ(GEN6_MBCTL);
2590
2591         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2592         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2593         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2594         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2595         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2596         s->rstctl               = I915_READ(GEN6_RSTCTL);
2597         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2598
2599         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2600         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2601         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2602         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2603         s->ecobus               = I915_READ(ECOBUS);
2604         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2605         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2606         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2607         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2608         s->rcedata              = I915_READ(VLV_RCEDATA);
2609         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2610
2611         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2612         s->gt_imr               = I915_READ(GTIMR);
2613         s->gt_ier               = I915_READ(GTIER);
2614         s->pm_imr               = I915_READ(GEN6_PMIMR);
2615         s->pm_ier               = I915_READ(GEN6_PMIER);
2616
2617         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2618                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2619
2620         /* GT SA CZ domain, 0x100000-0x138124 */
2621         s->tilectl              = I915_READ(TILECTL);
2622         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2623         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2624         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2625         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2626
2627         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2628         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2629         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2630         s->pcbr                 = I915_READ(VLV_PCBR);
2631         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2632
2633         /*
2634          * Not saving any of:
2635          * DFT,         0x9800-0x9EC0
2636          * SARB,        0xB000-0xB1FC
2637          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2638          * PCI CFG
2639          */
2640 }
2641
2642 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2643 {
2644         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2645         u32 val;
2646         int i;
2647
2648         /* GAM 0x4000-0x4770 */
2649         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2650         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2651         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2652         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2653         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2654
2655         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2656                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2657
2658         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2659         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2660
2661         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2662         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2663         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2664         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2665
2666         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2667
2668         /* MBC 0x9024-0x91D0, 0x8500 */
2669         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2670         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2671         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2672
2673         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2674         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2675         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2676         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2677         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2678         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2679         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2680
2681         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2682         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2683         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2684         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2685         I915_WRITE(ECOBUS,              s->ecobus);
2686         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2687         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2688         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2689         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2690         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2691         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2692
2693         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2694         I915_WRITE(GTIMR,               s->gt_imr);
2695         I915_WRITE(GTIER,               s->gt_ier);
2696         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2697         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2698
2699         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2700                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2701
2702         /* GT SA CZ domain, 0x100000-0x138124 */
2703         I915_WRITE(TILECTL,                     s->tilectl);
2704         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2705         /*
2706          * Preserve the GT allow wake and GFX force clock bit, they are not
2707          * be restored, as they are used to control the s0ix suspend/resume
2708          * sequence by the caller.
2709          */
2710         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2711         val &= VLV_GTLC_ALLOWWAKEREQ;
2712         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2713         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2714
2715         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2716         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2717         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2718         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2719
2720         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2721
2722         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2723         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2724         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2725         I915_WRITE(VLV_PCBR,                    s->pcbr);
2726         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2727 }
2728
2729 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2730                                   u32 mask, u32 val)
2731 {
2732         /* The HW does not like us polling for PW_STATUS frequently, so
2733          * use the sleeping loop rather than risk the busy spin within
2734          * intel_wait_for_register().
2735          *
2736          * Transitioning between RC6 states should be at most 2ms (see
2737          * valleyview_enable_rps) so use a 3ms timeout.
2738          */
2739         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2740                         3);
2741 }
2742
2743 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2744 {
2745         u32 val;
2746         int err;
2747
2748         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2749         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2750         if (force_on)
2751                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2752         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2753
2754         if (!force_on)
2755                 return 0;
2756
2757         err = intel_wait_for_register(dev_priv,
2758                                       VLV_GTLC_SURVIVABILITY_REG,
2759                                       VLV_GFX_CLK_STATUS_BIT,
2760                                       VLV_GFX_CLK_STATUS_BIT,
2761                                       20);
2762         if (err)
2763                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2764                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2765
2766         return err;
2767 }
2768
2769 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2770 {
2771         u32 mask;
2772         u32 val;
2773         int err;
2774
2775         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2776         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2777         if (allow)
2778                 val |= VLV_GTLC_ALLOWWAKEREQ;
2779         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2780         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2781
2782         mask = VLV_GTLC_ALLOWWAKEACK;
2783         val = allow ? mask : 0;
2784
2785         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2786         if (err)
2787                 DRM_ERROR("timeout disabling GT waking\n");
2788
2789         return err;
2790 }
2791
2792 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2793                                   bool wait_for_on)
2794 {
2795         u32 mask;
2796         u32 val;
2797
2798         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2799         val = wait_for_on ? mask : 0;
2800
2801         /*
2802          * RC6 transitioning can be delayed up to 2 msec (see
2803          * valleyview_enable_rps), use 3 msec for safety.
2804          *
2805          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2806          * reset and we are trying to force the machine to sleep.
2807          */
2808         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2809                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2810                                  onoff(wait_for_on));
2811 }
2812
2813 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2814 {
2815         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2816                 return;
2817
2818         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2819         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2820 }
2821
2822 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2823 {
2824         u32 mask;
2825         int err;
2826
2827         /*
2828          * Bspec defines the following GT well on flags as debug only, so
2829          * don't treat them as hard failures.
2830          */
2831         vlv_wait_for_gt_wells(dev_priv, false);
2832
2833         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2834         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2835
2836         vlv_check_no_gt_access(dev_priv);
2837
2838         err = vlv_force_gfx_clock(dev_priv, true);
2839         if (err)
2840                 goto err1;
2841
2842         err = vlv_allow_gt_wake(dev_priv, false);
2843         if (err)
2844                 goto err2;
2845
2846         if (!IS_CHERRYVIEW(dev_priv))
2847                 vlv_save_gunit_s0ix_state(dev_priv);
2848
2849         err = vlv_force_gfx_clock(dev_priv, false);
2850         if (err)
2851                 goto err2;
2852
2853         return 0;
2854
2855 err2:
2856         /* For safety always re-enable waking and disable gfx clock forcing */
2857         vlv_allow_gt_wake(dev_priv, true);
2858 err1:
2859         vlv_force_gfx_clock(dev_priv, false);
2860
2861         return err;
2862 }
2863
2864 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2865                                 bool rpm_resume)
2866 {
2867         int err;
2868         int ret;
2869
2870         /*
2871          * If any of the steps fail just try to continue, that's the best we
2872          * can do at this point. Return the first error code (which will also
2873          * leave RPM permanently disabled).
2874          */
2875         ret = vlv_force_gfx_clock(dev_priv, true);
2876
2877         if (!IS_CHERRYVIEW(dev_priv))
2878                 vlv_restore_gunit_s0ix_state(dev_priv);
2879
2880         err = vlv_allow_gt_wake(dev_priv, true);
2881         if (!ret)
2882                 ret = err;
2883
2884         err = vlv_force_gfx_clock(dev_priv, false);
2885         if (!ret)
2886                 ret = err;
2887
2888         vlv_check_no_gt_access(dev_priv);
2889
2890         if (rpm_resume)
2891                 intel_init_clock_gating(dev_priv);
2892
2893         return ret;
2894 }
2895
2896 static int intel_runtime_suspend(struct device *kdev)
2897 {
2898         struct pci_dev *pdev = to_pci_dev(kdev);
2899         struct drm_device *dev = pci_get_drvdata(pdev);
2900         struct drm_i915_private *dev_priv = to_i915(dev);
2901         int ret;
2902
2903         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2904                 return -ENODEV;
2905
2906         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2907                 return -ENODEV;
2908
2909         DRM_DEBUG_KMS("Suspending device\n");
2910
2911         disable_rpm_wakeref_asserts(dev_priv);
2912
2913         /*
2914          * We are safe here against re-faults, since the fault handler takes
2915          * an RPM reference.
2916          */
2917         i915_gem_runtime_suspend(dev_priv);
2918
2919         intel_uc_suspend(dev_priv);
2920
2921         intel_runtime_pm_disable_interrupts(dev_priv);
2922
2923         intel_uncore_suspend(dev_priv);
2924
2925         ret = 0;
2926         if (IS_GEN9_LP(dev_priv)) {
2927                 bxt_display_core_uninit(dev_priv);
2928                 bxt_enable_dc9(dev_priv);
2929         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2930                 hsw_enable_pc8(dev_priv);
2931         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2932                 ret = vlv_suspend_complete(dev_priv);
2933         }
2934
2935         if (ret) {
2936                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2937                 intel_uncore_runtime_resume(dev_priv);
2938
2939                 intel_runtime_pm_enable_interrupts(dev_priv);
2940
2941                 intel_uc_resume(dev_priv);
2942
2943                 i915_gem_init_swizzling(dev_priv);
2944                 i915_gem_restore_fences(dev_priv);
2945
2946                 enable_rpm_wakeref_asserts(dev_priv);
2947
2948                 return ret;
2949         }
2950
2951         enable_rpm_wakeref_asserts(dev_priv);
2952         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2953
2954         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2955                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2956
2957         dev_priv->runtime_pm.suspended = true;
2958
2959         /*
2960          * FIXME: We really should find a document that references the arguments
2961          * used below!
2962          */
2963         if (IS_BROADWELL(dev_priv)) {
2964                 /*
2965                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2966                  * being detected, and the call we do at intel_runtime_resume()
2967                  * won't be able to restore them. Since PCI_D3hot matches the
2968                  * actual specification and appears to be working, use it.
2969                  */
2970                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2971         } else {
2972                 /*
2973                  * current versions of firmware which depend on this opregion
2974                  * notification have repurposed the D1 definition to mean
2975                  * "runtime suspended" vs. what you would normally expect (D3)
2976                  * to distinguish it from notifications that might be sent via
2977                  * the suspend path.
2978                  */
2979                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2980         }
2981
2982         assert_forcewakes_inactive(dev_priv);
2983
2984         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2985                 intel_hpd_poll_init(dev_priv);
2986
2987         DRM_DEBUG_KMS("Device suspended\n");
2988         return 0;
2989 }
2990
2991 static int intel_runtime_resume(struct device *kdev)
2992 {
2993         struct pci_dev *pdev = to_pci_dev(kdev);
2994         struct drm_device *dev = pci_get_drvdata(pdev);
2995         struct drm_i915_private *dev_priv = to_i915(dev);
2996         int ret = 0;
2997
2998         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2999                 return -ENODEV;
3000
3001         DRM_DEBUG_KMS("Resuming device\n");
3002
3003         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
3004         disable_rpm_wakeref_asserts(dev_priv);
3005
3006         intel_opregion_notify_adapter(dev_priv, PCI_D0);
3007         dev_priv->runtime_pm.suspended = false;
3008         if (intel_uncore_unclaimed_mmio(dev_priv))
3009                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
3010
3011         if (IS_GEN9_LP(dev_priv)) {
3012                 bxt_disable_dc9(dev_priv);
3013                 bxt_display_core_init(dev_priv, true);
3014                 if (dev_priv->csr.dmc_payload &&
3015                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
3016                         gen9_enable_dc5(dev_priv);
3017         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3018                 hsw_disable_pc8(dev_priv);
3019         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3020                 ret = vlv_resume_prepare(dev_priv, true);
3021         }
3022
3023         intel_uncore_runtime_resume(dev_priv);
3024
3025         intel_runtime_pm_enable_interrupts(dev_priv);
3026
3027         intel_uc_resume(dev_priv);
3028
3029         /*
3030          * No point of rolling back things in case of an error, as the best
3031          * we can do is to hope that things will still work (and disable RPM).
3032          */
3033         i915_gem_init_swizzling(dev_priv);
3034         i915_gem_restore_fences(dev_priv);
3035
3036         /*
3037          * On VLV/CHV display interrupts are part of the display
3038          * power well, so hpd is reinitialized from there. For
3039          * everyone else do it here.
3040          */
3041         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3042                 intel_hpd_init(dev_priv);
3043
3044         intel_enable_ipc(dev_priv);
3045
3046         enable_rpm_wakeref_asserts(dev_priv);
3047
3048         if (ret)
3049                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3050         else
3051                 DRM_DEBUG_KMS("Device resumed\n");
3052
3053         return ret;
3054 }
3055
3056 const struct dev_pm_ops i915_pm_ops = {
3057         /*
3058          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3059          * PMSG_RESUME]
3060          */
3061         .prepare = i915_pm_prepare,
3062         .suspend = i915_pm_suspend,
3063         .suspend_late = i915_pm_suspend_late,
3064         .resume_early = i915_pm_resume_early,
3065         .resume = i915_pm_resume,
3066
3067         /*
3068          * S4 event handlers
3069          * @freeze, @freeze_late    : called (1) before creating the
3070          *                            hibernation image [PMSG_FREEZE] and
3071          *                            (2) after rebooting, before restoring
3072          *                            the image [PMSG_QUIESCE]
3073          * @thaw, @thaw_early       : called (1) after creating the hibernation
3074          *                            image, before writing it [PMSG_THAW]
3075          *                            and (2) after failing to create or
3076          *                            restore the image [PMSG_RECOVER]
3077          * @poweroff, @poweroff_late: called after writing the hibernation
3078          *                            image, before rebooting [PMSG_HIBERNATE]
3079          * @restore, @restore_early : called after rebooting and restoring the
3080          *                            hibernation image [PMSG_RESTORE]
3081          */
3082         .freeze = i915_pm_freeze,
3083         .freeze_late = i915_pm_freeze_late,
3084         .thaw_early = i915_pm_thaw_early,
3085         .thaw = i915_pm_thaw,
3086         .poweroff = i915_pm_suspend,
3087         .poweroff_late = i915_pm_poweroff_late,
3088         .restore_early = i915_pm_restore_early,
3089         .restore = i915_pm_restore,
3090
3091         /* S0ix (via runtime suspend) event handlers */
3092         .runtime_suspend = intel_runtime_suspend,
3093         .runtime_resume = intel_runtime_resume,
3094 };
3095
3096 static const struct vm_operations_struct i915_gem_vm_ops = {
3097         .fault = i915_gem_fault,
3098         .open = drm_gem_vm_open,
3099         .close = drm_gem_vm_close,
3100 };
3101
3102 static const struct file_operations i915_driver_fops = {
3103         .owner = THIS_MODULE,
3104         .open = drm_open,
3105         .release = drm_release,
3106         .unlocked_ioctl = drm_ioctl,
3107         .mmap = drm_gem_mmap,
3108         .poll = drm_poll,
3109         .read = drm_read,
3110         .compat_ioctl = i915_compat_ioctl,
3111         .llseek = noop_llseek,
3112 };
3113
3114 static int
3115 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3116                           struct drm_file *file)
3117 {
3118         return -ENODEV;
3119 }
3120
3121 static const struct drm_ioctl_desc i915_ioctls[] = {
3122         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3123         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3124         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3125         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3126         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3127         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3128         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3129         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3130         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3131         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3132         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3133         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3134         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3135         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3136         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3137         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3138         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3139         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3140         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3141         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3142         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3143         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3144         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3145         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3146         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3147         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3148         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3149         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3150         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3151         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3152         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3153         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3154         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3155         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3156         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3157         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3158         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3159         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3160         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3161         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3162         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3163         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3164         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3165         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3166         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3167         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3168         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3169         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3170         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3171         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3172         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3173         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3174         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3175         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3176         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3177         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3178 };
3179
3180 static struct drm_driver driver = {
3181         /* Don't use MTRRs here; the Xserver or userspace app should
3182          * deal with them for Intel hardware.
3183          */
3184         .driver_features =
3185             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
3186             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3187         .release = i915_driver_release,
3188         .open = i915_driver_open,
3189         .lastclose = i915_driver_lastclose,
3190         .postclose = i915_driver_postclose,
3191
3192         .gem_close_object = i915_gem_close_object,
3193         .gem_free_object_unlocked = i915_gem_free_object,
3194         .gem_vm_ops = &i915_gem_vm_ops,
3195
3196         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3197         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3198         .gem_prime_export = i915_gem_prime_export,
3199         .gem_prime_import = i915_gem_prime_import,
3200
3201         .dumb_create = i915_gem_dumb_create,
3202         .dumb_map_offset = i915_gem_mmap_gtt,
3203         .ioctls = i915_ioctls,
3204         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3205         .fops = &i915_driver_fops,
3206         .name = DRIVER_NAME,
3207         .desc = DRIVER_DESC,
3208         .date = DRIVER_DATE,
3209         .major = DRIVER_MAJOR,
3210         .minor = DRIVER_MINOR,
3211         .patchlevel = DRIVER_PATCHLEVEL,
3212 };
3213
3214 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3215 #include "selftests/mock_drm.c"
3216 #endif