drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0400);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158
 159 static const struct intel_device_info intel_i830_info = {
 160         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .ring_mask = RENDER_RING,
 163 };
 164
 165 static const struct intel_device_info intel_845g_info = {
 166         .gen = 2, .num_pipes = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .ring_mask = RENDER_RING,
 169 };
 170
 171 static const struct intel_device_info intel_i85x_info = {
 172         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 173         .cursor_needs_physical = 1,
 174         .has_overlay = 1, .overlay_needs_physical = 1,
 175         .has_fbc = 1,
 176         .ring_mask = RENDER_RING,
 177 };
 178
 179 static const struct intel_device_info intel_i865g_info = {
 180         .gen = 2, .num_pipes = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .ring_mask = RENDER_RING,
 183 };
 184
 185 static const struct intel_device_info intel_i915g_info = {
 186         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 187         .has_overlay = 1, .overlay_needs_physical = 1,
 188         .ring_mask = RENDER_RING,
 189 };
 190 static const struct intel_device_info intel_i915gm_info = {
 191         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 192         .cursor_needs_physical = 1,
 193         .has_overlay = 1, .overlay_needs_physical = 1,
 194         .supports_tv = 1,
 195         .has_fbc = 1,
 196         .ring_mask = RENDER_RING,
 197 };
 198 static const struct intel_device_info intel_i945g_info = {
 199         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 200         .has_overlay = 1, .overlay_needs_physical = 1,
 201         .ring_mask = RENDER_RING,
 202 };
 203 static const struct intel_device_info intel_i945gm_info = {
 204         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 205         .has_hotplug = 1, .cursor_needs_physical = 1,
 206         .has_overlay = 1, .overlay_needs_physical = 1,
 207         .supports_tv = 1,
 208         .has_fbc = 1,
 209         .ring_mask = RENDER_RING,
 210 };
 211
 212 static const struct intel_device_info intel_i965g_info = {
 213         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 214         .has_hotplug = 1,
 215         .has_overlay = 1,
 216         .ring_mask = RENDER_RING,
 217 };
 218
 219 static const struct intel_device_info intel_i965gm_info = {
 220         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 221         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 222         .has_overlay = 1,
 223         .supports_tv = 1,
 224         .ring_mask = RENDER_RING,
 225 };
 226
 227 static const struct intel_device_info intel_g33_info = {
 228         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_overlay = 1,
 231         .ring_mask = RENDER_RING,
 232 };
 233
 234 static const struct intel_device_info intel_g45_info = {
 235         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 236         .has_pipe_cxsr = 1, .has_hotplug = 1,
 237         .ring_mask = RENDER_RING | BSD_RING,
 238 };
 239
 240 static const struct intel_device_info intel_gm45_info = {
 241         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 242         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 243         .has_pipe_cxsr = 1, .has_hotplug = 1,
 244         .supports_tv = 1,
 245         .ring_mask = RENDER_RING | BSD_RING,
 246 };
 247
 248 static const struct intel_device_info intel_pineview_info = {
 249         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_overlay = 1,
 252 };
 253
 254 static const struct intel_device_info intel_ironlake_d_info = {
 255         .gen = 5, .num_pipes = 2,
 256         .need_gfx_hws = 1, .has_hotplug = 1,
 257         .ring_mask = RENDER_RING | BSD_RING,
 258 };
 259
 260 static const struct intel_device_info intel_ironlake_m_info = {
 261         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 262         .need_gfx_hws = 1, .has_hotplug = 1,
 263         .has_fbc = 1,
 264         .ring_mask = RENDER_RING | BSD_RING,
 265 };
 266
 267 static const struct intel_device_info intel_sandybridge_d_info = {
 268         .gen = 6, .num_pipes = 2,
 269         .need_gfx_hws = 1, .has_hotplug = 1,
 270         .has_fbc = 1,
 271         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 272         .has_llc = 1,
 273 };
 274
 275 static const struct intel_device_info intel_sandybridge_m_info = {
 276         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 277         .need_gfx_hws = 1, .has_hotplug = 1,
 278         .has_fbc = 1,
 279         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 280         .has_llc = 1,
 281 };
 282
 283 #define GEN7_FEATURES  \
 284         .gen = 7, .num_pipes = 3, \
 285         .need_gfx_hws = 1, .has_hotplug = 1, \
 286         .has_fbc = 1, \
 287         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 288         .has_llc = 1
 289
 290 static const struct intel_device_info intel_ivybridge_d_info = {
 291         GEN7_FEATURES,
 292         .is_ivybridge = 1,
 293 };
 294
 295 static const struct intel_device_info intel_ivybridge_m_info = {
 296         GEN7_FEATURES,
 297         .is_ivybridge = 1,
 298         .is_mobile = 1,
 299 };
 300
 301 static const struct intel_device_info intel_ivybridge_q_info = {
 302         GEN7_FEATURES,
 303         .is_ivybridge = 1,
 304         .num_pipes = 0, /* legal, last one wins */
 305 };
 306
 307 static const struct intel_device_info intel_valleyview_m_info = {
 308         GEN7_FEATURES,
 309         .is_mobile = 1,
 310         .num_pipes = 2,
 311         .is_valleyview = 1,
 312         .display_mmio_offset = VLV_DISPLAY_BASE,
 313         .has_fbc = 0, /* legal, last one wins */
 314         .has_llc = 0, /* legal, last one wins */
 315 };
 316
 317 static const struct intel_device_info intel_valleyview_d_info = {
 318         GEN7_FEATURES,
 319         .num_pipes = 2,
 320         .is_valleyview = 1,
 321         .display_mmio_offset = VLV_DISPLAY_BASE,
 322         .has_fbc = 0, /* legal, last one wins */
 323         .has_llc = 0, /* legal, last one wins */
 324 };
 325
 326 static const struct intel_device_info intel_haswell_d_info = {
 327         GEN7_FEATURES,
 328         .is_haswell = 1,
 329         .has_ddi = 1,
 330         .has_fpga_dbg = 1,
 331         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 332 };
 333
 334 static const struct intel_device_info intel_haswell_m_info = {
 335         GEN7_FEATURES,
 336         .is_haswell = 1,
 337         .is_mobile = 1,
 338         .has_ddi = 1,
 339         .has_fpga_dbg = 1,
 340         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 341 };
 342
 343 static const struct intel_device_info intel_broadwell_d_info = {
 344         .gen = 8, .num_pipes = 3,
 345         .need_gfx_hws = 1, .has_hotplug = 1,
 346         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 347         .has_llc = 1,
 348         .has_ddi = 1,
 349 };
 350
 351 static const struct intel_device_info intel_broadwell_m_info = {
 352         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 353         .need_gfx_hws = 1, .has_hotplug = 1,
 354         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 355         .has_llc = 1,
 356         .has_ddi = 1,
 357 };
 358
 359 /*
 360  * Make sure any device matches here are from most specific to most
 361  * general.  For example, since the Quanta match is based on the subsystem
 362  * and subvendor IDs, we need it to come before the more general IVB
 363  * PCI ID matches, otherwise we'll use the wrong info struct above.
 364  */
 365 #define INTEL_PCI_IDS \
 366         INTEL_I830_IDS(&intel_i830_info),       \
 367         INTEL_I845G_IDS(&intel_845g_info),      \
 368         INTEL_I85X_IDS(&intel_i85x_info),       \
 369         INTEL_I865G_IDS(&intel_i865g_info),     \
 370         INTEL_I915G_IDS(&intel_i915g_info),     \
 371         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 372         INTEL_I945G_IDS(&intel_i945g_info),     \
 373         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 374         INTEL_I965G_IDS(&intel_i965g_info),     \
 375         INTEL_G33_IDS(&intel_g33_info),         \
 376         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 377         INTEL_GM45_IDS(&intel_gm45_info),       \
 378         INTEL_G45_IDS(&intel_g45_info),         \
 379         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 380         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 381         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 382         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 383         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 384         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 385         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 386         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 387         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 388         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 389         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 390         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 391         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 392         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 393
 394 static const struct pci_device_id pciidlist[] = {               /* aka */
 395         INTEL_PCI_IDS,
 396         {0, 0, 0}
 397 };
 398
 399 #if defined(CONFIG_DRM_I915_KMS)
 400 MODULE_DEVICE_TABLE(pci, pciidlist);
 401 #endif
 402
 403 void intel_detect_pch(struct drm_device *dev)
 404 {
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         struct pci_dev *pch = NULL;
 407
 408         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 409          * (which really amounts to a PCH but no South Display).
 410          */
 411         if (INTEL_INFO(dev)->num_pipes == 0) {
 412                 dev_priv->pch_type = PCH_NOP;
 413                 return;
 414         }
 415
 416         /*
 417          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 418          * make graphics device passthrough work easy for VMM, that only
 419          * need to expose ISA bridge to let driver know the real hardware
 420          * underneath. This is a requirement from virtualization team.
 421          *
 422          * In some virtualized environments (e.g. XEN), there is irrelevant
 423          * ISA bridge in the system. To work reliably, we should scan trhough
 424          * all the ISA bridge devices and check for the first match, instead
 425          * of only checking the first one.
 426          */
 427         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 428                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 429                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 430                         dev_priv->pch_id = id;
 431
 432                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 433                                 dev_priv->pch_type = PCH_IBX;
 434                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 435                                 WARN_ON(!IS_GEN5(dev));
 436                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 437                                 dev_priv->pch_type = PCH_CPT;
 438                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 439                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 440                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 441                                 /* PantherPoint is CPT compatible */
 442                                 dev_priv->pch_type = PCH_CPT;
 443                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 444                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 445                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 446                                 dev_priv->pch_type = PCH_LPT;
 447                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 448                                 WARN_ON(!IS_HASWELL(dev));
 449                                 WARN_ON(IS_ULT(dev));
 450                         } else if (IS_BROADWELL(dev)) {
 451                                 dev_priv->pch_type = PCH_LPT;
 452                                 dev_priv->pch_id =
 453                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 454                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 455                                               "LynxPoint LP PCH\n");
 456                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 457                                 dev_priv->pch_type = PCH_LPT;
 458                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 459                                 WARN_ON(!IS_HASWELL(dev));
 460                                 WARN_ON(!IS_ULT(dev));
 461                         } else
 462                                 continue;
 463
 464                         break;
 465                 }
 466         }
 467         if (!pch)
 468                 DRM_DEBUG_KMS("No PCH found.\n");
 469
 470         pci_dev_put(pch);
 471 }
 472
 473 bool i915_semaphore_is_enabled(struct drm_device *dev)
 474 {
 475         if (INTEL_INFO(dev)->gen < 6)
 476                 return false;
 477
 478         /* Until we get further testing... */
 479         if (IS_GEN8(dev)) {
 480                 WARN_ON(!i915_preliminary_hw_support);
 481                 return false;
 482         }
 483
 484         if (i915_semaphores >= 0)
 485                 return i915_semaphores;
 486
 487 #ifdef CONFIG_INTEL_IOMMU
 488         /* Enable semaphores on SNB when IO remapping is off */
 489         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 490                 return false;
 491 #endif
 492
 493         return true;
 494 }
 495
 496 static int i915_drm_freeze(struct drm_device *dev)
 497 {
 498         struct drm_i915_private *dev_priv = dev->dev_private;
 499         struct drm_crtc *crtc;
 500
 501         intel_runtime_pm_get(dev_priv);
 502
 503         /* ignore lid events during suspend */
 504         mutex_lock(&dev_priv->modeset_restore_lock);
 505         dev_priv->modeset_restore = MODESET_SUSPENDED;
 506         mutex_unlock(&dev_priv->modeset_restore_lock);
 507
 508         /* We do a lot of poking in a lot of registers, make sure they work
 509          * properly. */
 510         hsw_disable_package_c8(dev_priv);
 511         intel_display_set_init_power(dev, true);
 512
 513         drm_kms_helper_poll_disable(dev);
 514
 515         pci_save_state(dev->pdev);
 516
 517         /* If KMS is active, we do the leavevt stuff here */
 518         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 519                 int error;
 520
 521                 error = i915_gem_suspend(dev);
 522                 if (error) {
 523                         dev_err(&dev->pdev->dev,
 524                                 "GEM idle failed, resume might fail\n");
 525                         return error;
 526                 }
 527
 528                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 529
 530                 drm_irq_uninstall(dev);
 531                 dev_priv->enable_hotplug_processing = false;
 532                 /*
 533                  * Disable CRTCs directly since we want to preserve sw state
 534                  * for _thaw.
 535                  */
 536                 mutex_lock(&dev->mode_config.mutex);
 537                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 538                         dev_priv->display.crtc_disable(crtc);
 539                 mutex_unlock(&dev->mode_config.mutex);
 540
 541                 intel_modeset_suspend_hw(dev);
 542         }
 543
 544         i915_gem_suspend_gtt_mappings(dev);
 545
 546         i915_save_state(dev);
 547
 548         intel_opregion_fini(dev);
 549
 550         console_lock();
 551         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 552         console_unlock();
 553
 554         return 0;
 555 }
 556
 557 int i915_suspend(struct drm_device *dev, pm_message_t state)
 558 {
 559         int error;
 560
 561         if (!dev || !dev->dev_private) {
 562                 DRM_ERROR("dev: %p\n", dev);
 563                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 564                 return -ENODEV;
 565         }
 566
 567         if (state.event == PM_EVENT_PRETHAW)
 568                 return 0;
 569
 570
 571         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 572                 return 0;
 573
 574         error = i915_drm_freeze(dev);
 575         if (error)
 576                 return error;
 577
 578         if (state.event == PM_EVENT_SUSPEND) {
 579                 /* Shut down the device */
 580                 pci_disable_device(dev->pdev);
 581                 pci_set_power_state(dev->pdev, PCI_D3hot);
 582         }
 583
 584         return 0;
 585 }
 586
 587 void intel_console_resume(struct work_struct *work)
 588 {
 589         struct drm_i915_private *dev_priv =
 590                 container_of(work, struct drm_i915_private,
 591                              console_resume_work);
 592         struct drm_device *dev = dev_priv->dev;
 593
 594         console_lock();
 595         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 596         console_unlock();
 597 }
 598
 599 static void intel_resume_hotplug(struct drm_device *dev)
 600 {
 601         struct drm_mode_config *mode_config = &dev->mode_config;
 602         struct intel_encoder *encoder;
 603
 604         mutex_lock(&mode_config->mutex);
 605         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 606
 607         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 608                 if (encoder->hot_plug)
 609                         encoder->hot_plug(encoder);
 610
 611         mutex_unlock(&mode_config->mutex);
 612
 613         /* Just fire off a uevent and let userspace tell us what to do */
 614         drm_helper_hpd_irq_event(dev);
 615 }
 616
 617 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 618 {
 619         struct drm_i915_private *dev_priv = dev->dev_private;
 620         int error = 0;
 621
 622         intel_uncore_early_sanitize(dev);
 623
 624         intel_uncore_sanitize(dev);
 625
 626         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 627             restore_gtt_mappings) {
 628                 mutex_lock(&dev->struct_mutex);
 629                 i915_gem_restore_gtt_mappings(dev);
 630                 mutex_unlock(&dev->struct_mutex);
 631         }
 632
 633         intel_power_domains_init_hw(dev);
 634
 635         i915_restore_state(dev);
 636         intel_opregion_setup(dev);
 637
 638         /* KMS EnterVT equivalent */
 639         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 640                 intel_init_pch_refclk(dev);
 641
 642                 mutex_lock(&dev->struct_mutex);
 643
 644                 error = i915_gem_init_hw(dev);
 645                 mutex_unlock(&dev->struct_mutex);
 646
 647                 /* We need working interrupts for modeset enabling ... */
 648                 drm_irq_install(dev);
 649
 650                 intel_modeset_init_hw(dev);
 651
 652                 drm_modeset_lock_all(dev);
 653                 drm_mode_config_reset(dev);
 654                 intel_modeset_setup_hw_state(dev, true);
 655                 drm_modeset_unlock_all(dev);
 656
 657                 /*
 658                  * ... but also need to make sure that hotplug processing
 659                  * doesn't cause havoc. Like in the driver load code we don't
 660                  * bother with the tiny race here where we might loose hotplug
 661                  * notifications.
 662                  * */
 663                 intel_hpd_init(dev);
 664                 dev_priv->enable_hotplug_processing = true;
 665                 /* Config may have changed between suspend and resume */
 666                 intel_resume_hotplug(dev);
 667         }
 668
 669         intel_opregion_init(dev);
 670
 671         /*
 672          * The console lock can be pretty contented on resume due
 673          * to all the printk activity.  Try to keep it out of the hot
 674          * path of resume if possible.
 675          */
 676         if (console_trylock()) {
 677                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 678                 console_unlock();
 679         } else {
 680                 schedule_work(&dev_priv->console_resume_work);
 681         }
 682
 683         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 684          * expected level. */
 685         hsw_enable_package_c8(dev_priv);
 686
 687         mutex_lock(&dev_priv->modeset_restore_lock);
 688         dev_priv->modeset_restore = MODESET_DONE;
 689         mutex_unlock(&dev_priv->modeset_restore_lock);
 690
 691         intel_runtime_pm_put(dev_priv);
 692         return error;
 693 }
 694
 695 static int i915_drm_thaw(struct drm_device *dev)
 696 {
 697         if (drm_core_check_feature(dev, DRIVER_MODESET))
 698                 i915_check_and_clear_faults(dev);
 699
 700         return __i915_drm_thaw(dev, true);
 701 }
 702
 703 int i915_resume(struct drm_device *dev)
 704 {
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706         int ret;
 707
 708         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 709                 return 0;
 710
 711         if (pci_enable_device(dev->pdev))
 712                 return -EIO;
 713
 714         pci_set_master(dev->pdev);
 715
 716         /*
 717          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 718          * earlier) need to restore the GTT mappings since the BIOS might clear
 719          * all our scratch PTEs.
 720          */
 721         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 722         if (ret)
 723                 return ret;
 724
 725         drm_kms_helper_poll_enable(dev);
 726         return 0;
 727 }
 728
 729 /**
 730  * i915_reset - reset chip after a hang
 731  * @dev: drm device to reset
 732  *
 733  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 734  * reset or otherwise an error code.
 735  *
 736  * Procedure is fairly simple:
 737  *   - reset the chip using the reset reg
 738  *   - re-init context state
 739  *   - re-init hardware status page
 740  *   - re-init ring buffer
 741  *   - re-init interrupt state
 742  *   - re-init display
 743  */
 744 int i915_reset(struct drm_device *dev)
 745 {
 746         drm_i915_private_t *dev_priv = dev->dev_private;
 747         bool simulated;
 748         int ret;
 749
 750         if (!i915_try_reset)
 751                 return 0;
 752
 753         mutex_lock(&dev->struct_mutex);
 754
 755         i915_gem_reset(dev);
 756
 757         simulated = dev_priv->gpu_error.stop_rings != 0;
 758
 759         ret = intel_gpu_reset(dev);
 760
 761         /* Also reset the gpu hangman. */
 762         if (simulated) {
 763                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 764                 dev_priv->gpu_error.stop_rings = 0;
 765                 if (ret == -ENODEV) {
 766                         DRM_INFO("Reset not implemented, but ignoring "
 767                                  "error for simulated gpu hangs\n");
 768                         ret = 0;
 769                 }
 770         }
 771
 772         if (ret) {
 773                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 774                 mutex_unlock(&dev->struct_mutex);
 775                 return ret;
 776         }
 777
 778         /* Ok, now get things going again... */
 779
 780         /*
 781          * Everything depends on having the GTT running, so we need to start
 782          * there.  Fortunately we don't need to do this unless we reset the
 783          * chip at a PCI level.
 784          *
 785          * Next we need to restore the context, but we don't use those
 786          * yet either...
 787          *
 788          * Ring buffer needs to be re-initialized in the KMS case, or if X
 789          * was running at the time of the reset (i.e. we weren't VT
 790          * switched away).
 791          */
 792         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 793                         !dev_priv->ums.mm_suspended) {
 794                 dev_priv->ums.mm_suspended = 0;
 795
 796                 ret = i915_gem_init_hw(dev);
 797                 mutex_unlock(&dev->struct_mutex);
 798                 if (ret) {
 799                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 800                         return ret;
 801                 }
 802
 803                 drm_irq_uninstall(dev);
 804                 drm_irq_install(dev);
 805                 intel_hpd_init(dev);
 806         } else {
 807                 mutex_unlock(&dev->struct_mutex);
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 814 {
 815         struct intel_device_info *intel_info =
 816                 (struct intel_device_info *) ent->driver_data;
 817
 818         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 819                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 820                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 821                 return -ENODEV;
 822         }
 823
 824         /* Only bind to function 0 of the device. Early generations
 825          * used function 1 as a placeholder for multi-head. This causes
 826          * us confusion instead, especially on the systems where both
 827          * functions have the same PCI-ID!
 828          */
 829         if (PCI_FUNC(pdev->devfn))
 830                 return -ENODEV;
 831
 832         driver.driver_features &= ~(DRIVER_USE_AGP);
 833
 834         return drm_get_pci_dev(pdev, ent, &driver);
 835 }
 836
 837 static void
 838 i915_pci_remove(struct pci_dev *pdev)
 839 {
 840         struct drm_device *dev = pci_get_drvdata(pdev);
 841
 842         drm_put_dev(dev);
 843 }
 844
 845 static int i915_pm_suspend(struct device *dev)
 846 {
 847         struct pci_dev *pdev = to_pci_dev(dev);
 848         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 849         int error;
 850
 851         if (!drm_dev || !drm_dev->dev_private) {
 852                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 853                 return -ENODEV;
 854         }
 855
 856         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 857                 return 0;
 858
 859         error = i915_drm_freeze(drm_dev);
 860         if (error)
 861                 return error;
 862
 863         pci_disable_device(pdev);
 864         pci_set_power_state(pdev, PCI_D3hot);
 865
 866         return 0;
 867 }
 868
 869 static int i915_pm_resume(struct device *dev)
 870 {
 871         struct pci_dev *pdev = to_pci_dev(dev);
 872         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 873
 874         return i915_resume(drm_dev);
 875 }
 876
 877 static int i915_pm_freeze(struct device *dev)
 878 {
 879         struct pci_dev *pdev = to_pci_dev(dev);
 880         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 881
 882         if (!drm_dev || !drm_dev->dev_private) {
 883                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 884                 return -ENODEV;
 885         }
 886
 887         return i915_drm_freeze(drm_dev);
 888 }
 889
 890 static int i915_pm_thaw(struct device *dev)
 891 {
 892         struct pci_dev *pdev = to_pci_dev(dev);
 893         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 894
 895         return i915_drm_thaw(drm_dev);
 896 }
 897
 898 static int i915_pm_poweroff(struct device *dev)
 899 {
 900         struct pci_dev *pdev = to_pci_dev(dev);
 901         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 902
 903         return i915_drm_freeze(drm_dev);
 904 }
 905
 906 static int i915_runtime_suspend(struct device *device)
 907 {
 908         struct pci_dev *pdev = to_pci_dev(device);
 909         struct drm_device *dev = pci_get_drvdata(pdev);
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911
 912         WARN_ON(!HAS_RUNTIME_PM(dev));
 913
 914         DRM_DEBUG_KMS("Suspending device\n");
 915
 916         i915_gem_release_all_mmaps(dev_priv);
 917
 918         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 919         dev_priv->pm.suspended = true;
 920
 921         /*
 922          * current versions of firmware which depend on this opregion
 923          * notification have repurposed the D1 definition to mean
 924          * "runtime suspended" vs. what you would normally expect (D3)
 925          * to distinguish it from notifications that might be sent
 926          * via the suspend path.
 927          */
 928         intel_opregion_notify_adapter(dev, PCI_D1);
 929
 930         return 0;
 931 }
 932
 933 static int i915_runtime_resume(struct device *device)
 934 {
 935         struct pci_dev *pdev = to_pci_dev(device);
 936         struct drm_device *dev = pci_get_drvdata(pdev);
 937         struct drm_i915_private *dev_priv = dev->dev_private;
 938
 939         WARN_ON(!HAS_RUNTIME_PM(dev));
 940
 941         DRM_DEBUG_KMS("Resuming device\n");
 942
 943         intel_opregion_notify_adapter(dev, PCI_D0);
 944         dev_priv->pm.suspended = false;
 945
 946         return 0;
 947 }
 948
 949 static const struct dev_pm_ops i915_pm_ops = {
 950         .suspend = i915_pm_suspend,
 951         .resume = i915_pm_resume,
 952         .freeze = i915_pm_freeze,
 953         .thaw = i915_pm_thaw,
 954         .poweroff = i915_pm_poweroff,
 955         .restore = i915_pm_resume,
 956         .runtime_suspend = i915_runtime_suspend,
 957         .runtime_resume = i915_runtime_resume,
 958 };
 959
 960 static const struct vm_operations_struct i915_gem_vm_ops = {
 961         .fault = i915_gem_fault,
 962         .open = drm_gem_vm_open,
 963         .close = drm_gem_vm_close,
 964 };
 965
 966 static const struct file_operations i915_driver_fops = {
 967         .owner = THIS_MODULE,
 968         .open = drm_open,
 969         .release = drm_release,
 970         .unlocked_ioctl = drm_ioctl,
 971         .mmap = drm_gem_mmap,
 972         .poll = drm_poll,
 973         .read = drm_read,
 974 #ifdef CONFIG_COMPAT
 975         .compat_ioctl = i915_compat_ioctl,
 976 #endif
 977         .llseek = noop_llseek,
 978 };
 979
 980 static struct drm_driver driver = {
 981         /* Don't use MTRRs here; the Xserver or userspace app should
 982          * deal with them for Intel hardware.
 983          */
 984         .driver_features =
 985             DRIVER_USE_AGP |
 986             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 987             DRIVER_RENDER,
 988         .load = i915_driver_load,
 989         .unload = i915_driver_unload,
 990         .open = i915_driver_open,
 991         .lastclose = i915_driver_lastclose,
 992         .preclose = i915_driver_preclose,
 993         .postclose = i915_driver_postclose,
 994
 995         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 996         .suspend = i915_suspend,
 997         .resume = i915_resume,
 998
 999         .device_is_agp = i915_driver_device_is_agp,
1000         .master_create = i915_master_create,
1001         .master_destroy = i915_master_destroy,
1002 #if defined(CONFIG_DEBUG_FS)
1003         .debugfs_init = i915_debugfs_init,
1004         .debugfs_cleanup = i915_debugfs_cleanup,
1005 #endif
1006         .gem_free_object = i915_gem_free_object,
1007         .gem_vm_ops = &i915_gem_vm_ops,
1008
1009         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1010         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1011         .gem_prime_export = i915_gem_prime_export,
1012         .gem_prime_import = i915_gem_prime_import,
1013
1014         .dumb_create = i915_gem_dumb_create,
1015         .dumb_map_offset = i915_gem_mmap_gtt,
1016         .dumb_destroy = drm_gem_dumb_destroy,
1017         .ioctls = i915_ioctls,
1018         .fops = &i915_driver_fops,
1019         .name = DRIVER_NAME,
1020         .desc = DRIVER_DESC,
1021         .date = DRIVER_DATE,
1022         .major = DRIVER_MAJOR,
1023         .minor = DRIVER_MINOR,
1024         .patchlevel = DRIVER_PATCHLEVEL,
1025 };
1026
1027 static struct pci_driver i915_pci_driver = {
1028         .name = DRIVER_NAME,
1029         .id_table = pciidlist,
1030         .probe = i915_pci_probe,
1031         .remove = i915_pci_remove,
1032         .driver.pm = &i915_pm_ops,
1033 };
1034
1035 static int __init i915_init(void)
1036 {
1037         driver.num_ioctls = i915_max_ioctl;
1038
1039         /*
1040          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1041          * explicitly disabled with the module pararmeter.
1042          *
1043          * Otherwise, just follow the parameter (defaulting to off).
1044          *
1045          * Allow optional vga_text_mode_force boot option to override
1046          * the default behavior.
1047          */
1048 #if defined(CONFIG_DRM_I915_KMS)
1049         if (i915_modeset != 0)
1050                 driver.driver_features |= DRIVER_MODESET;
1051 #endif
1052         if (i915_modeset == 1)
1053                 driver.driver_features |= DRIVER_MODESET;
1054
1055 #ifdef CONFIG_VGA_CONSOLE
1056         if (vgacon_text_force() && i915_modeset == -1)
1057                 driver.driver_features &= ~DRIVER_MODESET;
1058 #endif
1059
1060         if (!(driver.driver_features & DRIVER_MODESET)) {
1061                 driver.get_vblank_timestamp = NULL;
1062 #ifndef CONFIG_DRM_I915_UMS
1063                 /* Silently fail loading to not upset userspace. */
1064                 return 0;
1065 #endif
1066         }
1067
1068         return drm_pci_init(&driver, &i915_pci_driver);
1069 }
1070
1071 static void __exit i915_exit(void)
1072 {
1073 #ifndef CONFIG_DRM_I915_UMS
1074         if (!(driver.driver_features & DRIVER_MODESET))
1075                 return; /* Never loaded a driver. */
1076 #endif
1077
1078         drm_pci_exit(&driver, &i915_pci_driver);
1079 }
1080
1081 module_init(i915_init);
1082 module_exit(i915_exit);
1083
1084 MODULE_AUTHOR(DRIVER_AUTHOR);
1085 MODULE_DESCRIPTION(DRIVER_DESC);
1086 MODULE_LICENSE("GPL and additional rights");