bbe1a5d56480b52a396a7b3160e91cac332e2016
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42 #include <acpi/video.h>
43
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_ioctl.h>
46 #include <drm/drm_irq.h>
47 #include <drm/drm_probe_helper.h>
48 #include <drm/i915_drm.h>
49
50 #include "i915_drv.h"
51 #include "i915_trace.h"
52 #include "i915_pmu.h"
53 #include "i915_reset.h"
54 #include "i915_query.h"
55 #include "i915_vgpu.h"
56 #include "intel_drv.h"
57 #include "intel_uc.h"
58 #include "intel_workarounds.h"
59
60 static struct drm_driver driver;
61
62 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
63 static unsigned int i915_load_fail_count;
64
65 bool __i915_inject_load_failure(const char *func, int line)
66 {
67         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
68                 return false;
69
70         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
71                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
72                          i915_modparams.inject_load_failure, func, line);
73                 i915_modparams.inject_load_failure = 0;
74                 return true;
75         }
76
77         return false;
78 }
79
80 bool i915_error_injected(void)
81 {
82         return i915_load_fail_count && !i915_modparams.inject_load_failure;
83 }
84
85 #endif
86
87 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
88 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
89                     "providing the dmesg log by booting with drm.debug=0xf"
90
91 void
92 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
93               const char *fmt, ...)
94 {
95         static bool shown_bug_once;
96         struct device *kdev = dev_priv->drm.dev;
97         bool is_error = level[1] <= KERN_ERR[1];
98         bool is_debug = level[1] == KERN_DEBUG[1];
99         struct va_format vaf;
100         va_list args;
101
102         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
103                 return;
104
105         va_start(args, fmt);
106
107         vaf.fmt = fmt;
108         vaf.va = &args;
109
110         if (is_error)
111                 dev_printk(level, kdev, "%pV", &vaf);
112         else
113                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
114                            __builtin_return_address(0), &vaf);
115
116         va_end(args);
117
118         if (is_error && !shown_bug_once) {
119                 /*
120                  * Ask the user to file a bug report for the error, except
121                  * if they may have caused the bug by fiddling with unsafe
122                  * module parameters.
123                  */
124                 if (!test_taint(TAINT_USER))
125                         dev_notice(kdev, "%s", FDO_BUG_MSG);
126                 shown_bug_once = true;
127         }
128 }
129
130 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
131 static enum intel_pch
132 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
133 {
134         switch (id) {
135         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
136                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
137                 WARN_ON(!IS_GEN(dev_priv, 5));
138                 return PCH_IBX;
139         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
140                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
141                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
142                 return PCH_CPT;
143         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
144                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
145                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
146                 /* PantherPoint is CPT compatible */
147                 return PCH_CPT;
148         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
149                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
150                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
151                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
152                 return PCH_LPT;
153         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
154                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
155                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
156                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
157                 return PCH_LPT;
158         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
159                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
160                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
161                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
162                 /* WildcatPoint is LPT compatible */
163                 return PCH_LPT;
164         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
165                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
166                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
167                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
168                 /* WildcatPoint is LPT compatible */
169                 return PCH_LPT;
170         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
171                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
173                 return PCH_SPT;
174         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
175                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
177                 return PCH_SPT;
178         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
179                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
180                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
181                         !IS_COFFEELAKE(dev_priv));
182                 return PCH_KBP;
183         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
184                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
186                 return PCH_CNP;
187         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
188                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
189                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
190                 return PCH_CNP;
191         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
192                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
193                 WARN_ON(!IS_COFFEELAKE(dev_priv));
194                 /* CometPoint is CNP Compatible */
195                 return PCH_CNP;
196         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
197                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
198                 WARN_ON(!IS_ICELAKE(dev_priv));
199                 return PCH_ICP;
200         default:
201                 return PCH_NONE;
202         }
203 }
204
205 static bool intel_is_virt_pch(unsigned short id,
206                               unsigned short svendor, unsigned short sdevice)
207 {
208         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
209                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
210                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
211                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
212                  sdevice == PCI_SUBDEVICE_ID_QEMU));
213 }
214
215 static unsigned short
216 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
217 {
218         unsigned short id = 0;
219
220         /*
221          * In a virtualized passthrough environment we can be in a
222          * setup where the ISA bridge is not able to be passed through.
223          * In this case, a south bridge can be emulated and we have to
224          * make an educated guess as to which PCH is really there.
225          */
226
227         if (IS_ICELAKE(dev_priv))
228                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
229         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
231         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
232                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
233         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
234                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
235         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
236                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
237         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
238                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
239         else if (IS_GEN(dev_priv, 5))
240                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
241
242         if (id)
243                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
244         else
245                 DRM_DEBUG_KMS("Assuming no PCH\n");
246
247         return id;
248 }
249
250 static void intel_detect_pch(struct drm_i915_private *dev_priv)
251 {
252         struct pci_dev *pch = NULL;
253
254         /*
255          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
256          * make graphics device passthrough work easy for VMM, that only
257          * need to expose ISA bridge to let driver know the real hardware
258          * underneath. This is a requirement from virtualization team.
259          *
260          * In some virtualized environments (e.g. XEN), there is irrelevant
261          * ISA bridge in the system. To work reliably, we should scan trhough
262          * all the ISA bridge devices and check for the first match, instead
263          * of only checking the first one.
264          */
265         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
266                 unsigned short id;
267                 enum intel_pch pch_type;
268
269                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
270                         continue;
271
272                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
273
274                 pch_type = intel_pch_type(dev_priv, id);
275                 if (pch_type != PCH_NONE) {
276                         dev_priv->pch_type = pch_type;
277                         dev_priv->pch_id = id;
278                         break;
279                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
280                                          pch->subsystem_device)) {
281                         id = intel_virt_detect_pch(dev_priv);
282                         pch_type = intel_pch_type(dev_priv, id);
283
284                         /* Sanity check virtual PCH id */
285                         if (WARN_ON(id && pch_type == PCH_NONE))
286                                 id = 0;
287
288                         dev_priv->pch_type = pch_type;
289                         dev_priv->pch_id = id;
290                         break;
291                 }
292         }
293
294         /*
295          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
296          * display.
297          */
298         if (pch && !HAS_DISPLAY(dev_priv)) {
299                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
300                 dev_priv->pch_type = PCH_NOP;
301                 dev_priv->pch_id = 0;
302         }
303
304         if (!pch)
305                 DRM_DEBUG_KMS("No PCH found.\n");
306
307         pci_dev_put(pch);
308 }
309
310 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
311                                struct drm_file *file_priv)
312 {
313         struct drm_i915_private *dev_priv = to_i915(dev);
314         struct pci_dev *pdev = dev_priv->drm.pdev;
315         drm_i915_getparam_t *param = data;
316         int value;
317
318         switch (param->param) {
319         case I915_PARAM_IRQ_ACTIVE:
320         case I915_PARAM_ALLOW_BATCHBUFFER:
321         case I915_PARAM_LAST_DISPATCH:
322         case I915_PARAM_HAS_EXEC_CONSTANTS:
323                 /* Reject all old ums/dri params. */
324                 return -ENODEV;
325         case I915_PARAM_CHIPSET_ID:
326                 value = pdev->device;
327                 break;
328         case I915_PARAM_REVISION:
329                 value = pdev->revision;
330                 break;
331         case I915_PARAM_NUM_FENCES_AVAIL:
332                 value = dev_priv->num_fence_regs;
333                 break;
334         case I915_PARAM_HAS_OVERLAY:
335                 value = dev_priv->overlay ? 1 : 0;
336                 break;
337         case I915_PARAM_HAS_BSD:
338                 value = !!dev_priv->engine[VCS0];
339                 break;
340         case I915_PARAM_HAS_BLT:
341                 value = !!dev_priv->engine[BCS0];
342                 break;
343         case I915_PARAM_HAS_VEBOX:
344                 value = !!dev_priv->engine[VECS0];
345                 break;
346         case I915_PARAM_HAS_BSD2:
347                 value = !!dev_priv->engine[VCS1];
348                 break;
349         case I915_PARAM_HAS_LLC:
350                 value = HAS_LLC(dev_priv);
351                 break;
352         case I915_PARAM_HAS_WT:
353                 value = HAS_WT(dev_priv);
354                 break;
355         case I915_PARAM_HAS_ALIASING_PPGTT:
356                 value = INTEL_PPGTT(dev_priv);
357                 break;
358         case I915_PARAM_HAS_SEMAPHORES:
359                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
360                 break;
361         case I915_PARAM_HAS_SECURE_BATCHES:
362                 value = capable(CAP_SYS_ADMIN);
363                 break;
364         case I915_PARAM_CMD_PARSER_VERSION:
365                 value = i915_cmd_parser_get_version(dev_priv);
366                 break;
367         case I915_PARAM_SUBSLICE_TOTAL:
368                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
369                 if (!value)
370                         return -ENODEV;
371                 break;
372         case I915_PARAM_EU_TOTAL:
373                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
374                 if (!value)
375                         return -ENODEV;
376                 break;
377         case I915_PARAM_HAS_GPU_RESET:
378                 value = i915_modparams.enable_hangcheck &&
379                         intel_has_gpu_reset(dev_priv);
380                 if (value && intel_has_reset_engine(dev_priv))
381                         value = 2;
382                 break;
383         case I915_PARAM_HAS_RESOURCE_STREAMER:
384                 value = 0;
385                 break;
386         case I915_PARAM_HAS_POOLED_EU:
387                 value = HAS_POOLED_EU(dev_priv);
388                 break;
389         case I915_PARAM_MIN_EU_IN_POOL:
390                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
391                 break;
392         case I915_PARAM_HUC_STATUS:
393                 value = intel_huc_check_status(&dev_priv->huc);
394                 if (value < 0)
395                         return value;
396                 break;
397         case I915_PARAM_MMAP_GTT_VERSION:
398                 /* Though we've started our numbering from 1, and so class all
399                  * earlier versions as 0, in effect their value is undefined as
400                  * the ioctl will report EINVAL for the unknown param!
401                  */
402                 value = i915_gem_mmap_gtt_version();
403                 break;
404         case I915_PARAM_HAS_SCHEDULER:
405                 value = dev_priv->caps.scheduler;
406                 break;
407
408         case I915_PARAM_MMAP_VERSION:
409                 /* Remember to bump this if the version changes! */
410         case I915_PARAM_HAS_GEM:
411         case I915_PARAM_HAS_PAGEFLIPPING:
412         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
413         case I915_PARAM_HAS_RELAXED_FENCING:
414         case I915_PARAM_HAS_COHERENT_RINGS:
415         case I915_PARAM_HAS_RELAXED_DELTA:
416         case I915_PARAM_HAS_GEN7_SOL_RESET:
417         case I915_PARAM_HAS_WAIT_TIMEOUT:
418         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
419         case I915_PARAM_HAS_PINNED_BATCHES:
420         case I915_PARAM_HAS_EXEC_NO_RELOC:
421         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
422         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
423         case I915_PARAM_HAS_EXEC_SOFTPIN:
424         case I915_PARAM_HAS_EXEC_ASYNC:
425         case I915_PARAM_HAS_EXEC_FENCE:
426         case I915_PARAM_HAS_EXEC_CAPTURE:
427         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
428         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
429                 /* For the time being all of these are always true;
430                  * if some supported hardware does not have one of these
431                  * features this value needs to be provided from
432                  * INTEL_INFO(), a feature macro, or similar.
433                  */
434                 value = 1;
435                 break;
436         case I915_PARAM_HAS_CONTEXT_ISOLATION:
437                 value = intel_engines_has_context_isolation(dev_priv);
438                 break;
439         case I915_PARAM_SLICE_MASK:
440                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
441                 if (!value)
442                         return -ENODEV;
443                 break;
444         case I915_PARAM_SUBSLICE_MASK:
445                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
446                 if (!value)
447                         return -ENODEV;
448                 break;
449         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
450                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
451                 break;
452         case I915_PARAM_MMAP_GTT_COHERENT:
453                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
454                 break;
455         default:
456                 DRM_DEBUG("Unknown parameter %d\n", param->param);
457                 return -EINVAL;
458         }
459
460         if (put_user(value, param->value))
461                 return -EFAULT;
462
463         return 0;
464 }
465
466 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
467 {
468         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
469
470         dev_priv->bridge_dev =
471                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
472         if (!dev_priv->bridge_dev) {
473                 DRM_ERROR("bridge device not found\n");
474                 return -1;
475         }
476         return 0;
477 }
478
479 /* Allocate space for the MCH regs if needed, return nonzero on error */
480 static int
481 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
482 {
483         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
484         u32 temp_lo, temp_hi = 0;
485         u64 mchbar_addr;
486         int ret;
487
488         if (INTEL_GEN(dev_priv) >= 4)
489                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
490         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
491         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
492
493         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
494 #ifdef CONFIG_PNP
495         if (mchbar_addr &&
496             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
497                 return 0;
498 #endif
499
500         /* Get some space for it */
501         dev_priv->mch_res.name = "i915 MCHBAR";
502         dev_priv->mch_res.flags = IORESOURCE_MEM;
503         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
504                                      &dev_priv->mch_res,
505                                      MCHBAR_SIZE, MCHBAR_SIZE,
506                                      PCIBIOS_MIN_MEM,
507                                      0, pcibios_align_resource,
508                                      dev_priv->bridge_dev);
509         if (ret) {
510                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
511                 dev_priv->mch_res.start = 0;
512                 return ret;
513         }
514
515         if (INTEL_GEN(dev_priv) >= 4)
516                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
517                                        upper_32_bits(dev_priv->mch_res.start));
518
519         pci_write_config_dword(dev_priv->bridge_dev, reg,
520                                lower_32_bits(dev_priv->mch_res.start));
521         return 0;
522 }
523
524 /* Setup MCHBAR if possible, return true if we should disable it again */
525 static void
526 intel_setup_mchbar(struct drm_i915_private *dev_priv)
527 {
528         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
529         u32 temp;
530         bool enabled;
531
532         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
533                 return;
534
535         dev_priv->mchbar_need_disable = false;
536
537         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
538                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
539                 enabled = !!(temp & DEVEN_MCHBAR_EN);
540         } else {
541                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
542                 enabled = temp & 1;
543         }
544
545         /* If it's already enabled, don't have to do anything */
546         if (enabled)
547                 return;
548
549         if (intel_alloc_mchbar_resource(dev_priv))
550                 return;
551
552         dev_priv->mchbar_need_disable = true;
553
554         /* Space is allocated or reserved, so enable it. */
555         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
556                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
557                                        temp | DEVEN_MCHBAR_EN);
558         } else {
559                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
560                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
561         }
562 }
563
564 static void
565 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
566 {
567         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
568
569         if (dev_priv->mchbar_need_disable) {
570                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
571                         u32 deven_val;
572
573                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
574                                               &deven_val);
575                         deven_val &= ~DEVEN_MCHBAR_EN;
576                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
577                                                deven_val);
578                 } else {
579                         u32 mchbar_val;
580
581                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
582                                               &mchbar_val);
583                         mchbar_val &= ~1;
584                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
585                                                mchbar_val);
586                 }
587         }
588
589         if (dev_priv->mch_res.start)
590                 release_resource(&dev_priv->mch_res);
591 }
592
593 /* true = enable decode, false = disable decoder */
594 static unsigned int i915_vga_set_decode(void *cookie, bool state)
595 {
596         struct drm_i915_private *dev_priv = cookie;
597
598         intel_modeset_vga_set_state(dev_priv, state);
599         if (state)
600                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
601                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
602         else
603                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
604 }
605
606 static int i915_resume_switcheroo(struct drm_device *dev);
607 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
608
609 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
610 {
611         struct drm_device *dev = pci_get_drvdata(pdev);
612         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
613
614         if (state == VGA_SWITCHEROO_ON) {
615                 pr_info("switched on\n");
616                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
617                 /* i915 resume handler doesn't set to D0 */
618                 pci_set_power_state(pdev, PCI_D0);
619                 i915_resume_switcheroo(dev);
620                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
621         } else {
622                 pr_info("switched off\n");
623                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
624                 i915_suspend_switcheroo(dev, pmm);
625                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
626         }
627 }
628
629 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
630 {
631         struct drm_device *dev = pci_get_drvdata(pdev);
632
633         /*
634          * FIXME: open_count is protected by drm_global_mutex but that would lead to
635          * locking inversion with the driver load path. And the access here is
636          * completely racy anyway. So don't bother with locking for now.
637          */
638         return dev->open_count == 0;
639 }
640
641 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
642         .set_gpu_state = i915_switcheroo_set_state,
643         .reprobe = NULL,
644         .can_switch = i915_switcheroo_can_switch,
645 };
646
647 static int i915_load_modeset_init(struct drm_device *dev)
648 {
649         struct drm_i915_private *dev_priv = to_i915(dev);
650         struct pci_dev *pdev = dev_priv->drm.pdev;
651         int ret;
652
653         if (i915_inject_load_failure())
654                 return -ENODEV;
655
656         if (HAS_DISPLAY(dev_priv)) {
657                 ret = drm_vblank_init(&dev_priv->drm,
658                                       INTEL_INFO(dev_priv)->num_pipes);
659                 if (ret)
660                         goto out;
661         }
662
663         intel_bios_init(dev_priv);
664
665         /* If we have > 1 VGA cards, then we need to arbitrate access
666          * to the common VGA resources.
667          *
668          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
669          * then we do not take part in VGA arbitration and the
670          * vga_client_register() fails with -ENODEV.
671          */
672         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
673         if (ret && ret != -ENODEV)
674                 goto out;
675
676         intel_register_dsm_handler();
677
678         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
679         if (ret)
680                 goto cleanup_vga_client;
681
682         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
683         intel_update_rawclk(dev_priv);
684
685         intel_power_domains_init_hw(dev_priv, false);
686
687         intel_csr_ucode_init(dev_priv);
688
689         ret = intel_irq_install(dev_priv);
690         if (ret)
691                 goto cleanup_csr;
692
693         intel_setup_gmbus(dev_priv);
694
695         /* Important: The output setup functions called by modeset_init need
696          * working irqs for e.g. gmbus and dp aux transfers. */
697         ret = intel_modeset_init(dev);
698         if (ret)
699                 goto cleanup_irq;
700
701         ret = i915_gem_init(dev_priv);
702         if (ret)
703                 goto cleanup_modeset;
704
705         intel_overlay_setup(dev_priv);
706
707         if (!HAS_DISPLAY(dev_priv))
708                 return 0;
709
710         ret = intel_fbdev_init(dev);
711         if (ret)
712                 goto cleanup_gem;
713
714         /* Only enable hotplug handling once the fbdev is fully set up. */
715         intel_hpd_init(dev_priv);
716
717         intel_init_ipc(dev_priv);
718
719         return 0;
720
721 cleanup_gem:
722         i915_gem_suspend(dev_priv);
723         i915_gem_fini(dev_priv);
724 cleanup_modeset:
725         intel_modeset_cleanup(dev);
726 cleanup_irq:
727         drm_irq_uninstall(dev);
728         intel_teardown_gmbus(dev_priv);
729 cleanup_csr:
730         intel_csr_ucode_fini(dev_priv);
731         intel_power_domains_fini_hw(dev_priv);
732         vga_switcheroo_unregister_client(pdev);
733 cleanup_vga_client:
734         vga_client_register(pdev, NULL, NULL, NULL);
735 out:
736         return ret;
737 }
738
739 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
740 {
741         struct apertures_struct *ap;
742         struct pci_dev *pdev = dev_priv->drm.pdev;
743         struct i915_ggtt *ggtt = &dev_priv->ggtt;
744         bool primary;
745         int ret;
746
747         ap = alloc_apertures(1);
748         if (!ap)
749                 return -ENOMEM;
750
751         ap->ranges[0].base = ggtt->gmadr.start;
752         ap->ranges[0].size = ggtt->mappable_end;
753
754         primary =
755                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
756
757         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
758
759         kfree(ap);
760
761         return ret;
762 }
763
764 static void intel_init_dpio(struct drm_i915_private *dev_priv)
765 {
766         /*
767          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
768          * CHV x1 PHY (DP/HDMI D)
769          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
770          */
771         if (IS_CHERRYVIEW(dev_priv)) {
772                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
773                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
774         } else if (IS_VALLEYVIEW(dev_priv)) {
775                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
776         }
777 }
778
779 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
780 {
781         /*
782          * The i915 workqueue is primarily used for batched retirement of
783          * requests (and thus managing bo) once the task has been completed
784          * by the GPU. i915_retire_requests() is called directly when we
785          * need high-priority retirement, such as waiting for an explicit
786          * bo.
787          *
788          * It is also used for periodic low-priority events, such as
789          * idle-timers and recording error state.
790          *
791          * All tasks on the workqueue are expected to acquire the dev mutex
792          * so there is no point in running more than one instance of the
793          * workqueue at any time.  Use an ordered one.
794          */
795         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
796         if (dev_priv->wq == NULL)
797                 goto out_err;
798
799         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
800         if (dev_priv->hotplug.dp_wq == NULL)
801                 goto out_free_wq;
802
803         return 0;
804
805 out_free_wq:
806         destroy_workqueue(dev_priv->wq);
807 out_err:
808         DRM_ERROR("Failed to allocate workqueues.\n");
809
810         return -ENOMEM;
811 }
812
813 static void i915_engines_cleanup(struct drm_i915_private *i915)
814 {
815         struct intel_engine_cs *engine;
816         enum intel_engine_id id;
817
818         for_each_engine(engine, i915, id)
819                 kfree(engine);
820 }
821
822 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
823 {
824         destroy_workqueue(dev_priv->hotplug.dp_wq);
825         destroy_workqueue(dev_priv->wq);
826 }
827
828 /*
829  * We don't keep the workarounds for pre-production hardware, so we expect our
830  * driver to fail on these machines in one way or another. A little warning on
831  * dmesg may help both the user and the bug triagers.
832  *
833  * Our policy for removing pre-production workarounds is to keep the
834  * current gen workarounds as a guide to the bring-up of the next gen
835  * (workarounds have a habit of persisting!). Anything older than that
836  * should be removed along with the complications they introduce.
837  */
838 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
839 {
840         bool pre = false;
841
842         pre |= IS_HSW_EARLY_SDV(dev_priv);
843         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
844         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
845         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
846
847         if (pre) {
848                 DRM_ERROR("This is a pre-production stepping. "
849                           "It may not be fully functional.\n");
850                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
851         }
852 }
853
854 /**
855  * i915_driver_init_early - setup state not requiring device access
856  * @dev_priv: device private
857  *
858  * Initialize everything that is a "SW-only" state, that is state not
859  * requiring accessing the device or exposing the driver via kernel internal
860  * or userspace interfaces. Example steps belonging here: lock initialization,
861  * system memory allocation, setting up device specific attributes and
862  * function hooks not requiring accessing the device.
863  */
864 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
865 {
866         int ret = 0;
867
868         if (i915_inject_load_failure())
869                 return -ENODEV;
870
871         spin_lock_init(&dev_priv->irq_lock);
872         spin_lock_init(&dev_priv->gpu_error.lock);
873         mutex_init(&dev_priv->backlight_lock);
874         spin_lock_init(&dev_priv->uncore.lock);
875
876         mutex_init(&dev_priv->sb_lock);
877         mutex_init(&dev_priv->av_mutex);
878         mutex_init(&dev_priv->wm.wm_mutex);
879         mutex_init(&dev_priv->pps_mutex);
880         mutex_init(&dev_priv->hdcp_comp_mutex);
881
882         i915_memcpy_init_early(dev_priv);
883         intel_runtime_pm_init_early(dev_priv);
884
885         ret = i915_workqueues_init(dev_priv);
886         if (ret < 0)
887                 goto err_engines;
888
889         ret = i915_gem_init_early(dev_priv);
890         if (ret < 0)
891                 goto err_workqueues;
892
893         /* This must be called before any calls to HAS_PCH_* */
894         intel_detect_pch(dev_priv);
895
896         intel_wopcm_init_early(&dev_priv->wopcm);
897         intel_uc_init_early(dev_priv);
898         intel_pm_setup(dev_priv);
899         intel_init_dpio(dev_priv);
900         ret = intel_power_domains_init(dev_priv);
901         if (ret < 0)
902                 goto err_uc;
903         intel_irq_init(dev_priv);
904         intel_hangcheck_init(dev_priv);
905         intel_init_display_hooks(dev_priv);
906         intel_init_clock_gating_hooks(dev_priv);
907         intel_init_audio_hooks(dev_priv);
908         intel_display_crc_init(dev_priv);
909
910         intel_detect_preproduction_hw(dev_priv);
911
912         return 0;
913
914 err_uc:
915         intel_uc_cleanup_early(dev_priv);
916         i915_gem_cleanup_early(dev_priv);
917 err_workqueues:
918         i915_workqueues_cleanup(dev_priv);
919 err_engines:
920         i915_engines_cleanup(dev_priv);
921         return ret;
922 }
923
924 /**
925  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
926  * @dev_priv: device private
927  */
928 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
929 {
930         intel_irq_fini(dev_priv);
931         intel_power_domains_cleanup(dev_priv);
932         intel_uc_cleanup_early(dev_priv);
933         i915_gem_cleanup_early(dev_priv);
934         i915_workqueues_cleanup(dev_priv);
935         i915_engines_cleanup(dev_priv);
936 }
937
938 /**
939  * i915_driver_init_mmio - setup device MMIO
940  * @dev_priv: device private
941  *
942  * Setup minimal device state necessary for MMIO accesses later in the
943  * initialization sequence. The setup here should avoid any other device-wide
944  * side effects or exposing the driver via kernel internal or user space
945  * interfaces.
946  */
947 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
948 {
949         int ret;
950
951         if (i915_inject_load_failure())
952                 return -ENODEV;
953
954         if (i915_get_bridge_dev(dev_priv))
955                 return -EIO;
956
957         ret = intel_uncore_init(&dev_priv->uncore);
958         if (ret < 0)
959                 goto err_bridge;
960
961         /* Try to make sure MCHBAR is enabled before poking at it */
962         intel_setup_mchbar(dev_priv);
963
964         intel_device_info_init_mmio(dev_priv);
965
966         intel_uncore_prune(&dev_priv->uncore);
967
968         intel_uc_init_mmio(dev_priv);
969
970         ret = intel_engines_init_mmio(dev_priv);
971         if (ret)
972                 goto err_uncore;
973
974         i915_gem_init_mmio(dev_priv);
975
976         return 0;
977
978 err_uncore:
979         intel_teardown_mchbar(dev_priv);
980         intel_uncore_fini(&dev_priv->uncore);
981 err_bridge:
982         pci_dev_put(dev_priv->bridge_dev);
983
984         return ret;
985 }
986
987 /**
988  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
989  * @dev_priv: device private
990  */
991 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
992 {
993         intel_teardown_mchbar(dev_priv);
994         intel_uncore_fini(&dev_priv->uncore);
995         pci_dev_put(dev_priv->bridge_dev);
996 }
997
998 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
999 {
1000         intel_gvt_sanitize_options(dev_priv);
1001 }
1002
1003 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1004
1005 static const char *intel_dram_type_str(enum intel_dram_type type)
1006 {
1007         static const char * const str[] = {
1008                 DRAM_TYPE_STR(UNKNOWN),
1009                 DRAM_TYPE_STR(DDR3),
1010                 DRAM_TYPE_STR(DDR4),
1011                 DRAM_TYPE_STR(LPDDR3),
1012                 DRAM_TYPE_STR(LPDDR4),
1013         };
1014
1015         if (type >= ARRAY_SIZE(str))
1016                 type = INTEL_DRAM_UNKNOWN;
1017
1018         return str[type];
1019 }
1020
1021 #undef DRAM_TYPE_STR
1022
1023 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1024 {
1025         return dimm->ranks * 64 / (dimm->width ?: 1);
1026 }
1027
1028 /* Returns total GB for the whole DIMM */
1029 static int skl_get_dimm_size(u16 val)
1030 {
1031         return val & SKL_DRAM_SIZE_MASK;
1032 }
1033
1034 static int skl_get_dimm_width(u16 val)
1035 {
1036         if (skl_get_dimm_size(val) == 0)
1037                 return 0;
1038
1039         switch (val & SKL_DRAM_WIDTH_MASK) {
1040         case SKL_DRAM_WIDTH_X8:
1041         case SKL_DRAM_WIDTH_X16:
1042         case SKL_DRAM_WIDTH_X32:
1043                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1044                 return 8 << val;
1045         default:
1046                 MISSING_CASE(val);
1047                 return 0;
1048         }
1049 }
1050
1051 static int skl_get_dimm_ranks(u16 val)
1052 {
1053         if (skl_get_dimm_size(val) == 0)
1054                 return 0;
1055
1056         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1057
1058         return val + 1;
1059 }
1060
1061 /* Returns total GB for the whole DIMM */
1062 static int cnl_get_dimm_size(u16 val)
1063 {
1064         return (val & CNL_DRAM_SIZE_MASK) / 2;
1065 }
1066
1067 static int cnl_get_dimm_width(u16 val)
1068 {
1069         if (cnl_get_dimm_size(val) == 0)
1070                 return 0;
1071
1072         switch (val & CNL_DRAM_WIDTH_MASK) {
1073         case CNL_DRAM_WIDTH_X8:
1074         case CNL_DRAM_WIDTH_X16:
1075         case CNL_DRAM_WIDTH_X32:
1076                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1077                 return 8 << val;
1078         default:
1079                 MISSING_CASE(val);
1080                 return 0;
1081         }
1082 }
1083
1084 static int cnl_get_dimm_ranks(u16 val)
1085 {
1086         if (cnl_get_dimm_size(val) == 0)
1087                 return 0;
1088
1089         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1090
1091         return val + 1;
1092 }
1093
1094 static bool
1095 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1096 {
1097         /* Convert total GB to Gb per DRAM device */
1098         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1099 }
1100
1101 static void
1102 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1103                        struct dram_dimm_info *dimm,
1104                        int channel, char dimm_name, u16 val)
1105 {
1106         if (INTEL_GEN(dev_priv) >= 10) {
1107                 dimm->size = cnl_get_dimm_size(val);
1108                 dimm->width = cnl_get_dimm_width(val);
1109                 dimm->ranks = cnl_get_dimm_ranks(val);
1110         } else {
1111                 dimm->size = skl_get_dimm_size(val);
1112                 dimm->width = skl_get_dimm_width(val);
1113                 dimm->ranks = skl_get_dimm_ranks(val);
1114         }
1115
1116         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1117                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1118                       yesno(skl_is_16gb_dimm(dimm)));
1119 }
1120
1121 static int
1122 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1123                           struct dram_channel_info *ch,
1124                           int channel, u32 val)
1125 {
1126         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1127                                channel, 'L', val & 0xffff);
1128         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1129                                channel, 'S', val >> 16);
1130
1131         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1132                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1133                 return -EINVAL;
1134         }
1135
1136         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1137                 ch->ranks = 2;
1138         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1139                 ch->ranks = 2;
1140         else
1141                 ch->ranks = 1;
1142
1143         ch->is_16gb_dimm =
1144                 skl_is_16gb_dimm(&ch->dimm_l) ||
1145                 skl_is_16gb_dimm(&ch->dimm_s);
1146
1147         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1148                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1149
1150         return 0;
1151 }
1152
1153 static bool
1154 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1155                         const struct dram_channel_info *ch1)
1156 {
1157         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1158                 (ch0->dimm_s.size == 0 ||
1159                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1160 }
1161
1162 static int
1163 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1164 {
1165         struct dram_info *dram_info = &dev_priv->dram_info;
1166         struct dram_channel_info ch0 = {}, ch1 = {};
1167         u32 val;
1168         int ret;
1169
1170         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1171         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1172         if (ret == 0)
1173                 dram_info->num_channels++;
1174
1175         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1176         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1177         if (ret == 0)
1178                 dram_info->num_channels++;
1179
1180         if (dram_info->num_channels == 0) {
1181                 DRM_INFO("Number of memory channels is zero\n");
1182                 return -EINVAL;
1183         }
1184
1185         /*
1186          * If any of the channel is single rank channel, worst case output
1187          * will be same as if single rank memory, so consider single rank
1188          * memory.
1189          */
1190         if (ch0.ranks == 1 || ch1.ranks == 1)
1191                 dram_info->ranks = 1;
1192         else
1193                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1194
1195         if (dram_info->ranks == 0) {
1196                 DRM_INFO("couldn't get memory rank information\n");
1197                 return -EINVAL;
1198         }
1199
1200         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1201
1202         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1203
1204         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1205                       yesno(dram_info->symmetric_memory));
1206         return 0;
1207 }
1208
1209 static enum intel_dram_type
1210 skl_get_dram_type(struct drm_i915_private *dev_priv)
1211 {
1212         u32 val;
1213
1214         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1215
1216         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1217         case SKL_DRAM_DDR_TYPE_DDR3:
1218                 return INTEL_DRAM_DDR3;
1219         case SKL_DRAM_DDR_TYPE_DDR4:
1220                 return INTEL_DRAM_DDR4;
1221         case SKL_DRAM_DDR_TYPE_LPDDR3:
1222                 return INTEL_DRAM_LPDDR3;
1223         case SKL_DRAM_DDR_TYPE_LPDDR4:
1224                 return INTEL_DRAM_LPDDR4;
1225         default:
1226                 MISSING_CASE(val);
1227                 return INTEL_DRAM_UNKNOWN;
1228         }
1229 }
1230
1231 static int
1232 skl_get_dram_info(struct drm_i915_private *dev_priv)
1233 {
1234         struct dram_info *dram_info = &dev_priv->dram_info;
1235         u32 mem_freq_khz, val;
1236         int ret;
1237
1238         dram_info->type = skl_get_dram_type(dev_priv);
1239         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1240
1241         ret = skl_dram_get_channels_info(dev_priv);
1242         if (ret)
1243                 return ret;
1244
1245         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1246         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1247                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1248
1249         dram_info->bandwidth_kbps = dram_info->num_channels *
1250                                                         mem_freq_khz * 8;
1251
1252         if (dram_info->bandwidth_kbps == 0) {
1253                 DRM_INFO("Couldn't get system memory bandwidth\n");
1254                 return -EINVAL;
1255         }
1256
1257         dram_info->valid = true;
1258         return 0;
1259 }
1260
1261 /* Returns Gb per DRAM device */
1262 static int bxt_get_dimm_size(u32 val)
1263 {
1264         switch (val & BXT_DRAM_SIZE_MASK) {
1265         case BXT_DRAM_SIZE_4GBIT:
1266                 return 4;
1267         case BXT_DRAM_SIZE_6GBIT:
1268                 return 6;
1269         case BXT_DRAM_SIZE_8GBIT:
1270                 return 8;
1271         case BXT_DRAM_SIZE_12GBIT:
1272                 return 12;
1273         case BXT_DRAM_SIZE_16GBIT:
1274                 return 16;
1275         default:
1276                 MISSING_CASE(val);
1277                 return 0;
1278         }
1279 }
1280
1281 static int bxt_get_dimm_width(u32 val)
1282 {
1283         if (!bxt_get_dimm_size(val))
1284                 return 0;
1285
1286         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1287
1288         return 8 << val;
1289 }
1290
1291 static int bxt_get_dimm_ranks(u32 val)
1292 {
1293         if (!bxt_get_dimm_size(val))
1294                 return 0;
1295
1296         switch (val & BXT_DRAM_RANK_MASK) {
1297         case BXT_DRAM_RANK_SINGLE:
1298                 return 1;
1299         case BXT_DRAM_RANK_DUAL:
1300                 return 2;
1301         default:
1302                 MISSING_CASE(val);
1303                 return 0;
1304         }
1305 }
1306
1307 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1308 {
1309         if (!bxt_get_dimm_size(val))
1310                 return INTEL_DRAM_UNKNOWN;
1311
1312         switch (val & BXT_DRAM_TYPE_MASK) {
1313         case BXT_DRAM_TYPE_DDR3:
1314                 return INTEL_DRAM_DDR3;
1315         case BXT_DRAM_TYPE_LPDDR3:
1316                 return INTEL_DRAM_LPDDR3;
1317         case BXT_DRAM_TYPE_DDR4:
1318                 return INTEL_DRAM_DDR4;
1319         case BXT_DRAM_TYPE_LPDDR4:
1320                 return INTEL_DRAM_LPDDR4;
1321         default:
1322                 MISSING_CASE(val);
1323                 return INTEL_DRAM_UNKNOWN;
1324         }
1325 }
1326
1327 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1328                               u32 val)
1329 {
1330         dimm->width = bxt_get_dimm_width(val);
1331         dimm->ranks = bxt_get_dimm_ranks(val);
1332
1333         /*
1334          * Size in register is Gb per DRAM device. Convert to total
1335          * GB to match the way we report this for non-LP platforms.
1336          */
1337         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1338 }
1339
1340 static int
1341 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1342 {
1343         struct dram_info *dram_info = &dev_priv->dram_info;
1344         u32 dram_channels;
1345         u32 mem_freq_khz, val;
1346         u8 num_active_channels;
1347         int i;
1348
1349         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1350         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1351                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1352
1353         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1354         num_active_channels = hweight32(dram_channels);
1355
1356         /* Each active bit represents 4-byte channel */
1357         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1358
1359         if (dram_info->bandwidth_kbps == 0) {
1360                 DRM_INFO("Couldn't get system memory bandwidth\n");
1361                 return -EINVAL;
1362         }
1363
1364         /*
1365          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1366          */
1367         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1368                 struct dram_dimm_info dimm;
1369                 enum intel_dram_type type;
1370
1371                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1372                 if (val == 0xFFFFFFFF)
1373                         continue;
1374
1375                 dram_info->num_channels++;
1376
1377                 bxt_get_dimm_info(&dimm, val);
1378                 type = bxt_get_dimm_type(val);
1379
1380                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1381                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1382                         dram_info->type != type);
1383
1384                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1385                               i - BXT_D_CR_DRP0_DUNIT_START,
1386                               dimm.size, dimm.width, dimm.ranks,
1387                               intel_dram_type_str(type));
1388
1389                 /*
1390                  * If any of the channel is single rank channel,
1391                  * worst case output will be same as if single rank
1392                  * memory, so consider single rank memory.
1393                  */
1394                 if (dram_info->ranks == 0)
1395                         dram_info->ranks = dimm.ranks;
1396                 else if (dimm.ranks == 1)
1397                         dram_info->ranks = 1;
1398
1399                 if (type != INTEL_DRAM_UNKNOWN)
1400                         dram_info->type = type;
1401         }
1402
1403         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1404             dram_info->ranks == 0) {
1405                 DRM_INFO("couldn't get memory information\n");
1406                 return -EINVAL;
1407         }
1408
1409         dram_info->valid = true;
1410         return 0;
1411 }
1412
1413 static void
1414 intel_get_dram_info(struct drm_i915_private *dev_priv)
1415 {
1416         struct dram_info *dram_info = &dev_priv->dram_info;
1417         int ret;
1418
1419         /*
1420          * Assume 16Gb DIMMs are present until proven otherwise.
1421          * This is only used for the level 0 watermark latency
1422          * w/a which does not apply to bxt/glk.
1423          */
1424         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1425
1426         if (INTEL_GEN(dev_priv) < 9)
1427                 return;
1428
1429         if (IS_GEN9_LP(dev_priv))
1430                 ret = bxt_get_dram_info(dev_priv);
1431         else
1432                 ret = skl_get_dram_info(dev_priv);
1433         if (ret)
1434                 return;
1435
1436         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1437                       dram_info->bandwidth_kbps,
1438                       dram_info->num_channels);
1439
1440         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1441                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1442 }
1443
1444 /**
1445  * i915_driver_init_hw - setup state requiring device access
1446  * @dev_priv: device private
1447  *
1448  * Setup state that requires accessing the device, but doesn't require
1449  * exposing the driver via kernel internal or userspace interfaces.
1450  */
1451 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1452 {
1453         struct pci_dev *pdev = dev_priv->drm.pdev;
1454         int ret;
1455
1456         if (i915_inject_load_failure())
1457                 return -ENODEV;
1458
1459         intel_device_info_runtime_init(dev_priv);
1460
1461         if (HAS_PPGTT(dev_priv)) {
1462                 if (intel_vgpu_active(dev_priv) &&
1463                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1464                         i915_report_error(dev_priv,
1465                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1466                         return -ENXIO;
1467                 }
1468         }
1469
1470         if (HAS_EXECLISTS(dev_priv)) {
1471                 /*
1472                  * Older GVT emulation depends upon intercepting CSB mmio,
1473                  * which we no longer use, preferring to use the HWSP cache
1474                  * instead.
1475                  */
1476                 if (intel_vgpu_active(dev_priv) &&
1477                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1478                         i915_report_error(dev_priv,
1479                                           "old vGPU host found, support for HWSP emulation required\n");
1480                         return -ENXIO;
1481                 }
1482         }
1483
1484         intel_sanitize_options(dev_priv);
1485
1486         i915_perf_init(dev_priv);
1487
1488         ret = i915_ggtt_probe_hw(dev_priv);
1489         if (ret)
1490                 goto err_perf;
1491
1492         /*
1493          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1494          * otherwise the vga fbdev driver falls over.
1495          */
1496         ret = i915_kick_out_firmware_fb(dev_priv);
1497         if (ret) {
1498                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1499                 goto err_ggtt;
1500         }
1501
1502         ret = vga_remove_vgacon(pdev);
1503         if (ret) {
1504                 DRM_ERROR("failed to remove conflicting VGA console\n");
1505                 goto err_ggtt;
1506         }
1507
1508         ret = i915_ggtt_init_hw(dev_priv);
1509         if (ret)
1510                 goto err_ggtt;
1511
1512         ret = i915_ggtt_enable_hw(dev_priv);
1513         if (ret) {
1514                 DRM_ERROR("failed to enable GGTT\n");
1515                 goto err_ggtt;
1516         }
1517
1518         pci_set_master(pdev);
1519
1520         /* overlay on gen2 is broken and can't address above 1G */
1521         if (IS_GEN(dev_priv, 2)) {
1522                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1523                 if (ret) {
1524                         DRM_ERROR("failed to set DMA mask\n");
1525
1526                         goto err_ggtt;
1527                 }
1528         }
1529
1530         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1531          * using 32bit addressing, overwriting memory if HWS is located
1532          * above 4GB.
1533          *
1534          * The documentation also mentions an issue with undefined
1535          * behaviour if any general state is accessed within a page above 4GB,
1536          * which also needs to be handled carefully.
1537          */
1538         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1539                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1540
1541                 if (ret) {
1542                         DRM_ERROR("failed to set DMA mask\n");
1543
1544                         goto err_ggtt;
1545                 }
1546         }
1547
1548         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1549                            PM_QOS_DEFAULT_VALUE);
1550
1551         intel_uncore_sanitize(dev_priv);
1552
1553         intel_gt_init_workarounds(dev_priv);
1554         i915_gem_load_init_fences(dev_priv);
1555
1556         /* On the 945G/GM, the chipset reports the MSI capability on the
1557          * integrated graphics even though the support isn't actually there
1558          * according to the published specs.  It doesn't appear to function
1559          * correctly in testing on 945G.
1560          * This may be a side effect of MSI having been made available for PEG
1561          * and the registers being closely associated.
1562          *
1563          * According to chipset errata, on the 965GM, MSI interrupts may
1564          * be lost or delayed, and was defeatured. MSI interrupts seem to
1565          * get lost on g4x as well, and interrupt delivery seems to stay
1566          * properly dead afterwards. So we'll just disable them for all
1567          * pre-gen5 chipsets.
1568          *
1569          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1570          * interrupts even when in MSI mode. This results in spurious
1571          * interrupt warnings if the legacy irq no. is shared with another
1572          * device. The kernel then disables that interrupt source and so
1573          * prevents the other device from working properly.
1574          */
1575         if (INTEL_GEN(dev_priv) >= 5) {
1576                 if (pci_enable_msi(pdev) < 0)
1577                         DRM_DEBUG_DRIVER("can't enable MSI");
1578         }
1579
1580         ret = intel_gvt_init(dev_priv);
1581         if (ret)
1582                 goto err_msi;
1583
1584         intel_opregion_setup(dev_priv);
1585         /*
1586          * Fill the dram structure to get the system raw bandwidth and
1587          * dram info. This will be used for memory latency calculation.
1588          */
1589         intel_get_dram_info(dev_priv);
1590
1591
1592         return 0;
1593
1594 err_msi:
1595         if (pdev->msi_enabled)
1596                 pci_disable_msi(pdev);
1597         pm_qos_remove_request(&dev_priv->pm_qos);
1598 err_ggtt:
1599         i915_ggtt_cleanup_hw(dev_priv);
1600 err_perf:
1601         i915_perf_fini(dev_priv);
1602         return ret;
1603 }
1604
1605 /**
1606  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1607  * @dev_priv: device private
1608  */
1609 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1610 {
1611         struct pci_dev *pdev = dev_priv->drm.pdev;
1612
1613         i915_perf_fini(dev_priv);
1614
1615         if (pdev->msi_enabled)
1616                 pci_disable_msi(pdev);
1617
1618         pm_qos_remove_request(&dev_priv->pm_qos);
1619         i915_ggtt_cleanup_hw(dev_priv);
1620 }
1621
1622 /**
1623  * i915_driver_register - register the driver with the rest of the system
1624  * @dev_priv: device private
1625  *
1626  * Perform any steps necessary to make the driver available via kernel
1627  * internal or userspace interfaces.
1628  */
1629 static void i915_driver_register(struct drm_i915_private *dev_priv)
1630 {
1631         struct drm_device *dev = &dev_priv->drm;
1632
1633         i915_gem_shrinker_register(dev_priv);
1634         i915_pmu_register(dev_priv);
1635
1636         /*
1637          * Notify a valid surface after modesetting,
1638          * when running inside a VM.
1639          */
1640         if (intel_vgpu_active(dev_priv))
1641                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1642
1643         /* Reveal our presence to userspace */
1644         if (drm_dev_register(dev, 0) == 0) {
1645                 i915_debugfs_register(dev_priv);
1646                 i915_setup_sysfs(dev_priv);
1647
1648                 /* Depends on sysfs having been initialized */
1649                 i915_perf_register(dev_priv);
1650         } else
1651                 DRM_ERROR("Failed to register driver for userspace access!\n");
1652
1653         if (HAS_DISPLAY(dev_priv)) {
1654                 /* Must be done after probing outputs */
1655                 intel_opregion_register(dev_priv);
1656                 acpi_video_register();
1657         }
1658
1659         if (IS_GEN(dev_priv, 5))
1660                 intel_gpu_ips_init(dev_priv);
1661
1662         intel_audio_init(dev_priv);
1663
1664         /*
1665          * Some ports require correctly set-up hpd registers for detection to
1666          * work properly (leading to ghost connected connector status), e.g. VGA
1667          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1668          * irqs are fully enabled. We do it last so that the async config
1669          * cannot run before the connectors are registered.
1670          */
1671         intel_fbdev_initial_config_async(dev);
1672
1673         /*
1674          * We need to coordinate the hotplugs with the asynchronous fbdev
1675          * configuration, for which we use the fbdev->async_cookie.
1676          */
1677         if (HAS_DISPLAY(dev_priv))
1678                 drm_kms_helper_poll_init(dev);
1679
1680         intel_power_domains_enable(dev_priv);
1681         intel_runtime_pm_enable(dev_priv);
1682 }
1683
1684 /**
1685  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1686  * @dev_priv: device private
1687  */
1688 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1689 {
1690         intel_runtime_pm_disable(dev_priv);
1691         intel_power_domains_disable(dev_priv);
1692
1693         intel_fbdev_unregister(dev_priv);
1694         intel_audio_deinit(dev_priv);
1695
1696         /*
1697          * After flushing the fbdev (incl. a late async config which will
1698          * have delayed queuing of a hotplug event), then flush the hotplug
1699          * events.
1700          */
1701         drm_kms_helper_poll_fini(&dev_priv->drm);
1702
1703         intel_gpu_ips_teardown();
1704         acpi_video_unregister();
1705         intel_opregion_unregister(dev_priv);
1706
1707         i915_perf_unregister(dev_priv);
1708         i915_pmu_unregister(dev_priv);
1709
1710         i915_teardown_sysfs(dev_priv);
1711         drm_dev_unregister(&dev_priv->drm);
1712
1713         i915_gem_shrinker_unregister(dev_priv);
1714 }
1715
1716 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1717 {
1718         if (drm_debug & DRM_UT_DRIVER) {
1719                 struct drm_printer p = drm_debug_printer("i915 device info:");
1720
1721                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1722                            INTEL_DEVID(dev_priv),
1723                            INTEL_REVID(dev_priv),
1724                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1725                            INTEL_GEN(dev_priv));
1726
1727                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1728                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1729         }
1730
1731         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1732                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1733         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1734                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1735         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1736                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1737 }
1738
1739 static struct drm_i915_private *
1740 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1741 {
1742         const struct intel_device_info *match_info =
1743                 (struct intel_device_info *)ent->driver_data;
1744         struct intel_device_info *device_info;
1745         struct drm_i915_private *i915;
1746         int err;
1747
1748         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1749         if (!i915)
1750                 return ERR_PTR(-ENOMEM);
1751
1752         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1753         if (err) {
1754                 kfree(i915);
1755                 return ERR_PTR(err);
1756         }
1757
1758         i915->drm.pdev = pdev;
1759         i915->drm.dev_private = i915;
1760         pci_set_drvdata(pdev, &i915->drm);
1761
1762         /* Setup the write-once "constant" device info */
1763         device_info = mkwrite_device_info(i915);
1764         memcpy(device_info, match_info, sizeof(*device_info));
1765         RUNTIME_INFO(i915)->device_id = pdev->device;
1766
1767         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1768                      BITS_PER_TYPE(device_info->platform_mask));
1769         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1770
1771         return i915;
1772 }
1773
1774 static void i915_driver_destroy(struct drm_i915_private *i915)
1775 {
1776         struct pci_dev *pdev = i915->drm.pdev;
1777
1778         drm_dev_fini(&i915->drm);
1779         kfree(i915);
1780
1781         /* And make sure we never chase our dangling pointer from pci_dev */
1782         pci_set_drvdata(pdev, NULL);
1783 }
1784
1785 /**
1786  * i915_driver_load - setup chip and create an initial config
1787  * @pdev: PCI device
1788  * @ent: matching PCI ID entry
1789  *
1790  * The driver load routine has to do several things:
1791  *   - drive output discovery via intel_modeset_init()
1792  *   - initialize the memory manager
1793  *   - allocate initial config memory
1794  *   - setup the DRM framebuffer with the allocated memory
1795  */
1796 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1797 {
1798         const struct intel_device_info *match_info =
1799                 (struct intel_device_info *)ent->driver_data;
1800         struct drm_i915_private *dev_priv;
1801         int ret;
1802
1803         dev_priv = i915_driver_create(pdev, ent);
1804         if (IS_ERR(dev_priv))
1805                 return PTR_ERR(dev_priv);
1806
1807         /* Disable nuclear pageflip by default on pre-ILK */
1808         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1809                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1810
1811         ret = pci_enable_device(pdev);
1812         if (ret)
1813                 goto out_fini;
1814
1815         ret = i915_driver_init_early(dev_priv);
1816         if (ret < 0)
1817                 goto out_pci_disable;
1818
1819         disable_rpm_wakeref_asserts(dev_priv);
1820
1821         ret = i915_driver_init_mmio(dev_priv);
1822         if (ret < 0)
1823                 goto out_runtime_pm_put;
1824
1825         ret = i915_driver_init_hw(dev_priv);
1826         if (ret < 0)
1827                 goto out_cleanup_mmio;
1828
1829         ret = i915_load_modeset_init(&dev_priv->drm);
1830         if (ret < 0)
1831                 goto out_cleanup_hw;
1832
1833         i915_driver_register(dev_priv);
1834
1835         enable_rpm_wakeref_asserts(dev_priv);
1836
1837         i915_welcome_messages(dev_priv);
1838
1839         return 0;
1840
1841 out_cleanup_hw:
1842         i915_driver_cleanup_hw(dev_priv);
1843 out_cleanup_mmio:
1844         i915_driver_cleanup_mmio(dev_priv);
1845 out_runtime_pm_put:
1846         enable_rpm_wakeref_asserts(dev_priv);
1847         i915_driver_cleanup_early(dev_priv);
1848 out_pci_disable:
1849         pci_disable_device(pdev);
1850 out_fini:
1851         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1852         i915_driver_destroy(dev_priv);
1853         return ret;
1854 }
1855
1856 void i915_driver_unload(struct drm_device *dev)
1857 {
1858         struct drm_i915_private *dev_priv = to_i915(dev);
1859         struct pci_dev *pdev = dev_priv->drm.pdev;
1860
1861         disable_rpm_wakeref_asserts(dev_priv);
1862
1863         i915_driver_unregister(dev_priv);
1864
1865         /* Flush any external code that still may be under the RCU lock */
1866         synchronize_rcu();
1867
1868         i915_gem_suspend(dev_priv);
1869
1870         drm_atomic_helper_shutdown(dev);
1871
1872         intel_gvt_cleanup(dev_priv);
1873
1874         intel_modeset_cleanup(dev);
1875
1876         intel_bios_cleanup(dev_priv);
1877
1878         vga_switcheroo_unregister_client(pdev);
1879         vga_client_register(pdev, NULL, NULL, NULL);
1880
1881         intel_csr_ucode_fini(dev_priv);
1882
1883         /* Free error state after interrupts are fully disabled. */
1884         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1885         i915_reset_error_state(dev_priv);
1886
1887         i915_gem_fini(dev_priv);
1888
1889         intel_power_domains_fini_hw(dev_priv);
1890
1891         i915_driver_cleanup_hw(dev_priv);
1892         i915_driver_cleanup_mmio(dev_priv);
1893
1894         enable_rpm_wakeref_asserts(dev_priv);
1895         intel_runtime_pm_cleanup(dev_priv);
1896 }
1897
1898 static void i915_driver_release(struct drm_device *dev)
1899 {
1900         struct drm_i915_private *dev_priv = to_i915(dev);
1901
1902         i915_driver_cleanup_early(dev_priv);
1903         i915_driver_destroy(dev_priv);
1904 }
1905
1906 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1907 {
1908         struct drm_i915_private *i915 = to_i915(dev);
1909         int ret;
1910
1911         ret = i915_gem_open(i915, file);
1912         if (ret)
1913                 return ret;
1914
1915         return 0;
1916 }
1917
1918 /**
1919  * i915_driver_lastclose - clean up after all DRM clients have exited
1920  * @dev: DRM device
1921  *
1922  * Take care of cleaning up after all DRM clients have exited.  In the
1923  * mode setting case, we want to restore the kernel's initial mode (just
1924  * in case the last client left us in a bad state).
1925  *
1926  * Additionally, in the non-mode setting case, we'll tear down the GTT
1927  * and DMA structures, since the kernel won't be using them, and clea
1928  * up any GEM state.
1929  */
1930 static void i915_driver_lastclose(struct drm_device *dev)
1931 {
1932         intel_fbdev_restore_mode(dev);
1933         vga_switcheroo_process_delayed_switch();
1934 }
1935
1936 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1937 {
1938         struct drm_i915_file_private *file_priv = file->driver_priv;
1939
1940         mutex_lock(&dev->struct_mutex);
1941         i915_gem_context_close(file);
1942         i915_gem_release(dev, file);
1943         mutex_unlock(&dev->struct_mutex);
1944
1945         kfree(file_priv);
1946 }
1947
1948 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1949 {
1950         struct drm_device *dev = &dev_priv->drm;
1951         struct intel_encoder *encoder;
1952
1953         drm_modeset_lock_all(dev);
1954         for_each_intel_encoder(dev, encoder)
1955                 if (encoder->suspend)
1956                         encoder->suspend(encoder);
1957         drm_modeset_unlock_all(dev);
1958 }
1959
1960 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1961                               bool rpm_resume);
1962 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1963
1964 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1965 {
1966 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1967         if (acpi_target_system_state() < ACPI_STATE_S3)
1968                 return true;
1969 #endif
1970         return false;
1971 }
1972
1973 static int i915_drm_prepare(struct drm_device *dev)
1974 {
1975         struct drm_i915_private *i915 = to_i915(dev);
1976
1977         /*
1978          * NB intel_display_suspend() may issue new requests after we've
1979          * ostensibly marked the GPU as ready-to-sleep here. We need to
1980          * split out that work and pull it forward so that after point,
1981          * the GPU is not woken again.
1982          */
1983         i915_gem_suspend(i915);
1984
1985         return 0;
1986 }
1987
1988 static int i915_drm_suspend(struct drm_device *dev)
1989 {
1990         struct drm_i915_private *dev_priv = to_i915(dev);
1991         struct pci_dev *pdev = dev_priv->drm.pdev;
1992         pci_power_t opregion_target_state;
1993
1994         disable_rpm_wakeref_asserts(dev_priv);
1995
1996         /* We do a lot of poking in a lot of registers, make sure they work
1997          * properly. */
1998         intel_power_domains_disable(dev_priv);
1999
2000         drm_kms_helper_poll_disable(dev);
2001
2002         pci_save_state(pdev);
2003
2004         intel_display_suspend(dev);
2005
2006         intel_dp_mst_suspend(dev_priv);
2007
2008         intel_runtime_pm_disable_interrupts(dev_priv);
2009         intel_hpd_cancel_work(dev_priv);
2010
2011         intel_suspend_encoders(dev_priv);
2012
2013         intel_suspend_hw(dev_priv);
2014
2015         i915_gem_suspend_gtt_mappings(dev_priv);
2016
2017         i915_save_state(dev_priv);
2018
2019         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2020         intel_opregion_suspend(dev_priv, opregion_target_state);
2021
2022         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2023
2024         dev_priv->suspend_count++;
2025
2026         intel_csr_ucode_suspend(dev_priv);
2027
2028         enable_rpm_wakeref_asserts(dev_priv);
2029
2030         return 0;
2031 }
2032
2033 static enum i915_drm_suspend_mode
2034 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2035 {
2036         if (hibernate)
2037                 return I915_DRM_SUSPEND_HIBERNATE;
2038
2039         if (suspend_to_idle(dev_priv))
2040                 return I915_DRM_SUSPEND_IDLE;
2041
2042         return I915_DRM_SUSPEND_MEM;
2043 }
2044
2045 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2046 {
2047         struct drm_i915_private *dev_priv = to_i915(dev);
2048         struct pci_dev *pdev = dev_priv->drm.pdev;
2049         int ret;
2050
2051         disable_rpm_wakeref_asserts(dev_priv);
2052
2053         i915_gem_suspend_late(dev_priv);
2054
2055         intel_uncore_suspend(&dev_priv->uncore);
2056
2057         intel_power_domains_suspend(dev_priv,
2058                                     get_suspend_mode(dev_priv, hibernation));
2059
2060         ret = 0;
2061         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2062                 bxt_enable_dc9(dev_priv);
2063         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2064                 hsw_enable_pc8(dev_priv);
2065         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2066                 ret = vlv_suspend_complete(dev_priv);
2067
2068         if (ret) {
2069                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2070                 intel_power_domains_resume(dev_priv);
2071
2072                 goto out;
2073         }
2074
2075         pci_disable_device(pdev);
2076         /*
2077          * During hibernation on some platforms the BIOS may try to access
2078          * the device even though it's already in D3 and hang the machine. So
2079          * leave the device in D0 on those platforms and hope the BIOS will
2080          * power down the device properly. The issue was seen on multiple old
2081          * GENs with different BIOS vendors, so having an explicit blacklist
2082          * is inpractical; apply the workaround on everything pre GEN6. The
2083          * platforms where the issue was seen:
2084          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2085          * Fujitsu FSC S7110
2086          * Acer Aspire 1830T
2087          */
2088         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2089                 pci_set_power_state(pdev, PCI_D3hot);
2090
2091 out:
2092         enable_rpm_wakeref_asserts(dev_priv);
2093         if (!dev_priv->uncore.user_forcewake.count)
2094                 intel_runtime_pm_cleanup(dev_priv);
2095
2096         return ret;
2097 }
2098
2099 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2100 {
2101         int error;
2102
2103         if (!dev) {
2104                 DRM_ERROR("dev: %p\n", dev);
2105                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2106                 return -ENODEV;
2107         }
2108
2109         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2110                          state.event != PM_EVENT_FREEZE))
2111                 return -EINVAL;
2112
2113         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2114                 return 0;
2115
2116         error = i915_drm_suspend(dev);
2117         if (error)
2118                 return error;
2119
2120         return i915_drm_suspend_late(dev, false);
2121 }
2122
2123 static int i915_drm_resume(struct drm_device *dev)
2124 {
2125         struct drm_i915_private *dev_priv = to_i915(dev);
2126         int ret;
2127
2128         disable_rpm_wakeref_asserts(dev_priv);
2129         intel_sanitize_gt_powersave(dev_priv);
2130
2131         i915_gem_sanitize(dev_priv);
2132
2133         ret = i915_ggtt_enable_hw(dev_priv);
2134         if (ret)
2135                 DRM_ERROR("failed to re-enable GGTT\n");
2136
2137         intel_csr_ucode_resume(dev_priv);
2138
2139         i915_restore_state(dev_priv);
2140         intel_pps_unlock_regs_wa(dev_priv);
2141
2142         intel_init_pch_refclk(dev_priv);
2143
2144         /*
2145          * Interrupts have to be enabled before any batches are run. If not the
2146          * GPU will hang. i915_gem_init_hw() will initiate batches to
2147          * update/restore the context.
2148          *
2149          * drm_mode_config_reset() needs AUX interrupts.
2150          *
2151          * Modeset enabling in intel_modeset_init_hw() also needs working
2152          * interrupts.
2153          */
2154         intel_runtime_pm_enable_interrupts(dev_priv);
2155
2156         drm_mode_config_reset(dev);
2157
2158         i915_gem_resume(dev_priv);
2159
2160         intel_modeset_init_hw(dev);
2161         intel_init_clock_gating(dev_priv);
2162
2163         spin_lock_irq(&dev_priv->irq_lock);
2164         if (dev_priv->display.hpd_irq_setup)
2165                 dev_priv->display.hpd_irq_setup(dev_priv);
2166         spin_unlock_irq(&dev_priv->irq_lock);
2167
2168         intel_dp_mst_resume(dev_priv);
2169
2170         intel_display_resume(dev);
2171
2172         drm_kms_helper_poll_enable(dev);
2173
2174         /*
2175          * ... but also need to make sure that hotplug processing
2176          * doesn't cause havoc. Like in the driver load code we don't
2177          * bother with the tiny race here where we might lose hotplug
2178          * notifications.
2179          * */
2180         intel_hpd_init(dev_priv);
2181
2182         intel_opregion_resume(dev_priv);
2183
2184         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2185
2186         intel_power_domains_enable(dev_priv);
2187
2188         enable_rpm_wakeref_asserts(dev_priv);
2189
2190         return 0;
2191 }
2192
2193 static int i915_drm_resume_early(struct drm_device *dev)
2194 {
2195         struct drm_i915_private *dev_priv = to_i915(dev);
2196         struct pci_dev *pdev = dev_priv->drm.pdev;
2197         int ret;
2198
2199         /*
2200          * We have a resume ordering issue with the snd-hda driver also
2201          * requiring our device to be power up. Due to the lack of a
2202          * parent/child relationship we currently solve this with an early
2203          * resume hook.
2204          *
2205          * FIXME: This should be solved with a special hdmi sink device or
2206          * similar so that power domains can be employed.
2207          */
2208
2209         /*
2210          * Note that we need to set the power state explicitly, since we
2211          * powered off the device during freeze and the PCI core won't power
2212          * it back up for us during thaw. Powering off the device during
2213          * freeze is not a hard requirement though, and during the
2214          * suspend/resume phases the PCI core makes sure we get here with the
2215          * device powered on. So in case we change our freeze logic and keep
2216          * the device powered we can also remove the following set power state
2217          * call.
2218          */
2219         ret = pci_set_power_state(pdev, PCI_D0);
2220         if (ret) {
2221                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2222                 return ret;
2223         }
2224
2225         /*
2226          * Note that pci_enable_device() first enables any parent bridge
2227          * device and only then sets the power state for this device. The
2228          * bridge enabling is a nop though, since bridge devices are resumed
2229          * first. The order of enabling power and enabling the device is
2230          * imposed by the PCI core as described above, so here we preserve the
2231          * same order for the freeze/thaw phases.
2232          *
2233          * TODO: eventually we should remove pci_disable_device() /
2234          * pci_enable_enable_device() from suspend/resume. Due to how they
2235          * depend on the device enable refcount we can't anyway depend on them
2236          * disabling/enabling the device.
2237          */
2238         if (pci_enable_device(pdev))
2239                 return -EIO;
2240
2241         pci_set_master(pdev);
2242
2243         disable_rpm_wakeref_asserts(dev_priv);
2244
2245         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2246                 ret = vlv_resume_prepare(dev_priv, false);
2247         if (ret)
2248                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2249                           ret);
2250
2251         intel_uncore_resume_early(&dev_priv->uncore);
2252
2253         i915_check_and_clear_faults(dev_priv);
2254
2255         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2256                 gen9_sanitize_dc_state(dev_priv);
2257                 bxt_disable_dc9(dev_priv);
2258         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2259                 hsw_disable_pc8(dev_priv);
2260         }
2261
2262         intel_uncore_sanitize(dev_priv);
2263
2264         intel_power_domains_resume(dev_priv);
2265
2266         intel_engines_sanitize(dev_priv, true);
2267
2268         enable_rpm_wakeref_asserts(dev_priv);
2269
2270         return ret;
2271 }
2272
2273 static int i915_resume_switcheroo(struct drm_device *dev)
2274 {
2275         int ret;
2276
2277         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2278                 return 0;
2279
2280         ret = i915_drm_resume_early(dev);
2281         if (ret)
2282                 return ret;
2283
2284         return i915_drm_resume(dev);
2285 }
2286
2287 static int i915_pm_prepare(struct device *kdev)
2288 {
2289         struct pci_dev *pdev = to_pci_dev(kdev);
2290         struct drm_device *dev = pci_get_drvdata(pdev);
2291
2292         if (!dev) {
2293                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2294                 return -ENODEV;
2295         }
2296
2297         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2298                 return 0;
2299
2300         return i915_drm_prepare(dev);
2301 }
2302
2303 static int i915_pm_suspend(struct device *kdev)
2304 {
2305         struct pci_dev *pdev = to_pci_dev(kdev);
2306         struct drm_device *dev = pci_get_drvdata(pdev);
2307
2308         if (!dev) {
2309                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2310                 return -ENODEV;
2311         }
2312
2313         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2314                 return 0;
2315
2316         return i915_drm_suspend(dev);
2317 }
2318
2319 static int i915_pm_suspend_late(struct device *kdev)
2320 {
2321         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2322
2323         /*
2324          * We have a suspend ordering issue with the snd-hda driver also
2325          * requiring our device to be power up. Due to the lack of a
2326          * parent/child relationship we currently solve this with an late
2327          * suspend hook.
2328          *
2329          * FIXME: This should be solved with a special hdmi sink device or
2330          * similar so that power domains can be employed.
2331          */
2332         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2333                 return 0;
2334
2335         return i915_drm_suspend_late(dev, false);
2336 }
2337
2338 static int i915_pm_poweroff_late(struct device *kdev)
2339 {
2340         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2341
2342         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2343                 return 0;
2344
2345         return i915_drm_suspend_late(dev, true);
2346 }
2347
2348 static int i915_pm_resume_early(struct device *kdev)
2349 {
2350         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2351
2352         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2353                 return 0;
2354
2355         return i915_drm_resume_early(dev);
2356 }
2357
2358 static int i915_pm_resume(struct device *kdev)
2359 {
2360         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2361
2362         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2363                 return 0;
2364
2365         return i915_drm_resume(dev);
2366 }
2367
2368 /* freeze: before creating the hibernation_image */
2369 static int i915_pm_freeze(struct device *kdev)
2370 {
2371         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2372         int ret;
2373
2374         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2375                 ret = i915_drm_suspend(dev);
2376                 if (ret)
2377                         return ret;
2378         }
2379
2380         ret = i915_gem_freeze(kdev_to_i915(kdev));
2381         if (ret)
2382                 return ret;
2383
2384         return 0;
2385 }
2386
2387 static int i915_pm_freeze_late(struct device *kdev)
2388 {
2389         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2390         int ret;
2391
2392         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2393                 ret = i915_drm_suspend_late(dev, true);
2394                 if (ret)
2395                         return ret;
2396         }
2397
2398         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2399         if (ret)
2400                 return ret;
2401
2402         return 0;
2403 }
2404
2405 /* thaw: called after creating the hibernation image, but before turning off. */
2406 static int i915_pm_thaw_early(struct device *kdev)
2407 {
2408         return i915_pm_resume_early(kdev);
2409 }
2410
2411 static int i915_pm_thaw(struct device *kdev)
2412 {
2413         return i915_pm_resume(kdev);
2414 }
2415
2416 /* restore: called after loading the hibernation image. */
2417 static int i915_pm_restore_early(struct device *kdev)
2418 {
2419         return i915_pm_resume_early(kdev);
2420 }
2421
2422 static int i915_pm_restore(struct device *kdev)
2423 {
2424         return i915_pm_resume(kdev);
2425 }
2426
2427 /*
2428  * Save all Gunit registers that may be lost after a D3 and a subsequent
2429  * S0i[R123] transition. The list of registers needing a save/restore is
2430  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2431  * registers in the following way:
2432  * - Driver: saved/restored by the driver
2433  * - Punit : saved/restored by the Punit firmware
2434  * - No, w/o marking: no need to save/restore, since the register is R/O or
2435  *                    used internally by the HW in a way that doesn't depend
2436  *                    keeping the content across a suspend/resume.
2437  * - Debug : used for debugging
2438  *
2439  * We save/restore all registers marked with 'Driver', with the following
2440  * exceptions:
2441  * - Registers out of use, including also registers marked with 'Debug'.
2442  *   These have no effect on the driver's operation, so we don't save/restore
2443  *   them to reduce the overhead.
2444  * - Registers that are fully setup by an initialization function called from
2445  *   the resume path. For example many clock gating and RPS/RC6 registers.
2446  * - Registers that provide the right functionality with their reset defaults.
2447  *
2448  * TODO: Except for registers that based on the above 3 criteria can be safely
2449  * ignored, we save/restore all others, practically treating the HW context as
2450  * a black-box for the driver. Further investigation is needed to reduce the
2451  * saved/restored registers even further, by following the same 3 criteria.
2452  */
2453 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2454 {
2455         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2456         int i;
2457
2458         /* GAM 0x4000-0x4770 */
2459         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2460         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2461         s->arb_mode             = I915_READ(ARB_MODE);
2462         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2463         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2464
2465         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2466                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2467
2468         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2469         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2470
2471         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2472         s->ecochk               = I915_READ(GAM_ECOCHK);
2473         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2474         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2475
2476         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2477
2478         /* MBC 0x9024-0x91D0, 0x8500 */
2479         s->g3dctl               = I915_READ(VLV_G3DCTL);
2480         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2481         s->mbctl                = I915_READ(GEN6_MBCTL);
2482
2483         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2484         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2485         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2486         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2487         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2488         s->rstctl               = I915_READ(GEN6_RSTCTL);
2489         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2490
2491         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2492         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2493         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2494         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2495         s->ecobus               = I915_READ(ECOBUS);
2496         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2497         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2498         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2499         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2500         s->rcedata              = I915_READ(VLV_RCEDATA);
2501         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2502
2503         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2504         s->gt_imr               = I915_READ(GTIMR);
2505         s->gt_ier               = I915_READ(GTIER);
2506         s->pm_imr               = I915_READ(GEN6_PMIMR);
2507         s->pm_ier               = I915_READ(GEN6_PMIER);
2508
2509         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2510                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2511
2512         /* GT SA CZ domain, 0x100000-0x138124 */
2513         s->tilectl              = I915_READ(TILECTL);
2514         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2515         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2516         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2517         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2518
2519         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2520         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2521         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2522         s->pcbr                 = I915_READ(VLV_PCBR);
2523         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2524
2525         /*
2526          * Not saving any of:
2527          * DFT,         0x9800-0x9EC0
2528          * SARB,        0xB000-0xB1FC
2529          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2530          * PCI CFG
2531          */
2532 }
2533
2534 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2535 {
2536         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2537         u32 val;
2538         int i;
2539
2540         /* GAM 0x4000-0x4770 */
2541         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2542         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2543         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2544         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2545         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2546
2547         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2548                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2549
2550         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2551         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2552
2553         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2554         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2555         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2556         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2557
2558         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2559
2560         /* MBC 0x9024-0x91D0, 0x8500 */
2561         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2562         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2563         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2564
2565         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2566         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2567         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2568         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2569         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2570         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2571         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2572
2573         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2574         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2575         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2576         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2577         I915_WRITE(ECOBUS,              s->ecobus);
2578         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2579         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2580         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2581         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2582         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2583         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2584
2585         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2586         I915_WRITE(GTIMR,               s->gt_imr);
2587         I915_WRITE(GTIER,               s->gt_ier);
2588         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2589         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2590
2591         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2592                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2593
2594         /* GT SA CZ domain, 0x100000-0x138124 */
2595         I915_WRITE(TILECTL,                     s->tilectl);
2596         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2597         /*
2598          * Preserve the GT allow wake and GFX force clock bit, they are not
2599          * be restored, as they are used to control the s0ix suspend/resume
2600          * sequence by the caller.
2601          */
2602         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2603         val &= VLV_GTLC_ALLOWWAKEREQ;
2604         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2605         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2606
2607         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2608         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2609         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2610         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2611
2612         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2613
2614         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2615         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2616         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2617         I915_WRITE(VLV_PCBR,                    s->pcbr);
2618         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2619 }
2620
2621 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2622                                   u32 mask, u32 val)
2623 {
2624         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2625         u32 reg_value;
2626         int ret;
2627
2628         /* The HW does not like us polling for PW_STATUS frequently, so
2629          * use the sleeping loop rather than risk the busy spin within
2630          * intel_wait_for_register().
2631          *
2632          * Transitioning between RC6 states should be at most 2ms (see
2633          * valleyview_enable_rps) so use a 3ms timeout.
2634          */
2635         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2636
2637         /* just trace the final value */
2638         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2639
2640         return ret;
2641 }
2642
2643 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2644 {
2645         u32 val;
2646         int err;
2647
2648         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2649         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2650         if (force_on)
2651                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2652         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2653
2654         if (!force_on)
2655                 return 0;
2656
2657         err = intel_wait_for_register(&dev_priv->uncore,
2658                                       VLV_GTLC_SURVIVABILITY_REG,
2659                                       VLV_GFX_CLK_STATUS_BIT,
2660                                       VLV_GFX_CLK_STATUS_BIT,
2661                                       20);
2662         if (err)
2663                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2664                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2665
2666         return err;
2667 }
2668
2669 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2670 {
2671         u32 mask;
2672         u32 val;
2673         int err;
2674
2675         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2676         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2677         if (allow)
2678                 val |= VLV_GTLC_ALLOWWAKEREQ;
2679         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2680         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2681
2682         mask = VLV_GTLC_ALLOWWAKEACK;
2683         val = allow ? mask : 0;
2684
2685         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2686         if (err)
2687                 DRM_ERROR("timeout disabling GT waking\n");
2688
2689         return err;
2690 }
2691
2692 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2693                                   bool wait_for_on)
2694 {
2695         u32 mask;
2696         u32 val;
2697
2698         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2699         val = wait_for_on ? mask : 0;
2700
2701         /*
2702          * RC6 transitioning can be delayed up to 2 msec (see
2703          * valleyview_enable_rps), use 3 msec for safety.
2704          *
2705          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2706          * reset and we are trying to force the machine to sleep.
2707          */
2708         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2709                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2710                                  onoff(wait_for_on));
2711 }
2712
2713 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2714 {
2715         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2716                 return;
2717
2718         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2719         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2720 }
2721
2722 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2723 {
2724         u32 mask;
2725         int err;
2726
2727         /*
2728          * Bspec defines the following GT well on flags as debug only, so
2729          * don't treat them as hard failures.
2730          */
2731         vlv_wait_for_gt_wells(dev_priv, false);
2732
2733         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2734         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2735
2736         vlv_check_no_gt_access(dev_priv);
2737
2738         err = vlv_force_gfx_clock(dev_priv, true);
2739         if (err)
2740                 goto err1;
2741
2742         err = vlv_allow_gt_wake(dev_priv, false);
2743         if (err)
2744                 goto err2;
2745
2746         if (!IS_CHERRYVIEW(dev_priv))
2747                 vlv_save_gunit_s0ix_state(dev_priv);
2748
2749         err = vlv_force_gfx_clock(dev_priv, false);
2750         if (err)
2751                 goto err2;
2752
2753         return 0;
2754
2755 err2:
2756         /* For safety always re-enable waking and disable gfx clock forcing */
2757         vlv_allow_gt_wake(dev_priv, true);
2758 err1:
2759         vlv_force_gfx_clock(dev_priv, false);
2760
2761         return err;
2762 }
2763
2764 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2765                                 bool rpm_resume)
2766 {
2767         int err;
2768         int ret;
2769
2770         /*
2771          * If any of the steps fail just try to continue, that's the best we
2772          * can do at this point. Return the first error code (which will also
2773          * leave RPM permanently disabled).
2774          */
2775         ret = vlv_force_gfx_clock(dev_priv, true);
2776
2777         if (!IS_CHERRYVIEW(dev_priv))
2778                 vlv_restore_gunit_s0ix_state(dev_priv);
2779
2780         err = vlv_allow_gt_wake(dev_priv, true);
2781         if (!ret)
2782                 ret = err;
2783
2784         err = vlv_force_gfx_clock(dev_priv, false);
2785         if (!ret)
2786                 ret = err;
2787
2788         vlv_check_no_gt_access(dev_priv);
2789
2790         if (rpm_resume)
2791                 intel_init_clock_gating(dev_priv);
2792
2793         return ret;
2794 }
2795
2796 static int intel_runtime_suspend(struct device *kdev)
2797 {
2798         struct pci_dev *pdev = to_pci_dev(kdev);
2799         struct drm_device *dev = pci_get_drvdata(pdev);
2800         struct drm_i915_private *dev_priv = to_i915(dev);
2801         int ret;
2802
2803         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2804                 return -ENODEV;
2805
2806         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2807                 return -ENODEV;
2808
2809         DRM_DEBUG_KMS("Suspending device\n");
2810
2811         disable_rpm_wakeref_asserts(dev_priv);
2812
2813         /*
2814          * We are safe here against re-faults, since the fault handler takes
2815          * an RPM reference.
2816          */
2817         i915_gem_runtime_suspend(dev_priv);
2818
2819         intel_uc_suspend(dev_priv);
2820
2821         intel_runtime_pm_disable_interrupts(dev_priv);
2822
2823         intel_uncore_suspend(&dev_priv->uncore);
2824
2825         ret = 0;
2826         if (INTEL_GEN(dev_priv) >= 11) {
2827                 icl_display_core_uninit(dev_priv);
2828                 bxt_enable_dc9(dev_priv);
2829         } else if (IS_GEN9_LP(dev_priv)) {
2830                 bxt_display_core_uninit(dev_priv);
2831                 bxt_enable_dc9(dev_priv);
2832         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2833                 hsw_enable_pc8(dev_priv);
2834         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2835                 ret = vlv_suspend_complete(dev_priv);
2836         }
2837
2838         if (ret) {
2839                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2840                 intel_uncore_runtime_resume(&dev_priv->uncore);
2841
2842                 intel_runtime_pm_enable_interrupts(dev_priv);
2843
2844                 intel_uc_resume(dev_priv);
2845
2846                 i915_gem_init_swizzling(dev_priv);
2847                 i915_gem_restore_fences(dev_priv);
2848
2849                 enable_rpm_wakeref_asserts(dev_priv);
2850
2851                 return ret;
2852         }
2853
2854         enable_rpm_wakeref_asserts(dev_priv);
2855         intel_runtime_pm_cleanup(dev_priv);
2856
2857         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2858                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2859
2860         dev_priv->runtime_pm.suspended = true;
2861
2862         /*
2863          * FIXME: We really should find a document that references the arguments
2864          * used below!
2865          */
2866         if (IS_BROADWELL(dev_priv)) {
2867                 /*
2868                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2869                  * being detected, and the call we do at intel_runtime_resume()
2870                  * won't be able to restore them. Since PCI_D3hot matches the
2871                  * actual specification and appears to be working, use it.
2872                  */
2873                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2874         } else {
2875                 /*
2876                  * current versions of firmware which depend on this opregion
2877                  * notification have repurposed the D1 definition to mean
2878                  * "runtime suspended" vs. what you would normally expect (D3)
2879                  * to distinguish it from notifications that might be sent via
2880                  * the suspend path.
2881                  */
2882                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2883         }
2884
2885         assert_forcewakes_inactive(&dev_priv->uncore);
2886
2887         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2888                 intel_hpd_poll_init(dev_priv);
2889
2890         DRM_DEBUG_KMS("Device suspended\n");
2891         return 0;
2892 }
2893
2894 static int intel_runtime_resume(struct device *kdev)
2895 {
2896         struct pci_dev *pdev = to_pci_dev(kdev);
2897         struct drm_device *dev = pci_get_drvdata(pdev);
2898         struct drm_i915_private *dev_priv = to_i915(dev);
2899         int ret = 0;
2900
2901         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2902                 return -ENODEV;
2903
2904         DRM_DEBUG_KMS("Resuming device\n");
2905
2906         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2907         disable_rpm_wakeref_asserts(dev_priv);
2908
2909         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2910         dev_priv->runtime_pm.suspended = false;
2911         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
2912                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2913
2914         if (INTEL_GEN(dev_priv) >= 11) {
2915                 bxt_disable_dc9(dev_priv);
2916                 icl_display_core_init(dev_priv, true);
2917                 if (dev_priv->csr.dmc_payload) {
2918                         if (dev_priv->csr.allowed_dc_mask &
2919                             DC_STATE_EN_UPTO_DC6)
2920                                 skl_enable_dc6(dev_priv);
2921                         else if (dev_priv->csr.allowed_dc_mask &
2922                                  DC_STATE_EN_UPTO_DC5)
2923                                 gen9_enable_dc5(dev_priv);
2924                 }
2925         } else if (IS_GEN9_LP(dev_priv)) {
2926                 bxt_disable_dc9(dev_priv);
2927                 bxt_display_core_init(dev_priv, true);
2928                 if (dev_priv->csr.dmc_payload &&
2929                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2930                         gen9_enable_dc5(dev_priv);
2931         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2932                 hsw_disable_pc8(dev_priv);
2933         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2934                 ret = vlv_resume_prepare(dev_priv, true);
2935         }
2936
2937         intel_uncore_runtime_resume(&dev_priv->uncore);
2938
2939         intel_runtime_pm_enable_interrupts(dev_priv);
2940
2941         intel_uc_resume(dev_priv);
2942
2943         /*
2944          * No point of rolling back things in case of an error, as the best
2945          * we can do is to hope that things will still work (and disable RPM).
2946          */
2947         i915_gem_init_swizzling(dev_priv);
2948         i915_gem_restore_fences(dev_priv);
2949
2950         /*
2951          * On VLV/CHV display interrupts are part of the display
2952          * power well, so hpd is reinitialized from there. For
2953          * everyone else do it here.
2954          */
2955         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2956                 intel_hpd_init(dev_priv);
2957
2958         intel_enable_ipc(dev_priv);
2959
2960         enable_rpm_wakeref_asserts(dev_priv);
2961
2962         if (ret)
2963                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2964         else
2965                 DRM_DEBUG_KMS("Device resumed\n");
2966
2967         return ret;
2968 }
2969
2970 const struct dev_pm_ops i915_pm_ops = {
2971         /*
2972          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2973          * PMSG_RESUME]
2974          */
2975         .prepare = i915_pm_prepare,
2976         .suspend = i915_pm_suspend,
2977         .suspend_late = i915_pm_suspend_late,
2978         .resume_early = i915_pm_resume_early,
2979         .resume = i915_pm_resume,
2980
2981         /*
2982          * S4 event handlers
2983          * @freeze, @freeze_late    : called (1) before creating the
2984          *                            hibernation image [PMSG_FREEZE] and
2985          *                            (2) after rebooting, before restoring
2986          *                            the image [PMSG_QUIESCE]
2987          * @thaw, @thaw_early       : called (1) after creating the hibernation
2988          *                            image, before writing it [PMSG_THAW]
2989          *                            and (2) after failing to create or
2990          *                            restore the image [PMSG_RECOVER]
2991          * @poweroff, @poweroff_late: called after writing the hibernation
2992          *                            image, before rebooting [PMSG_HIBERNATE]
2993          * @restore, @restore_early : called after rebooting and restoring the
2994          *                            hibernation image [PMSG_RESTORE]
2995          */
2996         .freeze = i915_pm_freeze,
2997         .freeze_late = i915_pm_freeze_late,
2998         .thaw_early = i915_pm_thaw_early,
2999         .thaw = i915_pm_thaw,
3000         .poweroff = i915_pm_suspend,
3001         .poweroff_late = i915_pm_poweroff_late,
3002         .restore_early = i915_pm_restore_early,
3003         .restore = i915_pm_restore,
3004
3005         /* S0ix (via runtime suspend) event handlers */
3006         .runtime_suspend = intel_runtime_suspend,
3007         .runtime_resume = intel_runtime_resume,
3008 };
3009
3010 static const struct vm_operations_struct i915_gem_vm_ops = {
3011         .fault = i915_gem_fault,
3012         .open = drm_gem_vm_open,
3013         .close = drm_gem_vm_close,
3014 };
3015
3016 static const struct file_operations i915_driver_fops = {
3017         .owner = THIS_MODULE,
3018         .open = drm_open,
3019         .release = drm_release,
3020         .unlocked_ioctl = drm_ioctl,
3021         .mmap = drm_gem_mmap,
3022         .poll = drm_poll,
3023         .read = drm_read,
3024         .compat_ioctl = i915_compat_ioctl,
3025         .llseek = noop_llseek,
3026 };
3027
3028 static int
3029 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3030                           struct drm_file *file)
3031 {
3032         return -ENODEV;
3033 }
3034
3035 static const struct drm_ioctl_desc i915_ioctls[] = {
3036         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3037         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3038         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3039         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3040         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3041         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3042         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3043         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3044         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3045         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3046         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3047         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3048         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3049         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3050         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3051         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3052         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3053         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3054         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3055         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3056         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3057         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3058         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3059         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3060         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3061         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3062         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3063         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3064         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3065         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3066         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3067         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3068         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3069         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3070         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3071         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3072         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3073         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3074         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3075         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3076         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3077         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3078         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3079         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3080         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3081         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3082         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3083         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3084         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3085         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3086         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3087         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3088         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3089         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3090         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3091         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3092 };
3093
3094 static struct drm_driver driver = {
3095         /* Don't use MTRRs here; the Xserver or userspace app should
3096          * deal with them for Intel hardware.
3097          */
3098         .driver_features =
3099             DRIVER_GEM | DRIVER_PRIME |
3100             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3101         .release = i915_driver_release,
3102         .open = i915_driver_open,
3103         .lastclose = i915_driver_lastclose,
3104         .postclose = i915_driver_postclose,
3105
3106         .gem_close_object = i915_gem_close_object,
3107         .gem_free_object_unlocked = i915_gem_free_object,
3108         .gem_vm_ops = &i915_gem_vm_ops,
3109
3110         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3111         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3112         .gem_prime_export = i915_gem_prime_export,
3113         .gem_prime_import = i915_gem_prime_import,
3114
3115         .dumb_create = i915_gem_dumb_create,
3116         .dumb_map_offset = i915_gem_mmap_gtt,
3117         .ioctls = i915_ioctls,
3118         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3119         .fops = &i915_driver_fops,
3120         .name = DRIVER_NAME,
3121         .desc = DRIVER_DESC,
3122         .date = DRIVER_DATE,
3123         .major = DRIVER_MAJOR,
3124         .minor = DRIVER_MINOR,
3125         .patchlevel = DRIVER_PATCHLEVEL,
3126 };
3127
3128 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3129 #include "selftests/mock_drm.c"
3130 #endif