drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "display/intel_acpi.h"
  51 #include "display/intel_audio.h"
  52 #include "display/intel_bw.h"
  53 #include "display/intel_cdclk.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_fbdev.h"
  56 #include "display/intel_gmbus.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pipe_crc.h"
  60 #include "display/intel_sprite.h"
  61
  62 #include "gem/i915_gem_context.h"
  63 #include "gem/i915_gem_ioctls.h"
  64 #include "gt/intel_gt_pm.h"
  65 #include "gt/intel_reset.h"
  66 #include "gt/intel_workarounds.h"
  67
  68 #include "i915_debugfs.h"
  69 #include "i915_drv.h"
  70 #include "i915_irq.h"
  71 #include "i915_pmu.h"
  72 #include "i915_query.h"
  73 #include "i915_trace.h"
  74 #include "i915_vgpu.h"
  75 #include "intel_csr.h"
  76 #include "intel_drv.h"
  77 #include "intel_pm.h"
  78 #include "intel_uc.h"
  79
  80 static struct drm_driver driver;
  81
  82 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  83 static unsigned int i915_load_fail_count;
  84
  85 bool __i915_inject_load_failure(const char *func, int line)
  86 {
  87         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  88                 return false;
  89
  90         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  91                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  92                          i915_modparams.inject_load_failure, func, line);
  93                 i915_modparams.inject_load_failure = 0;
  94                 return true;
  95         }
  96
  97         return false;
  98 }
  99
 100 bool i915_error_injected(void)
 101 {
 102         return i915_load_fail_count && !i915_modparams.inject_load_failure;
 103 }
 104
 105 #endif
 106
 107 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
 108 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
 109                     "providing the dmesg log by booting with drm.debug=0xf"
 110
 111 void
 112 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
 113               const char *fmt, ...)
 114 {
 115         static bool shown_bug_once;
 116         struct device *kdev = dev_priv->drm.dev;
 117         bool is_error = level[1] <= KERN_ERR[1];
 118         bool is_debug = level[1] == KERN_DEBUG[1];
 119         struct va_format vaf;
 120         va_list args;
 121
 122         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 123                 return;
 124
 125         va_start(args, fmt);
 126
 127         vaf.fmt = fmt;
 128         vaf.va = &args;
 129
 130         if (is_error)
 131                 dev_printk(level, kdev, "%pV", &vaf);
 132         else
 133                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 134                            __builtin_return_address(0), &vaf);
 135
 136         va_end(args);
 137
 138         if (is_error && !shown_bug_once) {
 139                 /*
 140                  * Ask the user to file a bug report for the error, except
 141                  * if they may have caused the bug by fiddling with unsafe
 142                  * module parameters.
 143                  */
 144                 if (!test_taint(TAINT_USER))
 145                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 146                 shown_bug_once = true;
 147         }
 148 }
 149
 150 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 151 static enum intel_pch
 152 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 153 {
 154         switch (id) {
 155         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 157                 WARN_ON(!IS_GEN(dev_priv, 5));
 158                 return PCH_IBX;
 159         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 160                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 161                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 162                 return PCH_CPT;
 163         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 164                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 165                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 166                 /* PantherPoint is CPT compatible */
 167                 return PCH_CPT;
 168         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 169                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 170                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 171                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 172                 return PCH_LPT;
 173         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 174                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 175                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 176                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 177                 return PCH_LPT;
 178         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 179                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 180                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 181                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 182                 /* WildcatPoint is LPT compatible */
 183                 return PCH_LPT;
 184         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 185                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 186                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 187                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 188                 /* WildcatPoint is LPT compatible */
 189                 return PCH_LPT;
 190         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 191                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 192                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 193                 return PCH_SPT;
 194         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 195                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 196                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 197                 return PCH_SPT;
 198         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 199                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 200                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 201                         !IS_COFFEELAKE(dev_priv));
 202                 /* KBP is SPT compatible */
 203                 return PCH_SPT;
 204         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 205                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 206                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 207                 return PCH_CNP;
 208         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 209                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 210                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 211                 return PCH_CNP;
 212         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
 213                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
 214                 WARN_ON(!IS_COFFEELAKE(dev_priv));
 215                 /* CometPoint is CNP Compatible */
 216                 return PCH_CNP;
 217         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 218                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 219                 WARN_ON(!IS_ICELAKE(dev_priv));
 220                 return PCH_ICP;
 221         case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 222                 DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
 223                 WARN_ON(!IS_ELKHARTLAKE(dev_priv));
 224                 return PCH_MCC;
 225         default:
 226                 return PCH_NONE;
 227         }
 228 }
 229
 230 static bool intel_is_virt_pch(unsigned short id,
 231                               unsigned short svendor, unsigned short sdevice)
 232 {
 233         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 234                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 235                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 236                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 237                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 238 }
 239
 240 static unsigned short
 241 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 242 {
 243         unsigned short id = 0;
 244
 245         /*
 246          * In a virtualized passthrough environment we can be in a
 247          * setup where the ISA bridge is not able to be passed through.
 248          * In this case, a south bridge can be emulated and we have to
 249          * make an educated guess as to which PCH is really there.
 250          */
 251
 252         if (IS_ELKHARTLAKE(dev_priv))
 253                 id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 254         else if (IS_ICELAKE(dev_priv))
 255                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 256         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 257                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 258         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
 259                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 260         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 261                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 262         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 263                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 264         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 265                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 266         else if (IS_GEN(dev_priv, 5))
 267                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 268
 269         if (id)
 270                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 271         else
 272                 DRM_DEBUG_KMS("Assuming no PCH\n");
 273
 274         return id;
 275 }
 276
 277 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 278 {
 279         struct pci_dev *pch = NULL;
 280
 281         /*
 282          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 283          * make graphics device passthrough work easy for VMM, that only
 284          * need to expose ISA bridge to let driver know the real hardware
 285          * underneath. This is a requirement from virtualization team.
 286          *
 287          * In some virtualized environments (e.g. XEN), there is irrelevant
 288          * ISA bridge in the system. To work reliably, we should scan trhough
 289          * all the ISA bridge devices and check for the first match, instead
 290          * of only checking the first one.
 291          */
 292         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 293                 unsigned short id;
 294                 enum intel_pch pch_type;
 295
 296                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 297                         continue;
 298
 299                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 300
 301                 pch_type = intel_pch_type(dev_priv, id);
 302                 if (pch_type != PCH_NONE) {
 303                         dev_priv->pch_type = pch_type;
 304                         dev_priv->pch_id = id;
 305                         break;
 306                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 307                                          pch->subsystem_device)) {
 308                         id = intel_virt_detect_pch(dev_priv);
 309                         pch_type = intel_pch_type(dev_priv, id);
 310
 311                         /* Sanity check virtual PCH id */
 312                         if (WARN_ON(id && pch_type == PCH_NONE))
 313                                 id = 0;
 314
 315                         dev_priv->pch_type = pch_type;
 316                         dev_priv->pch_id = id;
 317                         break;
 318                 }
 319         }
 320
 321         /*
 322          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 323          * display.
 324          */
 325         if (pch && !HAS_DISPLAY(dev_priv)) {
 326                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 327                 dev_priv->pch_type = PCH_NOP;
 328                 dev_priv->pch_id = 0;
 329         }
 330
 331         if (!pch)
 332                 DRM_DEBUG_KMS("No PCH found.\n");
 333
 334         pci_dev_put(pch);
 335 }
 336
 337 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 338                                struct drm_file *file_priv)
 339 {
 340         struct drm_i915_private *dev_priv = to_i915(dev);
 341         struct pci_dev *pdev = dev_priv->drm.pdev;
 342         const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 343         drm_i915_getparam_t *param = data;
 344         int value;
 345
 346         switch (param->param) {
 347         case I915_PARAM_IRQ_ACTIVE:
 348         case I915_PARAM_ALLOW_BATCHBUFFER:
 349         case I915_PARAM_LAST_DISPATCH:
 350         case I915_PARAM_HAS_EXEC_CONSTANTS:
 351                 /* Reject all old ums/dri params. */
 352                 return -ENODEV;
 353         case I915_PARAM_CHIPSET_ID:
 354                 value = pdev->device;
 355                 break;
 356         case I915_PARAM_REVISION:
 357                 value = pdev->revision;
 358                 break;
 359         case I915_PARAM_NUM_FENCES_AVAIL:
 360                 value = dev_priv->ggtt.num_fences;
 361                 break;
 362         case I915_PARAM_HAS_OVERLAY:
 363                 value = dev_priv->overlay ? 1 : 0;
 364                 break;
 365         case I915_PARAM_HAS_BSD:
 366                 value = !!dev_priv->engine[VCS0];
 367                 break;
 368         case I915_PARAM_HAS_BLT:
 369                 value = !!dev_priv->engine[BCS0];
 370                 break;
 371         case I915_PARAM_HAS_VEBOX:
 372                 value = !!dev_priv->engine[VECS0];
 373                 break;
 374         case I915_PARAM_HAS_BSD2:
 375                 value = !!dev_priv->engine[VCS1];
 376                 break;
 377         case I915_PARAM_HAS_LLC:
 378                 value = HAS_LLC(dev_priv);
 379                 break;
 380         case I915_PARAM_HAS_WT:
 381                 value = HAS_WT(dev_priv);
 382                 break;
 383         case I915_PARAM_HAS_ALIASING_PPGTT:
 384                 value = INTEL_PPGTT(dev_priv);
 385                 break;
 386         case I915_PARAM_HAS_SEMAPHORES:
 387                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
 388                 break;
 389         case I915_PARAM_HAS_SECURE_BATCHES:
 390                 value = capable(CAP_SYS_ADMIN);
 391                 break;
 392         case I915_PARAM_CMD_PARSER_VERSION:
 393                 value = i915_cmd_parser_get_version(dev_priv);
 394                 break;
 395         case I915_PARAM_SUBSLICE_TOTAL:
 396                 value = intel_sseu_subslice_total(sseu);
 397                 if (!value)
 398                         return -ENODEV;
 399                 break;
 400         case I915_PARAM_EU_TOTAL:
 401                 value = sseu->eu_total;
 402                 if (!value)
 403                         return -ENODEV;
 404                 break;
 405         case I915_PARAM_HAS_GPU_RESET:
 406                 value = i915_modparams.enable_hangcheck &&
 407                         intel_has_gpu_reset(dev_priv);
 408                 if (value && intel_has_reset_engine(dev_priv))
 409                         value = 2;
 410                 break;
 411         case I915_PARAM_HAS_RESOURCE_STREAMER:
 412                 value = 0;
 413                 break;
 414         case I915_PARAM_HAS_POOLED_EU:
 415                 value = HAS_POOLED_EU(dev_priv);
 416                 break;
 417         case I915_PARAM_MIN_EU_IN_POOL:
 418                 value = sseu->min_eu_in_pool;
 419                 break;
 420         case I915_PARAM_HUC_STATUS:
 421                 value = intel_huc_check_status(&dev_priv->huc);
 422                 if (value < 0)
 423                         return value;
 424                 break;
 425         case I915_PARAM_MMAP_GTT_VERSION:
 426                 /* Though we've started our numbering from 1, and so class all
 427                  * earlier versions as 0, in effect their value is undefined as
 428                  * the ioctl will report EINVAL for the unknown param!
 429                  */
 430                 value = i915_gem_mmap_gtt_version();
 431                 break;
 432         case I915_PARAM_HAS_SCHEDULER:
 433                 value = dev_priv->caps.scheduler;
 434                 break;
 435
 436         case I915_PARAM_MMAP_VERSION:
 437                 /* Remember to bump this if the version changes! */
 438         case I915_PARAM_HAS_GEM:
 439         case I915_PARAM_HAS_PAGEFLIPPING:
 440         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 441         case I915_PARAM_HAS_RELAXED_FENCING:
 442         case I915_PARAM_HAS_COHERENT_RINGS:
 443         case I915_PARAM_HAS_RELAXED_DELTA:
 444         case I915_PARAM_HAS_GEN7_SOL_RESET:
 445         case I915_PARAM_HAS_WAIT_TIMEOUT:
 446         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 447         case I915_PARAM_HAS_PINNED_BATCHES:
 448         case I915_PARAM_HAS_EXEC_NO_RELOC:
 449         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 450         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 451         case I915_PARAM_HAS_EXEC_SOFTPIN:
 452         case I915_PARAM_HAS_EXEC_ASYNC:
 453         case I915_PARAM_HAS_EXEC_FENCE:
 454         case I915_PARAM_HAS_EXEC_CAPTURE:
 455         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 456         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 457         case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
 458                 /* For the time being all of these are always true;
 459                  * if some supported hardware does not have one of these
 460                  * features this value needs to be provided from
 461                  * INTEL_INFO(), a feature macro, or similar.
 462                  */
 463                 value = 1;
 464                 break;
 465         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 466                 value = intel_engines_has_context_isolation(dev_priv);
 467                 break;
 468         case I915_PARAM_SLICE_MASK:
 469                 value = sseu->slice_mask;
 470                 if (!value)
 471                         return -ENODEV;
 472                 break;
 473         case I915_PARAM_SUBSLICE_MASK:
 474                 value = sseu->subslice_mask[0];
 475                 if (!value)
 476                         return -ENODEV;
 477                 break;
 478         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 479                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
 480                 break;
 481         case I915_PARAM_MMAP_GTT_COHERENT:
 482                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 483                 break;
 484         default:
 485                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 486                 return -EINVAL;
 487         }
 488
 489         if (put_user(value, param->value))
 490                 return -EFAULT;
 491
 492         return 0;
 493 }
 494
 495 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 496 {
 497         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 498
 499         dev_priv->bridge_dev =
 500                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 501         if (!dev_priv->bridge_dev) {
 502                 DRM_ERROR("bridge device not found\n");
 503                 return -1;
 504         }
 505         return 0;
 506 }
 507
 508 /* Allocate space for the MCH regs if needed, return nonzero on error */
 509 static int
 510 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 511 {
 512         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 513         u32 temp_lo, temp_hi = 0;
 514         u64 mchbar_addr;
 515         int ret;
 516
 517         if (INTEL_GEN(dev_priv) >= 4)
 518                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 519         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 520         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 521
 522         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 523 #ifdef CONFIG_PNP
 524         if (mchbar_addr &&
 525             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 526                 return 0;
 527 #endif
 528
 529         /* Get some space for it */
 530         dev_priv->mch_res.name = "i915 MCHBAR";
 531         dev_priv->mch_res.flags = IORESOURCE_MEM;
 532         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 533                                      &dev_priv->mch_res,
 534                                      MCHBAR_SIZE, MCHBAR_SIZE,
 535                                      PCIBIOS_MIN_MEM,
 536                                      0, pcibios_align_resource,
 537                                      dev_priv->bridge_dev);
 538         if (ret) {
 539                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 540                 dev_priv->mch_res.start = 0;
 541                 return ret;
 542         }
 543
 544         if (INTEL_GEN(dev_priv) >= 4)
 545                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 546                                        upper_32_bits(dev_priv->mch_res.start));
 547
 548         pci_write_config_dword(dev_priv->bridge_dev, reg,
 549                                lower_32_bits(dev_priv->mch_res.start));
 550         return 0;
 551 }
 552
 553 /* Setup MCHBAR if possible, return true if we should disable it again */
 554 static void
 555 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 556 {
 557         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 558         u32 temp;
 559         bool enabled;
 560
 561         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 562                 return;
 563
 564         dev_priv->mchbar_need_disable = false;
 565
 566         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 567                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 568                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 569         } else {
 570                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 571                 enabled = temp & 1;
 572         }
 573
 574         /* If it's already enabled, don't have to do anything */
 575         if (enabled)
 576                 return;
 577
 578         if (intel_alloc_mchbar_resource(dev_priv))
 579                 return;
 580
 581         dev_priv->mchbar_need_disable = true;
 582
 583         /* Space is allocated or reserved, so enable it. */
 584         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 585                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 586                                        temp | DEVEN_MCHBAR_EN);
 587         } else {
 588                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 589                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 590         }
 591 }
 592
 593 static void
 594 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 595 {
 596         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 597
 598         if (dev_priv->mchbar_need_disable) {
 599                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 600                         u32 deven_val;
 601
 602                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 603                                               &deven_val);
 604                         deven_val &= ~DEVEN_MCHBAR_EN;
 605                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 606                                                deven_val);
 607                 } else {
 608                         u32 mchbar_val;
 609
 610                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 611                                               &mchbar_val);
 612                         mchbar_val &= ~1;
 613                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 614                                                mchbar_val);
 615                 }
 616         }
 617
 618         if (dev_priv->mch_res.start)
 619                 release_resource(&dev_priv->mch_res);
 620 }
 621
 622 /* true = enable decode, false = disable decoder */
 623 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 624 {
 625         struct drm_i915_private *dev_priv = cookie;
 626
 627         intel_modeset_vga_set_state(dev_priv, state);
 628         if (state)
 629                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 630                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 631         else
 632                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 633 }
 634
 635 static int i915_resume_switcheroo(struct drm_device *dev);
 636 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 637
 638 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 639 {
 640         struct drm_device *dev = pci_get_drvdata(pdev);
 641         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 642
 643         if (state == VGA_SWITCHEROO_ON) {
 644                 pr_info("switched on\n");
 645                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 646                 /* i915 resume handler doesn't set to D0 */
 647                 pci_set_power_state(pdev, PCI_D0);
 648                 i915_resume_switcheroo(dev);
 649                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 650         } else {
 651                 pr_info("switched off\n");
 652                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 653                 i915_suspend_switcheroo(dev, pmm);
 654                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 655         }
 656 }
 657
 658 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 659 {
 660         struct drm_device *dev = pci_get_drvdata(pdev);
 661
 662         /*
 663          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 664          * locking inversion with the driver load path. And the access here is
 665          * completely racy anyway. So don't bother with locking for now.
 666          */
 667         return dev->open_count == 0;
 668 }
 669
 670 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 671         .set_gpu_state = i915_switcheroo_set_state,
 672         .reprobe = NULL,
 673         .can_switch = i915_switcheroo_can_switch,
 674 };
 675
 676 static int i915_load_modeset_init(struct drm_device *dev)
 677 {
 678         struct drm_i915_private *dev_priv = to_i915(dev);
 679         struct pci_dev *pdev = dev_priv->drm.pdev;
 680         int ret;
 681
 682         if (i915_inject_load_failure())
 683                 return -ENODEV;
 684
 685         if (HAS_DISPLAY(dev_priv)) {
 686                 ret = drm_vblank_init(&dev_priv->drm,
 687                                       INTEL_INFO(dev_priv)->num_pipes);
 688                 if (ret)
 689                         goto out;
 690         }
 691
 692         intel_bios_init(dev_priv);
 693
 694         /* If we have > 1 VGA cards, then we need to arbitrate access
 695          * to the common VGA resources.
 696          *
 697          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 698          * then we do not take part in VGA arbitration and the
 699          * vga_client_register() fails with -ENODEV.
 700          */
 701         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 702         if (ret && ret != -ENODEV)
 703                 goto out;
 704
 705         intel_register_dsm_handler();
 706
 707         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 708         if (ret)
 709                 goto cleanup_vga_client;
 710
 711         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 712         intel_update_rawclk(dev_priv);
 713
 714         intel_power_domains_init_hw(dev_priv, false);
 715
 716         intel_csr_ucode_init(dev_priv);
 717
 718         ret = intel_irq_install(dev_priv);
 719         if (ret)
 720                 goto cleanup_csr;
 721
 722         intel_gmbus_setup(dev_priv);
 723
 724         /* Important: The output setup functions called by modeset_init need
 725          * working irqs for e.g. gmbus and dp aux transfers. */
 726         ret = intel_modeset_init(dev);
 727         if (ret)
 728                 goto cleanup_irq;
 729
 730         ret = i915_gem_init(dev_priv);
 731         if (ret)
 732                 goto cleanup_modeset;
 733
 734         intel_overlay_setup(dev_priv);
 735
 736         if (!HAS_DISPLAY(dev_priv))
 737                 return 0;
 738
 739         ret = intel_fbdev_init(dev);
 740         if (ret)
 741                 goto cleanup_gem;
 742
 743         /* Only enable hotplug handling once the fbdev is fully set up. */
 744         intel_hpd_init(dev_priv);
 745
 746         intel_init_ipc(dev_priv);
 747
 748         return 0;
 749
 750 cleanup_gem:
 751         i915_gem_suspend(dev_priv);
 752         i915_gem_fini_hw(dev_priv);
 753         i915_gem_fini(dev_priv);
 754 cleanup_modeset:
 755         intel_modeset_cleanup(dev);
 756 cleanup_irq:
 757         drm_irq_uninstall(dev);
 758         intel_gmbus_teardown(dev_priv);
 759 cleanup_csr:
 760         intel_csr_ucode_fini(dev_priv);
 761         intel_power_domains_fini_hw(dev_priv);
 762         vga_switcheroo_unregister_client(pdev);
 763 cleanup_vga_client:
 764         vga_client_register(pdev, NULL, NULL, NULL);
 765 out:
 766         return ret;
 767 }
 768
 769 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 770 {
 771         struct apertures_struct *ap;
 772         struct pci_dev *pdev = dev_priv->drm.pdev;
 773         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 774         bool primary;
 775         int ret;
 776
 777         ap = alloc_apertures(1);
 778         if (!ap)
 779                 return -ENOMEM;
 780
 781         ap->ranges[0].base = ggtt->gmadr.start;
 782         ap->ranges[0].size = ggtt->mappable_end;
 783
 784         primary =
 785                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 786
 787         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 788
 789         kfree(ap);
 790
 791         return ret;
 792 }
 793
 794 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 795 {
 796         /*
 797          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 798          * CHV x1 PHY (DP/HDMI D)
 799          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 800          */
 801         if (IS_CHERRYVIEW(dev_priv)) {
 802                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 803                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 804         } else if (IS_VALLEYVIEW(dev_priv)) {
 805                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 806         }
 807 }
 808
 809 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 810 {
 811         /*
 812          * The i915 workqueue is primarily used for batched retirement of
 813          * requests (and thus managing bo) once the task has been completed
 814          * by the GPU. i915_retire_requests() is called directly when we
 815          * need high-priority retirement, such as waiting for an explicit
 816          * bo.
 817          *
 818          * It is also used for periodic low-priority events, such as
 819          * idle-timers and recording error state.
 820          *
 821          * All tasks on the workqueue are expected to acquire the dev mutex
 822          * so there is no point in running more than one instance of the
 823          * workqueue at any time.  Use an ordered one.
 824          */
 825         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 826         if (dev_priv->wq == NULL)
 827                 goto out_err;
 828
 829         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 830         if (dev_priv->hotplug.dp_wq == NULL)
 831                 goto out_free_wq;
 832
 833         return 0;
 834
 835 out_free_wq:
 836         destroy_workqueue(dev_priv->wq);
 837 out_err:
 838         DRM_ERROR("Failed to allocate workqueues.\n");
 839
 840         return -ENOMEM;
 841 }
 842
 843 static void i915_engines_cleanup(struct drm_i915_private *i915)
 844 {
 845         struct intel_engine_cs *engine;
 846         enum intel_engine_id id;
 847
 848         for_each_engine(engine, i915, id)
 849                 kfree(engine);
 850 }
 851
 852 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 853 {
 854         destroy_workqueue(dev_priv->hotplug.dp_wq);
 855         destroy_workqueue(dev_priv->wq);
 856 }
 857
 858 /*
 859  * We don't keep the workarounds for pre-production hardware, so we expect our
 860  * driver to fail on these machines in one way or another. A little warning on
 861  * dmesg may help both the user and the bug triagers.
 862  *
 863  * Our policy for removing pre-production workarounds is to keep the
 864  * current gen workarounds as a guide to the bring-up of the next gen
 865  * (workarounds have a habit of persisting!). Anything older than that
 866  * should be removed along with the complications they introduce.
 867  */
 868 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 869 {
 870         bool pre = false;
 871
 872         pre |= IS_HSW_EARLY_SDV(dev_priv);
 873         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 874         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 875         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 876
 877         if (pre) {
 878                 DRM_ERROR("This is a pre-production stepping. "
 879                           "It may not be fully functional.\n");
 880                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 881         }
 882 }
 883
 884 /**
 885  * i915_driver_init_early - setup state not requiring device access
 886  * @dev_priv: device private
 887  *
 888  * Initialize everything that is a "SW-only" state, that is state not
 889  * requiring accessing the device or exposing the driver via kernel internal
 890  * or userspace interfaces. Example steps belonging here: lock initialization,
 891  * system memory allocation, setting up device specific attributes and
 892  * function hooks not requiring accessing the device.
 893  */
 894 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 895 {
 896         int ret = 0;
 897
 898         if (i915_inject_load_failure())
 899                 return -ENODEV;
 900
 901         intel_device_info_subplatform_init(dev_priv);
 902
 903         intel_uncore_init_early(&dev_priv->uncore);
 904
 905         spin_lock_init(&dev_priv->irq_lock);
 906         spin_lock_init(&dev_priv->gpu_error.lock);
 907         mutex_init(&dev_priv->backlight_lock);
 908
 909         mutex_init(&dev_priv->sb_lock);
 910         pm_qos_add_request(&dev_priv->sb_qos,
 911                            PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
 912
 913         mutex_init(&dev_priv->av_mutex);
 914         mutex_init(&dev_priv->wm.wm_mutex);
 915         mutex_init(&dev_priv->pps_mutex);
 916         mutex_init(&dev_priv->hdcp_comp_mutex);
 917
 918         i915_memcpy_init_early(dev_priv);
 919         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 920
 921         ret = i915_workqueues_init(dev_priv);
 922         if (ret < 0)
 923                 goto err_engines;
 924
 925         ret = i915_gem_init_early(dev_priv);
 926         if (ret < 0)
 927                 goto err_workqueues;
 928
 929         /* This must be called before any calls to HAS_PCH_* */
 930         intel_detect_pch(dev_priv);
 931
 932         intel_wopcm_init_early(&dev_priv->wopcm);
 933         intel_uc_init_early(dev_priv);
 934         intel_pm_setup(dev_priv);
 935         intel_init_dpio(dev_priv);
 936         ret = intel_power_domains_init(dev_priv);
 937         if (ret < 0)
 938                 goto err_uc;
 939         intel_irq_init(dev_priv);
 940         intel_hangcheck_init(dev_priv);
 941         intel_init_display_hooks(dev_priv);
 942         intel_init_clock_gating_hooks(dev_priv);
 943         intel_init_audio_hooks(dev_priv);
 944         intel_display_crc_init(dev_priv);
 945
 946         intel_detect_preproduction_hw(dev_priv);
 947
 948         return 0;
 949
 950 err_uc:
 951         intel_uc_cleanup_early(dev_priv);
 952         i915_gem_cleanup_early(dev_priv);
 953 err_workqueues:
 954         i915_workqueues_cleanup(dev_priv);
 955 err_engines:
 956         i915_engines_cleanup(dev_priv);
 957         return ret;
 958 }
 959
 960 /**
 961  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 962  * @dev_priv: device private
 963  */
 964 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 965 {
 966         intel_irq_fini(dev_priv);
 967         intel_power_domains_cleanup(dev_priv);
 968         intel_uc_cleanup_early(dev_priv);
 969         i915_gem_cleanup_early(dev_priv);
 970         i915_workqueues_cleanup(dev_priv);
 971         i915_engines_cleanup(dev_priv);
 972
 973         pm_qos_remove_request(&dev_priv->sb_qos);
 974         mutex_destroy(&dev_priv->sb_lock);
 975 }
 976
 977 /**
 978  * i915_driver_init_mmio - setup device MMIO
 979  * @dev_priv: device private
 980  *
 981  * Setup minimal device state necessary for MMIO accesses later in the
 982  * initialization sequence. The setup here should avoid any other device-wide
 983  * side effects or exposing the driver via kernel internal or user space
 984  * interfaces.
 985  */
 986 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 987 {
 988         int ret;
 989
 990         if (i915_inject_load_failure())
 991                 return -ENODEV;
 992
 993         if (i915_get_bridge_dev(dev_priv))
 994                 return -EIO;
 995
 996         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 997         if (ret < 0)
 998                 goto err_bridge;
 999
1000         /* Try to make sure MCHBAR is enabled before poking at it */
1001         intel_setup_mchbar(dev_priv);
1002
1003         intel_device_info_init_mmio(dev_priv);
1004
1005         intel_uncore_prune_mmio_domains(&dev_priv->uncore);
1006
1007         intel_uc_init_mmio(dev_priv);
1008
1009         ret = intel_engines_init_mmio(dev_priv);
1010         if (ret)
1011                 goto err_uncore;
1012
1013         i915_gem_init_mmio(dev_priv);
1014
1015         return 0;
1016
1017 err_uncore:
1018         intel_teardown_mchbar(dev_priv);
1019         intel_uncore_fini_mmio(&dev_priv->uncore);
1020 err_bridge:
1021         pci_dev_put(dev_priv->bridge_dev);
1022
1023         return ret;
1024 }
1025
1026 /**
1027  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1028  * @dev_priv: device private
1029  */
1030 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1031 {
1032         intel_teardown_mchbar(dev_priv);
1033         intel_uncore_fini_mmio(&dev_priv->uncore);
1034         pci_dev_put(dev_priv->bridge_dev);
1035 }
1036
1037 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1038 {
1039         intel_gvt_sanitize_options(dev_priv);
1040 }
1041
1042 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1043
1044 static const char *intel_dram_type_str(enum intel_dram_type type)
1045 {
1046         static const char * const str[] = {
1047                 DRAM_TYPE_STR(UNKNOWN),
1048                 DRAM_TYPE_STR(DDR3),
1049                 DRAM_TYPE_STR(DDR4),
1050                 DRAM_TYPE_STR(LPDDR3),
1051                 DRAM_TYPE_STR(LPDDR4),
1052         };
1053
1054         if (type >= ARRAY_SIZE(str))
1055                 type = INTEL_DRAM_UNKNOWN;
1056
1057         return str[type];
1058 }
1059
1060 #undef DRAM_TYPE_STR
1061
1062 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1063 {
1064         return dimm->ranks * 64 / (dimm->width ?: 1);
1065 }
1066
1067 /* Returns total GB for the whole DIMM */
1068 static int skl_get_dimm_size(u16 val)
1069 {
1070         return val & SKL_DRAM_SIZE_MASK;
1071 }
1072
1073 static int skl_get_dimm_width(u16 val)
1074 {
1075         if (skl_get_dimm_size(val) == 0)
1076                 return 0;
1077
1078         switch (val & SKL_DRAM_WIDTH_MASK) {
1079         case SKL_DRAM_WIDTH_X8:
1080         case SKL_DRAM_WIDTH_X16:
1081         case SKL_DRAM_WIDTH_X32:
1082                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1083                 return 8 << val;
1084         default:
1085                 MISSING_CASE(val);
1086                 return 0;
1087         }
1088 }
1089
1090 static int skl_get_dimm_ranks(u16 val)
1091 {
1092         if (skl_get_dimm_size(val) == 0)
1093                 return 0;
1094
1095         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1096
1097         return val + 1;
1098 }
1099
1100 /* Returns total GB for the whole DIMM */
1101 static int cnl_get_dimm_size(u16 val)
1102 {
1103         return (val & CNL_DRAM_SIZE_MASK) / 2;
1104 }
1105
1106 static int cnl_get_dimm_width(u16 val)
1107 {
1108         if (cnl_get_dimm_size(val) == 0)
1109                 return 0;
1110
1111         switch (val & CNL_DRAM_WIDTH_MASK) {
1112         case CNL_DRAM_WIDTH_X8:
1113         case CNL_DRAM_WIDTH_X16:
1114         case CNL_DRAM_WIDTH_X32:
1115                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1116                 return 8 << val;
1117         default:
1118                 MISSING_CASE(val);
1119                 return 0;
1120         }
1121 }
1122
1123 static int cnl_get_dimm_ranks(u16 val)
1124 {
1125         if (cnl_get_dimm_size(val) == 0)
1126                 return 0;
1127
1128         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1129
1130         return val + 1;
1131 }
1132
1133 static bool
1134 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1135 {
1136         /* Convert total GB to Gb per DRAM device */
1137         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1138 }
1139
1140 static void
1141 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1142                        struct dram_dimm_info *dimm,
1143                        int channel, char dimm_name, u16 val)
1144 {
1145         if (INTEL_GEN(dev_priv) >= 10) {
1146                 dimm->size = cnl_get_dimm_size(val);
1147                 dimm->width = cnl_get_dimm_width(val);
1148                 dimm->ranks = cnl_get_dimm_ranks(val);
1149         } else {
1150                 dimm->size = skl_get_dimm_size(val);
1151                 dimm->width = skl_get_dimm_width(val);
1152                 dimm->ranks = skl_get_dimm_ranks(val);
1153         }
1154
1155         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1156                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1157                       yesno(skl_is_16gb_dimm(dimm)));
1158 }
1159
1160 static int
1161 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1162                           struct dram_channel_info *ch,
1163                           int channel, u32 val)
1164 {
1165         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1166                                channel, 'L', val & 0xffff);
1167         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1168                                channel, 'S', val >> 16);
1169
1170         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1171                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1172                 return -EINVAL;
1173         }
1174
1175         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1176                 ch->ranks = 2;
1177         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1178                 ch->ranks = 2;
1179         else
1180                 ch->ranks = 1;
1181
1182         ch->is_16gb_dimm =
1183                 skl_is_16gb_dimm(&ch->dimm_l) ||
1184                 skl_is_16gb_dimm(&ch->dimm_s);
1185
1186         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1187                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1188
1189         return 0;
1190 }
1191
1192 static bool
1193 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1194                         const struct dram_channel_info *ch1)
1195 {
1196         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1197                 (ch0->dimm_s.size == 0 ||
1198                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1199 }
1200
1201 static int
1202 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1203 {
1204         struct dram_info *dram_info = &dev_priv->dram_info;
1205         struct dram_channel_info ch0 = {}, ch1 = {};
1206         u32 val;
1207         int ret;
1208
1209         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1210         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1211         if (ret == 0)
1212                 dram_info->num_channels++;
1213
1214         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1215         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1216         if (ret == 0)
1217                 dram_info->num_channels++;
1218
1219         if (dram_info->num_channels == 0) {
1220                 DRM_INFO("Number of memory channels is zero\n");
1221                 return -EINVAL;
1222         }
1223
1224         /*
1225          * If any of the channel is single rank channel, worst case output
1226          * will be same as if single rank memory, so consider single rank
1227          * memory.
1228          */
1229         if (ch0.ranks == 1 || ch1.ranks == 1)
1230                 dram_info->ranks = 1;
1231         else
1232                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1233
1234         if (dram_info->ranks == 0) {
1235                 DRM_INFO("couldn't get memory rank information\n");
1236                 return -EINVAL;
1237         }
1238
1239         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1240
1241         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1242
1243         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1244                       yesno(dram_info->symmetric_memory));
1245         return 0;
1246 }
1247
1248 static enum intel_dram_type
1249 skl_get_dram_type(struct drm_i915_private *dev_priv)
1250 {
1251         u32 val;
1252
1253         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1254
1255         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1256         case SKL_DRAM_DDR_TYPE_DDR3:
1257                 return INTEL_DRAM_DDR3;
1258         case SKL_DRAM_DDR_TYPE_DDR4:
1259                 return INTEL_DRAM_DDR4;
1260         case SKL_DRAM_DDR_TYPE_LPDDR3:
1261                 return INTEL_DRAM_LPDDR3;
1262         case SKL_DRAM_DDR_TYPE_LPDDR4:
1263                 return INTEL_DRAM_LPDDR4;
1264         default:
1265                 MISSING_CASE(val);
1266                 return INTEL_DRAM_UNKNOWN;
1267         }
1268 }
1269
1270 static int
1271 skl_get_dram_info(struct drm_i915_private *dev_priv)
1272 {
1273         struct dram_info *dram_info = &dev_priv->dram_info;
1274         u32 mem_freq_khz, val;
1275         int ret;
1276
1277         dram_info->type = skl_get_dram_type(dev_priv);
1278         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1279
1280         ret = skl_dram_get_channels_info(dev_priv);
1281         if (ret)
1282                 return ret;
1283
1284         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1285         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1286                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1287
1288         dram_info->bandwidth_kbps = dram_info->num_channels *
1289                                                         mem_freq_khz * 8;
1290
1291         if (dram_info->bandwidth_kbps == 0) {
1292                 DRM_INFO("Couldn't get system memory bandwidth\n");
1293                 return -EINVAL;
1294         }
1295
1296         dram_info->valid = true;
1297         return 0;
1298 }
1299
1300 /* Returns Gb per DRAM device */
1301 static int bxt_get_dimm_size(u32 val)
1302 {
1303         switch (val & BXT_DRAM_SIZE_MASK) {
1304         case BXT_DRAM_SIZE_4GBIT:
1305                 return 4;
1306         case BXT_DRAM_SIZE_6GBIT:
1307                 return 6;
1308         case BXT_DRAM_SIZE_8GBIT:
1309                 return 8;
1310         case BXT_DRAM_SIZE_12GBIT:
1311                 return 12;
1312         case BXT_DRAM_SIZE_16GBIT:
1313                 return 16;
1314         default:
1315                 MISSING_CASE(val);
1316                 return 0;
1317         }
1318 }
1319
1320 static int bxt_get_dimm_width(u32 val)
1321 {
1322         if (!bxt_get_dimm_size(val))
1323                 return 0;
1324
1325         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1326
1327         return 8 << val;
1328 }
1329
1330 static int bxt_get_dimm_ranks(u32 val)
1331 {
1332         if (!bxt_get_dimm_size(val))
1333                 return 0;
1334
1335         switch (val & BXT_DRAM_RANK_MASK) {
1336         case BXT_DRAM_RANK_SINGLE:
1337                 return 1;
1338         case BXT_DRAM_RANK_DUAL:
1339                 return 2;
1340         default:
1341                 MISSING_CASE(val);
1342                 return 0;
1343         }
1344 }
1345
1346 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1347 {
1348         if (!bxt_get_dimm_size(val))
1349                 return INTEL_DRAM_UNKNOWN;
1350
1351         switch (val & BXT_DRAM_TYPE_MASK) {
1352         case BXT_DRAM_TYPE_DDR3:
1353                 return INTEL_DRAM_DDR3;
1354         case BXT_DRAM_TYPE_LPDDR3:
1355                 return INTEL_DRAM_LPDDR3;
1356         case BXT_DRAM_TYPE_DDR4:
1357                 return INTEL_DRAM_DDR4;
1358         case BXT_DRAM_TYPE_LPDDR4:
1359                 return INTEL_DRAM_LPDDR4;
1360         default:
1361                 MISSING_CASE(val);
1362                 return INTEL_DRAM_UNKNOWN;
1363         }
1364 }
1365
1366 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1367                               u32 val)
1368 {
1369         dimm->width = bxt_get_dimm_width(val);
1370         dimm->ranks = bxt_get_dimm_ranks(val);
1371
1372         /*
1373          * Size in register is Gb per DRAM device. Convert to total
1374          * GB to match the way we report this for non-LP platforms.
1375          */
1376         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1377 }
1378
1379 static int
1380 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1381 {
1382         struct dram_info *dram_info = &dev_priv->dram_info;
1383         u32 dram_channels;
1384         u32 mem_freq_khz, val;
1385         u8 num_active_channels;
1386         int i;
1387
1388         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1389         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1390                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1391
1392         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1393         num_active_channels = hweight32(dram_channels);
1394
1395         /* Each active bit represents 4-byte channel */
1396         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1397
1398         if (dram_info->bandwidth_kbps == 0) {
1399                 DRM_INFO("Couldn't get system memory bandwidth\n");
1400                 return -EINVAL;
1401         }
1402
1403         /*
1404          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1405          */
1406         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1407                 struct dram_dimm_info dimm;
1408                 enum intel_dram_type type;
1409
1410                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1411                 if (val == 0xFFFFFFFF)
1412                         continue;
1413
1414                 dram_info->num_channels++;
1415
1416                 bxt_get_dimm_info(&dimm, val);
1417                 type = bxt_get_dimm_type(val);
1418
1419                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1420                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1421                         dram_info->type != type);
1422
1423                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1424                               i - BXT_D_CR_DRP0_DUNIT_START,
1425                               dimm.size, dimm.width, dimm.ranks,
1426                               intel_dram_type_str(type));
1427
1428                 /*
1429                  * If any of the channel is single rank channel,
1430                  * worst case output will be same as if single rank
1431                  * memory, so consider single rank memory.
1432                  */
1433                 if (dram_info->ranks == 0)
1434                         dram_info->ranks = dimm.ranks;
1435                 else if (dimm.ranks == 1)
1436                         dram_info->ranks = 1;
1437
1438                 if (type != INTEL_DRAM_UNKNOWN)
1439                         dram_info->type = type;
1440         }
1441
1442         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1443             dram_info->ranks == 0) {
1444                 DRM_INFO("couldn't get memory information\n");
1445                 return -EINVAL;
1446         }
1447
1448         dram_info->valid = true;
1449         return 0;
1450 }
1451
1452 static void
1453 intel_get_dram_info(struct drm_i915_private *dev_priv)
1454 {
1455         struct dram_info *dram_info = &dev_priv->dram_info;
1456         int ret;
1457
1458         /*
1459          * Assume 16Gb DIMMs are present until proven otherwise.
1460          * This is only used for the level 0 watermark latency
1461          * w/a which does not apply to bxt/glk.
1462          */
1463         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1464
1465         if (INTEL_GEN(dev_priv) < 9)
1466                 return;
1467
1468         if (IS_GEN9_LP(dev_priv))
1469                 ret = bxt_get_dram_info(dev_priv);
1470         else
1471                 ret = skl_get_dram_info(dev_priv);
1472         if (ret)
1473                 return;
1474
1475         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1476                       dram_info->bandwidth_kbps,
1477                       dram_info->num_channels);
1478
1479         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1480                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1481 }
1482
1483 static u32 gen9_edram_size_mb(struct drm_i915_private *dev_priv, u32 cap)
1484 {
1485         const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
1486         const unsigned int sets[4] = { 1, 1, 2, 2 };
1487
1488         return EDRAM_NUM_BANKS(cap) *
1489                 ways[EDRAM_WAYS_IDX(cap)] *
1490                 sets[EDRAM_SETS_IDX(cap)];
1491 }
1492
1493 static void edram_detect(struct drm_i915_private *dev_priv)
1494 {
1495         u32 edram_cap = 0;
1496
1497         if (!(IS_HASWELL(dev_priv) ||
1498               IS_BROADWELL(dev_priv) ||
1499               INTEL_GEN(dev_priv) >= 9))
1500                 return;
1501
1502         edram_cap = __raw_uncore_read32(&dev_priv->uncore, HSW_EDRAM_CAP);
1503
1504         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
1505
1506         if (!(edram_cap & EDRAM_ENABLED))
1507                 return;
1508
1509         /*
1510          * The needed capability bits for size calculation are not there with
1511          * pre gen9 so return 128MB always.
1512          */
1513         if (INTEL_GEN(dev_priv) < 9)
1514                 dev_priv->edram_size_mb = 128;
1515         else
1516                 dev_priv->edram_size_mb =
1517                         gen9_edram_size_mb(dev_priv, edram_cap);
1518
1519         DRM_INFO("Found %uMB of eDRAM\n", dev_priv->edram_size_mb);
1520 }
1521
1522 /**
1523  * i915_driver_init_hw - setup state requiring device access
1524  * @dev_priv: device private
1525  *
1526  * Setup state that requires accessing the device, but doesn't require
1527  * exposing the driver via kernel internal or userspace interfaces.
1528  */
1529 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1530 {
1531         struct pci_dev *pdev = dev_priv->drm.pdev;
1532         int ret;
1533
1534         if (i915_inject_load_failure())
1535                 return -ENODEV;
1536
1537         intel_device_info_runtime_init(dev_priv);
1538
1539         if (HAS_PPGTT(dev_priv)) {
1540                 if (intel_vgpu_active(dev_priv) &&
1541                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1542                         i915_report_error(dev_priv,
1543                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1544                         return -ENXIO;
1545                 }
1546         }
1547
1548         if (HAS_EXECLISTS(dev_priv)) {
1549                 /*
1550                  * Older GVT emulation depends upon intercepting CSB mmio,
1551                  * which we no longer use, preferring to use the HWSP cache
1552                  * instead.
1553                  */
1554                 if (intel_vgpu_active(dev_priv) &&
1555                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1556                         i915_report_error(dev_priv,
1557                                           "old vGPU host found, support for HWSP emulation required\n");
1558                         return -ENXIO;
1559                 }
1560         }
1561
1562         intel_sanitize_options(dev_priv);
1563
1564         /* needs to be done before ggtt probe */
1565         edram_detect(dev_priv);
1566
1567         i915_perf_init(dev_priv);
1568
1569         ret = i915_ggtt_probe_hw(dev_priv);
1570         if (ret)
1571                 goto err_perf;
1572
1573         /*
1574          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1575          * otherwise the vga fbdev driver falls over.
1576          */
1577         ret = i915_kick_out_firmware_fb(dev_priv);
1578         if (ret) {
1579                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1580                 goto err_ggtt;
1581         }
1582
1583         ret = vga_remove_vgacon(pdev);
1584         if (ret) {
1585                 DRM_ERROR("failed to remove conflicting VGA console\n");
1586                 goto err_ggtt;
1587         }
1588
1589         ret = i915_ggtt_init_hw(dev_priv);
1590         if (ret)
1591                 goto err_ggtt;
1592
1593         ret = i915_ggtt_enable_hw(dev_priv);
1594         if (ret) {
1595                 DRM_ERROR("failed to enable GGTT\n");
1596                 goto err_ggtt;
1597         }
1598
1599         pci_set_master(pdev);
1600
1601         /*
1602          * We don't have a max segment size, so set it to the max so sg's
1603          * debugging layer doesn't complain
1604          */
1605         dma_set_max_seg_size(&pdev->dev, UINT_MAX);
1606
1607         /* overlay on gen2 is broken and can't address above 1G */
1608         if (IS_GEN(dev_priv, 2)) {
1609                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1610                 if (ret) {
1611                         DRM_ERROR("failed to set DMA mask\n");
1612
1613                         goto err_ggtt;
1614                 }
1615         }
1616
1617         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1618          * using 32bit addressing, overwriting memory if HWS is located
1619          * above 4GB.
1620          *
1621          * The documentation also mentions an issue with undefined
1622          * behaviour if any general state is accessed within a page above 4GB,
1623          * which also needs to be handled carefully.
1624          */
1625         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1626                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1627
1628                 if (ret) {
1629                         DRM_ERROR("failed to set DMA mask\n");
1630
1631                         goto err_ggtt;
1632                 }
1633         }
1634
1635         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1636                            PM_QOS_DEFAULT_VALUE);
1637
1638         intel_uncore_sanitize(dev_priv);
1639
1640         intel_gt_init_workarounds(dev_priv);
1641
1642         /* On the 945G/GM, the chipset reports the MSI capability on the
1643          * integrated graphics even though the support isn't actually there
1644          * according to the published specs.  It doesn't appear to function
1645          * correctly in testing on 945G.
1646          * This may be a side effect of MSI having been made available for PEG
1647          * and the registers being closely associated.
1648          *
1649          * According to chipset errata, on the 965GM, MSI interrupts may
1650          * be lost or delayed, and was defeatured. MSI interrupts seem to
1651          * get lost on g4x as well, and interrupt delivery seems to stay
1652          * properly dead afterwards. So we'll just disable them for all
1653          * pre-gen5 chipsets.
1654          *
1655          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1656          * interrupts even when in MSI mode. This results in spurious
1657          * interrupt warnings if the legacy irq no. is shared with another
1658          * device. The kernel then disables that interrupt source and so
1659          * prevents the other device from working properly.
1660          */
1661         if (INTEL_GEN(dev_priv) >= 5) {
1662                 if (pci_enable_msi(pdev) < 0)
1663                         DRM_DEBUG_DRIVER("can't enable MSI");
1664         }
1665
1666         ret = intel_gvt_init(dev_priv);
1667         if (ret)
1668                 goto err_msi;
1669
1670         intel_opregion_setup(dev_priv);
1671         /*
1672          * Fill the dram structure to get the system raw bandwidth and
1673          * dram info. This will be used for memory latency calculation.
1674          */
1675         intel_get_dram_info(dev_priv);
1676
1677         intel_bw_init_hw(dev_priv);
1678
1679         return 0;
1680
1681 err_msi:
1682         if (pdev->msi_enabled)
1683                 pci_disable_msi(pdev);
1684         pm_qos_remove_request(&dev_priv->pm_qos);
1685 err_ggtt:
1686         i915_ggtt_cleanup_hw(dev_priv);
1687 err_perf:
1688         i915_perf_fini(dev_priv);
1689         return ret;
1690 }
1691
1692 /**
1693  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1694  * @dev_priv: device private
1695  */
1696 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1697 {
1698         struct pci_dev *pdev = dev_priv->drm.pdev;
1699
1700         i915_perf_fini(dev_priv);
1701
1702         if (pdev->msi_enabled)
1703                 pci_disable_msi(pdev);
1704
1705         pm_qos_remove_request(&dev_priv->pm_qos);
1706 }
1707
1708 /**
1709  * i915_driver_register - register the driver with the rest of the system
1710  * @dev_priv: device private
1711  *
1712  * Perform any steps necessary to make the driver available via kernel
1713  * internal or userspace interfaces.
1714  */
1715 static void i915_driver_register(struct drm_i915_private *dev_priv)
1716 {
1717         struct drm_device *dev = &dev_priv->drm;
1718
1719         i915_gem_shrinker_register(dev_priv);
1720         i915_pmu_register(dev_priv);
1721
1722         /*
1723          * Notify a valid surface after modesetting,
1724          * when running inside a VM.
1725          */
1726         if (intel_vgpu_active(dev_priv))
1727                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1728
1729         /* Reveal our presence to userspace */
1730         if (drm_dev_register(dev, 0) == 0) {
1731                 i915_debugfs_register(dev_priv);
1732                 i915_setup_sysfs(dev_priv);
1733
1734                 /* Depends on sysfs having been initialized */
1735                 i915_perf_register(dev_priv);
1736         } else
1737                 DRM_ERROR("Failed to register driver for userspace access!\n");
1738
1739         if (HAS_DISPLAY(dev_priv)) {
1740                 /* Must be done after probing outputs */
1741                 intel_opregion_register(dev_priv);
1742                 acpi_video_register();
1743         }
1744
1745         if (IS_GEN(dev_priv, 5))
1746                 intel_gpu_ips_init(dev_priv);
1747
1748         intel_audio_init(dev_priv);
1749
1750         /*
1751          * Some ports require correctly set-up hpd registers for detection to
1752          * work properly (leading to ghost connected connector status), e.g. VGA
1753          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1754          * irqs are fully enabled. We do it last so that the async config
1755          * cannot run before the connectors are registered.
1756          */
1757         intel_fbdev_initial_config_async(dev);
1758
1759         /*
1760          * We need to coordinate the hotplugs with the asynchronous fbdev
1761          * configuration, for which we use the fbdev->async_cookie.
1762          */
1763         if (HAS_DISPLAY(dev_priv))
1764                 drm_kms_helper_poll_init(dev);
1765
1766         intel_power_domains_enable(dev_priv);
1767         intel_runtime_pm_enable(&dev_priv->runtime_pm);
1768 }
1769
1770 /**
1771  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1772  * @dev_priv: device private
1773  */
1774 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1775 {
1776         intel_runtime_pm_disable(&dev_priv->runtime_pm);
1777         intel_power_domains_disable(dev_priv);
1778
1779         intel_fbdev_unregister(dev_priv);
1780         intel_audio_deinit(dev_priv);
1781
1782         /*
1783          * After flushing the fbdev (incl. a late async config which will
1784          * have delayed queuing of a hotplug event), then flush the hotplug
1785          * events.
1786          */
1787         drm_kms_helper_poll_fini(&dev_priv->drm);
1788
1789         intel_gpu_ips_teardown();
1790         acpi_video_unregister();
1791         intel_opregion_unregister(dev_priv);
1792
1793         i915_perf_unregister(dev_priv);
1794         i915_pmu_unregister(dev_priv);
1795
1796         i915_teardown_sysfs(dev_priv);
1797         drm_dev_unplug(&dev_priv->drm);
1798
1799         i915_gem_shrinker_unregister(dev_priv);
1800 }
1801
1802 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1803 {
1804         if (drm_debug & DRM_UT_DRIVER) {
1805                 struct drm_printer p = drm_debug_printer("i915 device info:");
1806
1807                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
1808                            INTEL_DEVID(dev_priv),
1809                            INTEL_REVID(dev_priv),
1810                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1811                            intel_subplatform(RUNTIME_INFO(dev_priv),
1812                                              INTEL_INFO(dev_priv)->platform),
1813                            INTEL_GEN(dev_priv));
1814
1815                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1816                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1817         }
1818
1819         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1820                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1821         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1822                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1823         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1824                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1825 }
1826
1827 static struct drm_i915_private *
1828 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1829 {
1830         const struct intel_device_info *match_info =
1831                 (struct intel_device_info *)ent->driver_data;
1832         struct intel_device_info *device_info;
1833         struct drm_i915_private *i915;
1834         int err;
1835
1836         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1837         if (!i915)
1838                 return ERR_PTR(-ENOMEM);
1839
1840         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1841         if (err) {
1842                 kfree(i915);
1843                 return ERR_PTR(err);
1844         }
1845
1846         i915->drm.pdev = pdev;
1847         i915->drm.dev_private = i915;
1848         pci_set_drvdata(pdev, &i915->drm);
1849
1850         /* Setup the write-once "constant" device info */
1851         device_info = mkwrite_device_info(i915);
1852         memcpy(device_info, match_info, sizeof(*device_info));
1853         RUNTIME_INFO(i915)->device_id = pdev->device;
1854
1855         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1856
1857         return i915;
1858 }
1859
1860 static void i915_driver_destroy(struct drm_i915_private *i915)
1861 {
1862         struct pci_dev *pdev = i915->drm.pdev;
1863
1864         drm_dev_fini(&i915->drm);
1865         kfree(i915);
1866
1867         /* And make sure we never chase our dangling pointer from pci_dev */
1868         pci_set_drvdata(pdev, NULL);
1869 }
1870
1871 /**
1872  * i915_driver_load - setup chip and create an initial config
1873  * @pdev: PCI device
1874  * @ent: matching PCI ID entry
1875  *
1876  * The driver load routine has to do several things:
1877  *   - drive output discovery via intel_modeset_init()
1878  *   - initialize the memory manager
1879  *   - allocate initial config memory
1880  *   - setup the DRM framebuffer with the allocated memory
1881  */
1882 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1883 {
1884         const struct intel_device_info *match_info =
1885                 (struct intel_device_info *)ent->driver_data;
1886         struct drm_i915_private *dev_priv;
1887         int ret;
1888
1889         dev_priv = i915_driver_create(pdev, ent);
1890         if (IS_ERR(dev_priv))
1891                 return PTR_ERR(dev_priv);
1892
1893         /* Disable nuclear pageflip by default on pre-ILK */
1894         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1895                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1896
1897         ret = pci_enable_device(pdev);
1898         if (ret)
1899                 goto out_fini;
1900
1901         ret = i915_driver_init_early(dev_priv);
1902         if (ret < 0)
1903                 goto out_pci_disable;
1904
1905         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1906
1907         ret = i915_driver_init_mmio(dev_priv);
1908         if (ret < 0)
1909                 goto out_runtime_pm_put;
1910
1911         ret = i915_driver_init_hw(dev_priv);
1912         if (ret < 0)
1913                 goto out_cleanup_mmio;
1914
1915         ret = i915_load_modeset_init(&dev_priv->drm);
1916         if (ret < 0)
1917                 goto out_cleanup_hw;
1918
1919         i915_driver_register(dev_priv);
1920
1921         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1922
1923         i915_welcome_messages(dev_priv);
1924
1925         return 0;
1926
1927 out_cleanup_hw:
1928         i915_driver_cleanup_hw(dev_priv);
1929         i915_ggtt_cleanup_hw(dev_priv);
1930 out_cleanup_mmio:
1931         i915_driver_cleanup_mmio(dev_priv);
1932 out_runtime_pm_put:
1933         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1934         i915_driver_cleanup_early(dev_priv);
1935 out_pci_disable:
1936         pci_disable_device(pdev);
1937 out_fini:
1938         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1939         i915_driver_destroy(dev_priv);
1940         return ret;
1941 }
1942
1943 void i915_driver_unload(struct drm_device *dev)
1944 {
1945         struct drm_i915_private *dev_priv = to_i915(dev);
1946         struct pci_dev *pdev = dev_priv->drm.pdev;
1947
1948         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1949
1950         i915_driver_unregister(dev_priv);
1951
1952         /*
1953          * After unregistering the device to prevent any new users, cancel
1954          * all in-flight requests so that we can quickly unbind the active
1955          * resources.
1956          */
1957         i915_gem_set_wedged(dev_priv);
1958
1959         /* Flush any external code that still may be under the RCU lock */
1960         synchronize_rcu();
1961
1962         i915_gem_suspend(dev_priv);
1963
1964         drm_atomic_helper_shutdown(dev);
1965
1966         intel_gvt_cleanup(dev_priv);
1967
1968         intel_modeset_cleanup(dev);
1969
1970         intel_bios_cleanup(dev_priv);
1971
1972         vga_switcheroo_unregister_client(pdev);
1973         vga_client_register(pdev, NULL, NULL, NULL);
1974
1975         intel_csr_ucode_fini(dev_priv);
1976
1977         /* Free error state after interrupts are fully disabled. */
1978         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1979         i915_reset_error_state(dev_priv);
1980
1981         i915_gem_fini_hw(dev_priv);
1982
1983         intel_power_domains_fini_hw(dev_priv);
1984
1985         i915_driver_cleanup_hw(dev_priv);
1986
1987         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1988 }
1989
1990 static void i915_driver_release(struct drm_device *dev)
1991 {
1992         struct drm_i915_private *dev_priv = to_i915(dev);
1993         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1994
1995         disable_rpm_wakeref_asserts(rpm);
1996
1997         i915_gem_fini(dev_priv);
1998
1999         i915_ggtt_cleanup_hw(dev_priv);
2000         i915_driver_cleanup_mmio(dev_priv);
2001
2002         enable_rpm_wakeref_asserts(rpm);
2003         intel_runtime_pm_cleanup(rpm);
2004
2005         i915_driver_cleanup_early(dev_priv);
2006         i915_driver_destroy(dev_priv);
2007 }
2008
2009 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2010 {
2011         struct drm_i915_private *i915 = to_i915(dev);
2012         int ret;
2013
2014         ret = i915_gem_open(i915, file);
2015         if (ret)
2016                 return ret;
2017
2018         return 0;
2019 }
2020
2021 /**
2022  * i915_driver_lastclose - clean up after all DRM clients have exited
2023  * @dev: DRM device
2024  *
2025  * Take care of cleaning up after all DRM clients have exited.  In the
2026  * mode setting case, we want to restore the kernel's initial mode (just
2027  * in case the last client left us in a bad state).
2028  *
2029  * Additionally, in the non-mode setting case, we'll tear down the GTT
2030  * and DMA structures, since the kernel won't be using them, and clea
2031  * up any GEM state.
2032  */
2033 static void i915_driver_lastclose(struct drm_device *dev)
2034 {
2035         intel_fbdev_restore_mode(dev);
2036         vga_switcheroo_process_delayed_switch();
2037 }
2038
2039 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2040 {
2041         struct drm_i915_file_private *file_priv = file->driver_priv;
2042
2043         mutex_lock(&dev->struct_mutex);
2044         i915_gem_context_close(file);
2045         i915_gem_release(dev, file);
2046         mutex_unlock(&dev->struct_mutex);
2047
2048         kfree(file_priv);
2049 }
2050
2051 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
2052 {
2053         struct drm_device *dev = &dev_priv->drm;
2054         struct intel_encoder *encoder;
2055
2056         drm_modeset_lock_all(dev);
2057         for_each_intel_encoder(dev, encoder)
2058                 if (encoder->suspend)
2059                         encoder->suspend(encoder);
2060         drm_modeset_unlock_all(dev);
2061 }
2062
2063 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2064                               bool rpm_resume);
2065 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
2066
2067 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
2068 {
2069 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2070         if (acpi_target_system_state() < ACPI_STATE_S3)
2071                 return true;
2072 #endif
2073         return false;
2074 }
2075
2076 static int i915_drm_prepare(struct drm_device *dev)
2077 {
2078         struct drm_i915_private *i915 = to_i915(dev);
2079
2080         /*
2081          * NB intel_display_suspend() may issue new requests after we've
2082          * ostensibly marked the GPU as ready-to-sleep here. We need to
2083          * split out that work and pull it forward so that after point,
2084          * the GPU is not woken again.
2085          */
2086         i915_gem_suspend(i915);
2087
2088         return 0;
2089 }
2090
2091 static int i915_drm_suspend(struct drm_device *dev)
2092 {
2093         struct drm_i915_private *dev_priv = to_i915(dev);
2094         struct pci_dev *pdev = dev_priv->drm.pdev;
2095         pci_power_t opregion_target_state;
2096
2097         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2098
2099         /* We do a lot of poking in a lot of registers, make sure they work
2100          * properly. */
2101         intel_power_domains_disable(dev_priv);
2102
2103         drm_kms_helper_poll_disable(dev);
2104
2105         pci_save_state(pdev);
2106
2107         intel_display_suspend(dev);
2108
2109         intel_dp_mst_suspend(dev_priv);
2110
2111         intel_runtime_pm_disable_interrupts(dev_priv);
2112         intel_hpd_cancel_work(dev_priv);
2113
2114         intel_suspend_encoders(dev_priv);
2115
2116         intel_suspend_hw(dev_priv);
2117
2118         i915_gem_suspend_gtt_mappings(dev_priv);
2119
2120         i915_save_state(dev_priv);
2121
2122         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2123         intel_opregion_suspend(dev_priv, opregion_target_state);
2124
2125         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2126
2127         dev_priv->suspend_count++;
2128
2129         intel_csr_ucode_suspend(dev_priv);
2130
2131         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2132
2133         return 0;
2134 }
2135
2136 static enum i915_drm_suspend_mode
2137 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2138 {
2139         if (hibernate)
2140                 return I915_DRM_SUSPEND_HIBERNATE;
2141
2142         if (suspend_to_idle(dev_priv))
2143                 return I915_DRM_SUSPEND_IDLE;
2144
2145         return I915_DRM_SUSPEND_MEM;
2146 }
2147
2148 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2149 {
2150         struct drm_i915_private *dev_priv = to_i915(dev);
2151         struct pci_dev *pdev = dev_priv->drm.pdev;
2152         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2153         int ret;
2154
2155         disable_rpm_wakeref_asserts(rpm);
2156
2157         i915_gem_suspend_late(dev_priv);
2158
2159         intel_uncore_suspend(&dev_priv->uncore);
2160
2161         intel_power_domains_suspend(dev_priv,
2162                                     get_suspend_mode(dev_priv, hibernation));
2163
2164         ret = 0;
2165         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2166                 bxt_enable_dc9(dev_priv);
2167         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2168                 hsw_enable_pc8(dev_priv);
2169         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2170                 ret = vlv_suspend_complete(dev_priv);
2171
2172         if (ret) {
2173                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2174                 intel_power_domains_resume(dev_priv);
2175
2176                 goto out;
2177         }
2178
2179         pci_disable_device(pdev);
2180         /*
2181          * During hibernation on some platforms the BIOS may try to access
2182          * the device even though it's already in D3 and hang the machine. So
2183          * leave the device in D0 on those platforms and hope the BIOS will
2184          * power down the device properly. The issue was seen on multiple old
2185          * GENs with different BIOS vendors, so having an explicit blacklist
2186          * is inpractical; apply the workaround on everything pre GEN6. The
2187          * platforms where the issue was seen:
2188          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2189          * Fujitsu FSC S7110
2190          * Acer Aspire 1830T
2191          */
2192         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2193                 pci_set_power_state(pdev, PCI_D3hot);
2194
2195 out:
2196         enable_rpm_wakeref_asserts(rpm);
2197         if (!dev_priv->uncore.user_forcewake.count)
2198                 intel_runtime_pm_cleanup(rpm);
2199
2200         return ret;
2201 }
2202
2203 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2204 {
2205         int error;
2206
2207         if (!dev) {
2208                 DRM_ERROR("dev: %p\n", dev);
2209                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2210                 return -ENODEV;
2211         }
2212
2213         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2214                          state.event != PM_EVENT_FREEZE))
2215                 return -EINVAL;
2216
2217         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2218                 return 0;
2219
2220         error = i915_drm_suspend(dev);
2221         if (error)
2222                 return error;
2223
2224         return i915_drm_suspend_late(dev, false);
2225 }
2226
2227 static int i915_drm_resume(struct drm_device *dev)
2228 {
2229         struct drm_i915_private *dev_priv = to_i915(dev);
2230         int ret;
2231
2232         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2233         intel_sanitize_gt_powersave(dev_priv);
2234
2235         i915_gem_sanitize(dev_priv);
2236
2237         ret = i915_ggtt_enable_hw(dev_priv);
2238         if (ret)
2239                 DRM_ERROR("failed to re-enable GGTT\n");
2240
2241         intel_csr_ucode_resume(dev_priv);
2242
2243         i915_restore_state(dev_priv);
2244         intel_pps_unlock_regs_wa(dev_priv);
2245
2246         intel_init_pch_refclk(dev_priv);
2247
2248         /*
2249          * Interrupts have to be enabled before any batches are run. If not the
2250          * GPU will hang. i915_gem_init_hw() will initiate batches to
2251          * update/restore the context.
2252          *
2253          * drm_mode_config_reset() needs AUX interrupts.
2254          *
2255          * Modeset enabling in intel_modeset_init_hw() also needs working
2256          * interrupts.
2257          */
2258         intel_runtime_pm_enable_interrupts(dev_priv);
2259
2260         drm_mode_config_reset(dev);
2261
2262         i915_gem_resume(dev_priv);
2263
2264         intel_modeset_init_hw(dev);
2265         intel_init_clock_gating(dev_priv);
2266
2267         spin_lock_irq(&dev_priv->irq_lock);
2268         if (dev_priv->display.hpd_irq_setup)
2269                 dev_priv->display.hpd_irq_setup(dev_priv);
2270         spin_unlock_irq(&dev_priv->irq_lock);
2271
2272         intel_dp_mst_resume(dev_priv);
2273
2274         intel_display_resume(dev);
2275
2276         drm_kms_helper_poll_enable(dev);
2277
2278         /*
2279          * ... but also need to make sure that hotplug processing
2280          * doesn't cause havoc. Like in the driver load code we don't
2281          * bother with the tiny race here where we might lose hotplug
2282          * notifications.
2283          * */
2284         intel_hpd_init(dev_priv);
2285
2286         intel_opregion_resume(dev_priv);
2287
2288         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2289
2290         intel_power_domains_enable(dev_priv);
2291
2292         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2293
2294         return 0;
2295 }
2296
2297 static int i915_drm_resume_early(struct drm_device *dev)
2298 {
2299         struct drm_i915_private *dev_priv = to_i915(dev);
2300         struct pci_dev *pdev = dev_priv->drm.pdev;
2301         int ret;
2302
2303         /*
2304          * We have a resume ordering issue with the snd-hda driver also
2305          * requiring our device to be power up. Due to the lack of a
2306          * parent/child relationship we currently solve this with an early
2307          * resume hook.
2308          *
2309          * FIXME: This should be solved with a special hdmi sink device or
2310          * similar so that power domains can be employed.
2311          */
2312
2313         /*
2314          * Note that we need to set the power state explicitly, since we
2315          * powered off the device during freeze and the PCI core won't power
2316          * it back up for us during thaw. Powering off the device during
2317          * freeze is not a hard requirement though, and during the
2318          * suspend/resume phases the PCI core makes sure we get here with the
2319          * device powered on. So in case we change our freeze logic and keep
2320          * the device powered we can also remove the following set power state
2321          * call.
2322          */
2323         ret = pci_set_power_state(pdev, PCI_D0);
2324         if (ret) {
2325                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2326                 return ret;
2327         }
2328
2329         /*
2330          * Note that pci_enable_device() first enables any parent bridge
2331          * device and only then sets the power state for this device. The
2332          * bridge enabling is a nop though, since bridge devices are resumed
2333          * first. The order of enabling power and enabling the device is
2334          * imposed by the PCI core as described above, so here we preserve the
2335          * same order for the freeze/thaw phases.
2336          *
2337          * TODO: eventually we should remove pci_disable_device() /
2338          * pci_enable_enable_device() from suspend/resume. Due to how they
2339          * depend on the device enable refcount we can't anyway depend on them
2340          * disabling/enabling the device.
2341          */
2342         if (pci_enable_device(pdev))
2343                 return -EIO;
2344
2345         pci_set_master(pdev);
2346
2347         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2348
2349         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2350                 ret = vlv_resume_prepare(dev_priv, false);
2351         if (ret)
2352                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2353                           ret);
2354
2355         intel_uncore_resume_early(&dev_priv->uncore);
2356
2357         i915_check_and_clear_faults(dev_priv);
2358
2359         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2360                 gen9_sanitize_dc_state(dev_priv);
2361                 bxt_disable_dc9(dev_priv);
2362         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2363                 hsw_disable_pc8(dev_priv);
2364         }
2365
2366         intel_uncore_sanitize(dev_priv);
2367
2368         intel_power_domains_resume(dev_priv);
2369
2370         intel_gt_sanitize(dev_priv, true);
2371
2372         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2373
2374         return ret;
2375 }
2376
2377 static int i915_resume_switcheroo(struct drm_device *dev)
2378 {
2379         int ret;
2380
2381         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2382                 return 0;
2383
2384         ret = i915_drm_resume_early(dev);
2385         if (ret)
2386                 return ret;
2387
2388         return i915_drm_resume(dev);
2389 }
2390
2391 static int i915_pm_prepare(struct device *kdev)
2392 {
2393         struct pci_dev *pdev = to_pci_dev(kdev);
2394         struct drm_device *dev = pci_get_drvdata(pdev);
2395
2396         if (!dev) {
2397                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2398                 return -ENODEV;
2399         }
2400
2401         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2402                 return 0;
2403
2404         return i915_drm_prepare(dev);
2405 }
2406
2407 static int i915_pm_suspend(struct device *kdev)
2408 {
2409         struct pci_dev *pdev = to_pci_dev(kdev);
2410         struct drm_device *dev = pci_get_drvdata(pdev);
2411
2412         if (!dev) {
2413                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2414                 return -ENODEV;
2415         }
2416
2417         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2418                 return 0;
2419
2420         return i915_drm_suspend(dev);
2421 }
2422
2423 static int i915_pm_suspend_late(struct device *kdev)
2424 {
2425         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2426
2427         /*
2428          * We have a suspend ordering issue with the snd-hda driver also
2429          * requiring our device to be power up. Due to the lack of a
2430          * parent/child relationship we currently solve this with an late
2431          * suspend hook.
2432          *
2433          * FIXME: This should be solved with a special hdmi sink device or
2434          * similar so that power domains can be employed.
2435          */
2436         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2437                 return 0;
2438
2439         return i915_drm_suspend_late(dev, false);
2440 }
2441
2442 static int i915_pm_poweroff_late(struct device *kdev)
2443 {
2444         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2445
2446         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2447                 return 0;
2448
2449         return i915_drm_suspend_late(dev, true);
2450 }
2451
2452 static int i915_pm_resume_early(struct device *kdev)
2453 {
2454         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2455
2456         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2457                 return 0;
2458
2459         return i915_drm_resume_early(dev);
2460 }
2461
2462 static int i915_pm_resume(struct device *kdev)
2463 {
2464         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2465
2466         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2467                 return 0;
2468
2469         return i915_drm_resume(dev);
2470 }
2471
2472 /* freeze: before creating the hibernation_image */
2473 static int i915_pm_freeze(struct device *kdev)
2474 {
2475         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2476         int ret;
2477
2478         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2479                 ret = i915_drm_suspend(dev);
2480                 if (ret)
2481                         return ret;
2482         }
2483
2484         ret = i915_gem_freeze(kdev_to_i915(kdev));
2485         if (ret)
2486                 return ret;
2487
2488         return 0;
2489 }
2490
2491 static int i915_pm_freeze_late(struct device *kdev)
2492 {
2493         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2494         int ret;
2495
2496         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2497                 ret = i915_drm_suspend_late(dev, true);
2498                 if (ret)
2499                         return ret;
2500         }
2501
2502         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2503         if (ret)
2504                 return ret;
2505
2506         return 0;
2507 }
2508
2509 /* thaw: called after creating the hibernation image, but before turning off. */
2510 static int i915_pm_thaw_early(struct device *kdev)
2511 {
2512         return i915_pm_resume_early(kdev);
2513 }
2514
2515 static int i915_pm_thaw(struct device *kdev)
2516 {
2517         return i915_pm_resume(kdev);
2518 }
2519
2520 /* restore: called after loading the hibernation image. */
2521 static int i915_pm_restore_early(struct device *kdev)
2522 {
2523         return i915_pm_resume_early(kdev);
2524 }
2525
2526 static int i915_pm_restore(struct device *kdev)
2527 {
2528         return i915_pm_resume(kdev);
2529 }
2530
2531 /*
2532  * Save all Gunit registers that may be lost after a D3 and a subsequent
2533  * S0i[R123] transition. The list of registers needing a save/restore is
2534  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2535  * registers in the following way:
2536  * - Driver: saved/restored by the driver
2537  * - Punit : saved/restored by the Punit firmware
2538  * - No, w/o marking: no need to save/restore, since the register is R/O or
2539  *                    used internally by the HW in a way that doesn't depend
2540  *                    keeping the content across a suspend/resume.
2541  * - Debug : used for debugging
2542  *
2543  * We save/restore all registers marked with 'Driver', with the following
2544  * exceptions:
2545  * - Registers out of use, including also registers marked with 'Debug'.
2546  *   These have no effect on the driver's operation, so we don't save/restore
2547  *   them to reduce the overhead.
2548  * - Registers that are fully setup by an initialization function called from
2549  *   the resume path. For example many clock gating and RPS/RC6 registers.
2550  * - Registers that provide the right functionality with their reset defaults.
2551  *
2552  * TODO: Except for registers that based on the above 3 criteria can be safely
2553  * ignored, we save/restore all others, practically treating the HW context as
2554  * a black-box for the driver. Further investigation is needed to reduce the
2555  * saved/restored registers even further, by following the same 3 criteria.
2556  */
2557 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2558 {
2559         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2560         int i;
2561
2562         /* GAM 0x4000-0x4770 */
2563         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2564         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2565         s->arb_mode             = I915_READ(ARB_MODE);
2566         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2567         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2568
2569         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2570                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2571
2572         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2573         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2574
2575         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2576         s->ecochk               = I915_READ(GAM_ECOCHK);
2577         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2578         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2579
2580         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2581
2582         /* MBC 0x9024-0x91D0, 0x8500 */
2583         s->g3dctl               = I915_READ(VLV_G3DCTL);
2584         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2585         s->mbctl                = I915_READ(GEN6_MBCTL);
2586
2587         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2588         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2589         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2590         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2591         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2592         s->rstctl               = I915_READ(GEN6_RSTCTL);
2593         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2594
2595         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2596         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2597         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2598         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2599         s->ecobus               = I915_READ(ECOBUS);
2600         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2601         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2602         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2603         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2604         s->rcedata              = I915_READ(VLV_RCEDATA);
2605         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2606
2607         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2608         s->gt_imr               = I915_READ(GTIMR);
2609         s->gt_ier               = I915_READ(GTIER);
2610         s->pm_imr               = I915_READ(GEN6_PMIMR);
2611         s->pm_ier               = I915_READ(GEN6_PMIER);
2612
2613         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2614                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2615
2616         /* GT SA CZ domain, 0x100000-0x138124 */
2617         s->tilectl              = I915_READ(TILECTL);
2618         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2619         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2620         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2621         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2622
2623         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2624         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2625         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2626         s->pcbr                 = I915_READ(VLV_PCBR);
2627         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2628
2629         /*
2630          * Not saving any of:
2631          * DFT,         0x9800-0x9EC0
2632          * SARB,        0xB000-0xB1FC
2633          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2634          * PCI CFG
2635          */
2636 }
2637
2638 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2639 {
2640         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2641         u32 val;
2642         int i;
2643
2644         /* GAM 0x4000-0x4770 */
2645         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2646         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2647         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2648         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2649         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2650
2651         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2652                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2653
2654         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2655         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2656
2657         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2658         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2659         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2660         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2661
2662         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2663
2664         /* MBC 0x9024-0x91D0, 0x8500 */
2665         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2666         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2667         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2668
2669         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2670         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2671         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2672         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2673         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2674         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2675         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2676
2677         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2678         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2679         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2680         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2681         I915_WRITE(ECOBUS,              s->ecobus);
2682         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2683         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2684         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2685         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2686         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2687         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2688
2689         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2690         I915_WRITE(GTIMR,               s->gt_imr);
2691         I915_WRITE(GTIER,               s->gt_ier);
2692         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2693         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2694
2695         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2696                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2697
2698         /* GT SA CZ domain, 0x100000-0x138124 */
2699         I915_WRITE(TILECTL,                     s->tilectl);
2700         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2701         /*
2702          * Preserve the GT allow wake and GFX force clock bit, they are not
2703          * be restored, as they are used to control the s0ix suspend/resume
2704          * sequence by the caller.
2705          */
2706         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2707         val &= VLV_GTLC_ALLOWWAKEREQ;
2708         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2709         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2710
2711         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2712         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2713         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2714         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2715
2716         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2717
2718         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2719         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2720         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2721         I915_WRITE(VLV_PCBR,                    s->pcbr);
2722         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2723 }
2724
2725 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
2726                                   u32 mask, u32 val)
2727 {
2728         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2729         u32 reg_value;
2730         int ret;
2731
2732         /* The HW does not like us polling for PW_STATUS frequently, so
2733          * use the sleeping loop rather than risk the busy spin within
2734          * intel_wait_for_register().
2735          *
2736          * Transitioning between RC6 states should be at most 2ms (see
2737          * valleyview_enable_rps) so use a 3ms timeout.
2738          */
2739         ret = wait_for(((reg_value =
2740                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
2741                        == val, 3);
2742
2743         /* just trace the final value */
2744         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2745
2746         return ret;
2747 }
2748
2749 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2750 {
2751         u32 val;
2752         int err;
2753
2754         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2755         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2756         if (force_on)
2757                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2758         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2759
2760         if (!force_on)
2761                 return 0;
2762
2763         err = intel_wait_for_register(&dev_priv->uncore,
2764                                       VLV_GTLC_SURVIVABILITY_REG,
2765                                       VLV_GFX_CLK_STATUS_BIT,
2766                                       VLV_GFX_CLK_STATUS_BIT,
2767                                       20);
2768         if (err)
2769                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2770                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2771
2772         return err;
2773 }
2774
2775 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2776 {
2777         u32 mask;
2778         u32 val;
2779         int err;
2780
2781         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2782         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2783         if (allow)
2784                 val |= VLV_GTLC_ALLOWWAKEREQ;
2785         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2786         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2787
2788         mask = VLV_GTLC_ALLOWWAKEACK;
2789         val = allow ? mask : 0;
2790
2791         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2792         if (err)
2793                 DRM_ERROR("timeout disabling GT waking\n");
2794
2795         return err;
2796 }
2797
2798 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2799                                   bool wait_for_on)
2800 {
2801         u32 mask;
2802         u32 val;
2803
2804         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2805         val = wait_for_on ? mask : 0;
2806
2807         /*
2808          * RC6 transitioning can be delayed up to 2 msec (see
2809          * valleyview_enable_rps), use 3 msec for safety.
2810          *
2811          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2812          * reset and we are trying to force the machine to sleep.
2813          */
2814         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2815                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2816                                  onoff(wait_for_on));
2817 }
2818
2819 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2820 {
2821         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2822                 return;
2823
2824         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2825         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2826 }
2827
2828 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2829 {
2830         u32 mask;
2831         int err;
2832
2833         /*
2834          * Bspec defines the following GT well on flags as debug only, so
2835          * don't treat them as hard failures.
2836          */
2837         vlv_wait_for_gt_wells(dev_priv, false);
2838
2839         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2840         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2841
2842         vlv_check_no_gt_access(dev_priv);
2843
2844         err = vlv_force_gfx_clock(dev_priv, true);
2845         if (err)
2846                 goto err1;
2847
2848         err = vlv_allow_gt_wake(dev_priv, false);
2849         if (err)
2850                 goto err2;
2851
2852         if (!IS_CHERRYVIEW(dev_priv))
2853                 vlv_save_gunit_s0ix_state(dev_priv);
2854
2855         err = vlv_force_gfx_clock(dev_priv, false);
2856         if (err)
2857                 goto err2;
2858
2859         return 0;
2860
2861 err2:
2862         /* For safety always re-enable waking and disable gfx clock forcing */
2863         vlv_allow_gt_wake(dev_priv, true);
2864 err1:
2865         vlv_force_gfx_clock(dev_priv, false);
2866
2867         return err;
2868 }
2869
2870 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2871                                 bool rpm_resume)
2872 {
2873         int err;
2874         int ret;
2875
2876         /*
2877          * If any of the steps fail just try to continue, that's the best we
2878          * can do at this point. Return the first error code (which will also
2879          * leave RPM permanently disabled).
2880          */
2881         ret = vlv_force_gfx_clock(dev_priv, true);
2882
2883         if (!IS_CHERRYVIEW(dev_priv))
2884                 vlv_restore_gunit_s0ix_state(dev_priv);
2885
2886         err = vlv_allow_gt_wake(dev_priv, true);
2887         if (!ret)
2888                 ret = err;
2889
2890         err = vlv_force_gfx_clock(dev_priv, false);
2891         if (!ret)
2892                 ret = err;
2893
2894         vlv_check_no_gt_access(dev_priv);
2895
2896         if (rpm_resume)
2897                 intel_init_clock_gating(dev_priv);
2898
2899         return ret;
2900 }
2901
2902 static int intel_runtime_suspend(struct device *kdev)
2903 {
2904         struct pci_dev *pdev = to_pci_dev(kdev);
2905         struct drm_device *dev = pci_get_drvdata(pdev);
2906         struct drm_i915_private *dev_priv = to_i915(dev);
2907         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
2908         int ret;
2909
2910         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2911                 return -ENODEV;
2912
2913         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2914                 return -ENODEV;
2915
2916         DRM_DEBUG_KMS("Suspending device\n");
2917
2918         disable_rpm_wakeref_asserts(rpm);
2919
2920         /*
2921          * We are safe here against re-faults, since the fault handler takes
2922          * an RPM reference.
2923          */
2924         i915_gem_runtime_suspend(dev_priv);
2925
2926         intel_uc_runtime_suspend(dev_priv);
2927
2928         intel_runtime_pm_disable_interrupts(dev_priv);
2929
2930         intel_uncore_suspend(&dev_priv->uncore);
2931
2932         ret = 0;
2933         if (INTEL_GEN(dev_priv) >= 11) {
2934                 icl_display_core_uninit(dev_priv);
2935                 bxt_enable_dc9(dev_priv);
2936         } else if (IS_GEN9_LP(dev_priv)) {
2937                 bxt_display_core_uninit(dev_priv);
2938                 bxt_enable_dc9(dev_priv);
2939         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2940                 hsw_enable_pc8(dev_priv);
2941         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2942                 ret = vlv_suspend_complete(dev_priv);
2943         }
2944
2945         if (ret) {
2946                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2947                 intel_uncore_runtime_resume(&dev_priv->uncore);
2948
2949                 intel_runtime_pm_enable_interrupts(dev_priv);
2950
2951                 intel_uc_resume(dev_priv);
2952
2953                 i915_gem_init_swizzling(dev_priv);
2954                 i915_gem_restore_fences(dev_priv);
2955
2956                 enable_rpm_wakeref_asserts(rpm);
2957
2958                 return ret;
2959         }
2960
2961         enable_rpm_wakeref_asserts(rpm);
2962         intel_runtime_pm_cleanup(rpm);
2963
2964         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
2965                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2966
2967         rpm->suspended = true;
2968
2969         /*
2970          * FIXME: We really should find a document that references the arguments
2971          * used below!
2972          */
2973         if (IS_BROADWELL(dev_priv)) {
2974                 /*
2975                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2976                  * being detected, and the call we do at intel_runtime_resume()
2977                  * won't be able to restore them. Since PCI_D3hot matches the
2978                  * actual specification and appears to be working, use it.
2979                  */
2980                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2981         } else {
2982                 /*
2983                  * current versions of firmware which depend on this opregion
2984                  * notification have repurposed the D1 definition to mean
2985                  * "runtime suspended" vs. what you would normally expect (D3)
2986                  * to distinguish it from notifications that might be sent via
2987                  * the suspend path.
2988                  */
2989                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2990         }
2991
2992         assert_forcewakes_inactive(&dev_priv->uncore);
2993
2994         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2995                 intel_hpd_poll_init(dev_priv);
2996
2997         DRM_DEBUG_KMS("Device suspended\n");
2998         return 0;
2999 }
3000
3001 static int intel_runtime_resume(struct device *kdev)
3002 {
3003         struct pci_dev *pdev = to_pci_dev(kdev);
3004         struct drm_device *dev = pci_get_drvdata(pdev);
3005         struct drm_i915_private *dev_priv = to_i915(dev);
3006         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
3007         int ret = 0;
3008
3009         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
3010                 return -ENODEV;
3011
3012         DRM_DEBUG_KMS("Resuming device\n");
3013
3014         WARN_ON_ONCE(atomic_read(&rpm->wakeref_count));
3015         disable_rpm_wakeref_asserts(rpm);
3016
3017         intel_opregion_notify_adapter(dev_priv, PCI_D0);
3018         rpm->suspended = false;
3019         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
3020                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
3021
3022         if (INTEL_GEN(dev_priv) >= 11) {
3023                 bxt_disable_dc9(dev_priv);
3024                 icl_display_core_init(dev_priv, true);
3025                 if (dev_priv->csr.dmc_payload) {
3026                         if (dev_priv->csr.allowed_dc_mask &
3027                             DC_STATE_EN_UPTO_DC6)
3028                                 skl_enable_dc6(dev_priv);
3029                         else if (dev_priv->csr.allowed_dc_mask &
3030                                  DC_STATE_EN_UPTO_DC5)
3031                                 gen9_enable_dc5(dev_priv);
3032                 }
3033         } else if (IS_GEN9_LP(dev_priv)) {
3034                 bxt_disable_dc9(dev_priv);
3035                 bxt_display_core_init(dev_priv, true);
3036                 if (dev_priv->csr.dmc_payload &&
3037                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
3038                         gen9_enable_dc5(dev_priv);
3039         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3040                 hsw_disable_pc8(dev_priv);
3041         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3042                 ret = vlv_resume_prepare(dev_priv, true);
3043         }
3044
3045         intel_uncore_runtime_resume(&dev_priv->uncore);
3046
3047         intel_runtime_pm_enable_interrupts(dev_priv);
3048
3049         intel_uc_resume(dev_priv);
3050
3051         /*
3052          * No point of rolling back things in case of an error, as the best
3053          * we can do is to hope that things will still work (and disable RPM).
3054          */
3055         i915_gem_init_swizzling(dev_priv);
3056         i915_gem_restore_fences(dev_priv);
3057
3058         /*
3059          * On VLV/CHV display interrupts are part of the display
3060          * power well, so hpd is reinitialized from there. For
3061          * everyone else do it here.
3062          */
3063         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
3064                 intel_hpd_init(dev_priv);
3065
3066         intel_enable_ipc(dev_priv);
3067
3068         enable_rpm_wakeref_asserts(rpm);
3069
3070         if (ret)
3071                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3072         else
3073                 DRM_DEBUG_KMS("Device resumed\n");
3074
3075         return ret;
3076 }
3077
3078 const struct dev_pm_ops i915_pm_ops = {
3079         /*
3080          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3081          * PMSG_RESUME]
3082          */
3083         .prepare = i915_pm_prepare,
3084         .suspend = i915_pm_suspend,
3085         .suspend_late = i915_pm_suspend_late,
3086         .resume_early = i915_pm_resume_early,
3087         .resume = i915_pm_resume,
3088
3089         /*
3090          * S4 event handlers
3091          * @freeze, @freeze_late    : called (1) before creating the
3092          *                            hibernation image [PMSG_FREEZE] and
3093          *                            (2) after rebooting, before restoring
3094          *                            the image [PMSG_QUIESCE]
3095          * @thaw, @thaw_early       : called (1) after creating the hibernation
3096          *                            image, before writing it [PMSG_THAW]
3097          *                            and (2) after failing to create or
3098          *                            restore the image [PMSG_RECOVER]
3099          * @poweroff, @poweroff_late: called after writing the hibernation
3100          *                            image, before rebooting [PMSG_HIBERNATE]
3101          * @restore, @restore_early : called after rebooting and restoring the
3102          *                            hibernation image [PMSG_RESTORE]
3103          */
3104         .freeze = i915_pm_freeze,
3105         .freeze_late = i915_pm_freeze_late,
3106         .thaw_early = i915_pm_thaw_early,
3107         .thaw = i915_pm_thaw,
3108         .poweroff = i915_pm_suspend,
3109         .poweroff_late = i915_pm_poweroff_late,
3110         .restore_early = i915_pm_restore_early,
3111         .restore = i915_pm_restore,
3112
3113         /* S0ix (via runtime suspend) event handlers */
3114         .runtime_suspend = intel_runtime_suspend,
3115         .runtime_resume = intel_runtime_resume,
3116 };
3117
3118 static const struct vm_operations_struct i915_gem_vm_ops = {
3119         .fault = i915_gem_fault,
3120         .open = drm_gem_vm_open,
3121         .close = drm_gem_vm_close,
3122 };
3123
3124 static const struct file_operations i915_driver_fops = {
3125         .owner = THIS_MODULE,
3126         .open = drm_open,
3127         .release = drm_release,
3128         .unlocked_ioctl = drm_ioctl,
3129         .mmap = drm_gem_mmap,
3130         .poll = drm_poll,
3131         .read = drm_read,
3132         .compat_ioctl = i915_compat_ioctl,
3133         .llseek = noop_llseek,
3134 };
3135
3136 static int
3137 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3138                           struct drm_file *file)
3139 {
3140         return -ENODEV;
3141 }
3142
3143 static const struct drm_ioctl_desc i915_ioctls[] = {
3144         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3145         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3146         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3147         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3148         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3149         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3150         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
3151         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3152         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3153         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3154         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3155         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3156         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3157         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3158         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3159         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3160         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3161         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3162         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3163         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
3164         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3165         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3166         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
3167         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3168         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3169         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
3170         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3171         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3172         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3173         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3174         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3175         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3176         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3177         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3178         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3179         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3180         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3181         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3182         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3183         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3184         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3185         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3186         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3187         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3188         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
3189         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3190         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3191         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3192         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3193         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3194         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3195         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3196         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3197         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3198         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3199         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3200         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
3201         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
3202 };
3203
3204 static struct drm_driver driver = {
3205         /* Don't use MTRRs here; the Xserver or userspace app should
3206          * deal with them for Intel hardware.
3207          */
3208         .driver_features =
3209             DRIVER_GEM | DRIVER_PRIME |
3210             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3211         .release = i915_driver_release,
3212         .open = i915_driver_open,
3213         .lastclose = i915_driver_lastclose,
3214         .postclose = i915_driver_postclose,
3215
3216         .gem_close_object = i915_gem_close_object,
3217         .gem_free_object_unlocked = i915_gem_free_object,
3218         .gem_vm_ops = &i915_gem_vm_ops,
3219
3220         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3221         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3222         .gem_prime_export = i915_gem_prime_export,
3223         .gem_prime_import = i915_gem_prime_import,
3224
3225         .dumb_create = i915_gem_dumb_create,
3226         .dumb_map_offset = i915_gem_mmap_gtt,
3227         .ioctls = i915_ioctls,
3228         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3229         .fops = &i915_driver_fops,
3230         .name = DRIVER_NAME,
3231         .desc = DRIVER_DESC,
3232         .date = DRIVER_DATE,
3233         .major = DRIVER_MAJOR,
3234         .minor = DRIVER_MINOR,
3235         .patchlevel = DRIVER_PATCHLEVEL,
3236 };
3237
3238 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3239 #include "selftests/mock_drm.c"
3240 #endif