drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *kdev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(kdev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev_priv)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev_priv));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 182                                         IS_IVYBRIDGE(dev_priv)));
 183                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 184                                 /* PantherPoint is CPT compatible */
 185                                 dev_priv->pch_type = PCH_CPT;
 186                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 187                                 WARN_ON(!(IS_GEN6(dev_priv) ||
 188                                         IS_IVYBRIDGE(dev_priv)));
 189                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 190                                 dev_priv->pch_type = PCH_LPT;
 191                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 192                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 193                                         !IS_BROADWELL(dev_priv));
 194                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
 195                                         IS_BDW_ULT(dev_priv));
 196                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 197                                 dev_priv->pch_type = PCH_LPT;
 198                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 199                                 WARN_ON(!IS_HASWELL(dev_priv) &&
 200                                         !IS_BROADWELL(dev_priv));
 201                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
 202                                         !IS_BDW_ULT(dev_priv));
 203                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 204                                 dev_priv->pch_type = PCH_SPT;
 205                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 206                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 207                                         !IS_KABYLAKE(dev_priv));
 208                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 209                                 dev_priv->pch_type = PCH_SPT;
 210                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 211                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
 212                                         !IS_KABYLAKE(dev_priv));
 213                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
 214                                 dev_priv->pch_type = PCH_KBP;
 215                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
 216                                 WARN_ON(!IS_KABYLAKE(dev_priv));
 217                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 218                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 219                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 220                                     pch->subsystem_vendor ==
 221                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 222                                     pch->subsystem_device ==
 223                                             PCI_SUBDEVICE_ID_QEMU)) {
 224                                 dev_priv->pch_type =
 225                                         intel_virt_detect_pch(dev_priv);
 226                         } else
 227                                 continue;
 228
 229                         break;
 230                 }
 231         }
 232         if (!pch)
 233                 DRM_DEBUG_KMS("No PCH found.\n");
 234
 235         pci_dev_put(pch);
 236 }
 237
 238 static int i915_getparam(struct drm_device *dev, void *data,
 239                          struct drm_file *file_priv)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(dev);
 242         struct pci_dev *pdev = dev_priv->drm.pdev;
 243         drm_i915_getparam_t *param = data;
 244         int value;
 245
 246         switch (param->param) {
 247         case I915_PARAM_IRQ_ACTIVE:
 248         case I915_PARAM_ALLOW_BATCHBUFFER:
 249         case I915_PARAM_LAST_DISPATCH:
 250                 /* Reject all old ums/dri params. */
 251                 return -ENODEV;
 252         case I915_PARAM_CHIPSET_ID:
 253                 value = pdev->device;
 254                 break;
 255         case I915_PARAM_REVISION:
 256                 value = pdev->revision;
 257                 break;
 258         case I915_PARAM_NUM_FENCES_AVAIL:
 259                 value = dev_priv->num_fence_regs;
 260                 break;
 261         case I915_PARAM_HAS_OVERLAY:
 262                 value = dev_priv->overlay ? 1 : 0;
 263                 break;
 264         case I915_PARAM_HAS_BSD:
 265                 value = !!dev_priv->engine[VCS];
 266                 break;
 267         case I915_PARAM_HAS_BLT:
 268                 value = !!dev_priv->engine[BCS];
 269                 break;
 270         case I915_PARAM_HAS_VEBOX:
 271                 value = !!dev_priv->engine[VECS];
 272                 break;
 273         case I915_PARAM_HAS_BSD2:
 274                 value = !!dev_priv->engine[VCS2];
 275                 break;
 276         case I915_PARAM_HAS_EXEC_CONSTANTS:
 277                 value = INTEL_GEN(dev_priv) >= 4;
 278                 break;
 279         case I915_PARAM_HAS_LLC:
 280                 value = HAS_LLC(dev_priv);
 281                 break;
 282         case I915_PARAM_HAS_WT:
 283                 value = HAS_WT(dev_priv);
 284                 break;
 285         case I915_PARAM_HAS_ALIASING_PPGTT:
 286                 value = USES_PPGTT(dev_priv);
 287                 break;
 288         case I915_PARAM_HAS_SEMAPHORES:
 289                 value = i915.semaphores;
 290                 break;
 291         case I915_PARAM_HAS_SECURE_BATCHES:
 292                 value = capable(CAP_SYS_ADMIN);
 293                 break;
 294         case I915_PARAM_CMD_PARSER_VERSION:
 295                 value = i915_cmd_parser_get_version(dev_priv);
 296                 break;
 297         case I915_PARAM_SUBSLICE_TOTAL:
 298                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 299                 if (!value)
 300                         return -ENODEV;
 301                 break;
 302         case I915_PARAM_EU_TOTAL:
 303                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 304                 if (!value)
 305                         return -ENODEV;
 306                 break;
 307         case I915_PARAM_HAS_GPU_RESET:
 308                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 309                 break;
 310         case I915_PARAM_HAS_RESOURCE_STREAMER:
 311                 value = HAS_RESOURCE_STREAMER(dev_priv);
 312                 break;
 313         case I915_PARAM_HAS_POOLED_EU:
 314                 value = HAS_POOLED_EU(dev_priv);
 315                 break;
 316         case I915_PARAM_MIN_EU_IN_POOL:
 317                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 318                 break;
 319         case I915_PARAM_MMAP_GTT_VERSION:
 320                 /* Though we've started our numbering from 1, and so class all
 321                  * earlier versions as 0, in effect their value is undefined as
 322                  * the ioctl will report EINVAL for the unknown param!
 323                  */
 324                 value = i915_gem_mmap_gtt_version();
 325                 break;
 326         case I915_PARAM_MMAP_VERSION:
 327                 /* Remember to bump this if the version changes! */
 328         case I915_PARAM_HAS_GEM:
 329         case I915_PARAM_HAS_PAGEFLIPPING:
 330         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 331         case I915_PARAM_HAS_RELAXED_FENCING:
 332         case I915_PARAM_HAS_COHERENT_RINGS:
 333         case I915_PARAM_HAS_RELAXED_DELTA:
 334         case I915_PARAM_HAS_GEN7_SOL_RESET:
 335         case I915_PARAM_HAS_WAIT_TIMEOUT:
 336         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 337         case I915_PARAM_HAS_PINNED_BATCHES:
 338         case I915_PARAM_HAS_EXEC_NO_RELOC:
 339         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 340         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 341         case I915_PARAM_HAS_EXEC_SOFTPIN:
 342                 /* For the time being all of these are always true;
 343                  * if some supported hardware does not have one of these
 344                  * features this value needs to be provided from
 345                  * INTEL_INFO(), a feature macro, or similar.
 346                  */
 347                 value = 1;
 348                 break;
 349         default:
 350                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 351                 return -EINVAL;
 352         }
 353
 354         if (put_user(value, param->value))
 355                 return -EFAULT;
 356
 357         return 0;
 358 }
 359
 360 static int i915_get_bridge_dev(struct drm_device *dev)
 361 {
 362         struct drm_i915_private *dev_priv = to_i915(dev);
 363
 364         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 365         if (!dev_priv->bridge_dev) {
 366                 DRM_ERROR("bridge device not found\n");
 367                 return -1;
 368         }
 369         return 0;
 370 }
 371
 372 /* Allocate space for the MCH regs if needed, return nonzero on error */
 373 static int
 374 intel_alloc_mchbar_resource(struct drm_device *dev)
 375 {
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 378         u32 temp_lo, temp_hi = 0;
 379         u64 mchbar_addr;
 380         int ret;
 381
 382         if (INTEL_INFO(dev)->gen >= 4)
 383                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 384         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 385         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 386
 387         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 388 #ifdef CONFIG_PNP
 389         if (mchbar_addr &&
 390             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 391                 return 0;
 392 #endif
 393
 394         /* Get some space for it */
 395         dev_priv->mch_res.name = "i915 MCHBAR";
 396         dev_priv->mch_res.flags = IORESOURCE_MEM;
 397         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 398                                      &dev_priv->mch_res,
 399                                      MCHBAR_SIZE, MCHBAR_SIZE,
 400                                      PCIBIOS_MIN_MEM,
 401                                      0, pcibios_align_resource,
 402                                      dev_priv->bridge_dev);
 403         if (ret) {
 404                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 405                 dev_priv->mch_res.start = 0;
 406                 return ret;
 407         }
 408
 409         if (INTEL_INFO(dev)->gen >= 4)
 410                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 411                                        upper_32_bits(dev_priv->mch_res.start));
 412
 413         pci_write_config_dword(dev_priv->bridge_dev, reg,
 414                                lower_32_bits(dev_priv->mch_res.start));
 415         return 0;
 416 }
 417
 418 /* Setup MCHBAR if possible, return true if we should disable it again */
 419 static void
 420 intel_setup_mchbar(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = to_i915(dev);
 423         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 424         u32 temp;
 425         bool enabled;
 426
 427         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 428                 return;
 429
 430         dev_priv->mchbar_need_disable = false;
 431
 432         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 433                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 434                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 435         } else {
 436                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 437                 enabled = temp & 1;
 438         }
 439
 440         /* If it's already enabled, don't have to do anything */
 441         if (enabled)
 442                 return;
 443
 444         if (intel_alloc_mchbar_resource(dev))
 445                 return;
 446
 447         dev_priv->mchbar_need_disable = true;
 448
 449         /* Space is allocated or reserved, so enable it. */
 450         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 451                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 452                                        temp | DEVEN_MCHBAR_EN);
 453         } else {
 454                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 455                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 456         }
 457 }
 458
 459 static void
 460 intel_teardown_mchbar(struct drm_device *dev)
 461 {
 462         struct drm_i915_private *dev_priv = to_i915(dev);
 463         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 464
 465         if (dev_priv->mchbar_need_disable) {
 466                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 467                         u32 deven_val;
 468
 469                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 470                                               &deven_val);
 471                         deven_val &= ~DEVEN_MCHBAR_EN;
 472                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 473                                                deven_val);
 474                 } else {
 475                         u32 mchbar_val;
 476
 477                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 478                                               &mchbar_val);
 479                         mchbar_val &= ~1;
 480                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 481                                                mchbar_val);
 482                 }
 483         }
 484
 485         if (dev_priv->mch_res.start)
 486                 release_resource(&dev_priv->mch_res);
 487 }
 488
 489 /* true = enable decode, false = disable decoder */
 490 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 491 {
 492         struct drm_device *dev = cookie;
 493
 494         intel_modeset_vga_set_state(dev, state);
 495         if (state)
 496                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 497                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 498         else
 499                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 500 }
 501
 502 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 503 {
 504         struct drm_device *dev = pci_get_drvdata(pdev);
 505         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 506
 507         if (state == VGA_SWITCHEROO_ON) {
 508                 pr_info("switched on\n");
 509                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 510                 /* i915 resume handler doesn't set to D0 */
 511                 pci_set_power_state(pdev, PCI_D0);
 512                 i915_resume_switcheroo(dev);
 513                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 514         } else {
 515                 pr_info("switched off\n");
 516                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 517                 i915_suspend_switcheroo(dev, pmm);
 518                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 519         }
 520 }
 521
 522 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 523 {
 524         struct drm_device *dev = pci_get_drvdata(pdev);
 525
 526         /*
 527          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 528          * locking inversion with the driver load path. And the access here is
 529          * completely racy anyway. So don't bother with locking for now.
 530          */
 531         return dev->open_count == 0;
 532 }
 533
 534 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 535         .set_gpu_state = i915_switcheroo_set_state,
 536         .reprobe = NULL,
 537         .can_switch = i915_switcheroo_can_switch,
 538 };
 539
 540 static void i915_gem_fini(struct drm_device *dev)
 541 {
 542         mutex_lock(&dev->struct_mutex);
 543         i915_gem_cleanup_engines(dev);
 544         i915_gem_context_fini(dev);
 545         mutex_unlock(&dev->struct_mutex);
 546
 547         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 548 }
 549
 550 static int i915_load_modeset_init(struct drm_device *dev)
 551 {
 552         struct drm_i915_private *dev_priv = to_i915(dev);
 553         struct pci_dev *pdev = dev_priv->drm.pdev;
 554         int ret;
 555
 556         if (i915_inject_load_failure())
 557                 return -ENODEV;
 558
 559         ret = intel_bios_init(dev_priv);
 560         if (ret)
 561                 DRM_INFO("failed to find VBIOS tables\n");
 562
 563         /* If we have > 1 VGA cards, then we need to arbitrate access
 564          * to the common VGA resources.
 565          *
 566          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 567          * then we do not take part in VGA arbitration and the
 568          * vga_client_register() fails with -ENODEV.
 569          */
 570         ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
 571         if (ret && ret != -ENODEV)
 572                 goto out;
 573
 574         intel_register_dsm_handler();
 575
 576         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 577         if (ret)
 578                 goto cleanup_vga_client;
 579
 580         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 581         intel_update_rawclk(dev_priv);
 582
 583         intel_power_domains_init_hw(dev_priv, false);
 584
 585         intel_csr_ucode_init(dev_priv);
 586
 587         ret = intel_irq_install(dev_priv);
 588         if (ret)
 589                 goto cleanup_csr;
 590
 591         intel_setup_gmbus(dev);
 592
 593         /* Important: The output setup functions called by modeset_init need
 594          * working irqs for e.g. gmbus and dp aux transfers. */
 595         intel_modeset_init(dev);
 596
 597         intel_guc_init(dev);
 598
 599         ret = i915_gem_init(dev);
 600         if (ret)
 601                 goto cleanup_irq;
 602
 603         intel_modeset_gem_init(dev);
 604
 605         if (INTEL_INFO(dev)->num_pipes == 0)
 606                 return 0;
 607
 608         ret = intel_fbdev_init(dev);
 609         if (ret)
 610                 goto cleanup_gem;
 611
 612         /* Only enable hotplug handling once the fbdev is fully set up. */
 613         intel_hpd_init(dev_priv);
 614
 615         drm_kms_helper_poll_init(dev);
 616
 617         return 0;
 618
 619 cleanup_gem:
 620         if (i915_gem_suspend(dev))
 621                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 622         i915_gem_fini(dev);
 623 cleanup_irq:
 624         intel_guc_fini(dev);
 625         drm_irq_uninstall(dev);
 626         intel_teardown_gmbus(dev);
 627 cleanup_csr:
 628         intel_csr_ucode_fini(dev_priv);
 629         intel_power_domains_fini(dev_priv);
 630         vga_switcheroo_unregister_client(pdev);
 631 cleanup_vga_client:
 632         vga_client_register(pdev, NULL, NULL, NULL);
 633 out:
 634         return ret;
 635 }
 636
 637 #if IS_ENABLED(CONFIG_FB)
 638 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 639 {
 640         struct apertures_struct *ap;
 641         struct pci_dev *pdev = dev_priv->drm.pdev;
 642         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 643         bool primary;
 644         int ret;
 645
 646         ap = alloc_apertures(1);
 647         if (!ap)
 648                 return -ENOMEM;
 649
 650         ap->ranges[0].base = ggtt->mappable_base;
 651         ap->ranges[0].size = ggtt->mappable_end;
 652
 653         primary =
 654                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 655
 656         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 657
 658         kfree(ap);
 659
 660         return ret;
 661 }
 662 #else
 663 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 664 {
 665         return 0;
 666 }
 667 #endif
 668
 669 #if !defined(CONFIG_VGA_CONSOLE)
 670 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 671 {
 672         return 0;
 673 }
 674 #elif !defined(CONFIG_DUMMY_CONSOLE)
 675 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 676 {
 677         return -ENODEV;
 678 }
 679 #else
 680 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 681 {
 682         int ret = 0;
 683
 684         DRM_INFO("Replacing VGA console driver\n");
 685
 686         console_lock();
 687         if (con_is_bound(&vga_con))
 688                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 689         if (ret == 0) {
 690                 ret = do_unregister_con_driver(&vga_con);
 691
 692                 /* Ignore "already unregistered". */
 693                 if (ret == -ENODEV)
 694                         ret = 0;
 695         }
 696         console_unlock();
 697
 698         return ret;
 699 }
 700 #endif
 701
 702 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 703 {
 704         /*
 705          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 706          * CHV x1 PHY (DP/HDMI D)
 707          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 708          */
 709         if (IS_CHERRYVIEW(dev_priv)) {
 710                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 711                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 712         } else if (IS_VALLEYVIEW(dev_priv)) {
 713                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 714         }
 715 }
 716
 717 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 718 {
 719         /*
 720          * The i915 workqueue is primarily used for batched retirement of
 721          * requests (and thus managing bo) once the task has been completed
 722          * by the GPU. i915_gem_retire_requests() is called directly when we
 723          * need high-priority retirement, such as waiting for an explicit
 724          * bo.
 725          *
 726          * It is also used for periodic low-priority events, such as
 727          * idle-timers and recording error state.
 728          *
 729          * All tasks on the workqueue are expected to acquire the dev mutex
 730          * so there is no point in running more than one instance of the
 731          * workqueue at any time.  Use an ordered one.
 732          */
 733         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 734         if (dev_priv->wq == NULL)
 735                 goto out_err;
 736
 737         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 738         if (dev_priv->hotplug.dp_wq == NULL)
 739                 goto out_free_wq;
 740
 741         return 0;
 742
 743 out_free_wq:
 744         destroy_workqueue(dev_priv->wq);
 745 out_err:
 746         DRM_ERROR("Failed to allocate workqueues.\n");
 747
 748         return -ENOMEM;
 749 }
 750
 751 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 752 {
 753         destroy_workqueue(dev_priv->hotplug.dp_wq);
 754         destroy_workqueue(dev_priv->wq);
 755 }
 756
 757 /*
 758  * We don't keep the workarounds for pre-production hardware, so we expect our
 759  * driver to fail on these machines in one way or another. A little warning on
 760  * dmesg may help both the user and the bug triagers.
 761  */
 762 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 763 {
 764         if (IS_HSW_EARLY_SDV(dev_priv) ||
 765             IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
 766                 DRM_ERROR("This is a pre-production stepping. "
 767                           "It may not be fully functional.\n");
 768 }
 769
 770 /**
 771  * i915_driver_init_early - setup state not requiring device access
 772  * @dev_priv: device private
 773  *
 774  * Initialize everything that is a "SW-only" state, that is state not
 775  * requiring accessing the device or exposing the driver via kernel internal
 776  * or userspace interfaces. Example steps belonging here: lock initialization,
 777  * system memory allocation, setting up device specific attributes and
 778  * function hooks not requiring accessing the device.
 779  */
 780 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 781                                   const struct pci_device_id *ent)
 782 {
 783         const struct intel_device_info *match_info =
 784                 (struct intel_device_info *)ent->driver_data;
 785         struct intel_device_info *device_info;
 786         int ret = 0;
 787
 788         if (i915_inject_load_failure())
 789                 return -ENODEV;
 790
 791         /* Setup the write-once "constant" device info */
 792         device_info = mkwrite_device_info(dev_priv);
 793         memcpy(device_info, match_info, sizeof(*device_info));
 794         device_info->device_id = dev_priv->drm.pdev->device;
 795
 796         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 797         device_info->gen_mask = BIT(device_info->gen - 1);
 798
 799         spin_lock_init(&dev_priv->irq_lock);
 800         spin_lock_init(&dev_priv->gpu_error.lock);
 801         mutex_init(&dev_priv->backlight_lock);
 802         spin_lock_init(&dev_priv->uncore.lock);
 803         spin_lock_init(&dev_priv->mm.object_stat_lock);
 804         spin_lock_init(&dev_priv->mmio_flip_lock);
 805         mutex_init(&dev_priv->sb_lock);
 806         mutex_init(&dev_priv->modeset_restore_lock);
 807         mutex_init(&dev_priv->av_mutex);
 808         mutex_init(&dev_priv->wm.wm_mutex);
 809         mutex_init(&dev_priv->pps_mutex);
 810
 811         i915_memcpy_init_early(dev_priv);
 812
 813         ret = i915_workqueues_init(dev_priv);
 814         if (ret < 0)
 815                 return ret;
 816
 817         ret = intel_gvt_init(dev_priv);
 818         if (ret < 0)
 819                 goto err_workqueues;
 820
 821         /* This must be called before any calls to HAS_PCH_* */
 822         intel_detect_pch(&dev_priv->drm);
 823
 824         intel_pm_setup(&dev_priv->drm);
 825         intel_init_dpio(dev_priv);
 826         intel_power_domains_init(dev_priv);
 827         intel_irq_init(dev_priv);
 828         intel_init_display_hooks(dev_priv);
 829         intel_init_clock_gating_hooks(dev_priv);
 830         intel_init_audio_hooks(dev_priv);
 831         i915_gem_load_init(&dev_priv->drm);
 832
 833         intel_display_crc_init(dev_priv);
 834
 835         intel_device_info_dump(dev_priv);
 836
 837         intel_detect_preproduction_hw(dev_priv);
 838
 839         return 0;
 840
 841 err_workqueues:
 842         i915_workqueues_cleanup(dev_priv);
 843         return ret;
 844 }
 845
 846 /**
 847  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 848  * @dev_priv: device private
 849  */
 850 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 851 {
 852         i915_gem_load_cleanup(&dev_priv->drm);
 853         i915_workqueues_cleanup(dev_priv);
 854 }
 855
 856 static int i915_mmio_setup(struct drm_device *dev)
 857 {
 858         struct drm_i915_private *dev_priv = to_i915(dev);
 859         struct pci_dev *pdev = dev_priv->drm.pdev;
 860         int mmio_bar;
 861         int mmio_size;
 862
 863         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 864         /*
 865          * Before gen4, the registers and the GTT are behind different BARs.
 866          * However, from gen4 onwards, the registers and the GTT are shared
 867          * in the same BAR, so we want to restrict this ioremap from
 868          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 869          * the register BAR remains the same size for all the earlier
 870          * generations up to Ironlake.
 871          */
 872         if (INTEL_INFO(dev)->gen < 5)
 873                 mmio_size = 512 * 1024;
 874         else
 875                 mmio_size = 2 * 1024 * 1024;
 876         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 877         if (dev_priv->regs == NULL) {
 878                 DRM_ERROR("failed to map registers\n");
 879
 880                 return -EIO;
 881         }
 882
 883         /* Try to make sure MCHBAR is enabled before poking at it */
 884         intel_setup_mchbar(dev);
 885
 886         return 0;
 887 }
 888
 889 static void i915_mmio_cleanup(struct drm_device *dev)
 890 {
 891         struct drm_i915_private *dev_priv = to_i915(dev);
 892         struct pci_dev *pdev = dev_priv->drm.pdev;
 893
 894         intel_teardown_mchbar(dev);
 895         pci_iounmap(pdev, dev_priv->regs);
 896 }
 897
 898 /**
 899  * i915_driver_init_mmio - setup device MMIO
 900  * @dev_priv: device private
 901  *
 902  * Setup minimal device state necessary for MMIO accesses later in the
 903  * initialization sequence. The setup here should avoid any other device-wide
 904  * side effects or exposing the driver via kernel internal or user space
 905  * interfaces.
 906  */
 907 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 908 {
 909         struct drm_device *dev = &dev_priv->drm;
 910         int ret;
 911
 912         if (i915_inject_load_failure())
 913                 return -ENODEV;
 914
 915         if (i915_get_bridge_dev(dev))
 916                 return -EIO;
 917
 918         ret = i915_mmio_setup(dev);
 919         if (ret < 0)
 920                 goto put_bridge;
 921
 922         intel_uncore_init(dev_priv);
 923
 924         return 0;
 925
 926 put_bridge:
 927         pci_dev_put(dev_priv->bridge_dev);
 928
 929         return ret;
 930 }
 931
 932 /**
 933  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 934  * @dev_priv: device private
 935  */
 936 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 937 {
 938         struct drm_device *dev = &dev_priv->drm;
 939
 940         intel_uncore_fini(dev_priv);
 941         i915_mmio_cleanup(dev);
 942         pci_dev_put(dev_priv->bridge_dev);
 943 }
 944
 945 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 946 {
 947         i915.enable_execlists =
 948                 intel_sanitize_enable_execlists(dev_priv,
 949                                                 i915.enable_execlists);
 950
 951         /*
 952          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 953          * user's requested state against the hardware/driver capabilities.  We
 954          * do this now so that we can print out any log messages once rather
 955          * than every time we check intel_enable_ppgtt().
 956          */
 957         i915.enable_ppgtt =
 958                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 959         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 960
 961         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
 962         DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 963 }
 964
 965 /**
 966  * i915_driver_init_hw - setup state requiring device access
 967  * @dev_priv: device private
 968  *
 969  * Setup state that requires accessing the device, but doesn't require
 970  * exposing the driver via kernel internal or userspace interfaces.
 971  */
 972 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 973 {
 974         struct pci_dev *pdev = dev_priv->drm.pdev;
 975         struct drm_device *dev = &dev_priv->drm;
 976         int ret;
 977
 978         if (i915_inject_load_failure())
 979                 return -ENODEV;
 980
 981         intel_device_info_runtime_init(dev_priv);
 982
 983         intel_sanitize_options(dev_priv);
 984
 985         ret = i915_ggtt_probe_hw(dev_priv);
 986         if (ret)
 987                 return ret;
 988
 989         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 990          * otherwise the vga fbdev driver falls over. */
 991         ret = i915_kick_out_firmware_fb(dev_priv);
 992         if (ret) {
 993                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 994                 goto out_ggtt;
 995         }
 996
 997         ret = i915_kick_out_vgacon(dev_priv);
 998         if (ret) {
 999                 DRM_ERROR("failed to remove conflicting VGA console\n");
1000                 goto out_ggtt;
1001         }
1002
1003         ret = i915_ggtt_init_hw(dev_priv);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_ggtt_enable_hw(dev_priv);
1008         if (ret) {
1009                 DRM_ERROR("failed to enable GGTT\n");
1010                 goto out_ggtt;
1011         }
1012
1013         pci_set_master(pdev);
1014
1015         /* overlay on gen2 is broken and can't address above 1G */
1016         if (IS_GEN2(dev_priv)) {
1017                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1018                 if (ret) {
1019                         DRM_ERROR("failed to set DMA mask\n");
1020
1021                         goto out_ggtt;
1022                 }
1023         }
1024
1025         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1026          * using 32bit addressing, overwriting memory if HWS is located
1027          * above 4GB.
1028          *
1029          * The documentation also mentions an issue with undefined
1030          * behaviour if any general state is accessed within a page above 4GB,
1031          * which also needs to be handled carefully.
1032          */
1033         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1034                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1035
1036                 if (ret) {
1037                         DRM_ERROR("failed to set DMA mask\n");
1038
1039                         goto out_ggtt;
1040                 }
1041         }
1042
1043         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1044                            PM_QOS_DEFAULT_VALUE);
1045
1046         intel_uncore_sanitize(dev_priv);
1047
1048         intel_opregion_setup(dev_priv);
1049
1050         i915_gem_load_init_fences(dev_priv);
1051
1052         /* On the 945G/GM, the chipset reports the MSI capability on the
1053          * integrated graphics even though the support isn't actually there
1054          * according to the published specs.  It doesn't appear to function
1055          * correctly in testing on 945G.
1056          * This may be a side effect of MSI having been made available for PEG
1057          * and the registers being closely associated.
1058          *
1059          * According to chipset errata, on the 965GM, MSI interrupts may
1060          * be lost or delayed, but we use them anyways to avoid
1061          * stuck interrupts on some machines.
1062          */
1063         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1064                 if (pci_enable_msi(pdev) < 0)
1065                         DRM_DEBUG_DRIVER("can't enable MSI");
1066         }
1067
1068         return 0;
1069
1070 out_ggtt:
1071         i915_ggtt_cleanup_hw(dev_priv);
1072
1073         return ret;
1074 }
1075
1076 /**
1077  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1078  * @dev_priv: device private
1079  */
1080 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1081 {
1082         struct pci_dev *pdev = dev_priv->drm.pdev;
1083
1084         if (pdev->msi_enabled)
1085                 pci_disable_msi(pdev);
1086
1087         pm_qos_remove_request(&dev_priv->pm_qos);
1088         i915_ggtt_cleanup_hw(dev_priv);
1089 }
1090
1091 /**
1092  * i915_driver_register - register the driver with the rest of the system
1093  * @dev_priv: device private
1094  *
1095  * Perform any steps necessary to make the driver available via kernel
1096  * internal or userspace interfaces.
1097  */
1098 static void i915_driver_register(struct drm_i915_private *dev_priv)
1099 {
1100         struct drm_device *dev = &dev_priv->drm;
1101
1102         i915_gem_shrinker_init(dev_priv);
1103
1104         /*
1105          * Notify a valid surface after modesetting,
1106          * when running inside a VM.
1107          */
1108         if (intel_vgpu_active(dev_priv))
1109                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1110
1111         /* Reveal our presence to userspace */
1112         if (drm_dev_register(dev, 0) == 0) {
1113                 i915_debugfs_register(dev_priv);
1114                 i915_setup_sysfs(dev_priv);
1115         } else
1116                 DRM_ERROR("Failed to register driver for userspace access!\n");
1117
1118         if (INTEL_INFO(dev_priv)->num_pipes) {
1119                 /* Must be done after probing outputs */
1120                 intel_opregion_register(dev_priv);
1121                 acpi_video_register();
1122         }
1123
1124         if (IS_GEN5(dev_priv))
1125                 intel_gpu_ips_init(dev_priv);
1126
1127         i915_audio_component_init(dev_priv);
1128
1129         /*
1130          * Some ports require correctly set-up hpd registers for detection to
1131          * work properly (leading to ghost connected connector status), e.g. VGA
1132          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1133          * irqs are fully enabled. We do it last so that the async config
1134          * cannot run before the connectors are registered.
1135          */
1136         intel_fbdev_initial_config_async(dev);
1137 }
1138
1139 /**
1140  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1141  * @dev_priv: device private
1142  */
1143 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1144 {
1145         i915_audio_component_cleanup(dev_priv);
1146
1147         intel_gpu_ips_teardown();
1148         acpi_video_unregister();
1149         intel_opregion_unregister(dev_priv);
1150
1151         i915_teardown_sysfs(dev_priv);
1152         i915_debugfs_unregister(dev_priv);
1153         drm_dev_unregister(&dev_priv->drm);
1154
1155         i915_gem_shrinker_cleanup(dev_priv);
1156 }
1157
1158 /**
1159  * i915_driver_load - setup chip and create an initial config
1160  * @dev: DRM device
1161  * @flags: startup flags
1162  *
1163  * The driver load routine has to do several things:
1164  *   - drive output discovery via intel_modeset_init()
1165  *   - initialize the memory manager
1166  *   - allocate initial config memory
1167  *   - setup the DRM framebuffer with the allocated memory
1168  */
1169 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1170 {
1171         struct drm_i915_private *dev_priv;
1172         int ret;
1173
1174         if (i915.nuclear_pageflip)
1175                 driver.driver_features |= DRIVER_ATOMIC;
1176
1177         ret = -ENOMEM;
1178         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1179         if (dev_priv)
1180                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1181         if (ret) {
1182                 dev_printk(KERN_ERR, &pdev->dev,
1183                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1184                 kfree(dev_priv);
1185                 return ret;
1186         }
1187
1188         dev_priv->drm.pdev = pdev;
1189         dev_priv->drm.dev_private = dev_priv;
1190
1191         ret = pci_enable_device(pdev);
1192         if (ret)
1193                 goto out_free_priv;
1194
1195         pci_set_drvdata(pdev, &dev_priv->drm);
1196
1197         ret = i915_driver_init_early(dev_priv, ent);
1198         if (ret < 0)
1199                 goto out_pci_disable;
1200
1201         intel_runtime_pm_get(dev_priv);
1202
1203         ret = i915_driver_init_mmio(dev_priv);
1204         if (ret < 0)
1205                 goto out_runtime_pm_put;
1206
1207         ret = i915_driver_init_hw(dev_priv);
1208         if (ret < 0)
1209                 goto out_cleanup_mmio;
1210
1211         /*
1212          * TODO: move the vblank init and parts of modeset init steps into one
1213          * of the i915_driver_init_/i915_driver_register functions according
1214          * to the role/effect of the given init step.
1215          */
1216         if (INTEL_INFO(dev_priv)->num_pipes) {
1217                 ret = drm_vblank_init(&dev_priv->drm,
1218                                       INTEL_INFO(dev_priv)->num_pipes);
1219                 if (ret)
1220                         goto out_cleanup_hw;
1221         }
1222
1223         ret = i915_load_modeset_init(&dev_priv->drm);
1224         if (ret < 0)
1225                 goto out_cleanup_vblank;
1226
1227         i915_driver_register(dev_priv);
1228
1229         intel_runtime_pm_enable(dev_priv);
1230
1231         /* Everything is in place, we can now relax! */
1232         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1233                  driver.name, driver.major, driver.minor, driver.patchlevel,
1234                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1235         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1236                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1237         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1238                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1239
1240         intel_runtime_pm_put(dev_priv);
1241
1242         return 0;
1243
1244 out_cleanup_vblank:
1245         drm_vblank_cleanup(&dev_priv->drm);
1246 out_cleanup_hw:
1247         i915_driver_cleanup_hw(dev_priv);
1248 out_cleanup_mmio:
1249         i915_driver_cleanup_mmio(dev_priv);
1250 out_runtime_pm_put:
1251         intel_runtime_pm_put(dev_priv);
1252         i915_driver_cleanup_early(dev_priv);
1253 out_pci_disable:
1254         pci_disable_device(pdev);
1255 out_free_priv:
1256         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1257         drm_dev_unref(&dev_priv->drm);
1258         return ret;
1259 }
1260
1261 void i915_driver_unload(struct drm_device *dev)
1262 {
1263         struct drm_i915_private *dev_priv = to_i915(dev);
1264         struct pci_dev *pdev = dev_priv->drm.pdev;
1265
1266         intel_fbdev_fini(dev);
1267
1268         if (i915_gem_suspend(dev))
1269                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1270
1271         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1272
1273         i915_driver_unregister(dev_priv);
1274
1275         drm_vblank_cleanup(dev);
1276
1277         intel_modeset_cleanup(dev);
1278
1279         /*
1280          * free the memory space allocated for the child device
1281          * config parsed from VBT
1282          */
1283         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1284                 kfree(dev_priv->vbt.child_dev);
1285                 dev_priv->vbt.child_dev = NULL;
1286                 dev_priv->vbt.child_dev_num = 0;
1287         }
1288         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1289         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1290         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1291         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1292
1293         vga_switcheroo_unregister_client(pdev);
1294         vga_client_register(pdev, NULL, NULL, NULL);
1295
1296         intel_csr_ucode_fini(dev_priv);
1297
1298         /* Free error state after interrupts are fully disabled. */
1299         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1300         i915_destroy_error_state(dev);
1301
1302         /* Flush any outstanding unpin_work. */
1303         drain_workqueue(dev_priv->wq);
1304
1305         intel_guc_fini(dev);
1306         i915_gem_fini(dev);
1307         intel_fbc_cleanup_cfb(dev_priv);
1308
1309         intel_power_domains_fini(dev_priv);
1310
1311         i915_driver_cleanup_hw(dev_priv);
1312         i915_driver_cleanup_mmio(dev_priv);
1313
1314         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1315
1316         i915_driver_cleanup_early(dev_priv);
1317 }
1318
1319 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1320 {
1321         int ret;
1322
1323         ret = i915_gem_open(dev, file);
1324         if (ret)
1325                 return ret;
1326
1327         return 0;
1328 }
1329
1330 /**
1331  * i915_driver_lastclose - clean up after all DRM clients have exited
1332  * @dev: DRM device
1333  *
1334  * Take care of cleaning up after all DRM clients have exited.  In the
1335  * mode setting case, we want to restore the kernel's initial mode (just
1336  * in case the last client left us in a bad state).
1337  *
1338  * Additionally, in the non-mode setting case, we'll tear down the GTT
1339  * and DMA structures, since the kernel won't be using them, and clea
1340  * up any GEM state.
1341  */
1342 static void i915_driver_lastclose(struct drm_device *dev)
1343 {
1344         intel_fbdev_restore_mode(dev);
1345         vga_switcheroo_process_delayed_switch();
1346 }
1347
1348 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1349 {
1350         mutex_lock(&dev->struct_mutex);
1351         i915_gem_context_close(dev, file);
1352         i915_gem_release(dev, file);
1353         mutex_unlock(&dev->struct_mutex);
1354 }
1355
1356 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1357 {
1358         struct drm_i915_file_private *file_priv = file->driver_priv;
1359
1360         kfree(file_priv);
1361 }
1362
1363 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1364 {
1365         struct drm_device *dev = &dev_priv->drm;
1366         struct intel_encoder *encoder;
1367
1368         drm_modeset_lock_all(dev);
1369         for_each_intel_encoder(dev, encoder)
1370                 if (encoder->suspend)
1371                         encoder->suspend(encoder);
1372         drm_modeset_unlock_all(dev);
1373 }
1374
1375 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1376                               bool rpm_resume);
1377 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1378
1379 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1380 {
1381 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1382         if (acpi_target_system_state() < ACPI_STATE_S3)
1383                 return true;
1384 #endif
1385         return false;
1386 }
1387
1388 static int i915_drm_suspend(struct drm_device *dev)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(dev);
1391         struct pci_dev *pdev = dev_priv->drm.pdev;
1392         pci_power_t opregion_target_state;
1393         int error;
1394
1395         /* ignore lid events during suspend */
1396         mutex_lock(&dev_priv->modeset_restore_lock);
1397         dev_priv->modeset_restore = MODESET_SUSPENDED;
1398         mutex_unlock(&dev_priv->modeset_restore_lock);
1399
1400         disable_rpm_wakeref_asserts(dev_priv);
1401
1402         /* We do a lot of poking in a lot of registers, make sure they work
1403          * properly. */
1404         intel_display_set_init_power(dev_priv, true);
1405
1406         drm_kms_helper_poll_disable(dev);
1407
1408         pci_save_state(pdev);
1409
1410         error = i915_gem_suspend(dev);
1411         if (error) {
1412                 dev_err(&pdev->dev,
1413                         "GEM idle failed, resume might fail\n");
1414                 goto out;
1415         }
1416
1417         intel_guc_suspend(dev);
1418
1419         intel_display_suspend(dev);
1420
1421         intel_dp_mst_suspend(dev);
1422
1423         intel_runtime_pm_disable_interrupts(dev_priv);
1424         intel_hpd_cancel_work(dev_priv);
1425
1426         intel_suspend_encoders(dev_priv);
1427
1428         intel_suspend_hw(dev);
1429
1430         i915_gem_suspend_gtt_mappings(dev);
1431
1432         i915_save_state(dev);
1433
1434         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1435         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1436
1437         intel_uncore_forcewake_reset(dev_priv, false);
1438         intel_opregion_unregister(dev_priv);
1439
1440         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1441
1442         dev_priv->suspend_count++;
1443
1444         intel_csr_ucode_suspend(dev_priv);
1445
1446 out:
1447         enable_rpm_wakeref_asserts(dev_priv);
1448
1449         return error;
1450 }
1451
1452 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1453 {
1454         struct drm_i915_private *dev_priv = to_i915(dev);
1455         struct pci_dev *pdev = dev_priv->drm.pdev;
1456         bool fw_csr;
1457         int ret;
1458
1459         disable_rpm_wakeref_asserts(dev_priv);
1460
1461         intel_display_set_init_power(dev_priv, false);
1462
1463         fw_csr = !IS_BROXTON(dev_priv) &&
1464                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1465         /*
1466          * In case of firmware assisted context save/restore don't manually
1467          * deinit the power domains. This also means the CSR/DMC firmware will
1468          * stay active, it will power down any HW resources as required and
1469          * also enable deeper system power states that would be blocked if the
1470          * firmware was inactive.
1471          */
1472         if (!fw_csr)
1473                 intel_power_domains_suspend(dev_priv);
1474
1475         ret = 0;
1476         if (IS_BROXTON(dev_priv))
1477                 bxt_enable_dc9(dev_priv);
1478         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1479                 hsw_enable_pc8(dev_priv);
1480         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1481                 ret = vlv_suspend_complete(dev_priv);
1482
1483         if (ret) {
1484                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1485                 if (!fw_csr)
1486                         intel_power_domains_init_hw(dev_priv, true);
1487
1488                 goto out;
1489         }
1490
1491         pci_disable_device(pdev);
1492         /*
1493          * During hibernation on some platforms the BIOS may try to access
1494          * the device even though it's already in D3 and hang the machine. So
1495          * leave the device in D0 on those platforms and hope the BIOS will
1496          * power down the device properly. The issue was seen on multiple old
1497          * GENs with different BIOS vendors, so having an explicit blacklist
1498          * is inpractical; apply the workaround on everything pre GEN6. The
1499          * platforms where the issue was seen:
1500          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1501          * Fujitsu FSC S7110
1502          * Acer Aspire 1830T
1503          */
1504         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1505                 pci_set_power_state(pdev, PCI_D3hot);
1506
1507         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1508
1509 out:
1510         enable_rpm_wakeref_asserts(dev_priv);
1511
1512         return ret;
1513 }
1514
1515 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1516 {
1517         int error;
1518
1519         if (!dev) {
1520                 DRM_ERROR("dev: %p\n", dev);
1521                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1522                 return -ENODEV;
1523         }
1524
1525         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1526                          state.event != PM_EVENT_FREEZE))
1527                 return -EINVAL;
1528
1529         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1530                 return 0;
1531
1532         error = i915_drm_suspend(dev);
1533         if (error)
1534                 return error;
1535
1536         return i915_drm_suspend_late(dev, false);
1537 }
1538
1539 static int i915_drm_resume(struct drm_device *dev)
1540 {
1541         struct drm_i915_private *dev_priv = to_i915(dev);
1542         int ret;
1543
1544         disable_rpm_wakeref_asserts(dev_priv);
1545         intel_sanitize_gt_powersave(dev_priv);
1546
1547         ret = i915_ggtt_enable_hw(dev_priv);
1548         if (ret)
1549                 DRM_ERROR("failed to re-enable GGTT\n");
1550
1551         intel_csr_ucode_resume(dev_priv);
1552
1553         i915_gem_resume(dev);
1554
1555         i915_restore_state(dev);
1556         intel_pps_unlock_regs_wa(dev_priv);
1557         intel_opregion_setup(dev_priv);
1558
1559         intel_init_pch_refclk(dev);
1560         drm_mode_config_reset(dev);
1561
1562         /*
1563          * Interrupts have to be enabled before any batches are run. If not the
1564          * GPU will hang. i915_gem_init_hw() will initiate batches to
1565          * update/restore the context.
1566          *
1567          * Modeset enabling in intel_modeset_init_hw() also needs working
1568          * interrupts.
1569          */
1570         intel_runtime_pm_enable_interrupts(dev_priv);
1571
1572         mutex_lock(&dev->struct_mutex);
1573         if (i915_gem_init_hw(dev)) {
1574                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1575                 i915_gem_set_wedged(dev_priv);
1576         }
1577         mutex_unlock(&dev->struct_mutex);
1578
1579         intel_guc_resume(dev);
1580
1581         intel_modeset_init_hw(dev);
1582
1583         spin_lock_irq(&dev_priv->irq_lock);
1584         if (dev_priv->display.hpd_irq_setup)
1585                 dev_priv->display.hpd_irq_setup(dev_priv);
1586         spin_unlock_irq(&dev_priv->irq_lock);
1587
1588         intel_dp_mst_resume(dev);
1589
1590         intel_display_resume(dev);
1591
1592         /*
1593          * ... but also need to make sure that hotplug processing
1594          * doesn't cause havoc. Like in the driver load code we don't
1595          * bother with the tiny race here where we might loose hotplug
1596          * notifications.
1597          * */
1598         intel_hpd_init(dev_priv);
1599         /* Config may have changed between suspend and resume */
1600         drm_helper_hpd_irq_event(dev);
1601
1602         intel_opregion_register(dev_priv);
1603
1604         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1605
1606         mutex_lock(&dev_priv->modeset_restore_lock);
1607         dev_priv->modeset_restore = MODESET_DONE;
1608         mutex_unlock(&dev_priv->modeset_restore_lock);
1609
1610         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1611
1612         intel_autoenable_gt_powersave(dev_priv);
1613         drm_kms_helper_poll_enable(dev);
1614
1615         enable_rpm_wakeref_asserts(dev_priv);
1616
1617         return 0;
1618 }
1619
1620 static int i915_drm_resume_early(struct drm_device *dev)
1621 {
1622         struct drm_i915_private *dev_priv = to_i915(dev);
1623         struct pci_dev *pdev = dev_priv->drm.pdev;
1624         int ret;
1625
1626         /*
1627          * We have a resume ordering issue with the snd-hda driver also
1628          * requiring our device to be power up. Due to the lack of a
1629          * parent/child relationship we currently solve this with an early
1630          * resume hook.
1631          *
1632          * FIXME: This should be solved with a special hdmi sink device or
1633          * similar so that power domains can be employed.
1634          */
1635
1636         /*
1637          * Note that we need to set the power state explicitly, since we
1638          * powered off the device during freeze and the PCI core won't power
1639          * it back up for us during thaw. Powering off the device during
1640          * freeze is not a hard requirement though, and during the
1641          * suspend/resume phases the PCI core makes sure we get here with the
1642          * device powered on. So in case we change our freeze logic and keep
1643          * the device powered we can also remove the following set power state
1644          * call.
1645          */
1646         ret = pci_set_power_state(pdev, PCI_D0);
1647         if (ret) {
1648                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1649                 goto out;
1650         }
1651
1652         /*
1653          * Note that pci_enable_device() first enables any parent bridge
1654          * device and only then sets the power state for this device. The
1655          * bridge enabling is a nop though, since bridge devices are resumed
1656          * first. The order of enabling power and enabling the device is
1657          * imposed by the PCI core as described above, so here we preserve the
1658          * same order for the freeze/thaw phases.
1659          *
1660          * TODO: eventually we should remove pci_disable_device() /
1661          * pci_enable_enable_device() from suspend/resume. Due to how they
1662          * depend on the device enable refcount we can't anyway depend on them
1663          * disabling/enabling the device.
1664          */
1665         if (pci_enable_device(pdev)) {
1666                 ret = -EIO;
1667                 goto out;
1668         }
1669
1670         pci_set_master(pdev);
1671
1672         disable_rpm_wakeref_asserts(dev_priv);
1673
1674         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1675                 ret = vlv_resume_prepare(dev_priv, false);
1676         if (ret)
1677                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1678                           ret);
1679
1680         intel_uncore_early_sanitize(dev_priv, true);
1681
1682         if (IS_BROXTON(dev_priv)) {
1683                 if (!dev_priv->suspended_to_idle)
1684                         gen9_sanitize_dc_state(dev_priv);
1685                 bxt_disable_dc9(dev_priv);
1686         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1687                 hsw_disable_pc8(dev_priv);
1688         }
1689
1690         intel_uncore_sanitize(dev_priv);
1691
1692         if (IS_BROXTON(dev_priv) ||
1693             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1694                 intel_power_domains_init_hw(dev_priv, true);
1695
1696         enable_rpm_wakeref_asserts(dev_priv);
1697
1698 out:
1699         dev_priv->suspended_to_idle = false;
1700
1701         return ret;
1702 }
1703
1704 int i915_resume_switcheroo(struct drm_device *dev)
1705 {
1706         int ret;
1707
1708         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1709                 return 0;
1710
1711         ret = i915_drm_resume_early(dev);
1712         if (ret)
1713                 return ret;
1714
1715         return i915_drm_resume(dev);
1716 }
1717
1718 static void disable_engines_irq(struct drm_i915_private *dev_priv)
1719 {
1720         struct intel_engine_cs *engine;
1721         enum intel_engine_id id;
1722
1723         /* Ensure irq handler finishes, and not run again. */
1724         disable_irq(dev_priv->drm.irq);
1725         for_each_engine(engine, dev_priv, id)
1726                 tasklet_kill(&engine->irq_tasklet);
1727 }
1728
1729 static void enable_engines_irq(struct drm_i915_private *dev_priv)
1730 {
1731         enable_irq(dev_priv->drm.irq);
1732 }
1733
1734 /**
1735  * i915_reset - reset chip after a hang
1736  * @dev: drm device to reset
1737  *
1738  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1739  * on failure.
1740  *
1741  * Caller must hold the struct_mutex.
1742  *
1743  * Procedure is fairly simple:
1744  *   - reset the chip using the reset reg
1745  *   - re-init context state
1746  *   - re-init hardware status page
1747  *   - re-init ring buffer
1748  *   - re-init interrupt state
1749  *   - re-init display
1750  */
1751 void i915_reset(struct drm_i915_private *dev_priv)
1752 {
1753         struct drm_device *dev = &dev_priv->drm;
1754         struct i915_gpu_error *error = &dev_priv->gpu_error;
1755         int ret;
1756
1757         lockdep_assert_held(&dev->struct_mutex);
1758
1759         if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
1760                 return;
1761
1762         /* Clear any previous failed attempts at recovery. Time to try again. */
1763         __clear_bit(I915_WEDGED, &error->flags);
1764         error->reset_count++;
1765
1766         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1767
1768         disable_engines_irq(dev_priv);
1769         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1770         enable_engines_irq(dev_priv);
1771
1772         if (ret) {
1773                 if (ret != -ENODEV)
1774                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1775                 else
1776                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1777                 goto error;
1778         }
1779
1780         i915_gem_reset(dev_priv);
1781         intel_overlay_reset(dev_priv);
1782
1783         /* Ok, now get things going again... */
1784
1785         /*
1786          * Everything depends on having the GTT running, so we need to start
1787          * there.  Fortunately we don't need to do this unless we reset the
1788          * chip at a PCI level.
1789          *
1790          * Next we need to restore the context, but we don't use those
1791          * yet either...
1792          *
1793          * Ring buffer needs to be re-initialized in the KMS case, or if X
1794          * was running at the time of the reset (i.e. we weren't VT
1795          * switched away).
1796          */
1797         ret = i915_gem_init_hw(dev);
1798         if (ret) {
1799                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1800                 goto error;
1801         }
1802
1803 wakeup:
1804         wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
1805         return;
1806
1807 error:
1808         i915_gem_set_wedged(dev_priv);
1809         goto wakeup;
1810 }
1811
1812 static int i915_pm_suspend(struct device *kdev)
1813 {
1814         struct pci_dev *pdev = to_pci_dev(kdev);
1815         struct drm_device *dev = pci_get_drvdata(pdev);
1816
1817         if (!dev) {
1818                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1819                 return -ENODEV;
1820         }
1821
1822         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1823                 return 0;
1824
1825         return i915_drm_suspend(dev);
1826 }
1827
1828 static int i915_pm_suspend_late(struct device *kdev)
1829 {
1830         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1831
1832         /*
1833          * We have a suspend ordering issue with the snd-hda driver also
1834          * requiring our device to be power up. Due to the lack of a
1835          * parent/child relationship we currently solve this with an late
1836          * suspend hook.
1837          *
1838          * FIXME: This should be solved with a special hdmi sink device or
1839          * similar so that power domains can be employed.
1840          */
1841         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1842                 return 0;
1843
1844         return i915_drm_suspend_late(dev, false);
1845 }
1846
1847 static int i915_pm_poweroff_late(struct device *kdev)
1848 {
1849         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1850
1851         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1852                 return 0;
1853
1854         return i915_drm_suspend_late(dev, true);
1855 }
1856
1857 static int i915_pm_resume_early(struct device *kdev)
1858 {
1859         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1860
1861         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1862                 return 0;
1863
1864         return i915_drm_resume_early(dev);
1865 }
1866
1867 static int i915_pm_resume(struct device *kdev)
1868 {
1869         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1870
1871         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1872                 return 0;
1873
1874         return i915_drm_resume(dev);
1875 }
1876
1877 /* freeze: before creating the hibernation_image */
1878 static int i915_pm_freeze(struct device *kdev)
1879 {
1880         int ret;
1881
1882         ret = i915_pm_suspend(kdev);
1883         if (ret)
1884                 return ret;
1885
1886         ret = i915_gem_freeze(kdev_to_i915(kdev));
1887         if (ret)
1888                 return ret;
1889
1890         return 0;
1891 }
1892
1893 static int i915_pm_freeze_late(struct device *kdev)
1894 {
1895         int ret;
1896
1897         ret = i915_pm_suspend_late(kdev);
1898         if (ret)
1899                 return ret;
1900
1901         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1902         if (ret)
1903                 return ret;
1904
1905         return 0;
1906 }
1907
1908 /* thaw: called after creating the hibernation image, but before turning off. */
1909 static int i915_pm_thaw_early(struct device *kdev)
1910 {
1911         return i915_pm_resume_early(kdev);
1912 }
1913
1914 static int i915_pm_thaw(struct device *kdev)
1915 {
1916         return i915_pm_resume(kdev);
1917 }
1918
1919 /* restore: called after loading the hibernation image. */
1920 static int i915_pm_restore_early(struct device *kdev)
1921 {
1922         return i915_pm_resume_early(kdev);
1923 }
1924
1925 static int i915_pm_restore(struct device *kdev)
1926 {
1927         return i915_pm_resume(kdev);
1928 }
1929
1930 /*
1931  * Save all Gunit registers that may be lost after a D3 and a subsequent
1932  * S0i[R123] transition. The list of registers needing a save/restore is
1933  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1934  * registers in the following way:
1935  * - Driver: saved/restored by the driver
1936  * - Punit : saved/restored by the Punit firmware
1937  * - No, w/o marking: no need to save/restore, since the register is R/O or
1938  *                    used internally by the HW in a way that doesn't depend
1939  *                    keeping the content across a suspend/resume.
1940  * - Debug : used for debugging
1941  *
1942  * We save/restore all registers marked with 'Driver', with the following
1943  * exceptions:
1944  * - Registers out of use, including also registers marked with 'Debug'.
1945  *   These have no effect on the driver's operation, so we don't save/restore
1946  *   them to reduce the overhead.
1947  * - Registers that are fully setup by an initialization function called from
1948  *   the resume path. For example many clock gating and RPS/RC6 registers.
1949  * - Registers that provide the right functionality with their reset defaults.
1950  *
1951  * TODO: Except for registers that based on the above 3 criteria can be safely
1952  * ignored, we save/restore all others, practically treating the HW context as
1953  * a black-box for the driver. Further investigation is needed to reduce the
1954  * saved/restored registers even further, by following the same 3 criteria.
1955  */
1956 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1957 {
1958         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1959         int i;
1960
1961         /* GAM 0x4000-0x4770 */
1962         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1963         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1964         s->arb_mode             = I915_READ(ARB_MODE);
1965         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1966         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1967
1968         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1969                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1970
1971         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1972         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1973
1974         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1975         s->ecochk               = I915_READ(GAM_ECOCHK);
1976         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1977         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1978
1979         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1980
1981         /* MBC 0x9024-0x91D0, 0x8500 */
1982         s->g3dctl               = I915_READ(VLV_G3DCTL);
1983         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1984         s->mbctl                = I915_READ(GEN6_MBCTL);
1985
1986         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1987         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1988         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1989         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1990         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1991         s->rstctl               = I915_READ(GEN6_RSTCTL);
1992         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1993
1994         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1995         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1996         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1997         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1998         s->ecobus               = I915_READ(ECOBUS);
1999         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2000         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2001         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2002         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2003         s->rcedata              = I915_READ(VLV_RCEDATA);
2004         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2005
2006         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2007         s->gt_imr               = I915_READ(GTIMR);
2008         s->gt_ier               = I915_READ(GTIER);
2009         s->pm_imr               = I915_READ(GEN6_PMIMR);
2010         s->pm_ier               = I915_READ(GEN6_PMIER);
2011
2012         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2013                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2014
2015         /* GT SA CZ domain, 0x100000-0x138124 */
2016         s->tilectl              = I915_READ(TILECTL);
2017         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2018         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2019         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2020         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2021
2022         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2023         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2024         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2025         s->pcbr                 = I915_READ(VLV_PCBR);
2026         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2027
2028         /*
2029          * Not saving any of:
2030          * DFT,         0x9800-0x9EC0
2031          * SARB,        0xB000-0xB1FC
2032          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2033          * PCI CFG
2034          */
2035 }
2036
2037 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2038 {
2039         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2040         u32 val;
2041         int i;
2042
2043         /* GAM 0x4000-0x4770 */
2044         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2045         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2046         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2047         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2048         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2049
2050         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2051                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2052
2053         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2054         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2055
2056         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2057         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2058         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2059         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2060
2061         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2062
2063         /* MBC 0x9024-0x91D0, 0x8500 */
2064         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2065         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2066         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2067
2068         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2069         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2070         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2071         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2072         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2073         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2074         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2075
2076         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2077         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2078         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2079         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2080         I915_WRITE(ECOBUS,              s->ecobus);
2081         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2082         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2083         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2084         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2085         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2086         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2087
2088         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2089         I915_WRITE(GTIMR,               s->gt_imr);
2090         I915_WRITE(GTIER,               s->gt_ier);
2091         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2092         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2093
2094         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2095                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2096
2097         /* GT SA CZ domain, 0x100000-0x138124 */
2098         I915_WRITE(TILECTL,                     s->tilectl);
2099         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2100         /*
2101          * Preserve the GT allow wake and GFX force clock bit, they are not
2102          * be restored, as they are used to control the s0ix suspend/resume
2103          * sequence by the caller.
2104          */
2105         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2106         val &= VLV_GTLC_ALLOWWAKEREQ;
2107         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2108         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2109
2110         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2111         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2112         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2113         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2114
2115         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2116
2117         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2118         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2119         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2120         I915_WRITE(VLV_PCBR,                    s->pcbr);
2121         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2122 }
2123
2124 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2125 {
2126         u32 val;
2127         int err;
2128
2129         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2130         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2131         if (force_on)
2132                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2133         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2134
2135         if (!force_on)
2136                 return 0;
2137
2138         err = intel_wait_for_register(dev_priv,
2139                                       VLV_GTLC_SURVIVABILITY_REG,
2140                                       VLV_GFX_CLK_STATUS_BIT,
2141                                       VLV_GFX_CLK_STATUS_BIT,
2142                                       20);
2143         if (err)
2144                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2145                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2146
2147         return err;
2148 }
2149
2150 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2151 {
2152         u32 val;
2153         int err = 0;
2154
2155         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2156         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2157         if (allow)
2158                 val |= VLV_GTLC_ALLOWWAKEREQ;
2159         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2160         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2161
2162         err = intel_wait_for_register(dev_priv,
2163                                       VLV_GTLC_PW_STATUS,
2164                                       VLV_GTLC_ALLOWWAKEACK,
2165                                       allow,
2166                                       1);
2167         if (err)
2168                 DRM_ERROR("timeout disabling GT waking\n");
2169
2170         return err;
2171 }
2172
2173 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2174                                  bool wait_for_on)
2175 {
2176         u32 mask;
2177         u32 val;
2178         int err;
2179
2180         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2181         val = wait_for_on ? mask : 0;
2182         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2183                 return 0;
2184
2185         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2186                       onoff(wait_for_on),
2187                       I915_READ(VLV_GTLC_PW_STATUS));
2188
2189         /*
2190          * RC6 transitioning can be delayed up to 2 msec (see
2191          * valleyview_enable_rps), use 3 msec for safety.
2192          */
2193         err = intel_wait_for_register(dev_priv,
2194                                       VLV_GTLC_PW_STATUS, mask, val,
2195                                       3);
2196         if (err)
2197                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2198                           onoff(wait_for_on));
2199
2200         return err;
2201 }
2202
2203 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2204 {
2205         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2206                 return;
2207
2208         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2209         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2210 }
2211
2212 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2213 {
2214         u32 mask;
2215         int err;
2216
2217         /*
2218          * Bspec defines the following GT well on flags as debug only, so
2219          * don't treat them as hard failures.
2220          */
2221         (void)vlv_wait_for_gt_wells(dev_priv, false);
2222
2223         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2224         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2225
2226         vlv_check_no_gt_access(dev_priv);
2227
2228         err = vlv_force_gfx_clock(dev_priv, true);
2229         if (err)
2230                 goto err1;
2231
2232         err = vlv_allow_gt_wake(dev_priv, false);
2233         if (err)
2234                 goto err2;
2235
2236         if (!IS_CHERRYVIEW(dev_priv))
2237                 vlv_save_gunit_s0ix_state(dev_priv);
2238
2239         err = vlv_force_gfx_clock(dev_priv, false);
2240         if (err)
2241                 goto err2;
2242
2243         return 0;
2244
2245 err2:
2246         /* For safety always re-enable waking and disable gfx clock forcing */
2247         vlv_allow_gt_wake(dev_priv, true);
2248 err1:
2249         vlv_force_gfx_clock(dev_priv, false);
2250
2251         return err;
2252 }
2253
2254 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2255                                 bool rpm_resume)
2256 {
2257         struct drm_device *dev = &dev_priv->drm;
2258         int err;
2259         int ret;
2260
2261         /*
2262          * If any of the steps fail just try to continue, that's the best we
2263          * can do at this point. Return the first error code (which will also
2264          * leave RPM permanently disabled).
2265          */
2266         ret = vlv_force_gfx_clock(dev_priv, true);
2267
2268         if (!IS_CHERRYVIEW(dev_priv))
2269                 vlv_restore_gunit_s0ix_state(dev_priv);
2270
2271         err = vlv_allow_gt_wake(dev_priv, true);
2272         if (!ret)
2273                 ret = err;
2274
2275         err = vlv_force_gfx_clock(dev_priv, false);
2276         if (!ret)
2277                 ret = err;
2278
2279         vlv_check_no_gt_access(dev_priv);
2280
2281         if (rpm_resume) {
2282                 intel_init_clock_gating(dev);
2283                 i915_gem_restore_fences(dev);
2284         }
2285
2286         return ret;
2287 }
2288
2289 static int intel_runtime_suspend(struct device *kdev)
2290 {
2291         struct pci_dev *pdev = to_pci_dev(kdev);
2292         struct drm_device *dev = pci_get_drvdata(pdev);
2293         struct drm_i915_private *dev_priv = to_i915(dev);
2294         int ret;
2295
2296         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2297                 return -ENODEV;
2298
2299         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2300                 return -ENODEV;
2301
2302         DRM_DEBUG_KMS("Suspending device\n");
2303
2304         /*
2305          * We could deadlock here in case another thread holding struct_mutex
2306          * calls RPM suspend concurrently, since the RPM suspend will wait
2307          * first for this RPM suspend to finish. In this case the concurrent
2308          * RPM resume will be followed by its RPM suspend counterpart. Still
2309          * for consistency return -EAGAIN, which will reschedule this suspend.
2310          */
2311         if (!mutex_trylock(&dev->struct_mutex)) {
2312                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2313                 /*
2314                  * Bump the expiration timestamp, otherwise the suspend won't
2315                  * be rescheduled.
2316                  */
2317                 pm_runtime_mark_last_busy(kdev);
2318
2319                 return -EAGAIN;
2320         }
2321
2322         disable_rpm_wakeref_asserts(dev_priv);
2323
2324         /*
2325          * We are safe here against re-faults, since the fault handler takes
2326          * an RPM reference.
2327          */
2328         i915_gem_release_all_mmaps(dev_priv);
2329         mutex_unlock(&dev->struct_mutex);
2330
2331         intel_guc_suspend(dev);
2332
2333         intel_runtime_pm_disable_interrupts(dev_priv);
2334
2335         ret = 0;
2336         if (IS_BROXTON(dev_priv)) {
2337                 bxt_display_core_uninit(dev_priv);
2338                 bxt_enable_dc9(dev_priv);
2339         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2340                 hsw_enable_pc8(dev_priv);
2341         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2342                 ret = vlv_suspend_complete(dev_priv);
2343         }
2344
2345         if (ret) {
2346                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2347                 intel_runtime_pm_enable_interrupts(dev_priv);
2348
2349                 enable_rpm_wakeref_asserts(dev_priv);
2350
2351                 return ret;
2352         }
2353
2354         intel_uncore_forcewake_reset(dev_priv, false);
2355
2356         enable_rpm_wakeref_asserts(dev_priv);
2357         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2358
2359         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2360                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2361
2362         dev_priv->pm.suspended = true;
2363
2364         /*
2365          * FIXME: We really should find a document that references the arguments
2366          * used below!
2367          */
2368         if (IS_BROADWELL(dev_priv)) {
2369                 /*
2370                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2371                  * being detected, and the call we do at intel_runtime_resume()
2372                  * won't be able to restore them. Since PCI_D3hot matches the
2373                  * actual specification and appears to be working, use it.
2374                  */
2375                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2376         } else {
2377                 /*
2378                  * current versions of firmware which depend on this opregion
2379                  * notification have repurposed the D1 definition to mean
2380                  * "runtime suspended" vs. what you would normally expect (D3)
2381                  * to distinguish it from notifications that might be sent via
2382                  * the suspend path.
2383                  */
2384                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2385         }
2386
2387         assert_forcewakes_inactive(dev_priv);
2388
2389         if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv))
2390                 intel_hpd_poll_init(dev_priv);
2391
2392         DRM_DEBUG_KMS("Device suspended\n");
2393         return 0;
2394 }
2395
2396 static int intel_runtime_resume(struct device *kdev)
2397 {
2398         struct pci_dev *pdev = to_pci_dev(kdev);
2399         struct drm_device *dev = pci_get_drvdata(pdev);
2400         struct drm_i915_private *dev_priv = to_i915(dev);
2401         int ret = 0;
2402
2403         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2404                 return -ENODEV;
2405
2406         DRM_DEBUG_KMS("Resuming device\n");
2407
2408         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2409         disable_rpm_wakeref_asserts(dev_priv);
2410
2411         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2412         dev_priv->pm.suspended = false;
2413         if (intel_uncore_unclaimed_mmio(dev_priv))
2414                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2415
2416         intel_guc_resume(dev);
2417
2418         if (IS_GEN6(dev_priv))
2419                 intel_init_pch_refclk(dev);
2420
2421         if (IS_BROXTON(dev_priv)) {
2422                 bxt_disable_dc9(dev_priv);
2423                 bxt_display_core_init(dev_priv, true);
2424                 if (dev_priv->csr.dmc_payload &&
2425                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2426                         gen9_enable_dc5(dev_priv);
2427         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2428                 hsw_disable_pc8(dev_priv);
2429         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2430                 ret = vlv_resume_prepare(dev_priv, true);
2431         }
2432
2433         /*
2434          * No point of rolling back things in case of an error, as the best
2435          * we can do is to hope that things will still work (and disable RPM).
2436          */
2437         i915_gem_init_swizzling(dev);
2438
2439         intel_runtime_pm_enable_interrupts(dev_priv);
2440
2441         /*
2442          * On VLV/CHV display interrupts are part of the display
2443          * power well, so hpd is reinitialized from there. For
2444          * everyone else do it here.
2445          */
2446         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2447                 intel_hpd_init(dev_priv);
2448
2449         enable_rpm_wakeref_asserts(dev_priv);
2450
2451         if (ret)
2452                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2453         else
2454                 DRM_DEBUG_KMS("Device resumed\n");
2455
2456         return ret;
2457 }
2458
2459 const struct dev_pm_ops i915_pm_ops = {
2460         /*
2461          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2462          * PMSG_RESUME]
2463          */
2464         .suspend = i915_pm_suspend,
2465         .suspend_late = i915_pm_suspend_late,
2466         .resume_early = i915_pm_resume_early,
2467         .resume = i915_pm_resume,
2468
2469         /*
2470          * S4 event handlers
2471          * @freeze, @freeze_late    : called (1) before creating the
2472          *                            hibernation image [PMSG_FREEZE] and
2473          *                            (2) after rebooting, before restoring
2474          *                            the image [PMSG_QUIESCE]
2475          * @thaw, @thaw_early       : called (1) after creating the hibernation
2476          *                            image, before writing it [PMSG_THAW]
2477          *                            and (2) after failing to create or
2478          *                            restore the image [PMSG_RECOVER]
2479          * @poweroff, @poweroff_late: called after writing the hibernation
2480          *                            image, before rebooting [PMSG_HIBERNATE]
2481          * @restore, @restore_early : called after rebooting and restoring the
2482          *                            hibernation image [PMSG_RESTORE]
2483          */
2484         .freeze = i915_pm_freeze,
2485         .freeze_late = i915_pm_freeze_late,
2486         .thaw_early = i915_pm_thaw_early,
2487         .thaw = i915_pm_thaw,
2488         .poweroff = i915_pm_suspend,
2489         .poweroff_late = i915_pm_poweroff_late,
2490         .restore_early = i915_pm_restore_early,
2491         .restore = i915_pm_restore,
2492
2493         /* S0ix (via runtime suspend) event handlers */
2494         .runtime_suspend = intel_runtime_suspend,
2495         .runtime_resume = intel_runtime_resume,
2496 };
2497
2498 static const struct vm_operations_struct i915_gem_vm_ops = {
2499         .fault = i915_gem_fault,
2500         .open = drm_gem_vm_open,
2501         .close = drm_gem_vm_close,
2502 };
2503
2504 static const struct file_operations i915_driver_fops = {
2505         .owner = THIS_MODULE,
2506         .open = drm_open,
2507         .release = drm_release,
2508         .unlocked_ioctl = drm_ioctl,
2509         .mmap = drm_gem_mmap,
2510         .poll = drm_poll,
2511         .read = drm_read,
2512 #ifdef CONFIG_COMPAT
2513         .compat_ioctl = i915_compat_ioctl,
2514 #endif
2515         .llseek = noop_llseek,
2516 };
2517
2518 static int
2519 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2520                           struct drm_file *file)
2521 {
2522         return -ENODEV;
2523 }
2524
2525 static const struct drm_ioctl_desc i915_ioctls[] = {
2526         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2527         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2528         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2529         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2530         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2531         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2532         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2533         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2534         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2535         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2536         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2537         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2538         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2539         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2540         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2541         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2542         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2543         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2544         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2545         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2546         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2547         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2548         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2549         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2550         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2551         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2552         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2553         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2554         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2556         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2557         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2558         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2559         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2560         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2561         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2562         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2563         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2564         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2565         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2567         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2569         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2570         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2571         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2572         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2573         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2574         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2575         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2576         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2577         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2578 };
2579
2580 static struct drm_driver driver = {
2581         /* Don't use MTRRs here; the Xserver or userspace app should
2582          * deal with them for Intel hardware.
2583          */
2584         .driver_features =
2585             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2586             DRIVER_RENDER | DRIVER_MODESET,
2587         .open = i915_driver_open,
2588         .lastclose = i915_driver_lastclose,
2589         .preclose = i915_driver_preclose,
2590         .postclose = i915_driver_postclose,
2591         .set_busid = drm_pci_set_busid,
2592
2593         .gem_close_object = i915_gem_close_object,
2594         .gem_free_object = i915_gem_free_object,
2595         .gem_vm_ops = &i915_gem_vm_ops,
2596
2597         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2598         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2599         .gem_prime_export = i915_gem_prime_export,
2600         .gem_prime_import = i915_gem_prime_import,
2601
2602         .dumb_create = i915_gem_dumb_create,
2603         .dumb_map_offset = i915_gem_mmap_gtt,
2604         .dumb_destroy = drm_gem_dumb_destroy,
2605         .ioctls = i915_ioctls,
2606         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2607         .fops = &i915_driver_fops,
2608         .name = DRIVER_NAME,
2609         .desc = DRIVER_DESC,
2610         .date = DRIVER_DATE,
2611         .major = DRIVER_MAJOR,
2612         .minor = DRIVER_MINOR,
2613         .patchlevel = DRIVER_PATCHLEVEL,
2614 };