drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. "
 125                 "Enable Haswell and ValleyView Support. "
 126                 "(default: false)");
 127
 128 static struct drm_driver driver;
 129 extern int intel_agp_enabled;
 130
 131 #define INTEL_VGA_DEVICE(id, info) {            \
 132         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 133         .class_mask = 0xff0000,                 \
 134         .vendor = 0x8086,                       \
 135         .device = id,                           \
 136         .subvendor = PCI_ANY_ID,                \
 137         .subdevice = PCI_ANY_ID,                \
 138         .driver_data = (unsigned long) info }
 139
 140 static const struct intel_device_info intel_i830_info = {
 141         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_845g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i85x_info = {
 151         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 152         .cursor_needs_physical = 1,
 153         .has_overlay = 1, .overlay_needs_physical = 1,
 154 };
 155
 156 static const struct intel_device_info intel_i865g_info = {
 157         .gen = 2,
 158         .has_overlay = 1, .overlay_needs_physical = 1,
 159 };
 160
 161 static const struct intel_device_info intel_i915g_info = {
 162         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 163         .has_overlay = 1, .overlay_needs_physical = 1,
 164 };
 165 static const struct intel_device_info intel_i915gm_info = {
 166         .gen = 3, .is_mobile = 1,
 167         .cursor_needs_physical = 1,
 168         .has_overlay = 1, .overlay_needs_physical = 1,
 169         .supports_tv = 1,
 170 };
 171 static const struct intel_device_info intel_i945g_info = {
 172         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 173         .has_overlay = 1, .overlay_needs_physical = 1,
 174 };
 175 static const struct intel_device_info intel_i945gm_info = {
 176         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 177         .has_hotplug = 1, .cursor_needs_physical = 1,
 178         .has_overlay = 1, .overlay_needs_physical = 1,
 179         .supports_tv = 1,
 180 };
 181
 182 static const struct intel_device_info intel_i965g_info = {
 183         .gen = 4, .is_broadwater = 1,
 184         .has_hotplug = 1,
 185         .has_overlay = 1,
 186 };
 187
 188 static const struct intel_device_info intel_i965gm_info = {
 189         .gen = 4, .is_crestline = 1,
 190         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_g33_info = {
 196         .gen = 3, .is_g33 = 1,
 197         .need_gfx_hws = 1, .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_g45_info = {
 202         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .has_bsd_ring = 1,
 205 };
 206
 207 static const struct intel_device_info intel_gm45_info = {
 208         .gen = 4, .is_g4x = 1,
 209         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 210         .has_pipe_cxsr = 1, .has_hotplug = 1,
 211         .supports_tv = 1,
 212         .has_bsd_ring = 1,
 213 };
 214
 215 static const struct intel_device_info intel_pineview_info = {
 216         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_overlay = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_d_info = {
 222         .gen = 5,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_bsd_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_ironlake_m_info = {
 228         .gen = 5, .is_mobile = 1,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_fbc = 1,
 231         .has_bsd_ring = 1,
 232 };
 233
 234 static const struct intel_device_info intel_sandybridge_d_info = {
 235         .gen = 6,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238         .has_blt_ring = 1,
 239         .has_llc = 1,
 240         .has_force_wake = 1,
 241 };
 242
 243 static const struct intel_device_info intel_sandybridge_m_info = {
 244         .gen = 6, .is_mobile = 1,
 245         .need_gfx_hws = 1, .has_hotplug = 1,
 246         .has_fbc = 1,
 247         .has_bsd_ring = 1,
 248         .has_blt_ring = 1,
 249         .has_llc = 1,
 250         .has_force_wake = 1,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_d_info = {
 254         .is_ivybridge = 1, .gen = 7,
 255         .need_gfx_hws = 1, .has_hotplug = 1,
 256         .has_bsd_ring = 1,
 257         .has_blt_ring = 1,
 258         .has_llc = 1,
 259         .has_force_wake = 1,
 260 };
 261
 262 static const struct intel_device_info intel_ivybridge_m_info = {
 263         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 264         .need_gfx_hws = 1, .has_hotplug = 1,
 265         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 266         .has_bsd_ring = 1,
 267         .has_blt_ring = 1,
 268         .has_llc = 1,
 269         .has_force_wake = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_m_info = {
 273         .gen = 7, .is_mobile = 1,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279 };
 280
 281 static const struct intel_device_info intel_valleyview_d_info = {
 282         .gen = 7,
 283         .need_gfx_hws = 1, .has_hotplug = 1,
 284         .has_fbc = 0,
 285         .has_bsd_ring = 1,
 286         .has_blt_ring = 1,
 287         .is_valleyview = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_d_info = {
 291         .is_haswell = 1, .gen = 7,
 292         .need_gfx_hws = 1, .has_hotplug = 1,
 293         .has_bsd_ring = 1,
 294         .has_blt_ring = 1,
 295         .has_llc = 1,
 296         .has_force_wake = 1,
 297 };
 298
 299 static const struct intel_device_info intel_haswell_m_info = {
 300         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 301         .need_gfx_hws = 1, .has_hotplug = 1,
 302         .has_bsd_ring = 1,
 303         .has_blt_ring = 1,
 304         .has_llc = 1,
 305         .has_force_wake = 1,
 306 };
 307
 308 static const struct pci_device_id pciidlist[] = {               /* aka */
 309         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 310         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 311         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 312         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 313         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 314         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 315         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 316         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 317         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 318         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 319         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 320         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 321         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 322         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 323         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 324         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 325         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 326         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 327         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 328         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 329         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 330         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 331         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 332         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 333         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 334         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 335         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 336         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 337         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 338         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 339         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 340         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 341         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 342         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 343         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 344         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 345         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 346         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 347         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 348         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 349         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 350         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 351         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 352         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 353         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 354         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 355         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 356         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 357         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 358         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 359         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 360         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 361         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 362         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 363         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 364         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 365         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 366         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 367         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 368         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 369         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 370         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 371         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 372         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 373         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 374         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 375         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 376         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 377         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 378         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 379         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 380         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
 381         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 382         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
 383         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
 384         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 385         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
 386         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
 387         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 388         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 389         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 390         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 391         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 392         {0, 0, 0}
 393 };
 394
 395 #if defined(CONFIG_DRM_I915_KMS)
 396 MODULE_DEVICE_TABLE(pci, pciidlist);
 397 #endif
 398
 399 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 400 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 401 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 402 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 403 #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
 404
 405 void intel_detect_pch(struct drm_device *dev)
 406 {
 407         struct drm_i915_private *dev_priv = dev->dev_private;
 408         struct pci_dev *pch;
 409
 410         /*
 411          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 412          * make graphics device passthrough work easy for VMM, that only
 413          * need to expose ISA bridge to let driver know the real hardware
 414          * underneath. This is a requirement from virtualization team.
 415          */
 416         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 417         if (pch) {
 418                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 419                         int id;
 420                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 421
 422                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 423                                 dev_priv->pch_type = PCH_IBX;
 424                                 dev_priv->num_pch_pll = 2;
 425                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 426                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 427                                 dev_priv->pch_type = PCH_CPT;
 428                                 dev_priv->num_pch_pll = 2;
 429                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 430                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 431                                 /* PantherPoint is CPT compatible */
 432                                 dev_priv->pch_type = PCH_CPT;
 433                                 dev_priv->num_pch_pll = 2;
 434                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 435                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_LPT;
 437                                 dev_priv->num_pch_pll = 0;
 438                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 439                         }
 440                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 441                 }
 442                 pci_dev_put(pch);
 443         }
 444 }
 445
 446 bool i915_semaphore_is_enabled(struct drm_device *dev)
 447 {
 448         if (INTEL_INFO(dev)->gen < 6)
 449                 return 0;
 450
 451         if (i915_semaphores >= 0)
 452                 return i915_semaphores;
 453
 454 #ifdef CONFIG_INTEL_IOMMU
 455         /* Enable semaphores on SNB when IO remapping is off */
 456         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 457                 return false;
 458 #endif
 459
 460         return 1;
 461 }
 462
 463 static int i915_drm_freeze(struct drm_device *dev)
 464 {
 465         struct drm_i915_private *dev_priv = dev->dev_private;
 466
 467         drm_kms_helper_poll_disable(dev);
 468
 469         pci_save_state(dev->pdev);
 470
 471         /* If KMS is active, we do the leavevt stuff here */
 472         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 473                 int error = i915_gem_idle(dev);
 474                 if (error) {
 475                         dev_err(&dev->pdev->dev,
 476                                 "GEM idle failed, resume might fail\n");
 477                         return error;
 478                 }
 479
 480                 intel_modeset_disable(dev);
 481
 482                 drm_irq_uninstall(dev);
 483         }
 484
 485         i915_save_state(dev);
 486
 487         intel_opregion_fini(dev);
 488
 489         /* Modeset on resume, not lid events */
 490         dev_priv->modeset_on_lid = 0;
 491
 492         console_lock();
 493         intel_fbdev_set_suspend(dev, 1);
 494         console_unlock();
 495
 496         return 0;
 497 }
 498
 499 int i915_suspend(struct drm_device *dev, pm_message_t state)
 500 {
 501         int error;
 502
 503         if (!dev || !dev->dev_private) {
 504                 DRM_ERROR("dev: %p\n", dev);
 505                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 506                 return -ENODEV;
 507         }
 508
 509         if (state.event == PM_EVENT_PRETHAW)
 510                 return 0;
 511
 512
 513         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 514                 return 0;
 515
 516         error = i915_drm_freeze(dev);
 517         if (error)
 518                 return error;
 519
 520         if (state.event == PM_EVENT_SUSPEND) {
 521                 /* Shut down the device */
 522                 pci_disable_device(dev->pdev);
 523                 pci_set_power_state(dev->pdev, PCI_D3hot);
 524         }
 525
 526         return 0;
 527 }
 528
 529 static int i915_drm_thaw(struct drm_device *dev)
 530 {
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         int error = 0;
 533
 534         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 535                 mutex_lock(&dev->struct_mutex);
 536                 i915_gem_restore_gtt_mappings(dev);
 537                 mutex_unlock(&dev->struct_mutex);
 538         }
 539
 540         i915_restore_state(dev);
 541         intel_opregion_setup(dev);
 542
 543         /* KMS EnterVT equivalent */
 544         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 545                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 546                         ironlake_init_pch_refclk(dev);
 547
 548                 mutex_lock(&dev->struct_mutex);
 549                 dev_priv->mm.suspended = 0;
 550
 551                 error = i915_gem_init_hw(dev);
 552                 mutex_unlock(&dev->struct_mutex);
 553
 554                 intel_modeset_init_hw(dev);
 555                 intel_modeset_setup_hw_state(dev);
 556                 drm_mode_config_reset(dev);
 557                 drm_irq_install(dev);
 558         }
 559
 560         intel_opregion_init(dev);
 561
 562         dev_priv->modeset_on_lid = 0;
 563
 564         console_lock();
 565         intel_fbdev_set_suspend(dev, 0);
 566         console_unlock();
 567         return error;
 568 }
 569
 570 int i915_resume(struct drm_device *dev)
 571 {
 572         int ret;
 573
 574         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 575                 return 0;
 576
 577         if (pci_enable_device(dev->pdev))
 578                 return -EIO;
 579
 580         pci_set_master(dev->pdev);
 581
 582         ret = i915_drm_thaw(dev);
 583         if (ret)
 584                 return ret;
 585
 586         drm_kms_helper_poll_enable(dev);
 587         return 0;
 588 }
 589
 590 static int i8xx_do_reset(struct drm_device *dev)
 591 {
 592         struct drm_i915_private *dev_priv = dev->dev_private;
 593
 594         if (IS_I85X(dev))
 595                 return -ENODEV;
 596
 597         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 598         POSTING_READ(D_STATE);
 599
 600         if (IS_I830(dev) || IS_845G(dev)) {
 601                 I915_WRITE(DEBUG_RESET_I830,
 602                            DEBUG_RESET_DISPLAY |
 603                            DEBUG_RESET_RENDER |
 604                            DEBUG_RESET_FULL);
 605                 POSTING_READ(DEBUG_RESET_I830);
 606                 msleep(1);
 607
 608                 I915_WRITE(DEBUG_RESET_I830, 0);
 609                 POSTING_READ(DEBUG_RESET_I830);
 610         }
 611
 612         msleep(1);
 613
 614         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 615         POSTING_READ(D_STATE);
 616
 617         return 0;
 618 }
 619
 620 static int i965_reset_complete(struct drm_device *dev)
 621 {
 622         u8 gdrst;
 623         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 624         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 625 }
 626
 627 static int i965_do_reset(struct drm_device *dev)
 628 {
 629         int ret;
 630         u8 gdrst;
 631
 632         /*
 633          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 634          * well as the reset bit (GR/bit 0).  Setting the GR bit
 635          * triggers the reset; when done, the hardware will clear it.
 636          */
 637         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 638         pci_write_config_byte(dev->pdev, I965_GDRST,
 639                               gdrst | GRDOM_RENDER |
 640                               GRDOM_RESET_ENABLE);
 641         ret =  wait_for(i965_reset_complete(dev), 500);
 642         if (ret)
 643                 return ret;
 644
 645         /* We can't reset render&media without also resetting display ... */
 646         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 647         pci_write_config_byte(dev->pdev, I965_GDRST,
 648                               gdrst | GRDOM_MEDIA |
 649                               GRDOM_RESET_ENABLE);
 650
 651         return wait_for(i965_reset_complete(dev), 500);
 652 }
 653
 654 static int ironlake_do_reset(struct drm_device *dev)
 655 {
 656         struct drm_i915_private *dev_priv = dev->dev_private;
 657         u32 gdrst;
 658         int ret;
 659
 660         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 661         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 662                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 663         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 664         if (ret)
 665                 return ret;
 666
 667         /* We can't reset render&media without also resetting display ... */
 668         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 669         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 670                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 671         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 672 }
 673
 674 static int gen6_do_reset(struct drm_device *dev)
 675 {
 676         struct drm_i915_private *dev_priv = dev->dev_private;
 677         int     ret;
 678         unsigned long irqflags;
 679
 680         /* Hold gt_lock across reset to prevent any register access
 681          * with forcewake not set correctly
 682          */
 683         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 684
 685         /* Reset the chip */
 686
 687         /* GEN6_GDRST is not in the gt power well, no need to check
 688          * for fifo space for the write or forcewake the chip for
 689          * the read
 690          */
 691         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 692
 693         /* Spin waiting for the device to ack the reset request */
 694         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 695
 696         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 697         if (dev_priv->forcewake_count)
 698                 dev_priv->gt.force_wake_get(dev_priv);
 699         else
 700                 dev_priv->gt.force_wake_put(dev_priv);
 701
 702         /* Restore fifo count */
 703         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 704
 705         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 706         return ret;
 707 }
 708
 709 int intel_gpu_reset(struct drm_device *dev)
 710 {
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         int ret = -ENODEV;
 713
 714         switch (INTEL_INFO(dev)->gen) {
 715         case 7:
 716         case 6:
 717                 ret = gen6_do_reset(dev);
 718                 break;
 719         case 5:
 720                 ret = ironlake_do_reset(dev);
 721                 break;
 722         case 4:
 723                 ret = i965_do_reset(dev);
 724                 break;
 725         case 2:
 726                 ret = i8xx_do_reset(dev);
 727                 break;
 728         }
 729
 730         /* Also reset the gpu hangman. */
 731         if (dev_priv->stop_rings) {
 732                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 733                 dev_priv->stop_rings = 0;
 734                 if (ret == -ENODEV) {
 735                         DRM_ERROR("Reset not implemented, but ignoring "
 736                                   "error for simulated gpu hangs\n");
 737                         ret = 0;
 738                 }
 739         }
 740
 741         return ret;
 742 }
 743
 744 /**
 745  * i915_reset - reset chip after a hang
 746  * @dev: drm device to reset
 747  *
 748  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 749  * reset or otherwise an error code.
 750  *
 751  * Procedure is fairly simple:
 752  *   - reset the chip using the reset reg
 753  *   - re-init context state
 754  *   - re-init hardware status page
 755  *   - re-init ring buffer
 756  *   - re-init interrupt state
 757  *   - re-init display
 758  */
 759 int i915_reset(struct drm_device *dev)
 760 {
 761         drm_i915_private_t *dev_priv = dev->dev_private;
 762         int ret;
 763
 764         if (!i915_try_reset)
 765                 return 0;
 766
 767         mutex_lock(&dev->struct_mutex);
 768
 769         i915_gem_reset(dev);
 770
 771         ret = -ENODEV;
 772         if (get_seconds() - dev_priv->last_gpu_reset < 5)
 773                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 774         else
 775                 ret = intel_gpu_reset(dev);
 776
 777         dev_priv->last_gpu_reset = get_seconds();
 778         if (ret) {
 779                 DRM_ERROR("Failed to reset chip.\n");
 780                 mutex_unlock(&dev->struct_mutex);
 781                 return ret;
 782         }
 783
 784         /* Ok, now get things going again... */
 785
 786         /*
 787          * Everything depends on having the GTT running, so we need to start
 788          * there.  Fortunately we don't need to do this unless we reset the
 789          * chip at a PCI level.
 790          *
 791          * Next we need to restore the context, but we don't use those
 792          * yet either...
 793          *
 794          * Ring buffer needs to be re-initialized in the KMS case, or if X
 795          * was running at the time of the reset (i.e. we weren't VT
 796          * switched away).
 797          */
 798         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 799                         !dev_priv->mm.suspended) {
 800                 struct intel_ring_buffer *ring;
 801                 int i;
 802
 803                 dev_priv->mm.suspended = 0;
 804
 805                 i915_gem_init_swizzling(dev);
 806
 807                 for_each_ring(ring, dev_priv, i)
 808                         ring->init(ring);
 809
 810                 i915_gem_context_init(dev);
 811                 i915_gem_init_ppgtt(dev);
 812
 813                 /*
 814                  * It would make sense to re-init all the other hw state, at
 815                  * least the rps/rc6/emon init done within modeset_init_hw. For
 816                  * some unknown reason, this blows up my ilk, so don't.
 817                  */
 818
 819                 mutex_unlock(&dev->struct_mutex);
 820
 821                 drm_irq_uninstall(dev);
 822                 drm_irq_install(dev);
 823         } else {
 824                 mutex_unlock(&dev->struct_mutex);
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int __devinit
 831 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 832 {
 833         struct intel_device_info *intel_info =
 834                 (struct intel_device_info *) ent->driver_data;
 835
 836         if (intel_info->is_haswell || intel_info->is_valleyview)
 837                 if(!i915_preliminary_hw_support) {
 838                         DRM_ERROR("Preliminary hardware support disabled\n");
 839                         return -ENODEV;
 840                 }
 841
 842         /* Only bind to function 0 of the device. Early generations
 843          * used function 1 as a placeholder for multi-head. This causes
 844          * us confusion instead, especially on the systems where both
 845          * functions have the same PCI-ID!
 846          */
 847         if (PCI_FUNC(pdev->devfn))
 848                 return -ENODEV;
 849
 850         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 851          * implementation for gen3 (and only gen3) that used legacy drm maps
 852          * (gasp!) to share buffers between X and the client. Hence we need to
 853          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 854         if (intel_info->gen != 3) {
 855                 driver.driver_features &=
 856                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 857         } else if (!intel_agp_enabled) {
 858                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 859                 return -ENODEV;
 860         }
 861
 862         return drm_get_pci_dev(pdev, ent, &driver);
 863 }
 864
 865 static void
 866 i915_pci_remove(struct pci_dev *pdev)
 867 {
 868         struct drm_device *dev = pci_get_drvdata(pdev);
 869
 870         drm_put_dev(dev);
 871 }
 872
 873 static int i915_pm_suspend(struct device *dev)
 874 {
 875         struct pci_dev *pdev = to_pci_dev(dev);
 876         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 877         int error;
 878
 879         if (!drm_dev || !drm_dev->dev_private) {
 880                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 881                 return -ENODEV;
 882         }
 883
 884         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 885                 return 0;
 886
 887         error = i915_drm_freeze(drm_dev);
 888         if (error)
 889                 return error;
 890
 891         pci_disable_device(pdev);
 892         pci_set_power_state(pdev, PCI_D3hot);
 893
 894         return 0;
 895 }
 896
 897 static int i915_pm_resume(struct device *dev)
 898 {
 899         struct pci_dev *pdev = to_pci_dev(dev);
 900         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 901
 902         return i915_resume(drm_dev);
 903 }
 904
 905 static int i915_pm_freeze(struct device *dev)
 906 {
 907         struct pci_dev *pdev = to_pci_dev(dev);
 908         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 909
 910         if (!drm_dev || !drm_dev->dev_private) {
 911                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 912                 return -ENODEV;
 913         }
 914
 915         return i915_drm_freeze(drm_dev);
 916 }
 917
 918 static int i915_pm_thaw(struct device *dev)
 919 {
 920         struct pci_dev *pdev = to_pci_dev(dev);
 921         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 922
 923         return i915_drm_thaw(drm_dev);
 924 }
 925
 926 static int i915_pm_poweroff(struct device *dev)
 927 {
 928         struct pci_dev *pdev = to_pci_dev(dev);
 929         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 930
 931         return i915_drm_freeze(drm_dev);
 932 }
 933
 934 static const struct dev_pm_ops i915_pm_ops = {
 935         .suspend = i915_pm_suspend,
 936         .resume = i915_pm_resume,
 937         .freeze = i915_pm_freeze,
 938         .thaw = i915_pm_thaw,
 939         .poweroff = i915_pm_poweroff,
 940         .restore = i915_pm_resume,
 941 };
 942
 943 static const struct vm_operations_struct i915_gem_vm_ops = {
 944         .fault = i915_gem_fault,
 945         .open = drm_gem_vm_open,
 946         .close = drm_gem_vm_close,
 947 };
 948
 949 static const struct file_operations i915_driver_fops = {
 950         .owner = THIS_MODULE,
 951         .open = drm_open,
 952         .release = drm_release,
 953         .unlocked_ioctl = drm_ioctl,
 954         .mmap = drm_gem_mmap,
 955         .poll = drm_poll,
 956         .fasync = drm_fasync,
 957         .read = drm_read,
 958 #ifdef CONFIG_COMPAT
 959         .compat_ioctl = i915_compat_ioctl,
 960 #endif
 961         .llseek = noop_llseek,
 962 };
 963
 964 static struct drm_driver driver = {
 965         /* Don't use MTRRs here; the Xserver or userspace app should
 966          * deal with them for Intel hardware.
 967          */
 968         .driver_features =
 969             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 970             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
 971         .load = i915_driver_load,
 972         .unload = i915_driver_unload,
 973         .open = i915_driver_open,
 974         .lastclose = i915_driver_lastclose,
 975         .preclose = i915_driver_preclose,
 976         .postclose = i915_driver_postclose,
 977
 978         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 979         .suspend = i915_suspend,
 980         .resume = i915_resume,
 981
 982         .device_is_agp = i915_driver_device_is_agp,
 983         .master_create = i915_master_create,
 984         .master_destroy = i915_master_destroy,
 985 #if defined(CONFIG_DEBUG_FS)
 986         .debugfs_init = i915_debugfs_init,
 987         .debugfs_cleanup = i915_debugfs_cleanup,
 988 #endif
 989         .gem_init_object = i915_gem_init_object,
 990         .gem_free_object = i915_gem_free_object,
 991         .gem_vm_ops = &i915_gem_vm_ops,
 992
 993         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 994         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 995         .gem_prime_export = i915_gem_prime_export,
 996         .gem_prime_import = i915_gem_prime_import,
 997
 998         .dumb_create = i915_gem_dumb_create,
 999         .dumb_map_offset = i915_gem_mmap_gtt,
1000         .dumb_destroy = i915_gem_dumb_destroy,
1001         .ioctls = i915_ioctls,
1002         .fops = &i915_driver_fops,
1003         .name = DRIVER_NAME,
1004         .desc = DRIVER_DESC,
1005         .date = DRIVER_DATE,
1006         .major = DRIVER_MAJOR,
1007         .minor = DRIVER_MINOR,
1008         .patchlevel = DRIVER_PATCHLEVEL,
1009 };
1010
1011 static struct pci_driver i915_pci_driver = {
1012         .name = DRIVER_NAME,
1013         .id_table = pciidlist,
1014         .probe = i915_pci_probe,
1015         .remove = i915_pci_remove,
1016         .driver.pm = &i915_pm_ops,
1017 };
1018
1019 static int __init i915_init(void)
1020 {
1021         driver.num_ioctls = i915_max_ioctl;
1022
1023         /*
1024          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1025          * explicitly disabled with the module pararmeter.
1026          *
1027          * Otherwise, just follow the parameter (defaulting to off).
1028          *
1029          * Allow optional vga_text_mode_force boot option to override
1030          * the default behavior.
1031          */
1032 #if defined(CONFIG_DRM_I915_KMS)
1033         if (i915_modeset != 0)
1034                 driver.driver_features |= DRIVER_MODESET;
1035 #endif
1036         if (i915_modeset == 1)
1037                 driver.driver_features |= DRIVER_MODESET;
1038
1039 #ifdef CONFIG_VGA_CONSOLE
1040         if (vgacon_text_force() && i915_modeset == -1)
1041                 driver.driver_features &= ~DRIVER_MODESET;
1042 #endif
1043
1044         if (!(driver.driver_features & DRIVER_MODESET))
1045                 driver.get_vblank_timestamp = NULL;
1046
1047         return drm_pci_init(&driver, &i915_pci_driver);
1048 }
1049
1050 static void __exit i915_exit(void)
1051 {
1052         drm_pci_exit(&driver, &i915_pci_driver);
1053 }
1054
1055 module_init(i915_init);
1056 module_exit(i915_exit);
1057
1058 MODULE_AUTHOR(DRIVER_AUTHOR);
1059 MODULE_DESCRIPTION(DRIVER_DESC);
1060 MODULE_LICENSE("GPL and additional rights");
1061
1062 /* We give fast paths for the really cool registers */
1063 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1064         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1065          ((reg) < 0x40000) &&            \
1066          ((reg) != FORCEWAKE))
1067
1068 static bool IS_DISPLAYREG(u32 reg)
1069 {
1070         /*
1071          * This should make it easier to transition modules over to the
1072          * new register block scheme, since we can do it incrementally.
1073          */
1074         if (reg >= VLV_DISPLAY_BASE)
1075                 return false;
1076
1077         if (reg >= RENDER_RING_BASE &&
1078             reg < RENDER_RING_BASE + 0xff)
1079                 return false;
1080         if (reg >= GEN6_BSD_RING_BASE &&
1081             reg < GEN6_BSD_RING_BASE + 0xff)
1082                 return false;
1083         if (reg >= BLT_RING_BASE &&
1084             reg < BLT_RING_BASE + 0xff)
1085                 return false;
1086
1087         if (reg == PGTBL_ER)
1088                 return false;
1089
1090         if (reg >= IPEIR_I965 &&
1091             reg < HWSTAM)
1092                 return false;
1093
1094         if (reg == MI_MODE)
1095                 return false;
1096
1097         if (reg == GFX_MODE_GEN7)
1098                 return false;
1099
1100         if (reg == RENDER_HWS_PGA_GEN7 ||
1101             reg == BSD_HWS_PGA_GEN7 ||
1102             reg == BLT_HWS_PGA_GEN7)
1103                 return false;
1104
1105         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1106             reg == GEN6_BSD_RNCID)
1107                 return false;
1108
1109         if (reg == GEN6_BLITTER_ECOSKPD)
1110                 return false;
1111
1112         if (reg >= 0x4000c &&
1113             reg <= 0x4002c)
1114                 return false;
1115
1116         if (reg >= 0x4f000 &&
1117             reg <= 0x4f08f)
1118                 return false;
1119
1120         if (reg >= 0x4f100 &&
1121             reg <= 0x4f11f)
1122                 return false;
1123
1124         if (reg >= VLV_MASTER_IER &&
1125             reg <= GEN6_PMIER)
1126                 return false;
1127
1128         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1129             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1130                 return false;
1131
1132         if (reg >= VLV_IIR_RW &&
1133             reg <= VLV_ISR)
1134                 return false;
1135
1136         if (reg == FORCEWAKE_VLV ||
1137             reg == FORCEWAKE_ACK_VLV)
1138                 return false;
1139
1140         if (reg == GEN6_GDRST)
1141                 return false;
1142
1143         return true;
1144 }
1145
1146 #define __i915_read(x, y) \
1147 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1148         u##x val = 0; \
1149         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1150                 unsigned long irqflags; \
1151                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1152                 if (dev_priv->forcewake_count == 0) \
1153                         dev_priv->gt.force_wake_get(dev_priv); \
1154                 val = read##y(dev_priv->regs + reg); \
1155                 if (dev_priv->forcewake_count == 0) \
1156                         dev_priv->gt.force_wake_put(dev_priv); \
1157                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1158         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1159                 val = read##y(dev_priv->regs + reg + 0x180000);         \
1160         } else { \
1161                 val = read##y(dev_priv->regs + reg); \
1162         } \
1163         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1164         return val; \
1165 }
1166
1167 __i915_read(8, b)
1168 __i915_read(16, w)
1169 __i915_read(32, l)
1170 __i915_read(64, q)
1171 #undef __i915_read
1172
1173 #define __i915_write(x, y) \
1174 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1175         u32 __fifo_ret = 0; \
1176         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1177         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1178                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1179         } \
1180         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1181                 write##y(val, dev_priv->regs + reg + 0x180000);         \
1182         } else {                                                        \
1183                 write##y(val, dev_priv->regs + reg);                    \
1184         }                                                               \
1185         if (unlikely(__fifo_ret)) { \
1186                 gen6_gt_check_fifodbg(dev_priv); \
1187         } \
1188         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1189                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1190                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
1191         } \
1192 }
1193 __i915_write(8, b)
1194 __i915_write(16, w)
1195 __i915_write(32, l)
1196 __i915_write(64, q)
1197 #undef __i915_write
1198
1199 static const struct register_whitelist {
1200         uint64_t offset;
1201         uint32_t size;
1202         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1203 } whitelist[] = {
1204         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1205 };
1206
1207 int i915_reg_read_ioctl(struct drm_device *dev,
1208                         void *data, struct drm_file *file)
1209 {
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211         struct drm_i915_reg_read *reg = data;
1212         struct register_whitelist const *entry = whitelist;
1213         int i;
1214
1215         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1216                 if (entry->offset == reg->offset &&
1217                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1218                         break;
1219         }
1220
1221         if (i == ARRAY_SIZE(whitelist))
1222                 return -EINVAL;
1223
1224         switch (entry->size) {
1225         case 8:
1226                 reg->val = I915_READ64(reg->offset);
1227                 break;
1228         case 4:
1229                 reg->val = I915_READ(reg->offset);
1230                 break;
1231         case 2:
1232                 reg->val = I915_READ16(reg->offset);
1233                 break;
1234         case 1:
1235                 reg->val = I915_READ8(reg->offset);
1236                 break;
1237         default:
1238                 WARN_ON(1);
1239                 return -EINVAL;
1240         }
1241
1242         return 0;
1243 }