3036d4835b0fa7a3b366a31d0b6ed18fc7889ae1
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42 #include <acpi/video.h>
43
44 #include <drm/drmP.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
48
49 #include "i915_drv.h"
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
53 #include "intel_uc.h"
54
55 static struct drm_driver driver;
56
57 static unsigned int i915_load_fail_count;
58
59 bool __i915_inject_load_failure(const char *func, int line)
60 {
61         if (i915_load_fail_count >= i915.inject_load_failure)
62                 return false;
63
64         if (++i915_load_fail_count == i915.inject_load_failure) {
65                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66                          i915.inject_load_failure, func, line);
67                 return true;
68         }
69
70         return false;
71 }
72
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75                     "providing the dmesg log by booting with drm.debug=0xf"
76
77 void
78 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
79               const char *fmt, ...)
80 {
81         static bool shown_bug_once;
82         struct device *kdev = dev_priv->drm.dev;
83         bool is_error = level[1] <= KERN_ERR[1];
84         bool is_debug = level[1] == KERN_DEBUG[1];
85         struct va_format vaf;
86         va_list args;
87
88         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
89                 return;
90
91         va_start(args, fmt);
92
93         vaf.fmt = fmt;
94         vaf.va = &args;
95
96         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
97                    __builtin_return_address(0), &vaf);
98
99         if (is_error && !shown_bug_once) {
100                 dev_notice(kdev, "%s", FDO_BUG_MSG);
101                 shown_bug_once = true;
102         }
103
104         va_end(args);
105 }
106
107 static bool i915_error_injected(struct drm_i915_private *dev_priv)
108 {
109         return i915.inject_load_failure &&
110                i915_load_fail_count == i915.inject_load_failure;
111 }
112
113 #define i915_load_error(dev_priv, fmt, ...)                                  \
114         __i915_printk(dev_priv,                                              \
115                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
116                       fmt, ##__VA_ARGS__)
117
118
119 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
120 {
121         enum intel_pch ret = PCH_NOP;
122
123         /*
124          * In a virtualized passthrough environment we can be in a
125          * setup where the ISA bridge is not able to be passed through.
126          * In this case, a south bridge can be emulated and we have to
127          * make an educated guess as to which PCH is really there.
128          */
129
130         if (IS_GEN5(dev_priv)) {
131                 ret = PCH_IBX;
132                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133         } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
134                 ret = PCH_CPT;
135                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
136         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
137                 ret = PCH_LPT;
138                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
139         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
140                 ret = PCH_SPT;
141                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
142         }
143
144         return ret;
145 }
146
147 static void intel_detect_pch(struct drm_i915_private *dev_priv)
148 {
149         struct pci_dev *pch = NULL;
150
151         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
152          * (which really amounts to a PCH but no South Display).
153          */
154         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
155                 dev_priv->pch_type = PCH_NOP;
156                 return;
157         }
158
159         /*
160          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
161          * make graphics device passthrough work easy for VMM, that only
162          * need to expose ISA bridge to let driver know the real hardware
163          * underneath. This is a requirement from virtualization team.
164          *
165          * In some virtualized environments (e.g. XEN), there is irrelevant
166          * ISA bridge in the system. To work reliably, we should scan trhough
167          * all the ISA bridge devices and check for the first match, instead
168          * of only checking the first one.
169          */
170         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
171                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
172                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
173                         dev_priv->pch_id = id;
174
175                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
176                                 dev_priv->pch_type = PCH_IBX;
177                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
178                                 WARN_ON(!IS_GEN5(dev_priv));
179                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
180                                 dev_priv->pch_type = PCH_CPT;
181                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
182                                 WARN_ON(!(IS_GEN6(dev_priv) ||
183                                         IS_IVYBRIDGE(dev_priv)));
184                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
185                                 /* PantherPoint is CPT compatible */
186                                 dev_priv->pch_type = PCH_CPT;
187                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
188                                 WARN_ON(!(IS_GEN6(dev_priv) ||
189                                         IS_IVYBRIDGE(dev_priv)));
190                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
191                                 dev_priv->pch_type = PCH_LPT;
192                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
193                                 WARN_ON(!IS_HASWELL(dev_priv) &&
194                                         !IS_BROADWELL(dev_priv));
195                                 WARN_ON(IS_HSW_ULT(dev_priv) ||
196                                         IS_BDW_ULT(dev_priv));
197                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
198                                 dev_priv->pch_type = PCH_LPT;
199                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
200                                 WARN_ON(!IS_HASWELL(dev_priv) &&
201                                         !IS_BROADWELL(dev_priv));
202                                 WARN_ON(!IS_HSW_ULT(dev_priv) &&
203                                         !IS_BDW_ULT(dev_priv));
204                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
205                                 dev_priv->pch_type = PCH_SPT;
206                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
207                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
208                                         !IS_KABYLAKE(dev_priv));
209                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
210                                 dev_priv->pch_type = PCH_SPT;
211                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
212                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
213                                         !IS_KABYLAKE(dev_priv));
214                         } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
215                                 dev_priv->pch_type = PCH_KBP;
216                                 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
217                                 WARN_ON(!IS_SKYLAKE(dev_priv) &&
218                                         !IS_KABYLAKE(dev_priv));
219                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
220                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
221                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
222                                     pch->subsystem_vendor ==
223                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
224                                     pch->subsystem_device ==
225                                             PCI_SUBDEVICE_ID_QEMU)) {
226                                 dev_priv->pch_type =
227                                         intel_virt_detect_pch(dev_priv);
228                         } else
229                                 continue;
230
231                         break;
232                 }
233         }
234         if (!pch)
235                 DRM_DEBUG_KMS("No PCH found.\n");
236
237         pci_dev_put(pch);
238 }
239
240 static int i915_getparam(struct drm_device *dev, void *data,
241                          struct drm_file *file_priv)
242 {
243         struct drm_i915_private *dev_priv = to_i915(dev);
244         struct pci_dev *pdev = dev_priv->drm.pdev;
245         drm_i915_getparam_t *param = data;
246         int value;
247
248         switch (param->param) {
249         case I915_PARAM_IRQ_ACTIVE:
250         case I915_PARAM_ALLOW_BATCHBUFFER:
251         case I915_PARAM_LAST_DISPATCH:
252         case I915_PARAM_HAS_EXEC_CONSTANTS:
253                 /* Reject all old ums/dri params. */
254                 return -ENODEV;
255         case I915_PARAM_CHIPSET_ID:
256                 value = pdev->device;
257                 break;
258         case I915_PARAM_REVISION:
259                 value = pdev->revision;
260                 break;
261         case I915_PARAM_NUM_FENCES_AVAIL:
262                 value = dev_priv->num_fence_regs;
263                 break;
264         case I915_PARAM_HAS_OVERLAY:
265                 value = dev_priv->overlay ? 1 : 0;
266                 break;
267         case I915_PARAM_HAS_BSD:
268                 value = !!dev_priv->engine[VCS];
269                 break;
270         case I915_PARAM_HAS_BLT:
271                 value = !!dev_priv->engine[BCS];
272                 break;
273         case I915_PARAM_HAS_VEBOX:
274                 value = !!dev_priv->engine[VECS];
275                 break;
276         case I915_PARAM_HAS_BSD2:
277                 value = !!dev_priv->engine[VCS2];
278                 break;
279         case I915_PARAM_HAS_LLC:
280                 value = HAS_LLC(dev_priv);
281                 break;
282         case I915_PARAM_HAS_WT:
283                 value = HAS_WT(dev_priv);
284                 break;
285         case I915_PARAM_HAS_ALIASING_PPGTT:
286                 value = USES_PPGTT(dev_priv);
287                 break;
288         case I915_PARAM_HAS_SEMAPHORES:
289                 value = i915.semaphores;
290                 break;
291         case I915_PARAM_HAS_SECURE_BATCHES:
292                 value = capable(CAP_SYS_ADMIN);
293                 break;
294         case I915_PARAM_CMD_PARSER_VERSION:
295                 value = i915_cmd_parser_get_version(dev_priv);
296                 break;
297         case I915_PARAM_SUBSLICE_TOTAL:
298                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
299                 if (!value)
300                         return -ENODEV;
301                 break;
302         case I915_PARAM_EU_TOTAL:
303                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
304                 if (!value)
305                         return -ENODEV;
306                 break;
307         case I915_PARAM_HAS_GPU_RESET:
308                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
309                 break;
310         case I915_PARAM_HAS_RESOURCE_STREAMER:
311                 value = HAS_RESOURCE_STREAMER(dev_priv);
312                 break;
313         case I915_PARAM_HAS_POOLED_EU:
314                 value = HAS_POOLED_EU(dev_priv);
315                 break;
316         case I915_PARAM_MIN_EU_IN_POOL:
317                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
318                 break;
319         case I915_PARAM_HUC_STATUS:
320                 intel_runtime_pm_get(dev_priv);
321                 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED;
322                 intel_runtime_pm_put(dev_priv);
323                 break;
324         case I915_PARAM_MMAP_GTT_VERSION:
325                 /* Though we've started our numbering from 1, and so class all
326                  * earlier versions as 0, in effect their value is undefined as
327                  * the ioctl will report EINVAL for the unknown param!
328                  */
329                 value = i915_gem_mmap_gtt_version();
330                 break;
331         case I915_PARAM_HAS_SCHEDULER:
332                 value = dev_priv->engine[RCS] &&
333                         dev_priv->engine[RCS]->schedule;
334                 break;
335         case I915_PARAM_MMAP_VERSION:
336                 /* Remember to bump this if the version changes! */
337         case I915_PARAM_HAS_GEM:
338         case I915_PARAM_HAS_PAGEFLIPPING:
339         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
340         case I915_PARAM_HAS_RELAXED_FENCING:
341         case I915_PARAM_HAS_COHERENT_RINGS:
342         case I915_PARAM_HAS_RELAXED_DELTA:
343         case I915_PARAM_HAS_GEN7_SOL_RESET:
344         case I915_PARAM_HAS_WAIT_TIMEOUT:
345         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
346         case I915_PARAM_HAS_PINNED_BATCHES:
347         case I915_PARAM_HAS_EXEC_NO_RELOC:
348         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
349         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
350         case I915_PARAM_HAS_EXEC_SOFTPIN:
351         case I915_PARAM_HAS_EXEC_ASYNC:
352         case I915_PARAM_HAS_EXEC_FENCE:
353                 /* For the time being all of these are always true;
354                  * if some supported hardware does not have one of these
355                  * features this value needs to be provided from
356                  * INTEL_INFO(), a feature macro, or similar.
357                  */
358                 value = 1;
359                 break;
360         default:
361                 DRM_DEBUG("Unknown parameter %d\n", param->param);
362                 return -EINVAL;
363         }
364
365         if (put_user(value, param->value))
366                 return -EFAULT;
367
368         return 0;
369 }
370
371 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
372 {
373         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
374         if (!dev_priv->bridge_dev) {
375                 DRM_ERROR("bridge device not found\n");
376                 return -1;
377         }
378         return 0;
379 }
380
381 /* Allocate space for the MCH regs if needed, return nonzero on error */
382 static int
383 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
384 {
385         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
386         u32 temp_lo, temp_hi = 0;
387         u64 mchbar_addr;
388         int ret;
389
390         if (INTEL_GEN(dev_priv) >= 4)
391                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
392         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
393         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
394
395         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
396 #ifdef CONFIG_PNP
397         if (mchbar_addr &&
398             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
399                 return 0;
400 #endif
401
402         /* Get some space for it */
403         dev_priv->mch_res.name = "i915 MCHBAR";
404         dev_priv->mch_res.flags = IORESOURCE_MEM;
405         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
406                                      &dev_priv->mch_res,
407                                      MCHBAR_SIZE, MCHBAR_SIZE,
408                                      PCIBIOS_MIN_MEM,
409                                      0, pcibios_align_resource,
410                                      dev_priv->bridge_dev);
411         if (ret) {
412                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
413                 dev_priv->mch_res.start = 0;
414                 return ret;
415         }
416
417         if (INTEL_GEN(dev_priv) >= 4)
418                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
419                                        upper_32_bits(dev_priv->mch_res.start));
420
421         pci_write_config_dword(dev_priv->bridge_dev, reg,
422                                lower_32_bits(dev_priv->mch_res.start));
423         return 0;
424 }
425
426 /* Setup MCHBAR if possible, return true if we should disable it again */
427 static void
428 intel_setup_mchbar(struct drm_i915_private *dev_priv)
429 {
430         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
431         u32 temp;
432         bool enabled;
433
434         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
435                 return;
436
437         dev_priv->mchbar_need_disable = false;
438
439         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
440                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
441                 enabled = !!(temp & DEVEN_MCHBAR_EN);
442         } else {
443                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
444                 enabled = temp & 1;
445         }
446
447         /* If it's already enabled, don't have to do anything */
448         if (enabled)
449                 return;
450
451         if (intel_alloc_mchbar_resource(dev_priv))
452                 return;
453
454         dev_priv->mchbar_need_disable = true;
455
456         /* Space is allocated or reserved, so enable it. */
457         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
458                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
459                                        temp | DEVEN_MCHBAR_EN);
460         } else {
461                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
462                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
463         }
464 }
465
466 static void
467 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
468 {
469         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
470
471         if (dev_priv->mchbar_need_disable) {
472                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
473                         u32 deven_val;
474
475                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
476                                               &deven_val);
477                         deven_val &= ~DEVEN_MCHBAR_EN;
478                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
479                                                deven_val);
480                 } else {
481                         u32 mchbar_val;
482
483                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
484                                               &mchbar_val);
485                         mchbar_val &= ~1;
486                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
487                                                mchbar_val);
488                 }
489         }
490
491         if (dev_priv->mch_res.start)
492                 release_resource(&dev_priv->mch_res);
493 }
494
495 /* true = enable decode, false = disable decoder */
496 static unsigned int i915_vga_set_decode(void *cookie, bool state)
497 {
498         struct drm_i915_private *dev_priv = cookie;
499
500         intel_modeset_vga_set_state(dev_priv, state);
501         if (state)
502                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
503                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
504         else
505                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
506 }
507
508 static int i915_resume_switcheroo(struct drm_device *dev);
509 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
510
511 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
512 {
513         struct drm_device *dev = pci_get_drvdata(pdev);
514         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
515
516         if (state == VGA_SWITCHEROO_ON) {
517                 pr_info("switched on\n");
518                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
519                 /* i915 resume handler doesn't set to D0 */
520                 pci_set_power_state(pdev, PCI_D0);
521                 i915_resume_switcheroo(dev);
522                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
523         } else {
524                 pr_info("switched off\n");
525                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
526                 i915_suspend_switcheroo(dev, pmm);
527                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
528         }
529 }
530
531 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
532 {
533         struct drm_device *dev = pci_get_drvdata(pdev);
534
535         /*
536          * FIXME: open_count is protected by drm_global_mutex but that would lead to
537          * locking inversion with the driver load path. And the access here is
538          * completely racy anyway. So don't bother with locking for now.
539          */
540         return dev->open_count == 0;
541 }
542
543 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
544         .set_gpu_state = i915_switcheroo_set_state,
545         .reprobe = NULL,
546         .can_switch = i915_switcheroo_can_switch,
547 };
548
549 static void i915_gem_fini(struct drm_i915_private *dev_priv)
550 {
551         mutex_lock(&dev_priv->drm.struct_mutex);
552         intel_uc_fini_hw(dev_priv);
553         i915_gem_cleanup_engines(dev_priv);
554         i915_gem_context_fini(dev_priv);
555         mutex_unlock(&dev_priv->drm.struct_mutex);
556
557         i915_gem_drain_freed_objects(dev_priv);
558
559         WARN_ON(!list_empty(&dev_priv->context_list));
560 }
561
562 static int i915_load_modeset_init(struct drm_device *dev)
563 {
564         struct drm_i915_private *dev_priv = to_i915(dev);
565         struct pci_dev *pdev = dev_priv->drm.pdev;
566         int ret;
567
568         if (i915_inject_load_failure())
569                 return -ENODEV;
570
571         intel_bios_init(dev_priv);
572
573         /* If we have > 1 VGA cards, then we need to arbitrate access
574          * to the common VGA resources.
575          *
576          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
577          * then we do not take part in VGA arbitration and the
578          * vga_client_register() fails with -ENODEV.
579          */
580         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
581         if (ret && ret != -ENODEV)
582                 goto out;
583
584         intel_register_dsm_handler();
585
586         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
587         if (ret)
588                 goto cleanup_vga_client;
589
590         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
591         intel_update_rawclk(dev_priv);
592
593         intel_power_domains_init_hw(dev_priv, false);
594
595         intel_csr_ucode_init(dev_priv);
596
597         ret = intel_irq_install(dev_priv);
598         if (ret)
599                 goto cleanup_csr;
600
601         intel_setup_gmbus(dev_priv);
602
603         /* Important: The output setup functions called by modeset_init need
604          * working irqs for e.g. gmbus and dp aux transfers. */
605         ret = intel_modeset_init(dev);
606         if (ret)
607                 goto cleanup_irq;
608
609         intel_uc_init_fw(dev_priv);
610
611         ret = i915_gem_init(dev_priv);
612         if (ret)
613                 goto cleanup_uc;
614
615         intel_modeset_gem_init(dev);
616
617         if (INTEL_INFO(dev_priv)->num_pipes == 0)
618                 return 0;
619
620         ret = intel_fbdev_init(dev);
621         if (ret)
622                 goto cleanup_gem;
623
624         /* Only enable hotplug handling once the fbdev is fully set up. */
625         intel_hpd_init(dev_priv);
626
627         drm_kms_helper_poll_init(dev);
628
629         return 0;
630
631 cleanup_gem:
632         if (i915_gem_suspend(dev_priv))
633                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
634         i915_gem_fini(dev_priv);
635 cleanup_uc:
636         intel_uc_fini_fw(dev_priv);
637 cleanup_irq:
638         drm_irq_uninstall(dev);
639         intel_teardown_gmbus(dev_priv);
640 cleanup_csr:
641         intel_csr_ucode_fini(dev_priv);
642         intel_power_domains_fini(dev_priv);
643         vga_switcheroo_unregister_client(pdev);
644 cleanup_vga_client:
645         vga_client_register(pdev, NULL, NULL, NULL);
646 out:
647         return ret;
648 }
649
650 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
651 {
652         struct apertures_struct *ap;
653         struct pci_dev *pdev = dev_priv->drm.pdev;
654         struct i915_ggtt *ggtt = &dev_priv->ggtt;
655         bool primary;
656         int ret;
657
658         ap = alloc_apertures(1);
659         if (!ap)
660                 return -ENOMEM;
661
662         ap->ranges[0].base = ggtt->mappable_base;
663         ap->ranges[0].size = ggtt->mappable_end;
664
665         primary =
666                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
667
668         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
669
670         kfree(ap);
671
672         return ret;
673 }
674
675 #if !defined(CONFIG_VGA_CONSOLE)
676 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
677 {
678         return 0;
679 }
680 #elif !defined(CONFIG_DUMMY_CONSOLE)
681 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
682 {
683         return -ENODEV;
684 }
685 #else
686 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
687 {
688         int ret = 0;
689
690         DRM_INFO("Replacing VGA console driver\n");
691
692         console_lock();
693         if (con_is_bound(&vga_con))
694                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
695         if (ret == 0) {
696                 ret = do_unregister_con_driver(&vga_con);
697
698                 /* Ignore "already unregistered". */
699                 if (ret == -ENODEV)
700                         ret = 0;
701         }
702         console_unlock();
703
704         return ret;
705 }
706 #endif
707
708 static void intel_init_dpio(struct drm_i915_private *dev_priv)
709 {
710         /*
711          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
712          * CHV x1 PHY (DP/HDMI D)
713          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
714          */
715         if (IS_CHERRYVIEW(dev_priv)) {
716                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
717                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
718         } else if (IS_VALLEYVIEW(dev_priv)) {
719                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
720         }
721 }
722
723 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
724 {
725         /*
726          * The i915 workqueue is primarily used for batched retirement of
727          * requests (and thus managing bo) once the task has been completed
728          * by the GPU. i915_gem_retire_requests() is called directly when we
729          * need high-priority retirement, such as waiting for an explicit
730          * bo.
731          *
732          * It is also used for periodic low-priority events, such as
733          * idle-timers and recording error state.
734          *
735          * All tasks on the workqueue are expected to acquire the dev mutex
736          * so there is no point in running more than one instance of the
737          * workqueue at any time.  Use an ordered one.
738          */
739         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
740         if (dev_priv->wq == NULL)
741                 goto out_err;
742
743         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
744         if (dev_priv->hotplug.dp_wq == NULL)
745                 goto out_free_wq;
746
747         return 0;
748
749 out_free_wq:
750         destroy_workqueue(dev_priv->wq);
751 out_err:
752         DRM_ERROR("Failed to allocate workqueues.\n");
753
754         return -ENOMEM;
755 }
756
757 static void i915_engines_cleanup(struct drm_i915_private *i915)
758 {
759         struct intel_engine_cs *engine;
760         enum intel_engine_id id;
761
762         for_each_engine(engine, i915, id)
763                 kfree(engine);
764 }
765
766 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
767 {
768         destroy_workqueue(dev_priv->hotplug.dp_wq);
769         destroy_workqueue(dev_priv->wq);
770 }
771
772 /*
773  * We don't keep the workarounds for pre-production hardware, so we expect our
774  * driver to fail on these machines in one way or another. A little warning on
775  * dmesg may help both the user and the bug triagers.
776  */
777 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
778 {
779         bool pre = false;
780
781         pre |= IS_HSW_EARLY_SDV(dev_priv);
782         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
783         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
784
785         if (pre) {
786                 DRM_ERROR("This is a pre-production stepping. "
787                           "It may not be fully functional.\n");
788                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
789         }
790 }
791
792 /**
793  * i915_driver_init_early - setup state not requiring device access
794  * @dev_priv: device private
795  *
796  * Initialize everything that is a "SW-only" state, that is state not
797  * requiring accessing the device or exposing the driver via kernel internal
798  * or userspace interfaces. Example steps belonging here: lock initialization,
799  * system memory allocation, setting up device specific attributes and
800  * function hooks not requiring accessing the device.
801  */
802 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
803                                   const struct pci_device_id *ent)
804 {
805         const struct intel_device_info *match_info =
806                 (struct intel_device_info *)ent->driver_data;
807         struct intel_device_info *device_info;
808         int ret = 0;
809
810         if (i915_inject_load_failure())
811                 return -ENODEV;
812
813         /* Setup the write-once "constant" device info */
814         device_info = mkwrite_device_info(dev_priv);
815         memcpy(device_info, match_info, sizeof(*device_info));
816         device_info->device_id = dev_priv->drm.pdev->device;
817
818         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
819         device_info->gen_mask = BIT(device_info->gen - 1);
820
821         spin_lock_init(&dev_priv->irq_lock);
822         spin_lock_init(&dev_priv->gpu_error.lock);
823         mutex_init(&dev_priv->backlight_lock);
824         spin_lock_init(&dev_priv->uncore.lock);
825
826         spin_lock_init(&dev_priv->mm.object_stat_lock);
827         spin_lock_init(&dev_priv->mmio_flip_lock);
828         mutex_init(&dev_priv->sb_lock);
829         mutex_init(&dev_priv->modeset_restore_lock);
830         mutex_init(&dev_priv->av_mutex);
831         mutex_init(&dev_priv->wm.wm_mutex);
832         mutex_init(&dev_priv->pps_mutex);
833
834         intel_uc_init_early(dev_priv);
835         i915_memcpy_init_early(dev_priv);
836
837         ret = intel_engines_init_early(dev_priv);
838         if (ret)
839                 return ret;
840
841         ret = i915_workqueues_init(dev_priv);
842         if (ret < 0)
843                 goto err_engines;
844
845         /* This must be called before any calls to HAS_PCH_* */
846         intel_detect_pch(dev_priv);
847
848         intel_pm_setup(dev_priv);
849         intel_init_dpio(dev_priv);
850         intel_power_domains_init(dev_priv);
851         intel_irq_init(dev_priv);
852         intel_hangcheck_init(dev_priv);
853         intel_init_display_hooks(dev_priv);
854         intel_init_clock_gating_hooks(dev_priv);
855         intel_init_audio_hooks(dev_priv);
856         ret = i915_gem_load_init(dev_priv);
857         if (ret < 0)
858                 goto err_workqueues;
859
860         intel_display_crc_init(dev_priv);
861
862         intel_device_info_dump(dev_priv);
863
864         intel_detect_preproduction_hw(dev_priv);
865
866         i915_perf_init(dev_priv);
867
868         return 0;
869
870 err_workqueues:
871         i915_workqueues_cleanup(dev_priv);
872 err_engines:
873         i915_engines_cleanup(dev_priv);
874         return ret;
875 }
876
877 /**
878  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
879  * @dev_priv: device private
880  */
881 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
882 {
883         i915_perf_fini(dev_priv);
884         i915_gem_load_cleanup(dev_priv);
885         i915_workqueues_cleanup(dev_priv);
886         i915_engines_cleanup(dev_priv);
887 }
888
889 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
890 {
891         struct pci_dev *pdev = dev_priv->drm.pdev;
892         int mmio_bar;
893         int mmio_size;
894
895         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
896         /*
897          * Before gen4, the registers and the GTT are behind different BARs.
898          * However, from gen4 onwards, the registers and the GTT are shared
899          * in the same BAR, so we want to restrict this ioremap from
900          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
901          * the register BAR remains the same size for all the earlier
902          * generations up to Ironlake.
903          */
904         if (INTEL_GEN(dev_priv) < 5)
905                 mmio_size = 512 * 1024;
906         else
907                 mmio_size = 2 * 1024 * 1024;
908         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
909         if (dev_priv->regs == NULL) {
910                 DRM_ERROR("failed to map registers\n");
911
912                 return -EIO;
913         }
914
915         /* Try to make sure MCHBAR is enabled before poking at it */
916         intel_setup_mchbar(dev_priv);
917
918         return 0;
919 }
920
921 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
922 {
923         struct pci_dev *pdev = dev_priv->drm.pdev;
924
925         intel_teardown_mchbar(dev_priv);
926         pci_iounmap(pdev, dev_priv->regs);
927 }
928
929 /**
930  * i915_driver_init_mmio - setup device MMIO
931  * @dev_priv: device private
932  *
933  * Setup minimal device state necessary for MMIO accesses later in the
934  * initialization sequence. The setup here should avoid any other device-wide
935  * side effects or exposing the driver via kernel internal or user space
936  * interfaces.
937  */
938 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
939 {
940         int ret;
941
942         if (i915_inject_load_failure())
943                 return -ENODEV;
944
945         if (i915_get_bridge_dev(dev_priv))
946                 return -EIO;
947
948         ret = i915_mmio_setup(dev_priv);
949         if (ret < 0)
950                 goto put_bridge;
951
952         intel_uncore_init(dev_priv);
953         i915_gem_init_mmio(dev_priv);
954
955         return 0;
956
957 put_bridge:
958         pci_dev_put(dev_priv->bridge_dev);
959
960         return ret;
961 }
962
963 /**
964  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
965  * @dev_priv: device private
966  */
967 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
968 {
969         intel_uncore_fini(dev_priv);
970         i915_mmio_cleanup(dev_priv);
971         pci_dev_put(dev_priv->bridge_dev);
972 }
973
974 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
975 {
976         i915.enable_execlists =
977                 intel_sanitize_enable_execlists(dev_priv,
978                                                 i915.enable_execlists);
979
980         /*
981          * i915.enable_ppgtt is read-only, so do an early pass to validate the
982          * user's requested state against the hardware/driver capabilities.  We
983          * do this now so that we can print out any log messages once rather
984          * than every time we check intel_enable_ppgtt().
985          */
986         i915.enable_ppgtt =
987                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
988         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
989
990         i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
991         DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915.semaphores));
992
993         intel_uc_sanitize_options(dev_priv);
994 }
995
996 /**
997  * i915_driver_init_hw - setup state requiring device access
998  * @dev_priv: device private
999  *
1000  * Setup state that requires accessing the device, but doesn't require
1001  * exposing the driver via kernel internal or userspace interfaces.
1002  */
1003 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1004 {
1005         struct pci_dev *pdev = dev_priv->drm.pdev;
1006         int ret;
1007
1008         if (i915_inject_load_failure())
1009                 return -ENODEV;
1010
1011         intel_device_info_runtime_init(dev_priv);
1012
1013         intel_sanitize_options(dev_priv);
1014
1015         ret = i915_ggtt_probe_hw(dev_priv);
1016         if (ret)
1017                 return ret;
1018
1019         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1020          * otherwise the vga fbdev driver falls over. */
1021         ret = i915_kick_out_firmware_fb(dev_priv);
1022         if (ret) {
1023                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1024                 goto out_ggtt;
1025         }
1026
1027         ret = i915_kick_out_vgacon(dev_priv);
1028         if (ret) {
1029                 DRM_ERROR("failed to remove conflicting VGA console\n");
1030                 goto out_ggtt;
1031         }
1032
1033         ret = i915_ggtt_init_hw(dev_priv);
1034         if (ret)
1035                 return ret;
1036
1037         ret = i915_ggtt_enable_hw(dev_priv);
1038         if (ret) {
1039                 DRM_ERROR("failed to enable GGTT\n");
1040                 goto out_ggtt;
1041         }
1042
1043         pci_set_master(pdev);
1044
1045         /* overlay on gen2 is broken and can't address above 1G */
1046         if (IS_GEN2(dev_priv)) {
1047                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1048                 if (ret) {
1049                         DRM_ERROR("failed to set DMA mask\n");
1050
1051                         goto out_ggtt;
1052                 }
1053         }
1054
1055         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1056          * using 32bit addressing, overwriting memory if HWS is located
1057          * above 4GB.
1058          *
1059          * The documentation also mentions an issue with undefined
1060          * behaviour if any general state is accessed within a page above 4GB,
1061          * which also needs to be handled carefully.
1062          */
1063         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1064                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1065
1066                 if (ret) {
1067                         DRM_ERROR("failed to set DMA mask\n");
1068
1069                         goto out_ggtt;
1070                 }
1071         }
1072
1073         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1074                            PM_QOS_DEFAULT_VALUE);
1075
1076         intel_uncore_sanitize(dev_priv);
1077
1078         intel_opregion_setup(dev_priv);
1079
1080         i915_gem_load_init_fences(dev_priv);
1081
1082         /* On the 945G/GM, the chipset reports the MSI capability on the
1083          * integrated graphics even though the support isn't actually there
1084          * according to the published specs.  It doesn't appear to function
1085          * correctly in testing on 945G.
1086          * This may be a side effect of MSI having been made available for PEG
1087          * and the registers being closely associated.
1088          *
1089          * According to chipset errata, on the 965GM, MSI interrupts may
1090          * be lost or delayed, but we use them anyways to avoid
1091          * stuck interrupts on some machines.
1092          */
1093         if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
1094                 if (pci_enable_msi(pdev) < 0)
1095                         DRM_DEBUG_DRIVER("can't enable MSI");
1096         }
1097
1098         ret = intel_gvt_init(dev_priv);
1099         if (ret)
1100                 goto out_ggtt;
1101
1102         return 0;
1103
1104 out_ggtt:
1105         i915_ggtt_cleanup_hw(dev_priv);
1106
1107         return ret;
1108 }
1109
1110 /**
1111  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1112  * @dev_priv: device private
1113  */
1114 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1115 {
1116         struct pci_dev *pdev = dev_priv->drm.pdev;
1117
1118         if (pdev->msi_enabled)
1119                 pci_disable_msi(pdev);
1120
1121         pm_qos_remove_request(&dev_priv->pm_qos);
1122         i915_ggtt_cleanup_hw(dev_priv);
1123 }
1124
1125 /**
1126  * i915_driver_register - register the driver with the rest of the system
1127  * @dev_priv: device private
1128  *
1129  * Perform any steps necessary to make the driver available via kernel
1130  * internal or userspace interfaces.
1131  */
1132 static void i915_driver_register(struct drm_i915_private *dev_priv)
1133 {
1134         struct drm_device *dev = &dev_priv->drm;
1135
1136         i915_gem_shrinker_init(dev_priv);
1137
1138         /*
1139          * Notify a valid surface after modesetting,
1140          * when running inside a VM.
1141          */
1142         if (intel_vgpu_active(dev_priv))
1143                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1144
1145         /* Reveal our presence to userspace */
1146         if (drm_dev_register(dev, 0) == 0) {
1147                 i915_debugfs_register(dev_priv);
1148                 i915_guc_log_register(dev_priv);
1149                 i915_setup_sysfs(dev_priv);
1150
1151                 /* Depends on sysfs having been initialized */
1152                 i915_perf_register(dev_priv);
1153         } else
1154                 DRM_ERROR("Failed to register driver for userspace access!\n");
1155
1156         if (INTEL_INFO(dev_priv)->num_pipes) {
1157                 /* Must be done after probing outputs */
1158                 intel_opregion_register(dev_priv);
1159                 acpi_video_register();
1160         }
1161
1162         if (IS_GEN5(dev_priv))
1163                 intel_gpu_ips_init(dev_priv);
1164
1165         intel_audio_init(dev_priv);
1166
1167         /*
1168          * Some ports require correctly set-up hpd registers for detection to
1169          * work properly (leading to ghost connected connector status), e.g. VGA
1170          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1171          * irqs are fully enabled. We do it last so that the async config
1172          * cannot run before the connectors are registered.
1173          */
1174         intel_fbdev_initial_config_async(dev);
1175 }
1176
1177 /**
1178  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1179  * @dev_priv: device private
1180  */
1181 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1182 {
1183         intel_audio_deinit(dev_priv);
1184
1185         intel_gpu_ips_teardown();
1186         acpi_video_unregister();
1187         intel_opregion_unregister(dev_priv);
1188
1189         i915_perf_unregister(dev_priv);
1190
1191         i915_teardown_sysfs(dev_priv);
1192         i915_guc_log_unregister(dev_priv);
1193         drm_dev_unregister(&dev_priv->drm);
1194
1195         i915_gem_shrinker_cleanup(dev_priv);
1196 }
1197
1198 /**
1199  * i915_driver_load - setup chip and create an initial config
1200  * @pdev: PCI device
1201  * @ent: matching PCI ID entry
1202  *
1203  * The driver load routine has to do several things:
1204  *   - drive output discovery via intel_modeset_init()
1205  *   - initialize the memory manager
1206  *   - allocate initial config memory
1207  *   - setup the DRM framebuffer with the allocated memory
1208  */
1209 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1210 {
1211         const struct intel_device_info *match_info =
1212                 (struct intel_device_info *)ent->driver_data;
1213         struct drm_i915_private *dev_priv;
1214         int ret;
1215
1216         /* Enable nuclear pageflip on ILK+, except vlv/chv */
1217         if (!i915.nuclear_pageflip &&
1218             (match_info->gen < 5 || match_info->has_gmch_display))
1219                 driver.driver_features &= ~DRIVER_ATOMIC;
1220
1221         ret = -ENOMEM;
1222         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1223         if (dev_priv)
1224                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1225         if (ret) {
1226                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1227                 goto out_free;
1228         }
1229
1230         dev_priv->drm.pdev = pdev;
1231         dev_priv->drm.dev_private = dev_priv;
1232
1233         ret = pci_enable_device(pdev);
1234         if (ret)
1235                 goto out_fini;
1236
1237         pci_set_drvdata(pdev, &dev_priv->drm);
1238
1239         ret = i915_driver_init_early(dev_priv, ent);
1240         if (ret < 0)
1241                 goto out_pci_disable;
1242
1243         intel_runtime_pm_get(dev_priv);
1244
1245         ret = i915_driver_init_mmio(dev_priv);
1246         if (ret < 0)
1247                 goto out_runtime_pm_put;
1248
1249         ret = i915_driver_init_hw(dev_priv);
1250         if (ret < 0)
1251                 goto out_cleanup_mmio;
1252
1253         /*
1254          * TODO: move the vblank init and parts of modeset init steps into one
1255          * of the i915_driver_init_/i915_driver_register functions according
1256          * to the role/effect of the given init step.
1257          */
1258         if (INTEL_INFO(dev_priv)->num_pipes) {
1259                 ret = drm_vblank_init(&dev_priv->drm,
1260                                       INTEL_INFO(dev_priv)->num_pipes);
1261                 if (ret)
1262                         goto out_cleanup_hw;
1263         }
1264
1265         ret = i915_load_modeset_init(&dev_priv->drm);
1266         if (ret < 0)
1267                 goto out_cleanup_vblank;
1268
1269         i915_driver_register(dev_priv);
1270
1271         intel_runtime_pm_enable(dev_priv);
1272
1273         dev_priv->ipc_enabled = false;
1274
1275         /* Everything is in place, we can now relax! */
1276         DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
1277                  driver.name, driver.major, driver.minor, driver.patchlevel,
1278                  driver.date, pci_name(pdev), dev_priv->drm.primary->index);
1279         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1280                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1281         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1282                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1283
1284         intel_runtime_pm_put(dev_priv);
1285
1286         return 0;
1287
1288 out_cleanup_vblank:
1289         drm_vblank_cleanup(&dev_priv->drm);
1290 out_cleanup_hw:
1291         i915_driver_cleanup_hw(dev_priv);
1292 out_cleanup_mmio:
1293         i915_driver_cleanup_mmio(dev_priv);
1294 out_runtime_pm_put:
1295         intel_runtime_pm_put(dev_priv);
1296         i915_driver_cleanup_early(dev_priv);
1297 out_pci_disable:
1298         pci_disable_device(pdev);
1299 out_fini:
1300         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1301         drm_dev_fini(&dev_priv->drm);
1302 out_free:
1303         kfree(dev_priv);
1304         return ret;
1305 }
1306
1307 void i915_driver_unload(struct drm_device *dev)
1308 {
1309         struct drm_i915_private *dev_priv = to_i915(dev);
1310         struct pci_dev *pdev = dev_priv->drm.pdev;
1311
1312         intel_fbdev_fini(dev);
1313
1314         if (i915_gem_suspend(dev_priv))
1315                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1316
1317         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1318
1319         drm_atomic_helper_shutdown(dev);
1320
1321         intel_gvt_cleanup(dev_priv);
1322
1323         i915_driver_unregister(dev_priv);
1324
1325         drm_vblank_cleanup(dev);
1326
1327         intel_modeset_cleanup(dev);
1328
1329         /*
1330          * free the memory space allocated for the child device
1331          * config parsed from VBT
1332          */
1333         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1334                 kfree(dev_priv->vbt.child_dev);
1335                 dev_priv->vbt.child_dev = NULL;
1336                 dev_priv->vbt.child_dev_num = 0;
1337         }
1338         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1339         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1340         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1341         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1342
1343         vga_switcheroo_unregister_client(pdev);
1344         vga_client_register(pdev, NULL, NULL, NULL);
1345
1346         intel_csr_ucode_fini(dev_priv);
1347
1348         /* Free error state after interrupts are fully disabled. */
1349         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1350         i915_reset_error_state(dev_priv);
1351
1352         /* Flush any outstanding unpin_work. */
1353         drain_workqueue(dev_priv->wq);
1354
1355         i915_gem_fini(dev_priv);
1356         intel_uc_fini_fw(dev_priv);
1357         intel_fbc_cleanup_cfb(dev_priv);
1358
1359         intel_power_domains_fini(dev_priv);
1360
1361         i915_driver_cleanup_hw(dev_priv);
1362         i915_driver_cleanup_mmio(dev_priv);
1363
1364         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1365 }
1366
1367 static void i915_driver_release(struct drm_device *dev)
1368 {
1369         struct drm_i915_private *dev_priv = to_i915(dev);
1370
1371         i915_driver_cleanup_early(dev_priv);
1372         drm_dev_fini(&dev_priv->drm);
1373
1374         kfree(dev_priv);
1375 }
1376
1377 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1378 {
1379         int ret;
1380
1381         ret = i915_gem_open(dev, file);
1382         if (ret)
1383                 return ret;
1384
1385         return 0;
1386 }
1387
1388 /**
1389  * i915_driver_lastclose - clean up after all DRM clients have exited
1390  * @dev: DRM device
1391  *
1392  * Take care of cleaning up after all DRM clients have exited.  In the
1393  * mode setting case, we want to restore the kernel's initial mode (just
1394  * in case the last client left us in a bad state).
1395  *
1396  * Additionally, in the non-mode setting case, we'll tear down the GTT
1397  * and DMA structures, since the kernel won't be using them, and clea
1398  * up any GEM state.
1399  */
1400 static void i915_driver_lastclose(struct drm_device *dev)
1401 {
1402         intel_fbdev_restore_mode(dev);
1403         vga_switcheroo_process_delayed_switch();
1404 }
1405
1406 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1407 {
1408         struct drm_i915_file_private *file_priv = file->driver_priv;
1409
1410         mutex_lock(&dev->struct_mutex);
1411         i915_gem_context_close(dev, file);
1412         i915_gem_release(dev, file);
1413         mutex_unlock(&dev->struct_mutex);
1414
1415         kfree(file_priv);
1416 }
1417
1418 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1419 {
1420         struct drm_device *dev = &dev_priv->drm;
1421         struct intel_encoder *encoder;
1422
1423         drm_modeset_lock_all(dev);
1424         for_each_intel_encoder(dev, encoder)
1425                 if (encoder->suspend)
1426                         encoder->suspend(encoder);
1427         drm_modeset_unlock_all(dev);
1428 }
1429
1430 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1431                               bool rpm_resume);
1432 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1433
1434 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1435 {
1436 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1437         if (acpi_target_system_state() < ACPI_STATE_S3)
1438                 return true;
1439 #endif
1440         return false;
1441 }
1442
1443 static int i915_drm_suspend(struct drm_device *dev)
1444 {
1445         struct drm_i915_private *dev_priv = to_i915(dev);
1446         struct pci_dev *pdev = dev_priv->drm.pdev;
1447         pci_power_t opregion_target_state;
1448         int error;
1449
1450         /* ignore lid events during suspend */
1451         mutex_lock(&dev_priv->modeset_restore_lock);
1452         dev_priv->modeset_restore = MODESET_SUSPENDED;
1453         mutex_unlock(&dev_priv->modeset_restore_lock);
1454
1455         disable_rpm_wakeref_asserts(dev_priv);
1456
1457         /* We do a lot of poking in a lot of registers, make sure they work
1458          * properly. */
1459         intel_display_set_init_power(dev_priv, true);
1460
1461         drm_kms_helper_poll_disable(dev);
1462
1463         pci_save_state(pdev);
1464
1465         error = i915_gem_suspend(dev_priv);
1466         if (error) {
1467                 dev_err(&pdev->dev,
1468                         "GEM idle failed, resume might fail\n");
1469                 goto out;
1470         }
1471
1472         intel_display_suspend(dev);
1473
1474         intel_dp_mst_suspend(dev);
1475
1476         intel_runtime_pm_disable_interrupts(dev_priv);
1477         intel_hpd_cancel_work(dev_priv);
1478
1479         intel_suspend_encoders(dev_priv);
1480
1481         intel_suspend_hw(dev_priv);
1482
1483         i915_gem_suspend_gtt_mappings(dev_priv);
1484
1485         i915_save_state(dev_priv);
1486
1487         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1488         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1489
1490         intel_uncore_suspend(dev_priv);
1491         intel_opregion_unregister(dev_priv);
1492
1493         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1494
1495         dev_priv->suspend_count++;
1496
1497         intel_csr_ucode_suspend(dev_priv);
1498
1499 out:
1500         enable_rpm_wakeref_asserts(dev_priv);
1501
1502         return error;
1503 }
1504
1505 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1506 {
1507         struct drm_i915_private *dev_priv = to_i915(dev);
1508         struct pci_dev *pdev = dev_priv->drm.pdev;
1509         bool fw_csr;
1510         int ret;
1511
1512         disable_rpm_wakeref_asserts(dev_priv);
1513
1514         intel_display_set_init_power(dev_priv, false);
1515
1516         fw_csr = !IS_GEN9_LP(dev_priv) &&
1517                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1518         /*
1519          * In case of firmware assisted context save/restore don't manually
1520          * deinit the power domains. This also means the CSR/DMC firmware will
1521          * stay active, it will power down any HW resources as required and
1522          * also enable deeper system power states that would be blocked if the
1523          * firmware was inactive.
1524          */
1525         if (!fw_csr)
1526                 intel_power_domains_suspend(dev_priv);
1527
1528         ret = 0;
1529         if (IS_GEN9_LP(dev_priv))
1530                 bxt_enable_dc9(dev_priv);
1531         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1532                 hsw_enable_pc8(dev_priv);
1533         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1534                 ret = vlv_suspend_complete(dev_priv);
1535
1536         if (ret) {
1537                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1538                 if (!fw_csr)
1539                         intel_power_domains_init_hw(dev_priv, true);
1540
1541                 goto out;
1542         }
1543
1544         pci_disable_device(pdev);
1545         /*
1546          * During hibernation on some platforms the BIOS may try to access
1547          * the device even though it's already in D3 and hang the machine. So
1548          * leave the device in D0 on those platforms and hope the BIOS will
1549          * power down the device properly. The issue was seen on multiple old
1550          * GENs with different BIOS vendors, so having an explicit blacklist
1551          * is inpractical; apply the workaround on everything pre GEN6. The
1552          * platforms where the issue was seen:
1553          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1554          * Fujitsu FSC S7110
1555          * Acer Aspire 1830T
1556          */
1557         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1558                 pci_set_power_state(pdev, PCI_D3hot);
1559
1560         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1561
1562 out:
1563         enable_rpm_wakeref_asserts(dev_priv);
1564
1565         return ret;
1566 }
1567
1568 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1569 {
1570         int error;
1571
1572         if (!dev) {
1573                 DRM_ERROR("dev: %p\n", dev);
1574                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1575                 return -ENODEV;
1576         }
1577
1578         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1579                          state.event != PM_EVENT_FREEZE))
1580                 return -EINVAL;
1581
1582         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1583                 return 0;
1584
1585         error = i915_drm_suspend(dev);
1586         if (error)
1587                 return error;
1588
1589         return i915_drm_suspend_late(dev, false);
1590 }
1591
1592 static int i915_drm_resume(struct drm_device *dev)
1593 {
1594         struct drm_i915_private *dev_priv = to_i915(dev);
1595         int ret;
1596
1597         disable_rpm_wakeref_asserts(dev_priv);
1598         intel_sanitize_gt_powersave(dev_priv);
1599
1600         ret = i915_ggtt_enable_hw(dev_priv);
1601         if (ret)
1602                 DRM_ERROR("failed to re-enable GGTT\n");
1603
1604         intel_csr_ucode_resume(dev_priv);
1605
1606         i915_gem_resume(dev_priv);
1607
1608         i915_restore_state(dev_priv);
1609         intel_pps_unlock_regs_wa(dev_priv);
1610         intel_opregion_setup(dev_priv);
1611
1612         intel_init_pch_refclk(dev_priv);
1613
1614         /*
1615          * Interrupts have to be enabled before any batches are run. If not the
1616          * GPU will hang. i915_gem_init_hw() will initiate batches to
1617          * update/restore the context.
1618          *
1619          * drm_mode_config_reset() needs AUX interrupts.
1620          *
1621          * Modeset enabling in intel_modeset_init_hw() also needs working
1622          * interrupts.
1623          */
1624         intel_runtime_pm_enable_interrupts(dev_priv);
1625
1626         drm_mode_config_reset(dev);
1627
1628         mutex_lock(&dev->struct_mutex);
1629         if (i915_gem_init_hw(dev_priv)) {
1630                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1631                 i915_gem_set_wedged(dev_priv);
1632         }
1633         mutex_unlock(&dev->struct_mutex);
1634
1635         intel_guc_resume(dev_priv);
1636
1637         intel_modeset_init_hw(dev);
1638
1639         spin_lock_irq(&dev_priv->irq_lock);
1640         if (dev_priv->display.hpd_irq_setup)
1641                 dev_priv->display.hpd_irq_setup(dev_priv);
1642         spin_unlock_irq(&dev_priv->irq_lock);
1643
1644         intel_dp_mst_resume(dev);
1645
1646         intel_display_resume(dev);
1647
1648         drm_kms_helper_poll_enable(dev);
1649
1650         /*
1651          * ... but also need to make sure that hotplug processing
1652          * doesn't cause havoc. Like in the driver load code we don't
1653          * bother with the tiny race here where we might loose hotplug
1654          * notifications.
1655          * */
1656         intel_hpd_init(dev_priv);
1657
1658         intel_opregion_register(dev_priv);
1659
1660         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1661
1662         mutex_lock(&dev_priv->modeset_restore_lock);
1663         dev_priv->modeset_restore = MODESET_DONE;
1664         mutex_unlock(&dev_priv->modeset_restore_lock);
1665
1666         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1667
1668         intel_autoenable_gt_powersave(dev_priv);
1669
1670         enable_rpm_wakeref_asserts(dev_priv);
1671
1672         return 0;
1673 }
1674
1675 static int i915_drm_resume_early(struct drm_device *dev)
1676 {
1677         struct drm_i915_private *dev_priv = to_i915(dev);
1678         struct pci_dev *pdev = dev_priv->drm.pdev;
1679         int ret;
1680
1681         /*
1682          * We have a resume ordering issue with the snd-hda driver also
1683          * requiring our device to be power up. Due to the lack of a
1684          * parent/child relationship we currently solve this with an early
1685          * resume hook.
1686          *
1687          * FIXME: This should be solved with a special hdmi sink device or
1688          * similar so that power domains can be employed.
1689          */
1690
1691         /*
1692          * Note that we need to set the power state explicitly, since we
1693          * powered off the device during freeze and the PCI core won't power
1694          * it back up for us during thaw. Powering off the device during
1695          * freeze is not a hard requirement though, and during the
1696          * suspend/resume phases the PCI core makes sure we get here with the
1697          * device powered on. So in case we change our freeze logic and keep
1698          * the device powered we can also remove the following set power state
1699          * call.
1700          */
1701         ret = pci_set_power_state(pdev, PCI_D0);
1702         if (ret) {
1703                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1704                 goto out;
1705         }
1706
1707         /*
1708          * Note that pci_enable_device() first enables any parent bridge
1709          * device and only then sets the power state for this device. The
1710          * bridge enabling is a nop though, since bridge devices are resumed
1711          * first. The order of enabling power and enabling the device is
1712          * imposed by the PCI core as described above, so here we preserve the
1713          * same order for the freeze/thaw phases.
1714          *
1715          * TODO: eventually we should remove pci_disable_device() /
1716          * pci_enable_enable_device() from suspend/resume. Due to how they
1717          * depend on the device enable refcount we can't anyway depend on them
1718          * disabling/enabling the device.
1719          */
1720         if (pci_enable_device(pdev)) {
1721                 ret = -EIO;
1722                 goto out;
1723         }
1724
1725         pci_set_master(pdev);
1726
1727         disable_rpm_wakeref_asserts(dev_priv);
1728
1729         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1730                 ret = vlv_resume_prepare(dev_priv, false);
1731         if (ret)
1732                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1733                           ret);
1734
1735         intel_uncore_resume_early(dev_priv);
1736
1737         if (IS_GEN9_LP(dev_priv)) {
1738                 if (!dev_priv->suspended_to_idle)
1739                         gen9_sanitize_dc_state(dev_priv);
1740                 bxt_disable_dc9(dev_priv);
1741         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1742                 hsw_disable_pc8(dev_priv);
1743         }
1744
1745         intel_uncore_sanitize(dev_priv);
1746
1747         if (IS_GEN9_LP(dev_priv) ||
1748             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1749                 intel_power_domains_init_hw(dev_priv, true);
1750
1751         i915_gem_sanitize(dev_priv);
1752
1753         enable_rpm_wakeref_asserts(dev_priv);
1754
1755 out:
1756         dev_priv->suspended_to_idle = false;
1757
1758         return ret;
1759 }
1760
1761 static int i915_resume_switcheroo(struct drm_device *dev)
1762 {
1763         int ret;
1764
1765         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1766                 return 0;
1767
1768         ret = i915_drm_resume_early(dev);
1769         if (ret)
1770                 return ret;
1771
1772         return i915_drm_resume(dev);
1773 }
1774
1775 /**
1776  * i915_reset - reset chip after a hang
1777  * @dev_priv: device private to reset
1778  *
1779  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1780  * on failure.
1781  *
1782  * Caller must hold the struct_mutex.
1783  *
1784  * Procedure is fairly simple:
1785  *   - reset the chip using the reset reg
1786  *   - re-init context state
1787  *   - re-init hardware status page
1788  *   - re-init ring buffer
1789  *   - re-init interrupt state
1790  *   - re-init display
1791  */
1792 void i915_reset(struct drm_i915_private *dev_priv)
1793 {
1794         struct i915_gpu_error *error = &dev_priv->gpu_error;
1795         int ret;
1796
1797         lockdep_assert_held(&dev_priv->drm.struct_mutex);
1798         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1799
1800         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1801                 return;
1802
1803         /* Clear any previous failed attempts at recovery. Time to try again. */
1804         if (!i915_gem_unset_wedged(dev_priv))
1805                 goto wakeup;
1806
1807         error->reset_count++;
1808
1809         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1810         disable_irq(dev_priv->drm.irq);
1811         ret = i915_gem_reset_prepare(dev_priv);
1812         if (ret) {
1813                 DRM_ERROR("GPU recovery failed\n");
1814                 intel_gpu_reset(dev_priv, ALL_ENGINES);
1815                 goto error;
1816         }
1817
1818         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1819         if (ret) {
1820                 if (ret != -ENODEV)
1821                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1822                 else
1823                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1824                 goto error;
1825         }
1826
1827         i915_gem_reset(dev_priv);
1828         intel_overlay_reset(dev_priv);
1829
1830         /* Ok, now get things going again... */
1831
1832         /*
1833          * Everything depends on having the GTT running, so we need to start
1834          * there.  Fortunately we don't need to do this unless we reset the
1835          * chip at a PCI level.
1836          *
1837          * Next we need to restore the context, but we don't use those
1838          * yet either...
1839          *
1840          * Ring buffer needs to be re-initialized in the KMS case, or if X
1841          * was running at the time of the reset (i.e. we weren't VT
1842          * switched away).
1843          */
1844         ret = i915_gem_init_hw(dev_priv);
1845         if (ret) {
1846                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1847                 goto error;
1848         }
1849
1850         i915_queue_hangcheck(dev_priv);
1851
1852 finish:
1853         i915_gem_reset_finish(dev_priv);
1854         enable_irq(dev_priv->drm.irq);
1855
1856 wakeup:
1857         clear_bit(I915_RESET_HANDOFF, &error->flags);
1858         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1859         return;
1860
1861 error:
1862         i915_gem_set_wedged(dev_priv);
1863         goto finish;
1864 }
1865
1866 static int i915_pm_suspend(struct device *kdev)
1867 {
1868         struct pci_dev *pdev = to_pci_dev(kdev);
1869         struct drm_device *dev = pci_get_drvdata(pdev);
1870
1871         if (!dev) {
1872                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1873                 return -ENODEV;
1874         }
1875
1876         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1877                 return 0;
1878
1879         return i915_drm_suspend(dev);
1880 }
1881
1882 static int i915_pm_suspend_late(struct device *kdev)
1883 {
1884         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1885
1886         /*
1887          * We have a suspend ordering issue with the snd-hda driver also
1888          * requiring our device to be power up. Due to the lack of a
1889          * parent/child relationship we currently solve this with an late
1890          * suspend hook.
1891          *
1892          * FIXME: This should be solved with a special hdmi sink device or
1893          * similar so that power domains can be employed.
1894          */
1895         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1896                 return 0;
1897
1898         return i915_drm_suspend_late(dev, false);
1899 }
1900
1901 static int i915_pm_poweroff_late(struct device *kdev)
1902 {
1903         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1904
1905         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1906                 return 0;
1907
1908         return i915_drm_suspend_late(dev, true);
1909 }
1910
1911 static int i915_pm_resume_early(struct device *kdev)
1912 {
1913         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1914
1915         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1916                 return 0;
1917
1918         return i915_drm_resume_early(dev);
1919 }
1920
1921 static int i915_pm_resume(struct device *kdev)
1922 {
1923         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
1924
1925         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1926                 return 0;
1927
1928         return i915_drm_resume(dev);
1929 }
1930
1931 /* freeze: before creating the hibernation_image */
1932 static int i915_pm_freeze(struct device *kdev)
1933 {
1934         int ret;
1935
1936         ret = i915_pm_suspend(kdev);
1937         if (ret)
1938                 return ret;
1939
1940         ret = i915_gem_freeze(kdev_to_i915(kdev));
1941         if (ret)
1942                 return ret;
1943
1944         return 0;
1945 }
1946
1947 static int i915_pm_freeze_late(struct device *kdev)
1948 {
1949         int ret;
1950
1951         ret = i915_pm_suspend_late(kdev);
1952         if (ret)
1953                 return ret;
1954
1955         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
1956         if (ret)
1957                 return ret;
1958
1959         return 0;
1960 }
1961
1962 /* thaw: called after creating the hibernation image, but before turning off. */
1963 static int i915_pm_thaw_early(struct device *kdev)
1964 {
1965         return i915_pm_resume_early(kdev);
1966 }
1967
1968 static int i915_pm_thaw(struct device *kdev)
1969 {
1970         return i915_pm_resume(kdev);
1971 }
1972
1973 /* restore: called after loading the hibernation image. */
1974 static int i915_pm_restore_early(struct device *kdev)
1975 {
1976         return i915_pm_resume_early(kdev);
1977 }
1978
1979 static int i915_pm_restore(struct device *kdev)
1980 {
1981         return i915_pm_resume(kdev);
1982 }
1983
1984 /*
1985  * Save all Gunit registers that may be lost after a D3 and a subsequent
1986  * S0i[R123] transition. The list of registers needing a save/restore is
1987  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1988  * registers in the following way:
1989  * - Driver: saved/restored by the driver
1990  * - Punit : saved/restored by the Punit firmware
1991  * - No, w/o marking: no need to save/restore, since the register is R/O or
1992  *                    used internally by the HW in a way that doesn't depend
1993  *                    keeping the content across a suspend/resume.
1994  * - Debug : used for debugging
1995  *
1996  * We save/restore all registers marked with 'Driver', with the following
1997  * exceptions:
1998  * - Registers out of use, including also registers marked with 'Debug'.
1999  *   These have no effect on the driver's operation, so we don't save/restore
2000  *   them to reduce the overhead.
2001  * - Registers that are fully setup by an initialization function called from
2002  *   the resume path. For example many clock gating and RPS/RC6 registers.
2003  * - Registers that provide the right functionality with their reset defaults.
2004  *
2005  * TODO: Except for registers that based on the above 3 criteria can be safely
2006  * ignored, we save/restore all others, practically treating the HW context as
2007  * a black-box for the driver. Further investigation is needed to reduce the
2008  * saved/restored registers even further, by following the same 3 criteria.
2009  */
2010 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2011 {
2012         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2013         int i;
2014
2015         /* GAM 0x4000-0x4770 */
2016         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2017         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2018         s->arb_mode             = I915_READ(ARB_MODE);
2019         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2020         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2021
2022         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2023                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2024
2025         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2026         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2027
2028         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2029         s->ecochk               = I915_READ(GAM_ECOCHK);
2030         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2031         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2032
2033         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2034
2035         /* MBC 0x9024-0x91D0, 0x8500 */
2036         s->g3dctl               = I915_READ(VLV_G3DCTL);
2037         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2038         s->mbctl                = I915_READ(GEN6_MBCTL);
2039
2040         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2041         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2042         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2043         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2044         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2045         s->rstctl               = I915_READ(GEN6_RSTCTL);
2046         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2047
2048         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2049         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2050         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2051         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2052         s->ecobus               = I915_READ(ECOBUS);
2053         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2054         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2055         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2056         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2057         s->rcedata              = I915_READ(VLV_RCEDATA);
2058         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2059
2060         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2061         s->gt_imr               = I915_READ(GTIMR);
2062         s->gt_ier               = I915_READ(GTIER);
2063         s->pm_imr               = I915_READ(GEN6_PMIMR);
2064         s->pm_ier               = I915_READ(GEN6_PMIER);
2065
2066         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2067                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2068
2069         /* GT SA CZ domain, 0x100000-0x138124 */
2070         s->tilectl              = I915_READ(TILECTL);
2071         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2072         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2073         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2074         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2075
2076         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2077         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2078         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2079         s->pcbr                 = I915_READ(VLV_PCBR);
2080         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2081
2082         /*
2083          * Not saving any of:
2084          * DFT,         0x9800-0x9EC0
2085          * SARB,        0xB000-0xB1FC
2086          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2087          * PCI CFG
2088          */
2089 }
2090
2091 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2092 {
2093         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2094         u32 val;
2095         int i;
2096
2097         /* GAM 0x4000-0x4770 */
2098         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2099         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2100         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2101         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2102         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2103
2104         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2105                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2106
2107         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2108         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2109
2110         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2111         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2112         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2113         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2114
2115         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2116
2117         /* MBC 0x9024-0x91D0, 0x8500 */
2118         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2119         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2120         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2121
2122         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2123         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2124         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2125         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2126         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2127         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2128         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2129
2130         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2131         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2132         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2133         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2134         I915_WRITE(ECOBUS,              s->ecobus);
2135         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2136         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2137         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2138         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2139         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2140         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2141
2142         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2143         I915_WRITE(GTIMR,               s->gt_imr);
2144         I915_WRITE(GTIER,               s->gt_ier);
2145         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2146         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2147
2148         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2149                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2150
2151         /* GT SA CZ domain, 0x100000-0x138124 */
2152         I915_WRITE(TILECTL,                     s->tilectl);
2153         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2154         /*
2155          * Preserve the GT allow wake and GFX force clock bit, they are not
2156          * be restored, as they are used to control the s0ix suspend/resume
2157          * sequence by the caller.
2158          */
2159         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2160         val &= VLV_GTLC_ALLOWWAKEREQ;
2161         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2162         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2163
2164         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2165         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2166         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2167         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2168
2169         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2170
2171         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2172         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2173         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2174         I915_WRITE(VLV_PCBR,                    s->pcbr);
2175         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2176 }
2177
2178 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2179                                   u32 mask, u32 val)
2180 {
2181         /* The HW does not like us polling for PW_STATUS frequently, so
2182          * use the sleeping loop rather than risk the busy spin within
2183          * intel_wait_for_register().
2184          *
2185          * Transitioning between RC6 states should be at most 2ms (see
2186          * valleyview_enable_rps) so use a 3ms timeout.
2187          */
2188         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2189                         3);
2190 }
2191
2192 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2193 {
2194         u32 val;
2195         int err;
2196
2197         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2198         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2199         if (force_on)
2200                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2201         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2202
2203         if (!force_on)
2204                 return 0;
2205
2206         err = intel_wait_for_register(dev_priv,
2207                                       VLV_GTLC_SURVIVABILITY_REG,
2208                                       VLV_GFX_CLK_STATUS_BIT,
2209                                       VLV_GFX_CLK_STATUS_BIT,
2210                                       20);
2211         if (err)
2212                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2213                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2214
2215         return err;
2216 }
2217
2218 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2219 {
2220         u32 mask;
2221         u32 val;
2222         int err;
2223
2224         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2225         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2226         if (allow)
2227                 val |= VLV_GTLC_ALLOWWAKEREQ;
2228         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2229         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2230
2231         mask = VLV_GTLC_ALLOWWAKEACK;
2232         val = allow ? mask : 0;
2233
2234         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2235         if (err)
2236                 DRM_ERROR("timeout disabling GT waking\n");
2237
2238         return err;
2239 }
2240
2241 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2242                                   bool wait_for_on)
2243 {
2244         u32 mask;
2245         u32 val;
2246
2247         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2248         val = wait_for_on ? mask : 0;
2249
2250         /*
2251          * RC6 transitioning can be delayed up to 2 msec (see
2252          * valleyview_enable_rps), use 3 msec for safety.
2253          */
2254         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2255                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2256                           onoff(wait_for_on));
2257 }
2258
2259 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2260 {
2261         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2262                 return;
2263
2264         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2265         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2266 }
2267
2268 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2269 {
2270         u32 mask;
2271         int err;
2272
2273         /*
2274          * Bspec defines the following GT well on flags as debug only, so
2275          * don't treat them as hard failures.
2276          */
2277         vlv_wait_for_gt_wells(dev_priv, false);
2278
2279         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2280         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2281
2282         vlv_check_no_gt_access(dev_priv);
2283
2284         err = vlv_force_gfx_clock(dev_priv, true);
2285         if (err)
2286                 goto err1;
2287
2288         err = vlv_allow_gt_wake(dev_priv, false);
2289         if (err)
2290                 goto err2;
2291
2292         if (!IS_CHERRYVIEW(dev_priv))
2293                 vlv_save_gunit_s0ix_state(dev_priv);
2294
2295         err = vlv_force_gfx_clock(dev_priv, false);
2296         if (err)
2297                 goto err2;
2298
2299         return 0;
2300
2301 err2:
2302         /* For safety always re-enable waking and disable gfx clock forcing */
2303         vlv_allow_gt_wake(dev_priv, true);
2304 err1:
2305         vlv_force_gfx_clock(dev_priv, false);
2306
2307         return err;
2308 }
2309
2310 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2311                                 bool rpm_resume)
2312 {
2313         int err;
2314         int ret;
2315
2316         /*
2317          * If any of the steps fail just try to continue, that's the best we
2318          * can do at this point. Return the first error code (which will also
2319          * leave RPM permanently disabled).
2320          */
2321         ret = vlv_force_gfx_clock(dev_priv, true);
2322
2323         if (!IS_CHERRYVIEW(dev_priv))
2324                 vlv_restore_gunit_s0ix_state(dev_priv);
2325
2326         err = vlv_allow_gt_wake(dev_priv, true);
2327         if (!ret)
2328                 ret = err;
2329
2330         err = vlv_force_gfx_clock(dev_priv, false);
2331         if (!ret)
2332                 ret = err;
2333
2334         vlv_check_no_gt_access(dev_priv);
2335
2336         if (rpm_resume)
2337                 intel_init_clock_gating(dev_priv);
2338
2339         return ret;
2340 }
2341
2342 static int intel_runtime_suspend(struct device *kdev)
2343 {
2344         struct pci_dev *pdev = to_pci_dev(kdev);
2345         struct drm_device *dev = pci_get_drvdata(pdev);
2346         struct drm_i915_private *dev_priv = to_i915(dev);
2347         int ret;
2348
2349         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2350                 return -ENODEV;
2351
2352         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2353                 return -ENODEV;
2354
2355         DRM_DEBUG_KMS("Suspending device\n");
2356
2357         disable_rpm_wakeref_asserts(dev_priv);
2358
2359         /*
2360          * We are safe here against re-faults, since the fault handler takes
2361          * an RPM reference.
2362          */
2363         i915_gem_runtime_suspend(dev_priv);
2364
2365         intel_guc_suspend(dev_priv);
2366
2367         intel_runtime_pm_disable_interrupts(dev_priv);
2368
2369         ret = 0;
2370         if (IS_GEN9_LP(dev_priv)) {
2371                 bxt_display_core_uninit(dev_priv);
2372                 bxt_enable_dc9(dev_priv);
2373         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2374                 hsw_enable_pc8(dev_priv);
2375         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2376                 ret = vlv_suspend_complete(dev_priv);
2377         }
2378
2379         if (ret) {
2380                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2381                 intel_runtime_pm_enable_interrupts(dev_priv);
2382
2383                 enable_rpm_wakeref_asserts(dev_priv);
2384
2385                 return ret;
2386         }
2387
2388         intel_uncore_suspend(dev_priv);
2389
2390         enable_rpm_wakeref_asserts(dev_priv);
2391         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2392
2393         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2394                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2395
2396         dev_priv->pm.suspended = true;
2397
2398         /*
2399          * FIXME: We really should find a document that references the arguments
2400          * used below!
2401          */
2402         if (IS_BROADWELL(dev_priv)) {
2403                 /*
2404                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2405                  * being detected, and the call we do at intel_runtime_resume()
2406                  * won't be able to restore them. Since PCI_D3hot matches the
2407                  * actual specification and appears to be working, use it.
2408                  */
2409                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2410         } else {
2411                 /*
2412                  * current versions of firmware which depend on this opregion
2413                  * notification have repurposed the D1 definition to mean
2414                  * "runtime suspended" vs. what you would normally expect (D3)
2415                  * to distinguish it from notifications that might be sent via
2416                  * the suspend path.
2417                  */
2418                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2419         }
2420
2421         assert_forcewakes_inactive(dev_priv);
2422
2423         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2424                 intel_hpd_poll_init(dev_priv);
2425
2426         DRM_DEBUG_KMS("Device suspended\n");
2427         return 0;
2428 }
2429
2430 static int intel_runtime_resume(struct device *kdev)
2431 {
2432         struct pci_dev *pdev = to_pci_dev(kdev);
2433         struct drm_device *dev = pci_get_drvdata(pdev);
2434         struct drm_i915_private *dev_priv = to_i915(dev);
2435         int ret = 0;
2436
2437         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2438                 return -ENODEV;
2439
2440         DRM_DEBUG_KMS("Resuming device\n");
2441
2442         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2443         disable_rpm_wakeref_asserts(dev_priv);
2444
2445         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2446         dev_priv->pm.suspended = false;
2447         if (intel_uncore_unclaimed_mmio(dev_priv))
2448                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2449
2450         intel_guc_resume(dev_priv);
2451
2452         if (IS_GEN6(dev_priv))
2453                 intel_init_pch_refclk(dev_priv);
2454
2455         if (IS_GEN9_LP(dev_priv)) {
2456                 bxt_disable_dc9(dev_priv);
2457                 bxt_display_core_init(dev_priv, true);
2458                 if (dev_priv->csr.dmc_payload &&
2459                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2460                         gen9_enable_dc5(dev_priv);
2461         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2462                 hsw_disable_pc8(dev_priv);
2463         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2464                 ret = vlv_resume_prepare(dev_priv, true);
2465         }
2466
2467         /*
2468          * No point of rolling back things in case of an error, as the best
2469          * we can do is to hope that things will still work (and disable RPM).
2470          */
2471         i915_gem_init_swizzling(dev_priv);
2472         i915_gem_restore_fences(dev_priv);
2473
2474         intel_runtime_pm_enable_interrupts(dev_priv);
2475
2476         /*
2477          * On VLV/CHV display interrupts are part of the display
2478          * power well, so hpd is reinitialized from there. For
2479          * everyone else do it here.
2480          */
2481         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2482                 intel_hpd_init(dev_priv);
2483
2484         enable_rpm_wakeref_asserts(dev_priv);
2485
2486         if (ret)
2487                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2488         else
2489                 DRM_DEBUG_KMS("Device resumed\n");
2490
2491         return ret;
2492 }
2493
2494 const struct dev_pm_ops i915_pm_ops = {
2495         /*
2496          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2497          * PMSG_RESUME]
2498          */
2499         .suspend = i915_pm_suspend,
2500         .suspend_late = i915_pm_suspend_late,
2501         .resume_early = i915_pm_resume_early,
2502         .resume = i915_pm_resume,
2503
2504         /*
2505          * S4 event handlers
2506          * @freeze, @freeze_late    : called (1) before creating the
2507          *                            hibernation image [PMSG_FREEZE] and
2508          *                            (2) after rebooting, before restoring
2509          *                            the image [PMSG_QUIESCE]
2510          * @thaw, @thaw_early       : called (1) after creating the hibernation
2511          *                            image, before writing it [PMSG_THAW]
2512          *                            and (2) after failing to create or
2513          *                            restore the image [PMSG_RECOVER]
2514          * @poweroff, @poweroff_late: called after writing the hibernation
2515          *                            image, before rebooting [PMSG_HIBERNATE]
2516          * @restore, @restore_early : called after rebooting and restoring the
2517          *                            hibernation image [PMSG_RESTORE]
2518          */
2519         .freeze = i915_pm_freeze,
2520         .freeze_late = i915_pm_freeze_late,
2521         .thaw_early = i915_pm_thaw_early,
2522         .thaw = i915_pm_thaw,
2523         .poweroff = i915_pm_suspend,
2524         .poweroff_late = i915_pm_poweroff_late,
2525         .restore_early = i915_pm_restore_early,
2526         .restore = i915_pm_restore,
2527
2528         /* S0ix (via runtime suspend) event handlers */
2529         .runtime_suspend = intel_runtime_suspend,
2530         .runtime_resume = intel_runtime_resume,
2531 };
2532
2533 static const struct vm_operations_struct i915_gem_vm_ops = {
2534         .fault = i915_gem_fault,
2535         .open = drm_gem_vm_open,
2536         .close = drm_gem_vm_close,
2537 };
2538
2539 static const struct file_operations i915_driver_fops = {
2540         .owner = THIS_MODULE,
2541         .open = drm_open,
2542         .release = drm_release,
2543         .unlocked_ioctl = drm_ioctl,
2544         .mmap = drm_gem_mmap,
2545         .poll = drm_poll,
2546         .read = drm_read,
2547         .compat_ioctl = i915_compat_ioctl,
2548         .llseek = noop_llseek,
2549 };
2550
2551 static int
2552 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2553                           struct drm_file *file)
2554 {
2555         return -ENODEV;
2556 }
2557
2558 static const struct drm_ioctl_desc i915_ioctls[] = {
2559         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2560         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2561         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2562         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2563         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2564         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2565         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2566         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2567         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2568         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2569         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2570         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2571         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2572         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2573         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2574         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2575         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2576         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2577         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2578         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2579         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2580         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2581         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2582         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2583         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2584         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2585         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2586         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2587         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2588         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2589         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2590         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2591         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2592         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2595         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2597         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2600         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2601         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2602         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2603         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2604         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2605         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2606         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2607         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2608         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2609         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2610         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2611         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2612 };
2613
2614 static struct drm_driver driver = {
2615         /* Don't use MTRRs here; the Xserver or userspace app should
2616          * deal with them for Intel hardware.
2617          */
2618         .driver_features =
2619             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2620             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
2621         .release = i915_driver_release,
2622         .open = i915_driver_open,
2623         .lastclose = i915_driver_lastclose,
2624         .postclose = i915_driver_postclose,
2625         .set_busid = drm_pci_set_busid,
2626
2627         .gem_close_object = i915_gem_close_object,
2628         .gem_free_object_unlocked = i915_gem_free_object,
2629         .gem_vm_ops = &i915_gem_vm_ops,
2630
2631         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2632         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2633         .gem_prime_export = i915_gem_prime_export,
2634         .gem_prime_import = i915_gem_prime_import,
2635
2636         .dumb_create = i915_gem_dumb_create,
2637         .dumb_map_offset = i915_gem_mmap_gtt,
2638         .dumb_destroy = drm_gem_dumb_destroy,
2639         .ioctls = i915_ioctls,
2640         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2641         .fops = &i915_driver_fops,
2642         .name = DRIVER_NAME,
2643         .desc = DRIVER_DESC,
2644         .date = DRIVER_DATE,
2645         .major = DRIVER_MAJOR,
2646         .minor = DRIVER_MINOR,
2647         .patchlevel = DRIVER_PATCHLEVEL,
2648 };
2649
2650 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2651 #include "selftests/mock_drm.c"
2652 #endif