drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 return true;
  71         }
  72
  73         return false;
  74 }
  75 #endif
  76
  77 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  78 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  79                     "providing the dmesg log by booting with drm.debug=0xf"
  80
  81 void
  82 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  83               const char *fmt, ...)
  84 {
  85         static bool shown_bug_once;
  86         struct device *kdev = dev_priv->drm.dev;
  87         bool is_error = level[1] <= KERN_ERR[1];
  88         bool is_debug = level[1] == KERN_DEBUG[1];
  89         struct va_format vaf;
  90         va_list args;
  91
  92         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  93                 return;
  94
  95         va_start(args, fmt);
  96
  97         vaf.fmt = fmt;
  98         vaf.va = &args;
  99
 100         dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 101                    __builtin_return_address(0), &vaf);
 102
 103         if (is_error && !shown_bug_once) {
 104                 /*
 105                  * Ask the user to file a bug report for the error, except
 106                  * if they may have caused the bug by fiddling with unsafe
 107                  * module parameters.
 108                  */
 109                 if (!test_taint(TAINT_USER))
 110                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 111                 shown_bug_once = true;
 112         }
 113
 114         va_end(args);
 115 }
 116
 117 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 118 {
 119 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 120         return i915_modparams.inject_load_failure &&
 121                i915_load_fail_count == i915_modparams.inject_load_failure;
 122 #else
 123         return false;
 124 #endif
 125 }
 126
 127 #define i915_load_error(dev_priv, fmt, ...)                                  \
 128         __i915_printk(dev_priv,                                              \
 129                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 130                       fmt, ##__VA_ARGS__)
 131
 132 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 133 static enum intel_pch
 134 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 135 {
 136         switch (id) {
 137         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 138                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 139                 WARN_ON(!IS_GEN5(dev_priv));
 140                 return PCH_IBX;
 141         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 142                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 143                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 144                 return PCH_CPT;
 145         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 147                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 148                 /* PantherPoint is CPT compatible */
 149                 return PCH_CPT;
 150         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 159                 return PCH_LPT;
 160         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 161                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 162                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 163                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 164                 /* WildcatPoint is LPT compatible */
 165                 return PCH_LPT;
 166         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 167                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 168                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 169                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 170                 /* WildcatPoint is LPT compatible */
 171                 return PCH_LPT;
 172         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 173                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 174                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 175                 return PCH_SPT;
 176         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 177                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 178                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 179                 return PCH_SPT;
 180         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 182                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 183                         !IS_COFFEELAKE(dev_priv));
 184                 return PCH_KBP;
 185         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 186                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 187                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 188                 return PCH_CNP;
 189         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 190                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 191                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 192                 return PCH_CNP;
 193         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 194                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 195                 WARN_ON(!IS_ICELAKE(dev_priv));
 196                 return PCH_ICP;
 197         default:
 198                 return PCH_NONE;
 199         }
 200 }
 201
 202 static bool intel_is_virt_pch(unsigned short id,
 203                               unsigned short svendor, unsigned short sdevice)
 204 {
 205         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 206                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 207                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 208                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 209                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 210 }
 211
 212 static unsigned short
 213 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 214 {
 215         unsigned short id = 0;
 216
 217         /*
 218          * In a virtualized passthrough environment we can be in a
 219          * setup where the ISA bridge is not able to be passed through.
 220          * In this case, a south bridge can be emulated and we have to
 221          * make an educated guess as to which PCH is really there.
 222          */
 223
 224         if (IS_GEN5(dev_priv))
 225                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 226         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 227                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 228         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 229                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 230         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 231                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 232         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 233                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 234         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 235                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 236
 237         if (id)
 238                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 239         else
 240                 DRM_DEBUG_KMS("Assuming no PCH\n");
 241
 242         return id;
 243 }
 244
 245 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 246 {
 247         struct pci_dev *pch = NULL;
 248
 249         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 250          * (which really amounts to a PCH but no South Display).
 251          */
 252         if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 253                 dev_priv->pch_type = PCH_NOP;
 254                 return;
 255         }
 256
 257         /*
 258          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 259          * make graphics device passthrough work easy for VMM, that only
 260          * need to expose ISA bridge to let driver know the real hardware
 261          * underneath. This is a requirement from virtualization team.
 262          *
 263          * In some virtualized environments (e.g. XEN), there is irrelevant
 264          * ISA bridge in the system. To work reliably, we should scan trhough
 265          * all the ISA bridge devices and check for the first match, instead
 266          * of only checking the first one.
 267          */
 268         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 269                 unsigned short id;
 270                 enum intel_pch pch_type;
 271
 272                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 273                         continue;
 274
 275                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 276
 277                 pch_type = intel_pch_type(dev_priv, id);
 278                 if (pch_type != PCH_NONE) {
 279                         dev_priv->pch_type = pch_type;
 280                         dev_priv->pch_id = id;
 281                         break;
 282                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 283                                          pch->subsystem_device)) {
 284                         id = intel_virt_detect_pch(dev_priv);
 285                         if (id) {
 286                                 pch_type = intel_pch_type(dev_priv, id);
 287                                 if (WARN_ON(pch_type == PCH_NONE))
 288                                         pch_type = PCH_NOP;
 289                         } else {
 290                                 pch_type = PCH_NOP;
 291                         }
 292                         dev_priv->pch_type = pch_type;
 293                         dev_priv->pch_id = id;
 294                         break;
 295                 }
 296         }
 297         if (!pch)
 298                 DRM_DEBUG_KMS("No PCH found.\n");
 299
 300         pci_dev_put(pch);
 301 }
 302
 303 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 304                                struct drm_file *file_priv)
 305 {
 306         struct drm_i915_private *dev_priv = to_i915(dev);
 307         struct pci_dev *pdev = dev_priv->drm.pdev;
 308         drm_i915_getparam_t *param = data;
 309         int value;
 310
 311         switch (param->param) {
 312         case I915_PARAM_IRQ_ACTIVE:
 313         case I915_PARAM_ALLOW_BATCHBUFFER:
 314         case I915_PARAM_LAST_DISPATCH:
 315         case I915_PARAM_HAS_EXEC_CONSTANTS:
 316                 /* Reject all old ums/dri params. */
 317                 return -ENODEV;
 318         case I915_PARAM_CHIPSET_ID:
 319                 value = pdev->device;
 320                 break;
 321         case I915_PARAM_REVISION:
 322                 value = pdev->revision;
 323                 break;
 324         case I915_PARAM_NUM_FENCES_AVAIL:
 325                 value = dev_priv->num_fence_regs;
 326                 break;
 327         case I915_PARAM_HAS_OVERLAY:
 328                 value = dev_priv->overlay ? 1 : 0;
 329                 break;
 330         case I915_PARAM_HAS_BSD:
 331                 value = !!dev_priv->engine[VCS];
 332                 break;
 333         case I915_PARAM_HAS_BLT:
 334                 value = !!dev_priv->engine[BCS];
 335                 break;
 336         case I915_PARAM_HAS_VEBOX:
 337                 value = !!dev_priv->engine[VECS];
 338                 break;
 339         case I915_PARAM_HAS_BSD2:
 340                 value = !!dev_priv->engine[VCS2];
 341                 break;
 342         case I915_PARAM_HAS_LLC:
 343                 value = HAS_LLC(dev_priv);
 344                 break;
 345         case I915_PARAM_HAS_WT:
 346                 value = HAS_WT(dev_priv);
 347                 break;
 348         case I915_PARAM_HAS_ALIASING_PPGTT:
 349                 value = USES_PPGTT(dev_priv);
 350                 break;
 351         case I915_PARAM_HAS_SEMAPHORES:
 352                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 353                 break;
 354         case I915_PARAM_HAS_SECURE_BATCHES:
 355                 value = capable(CAP_SYS_ADMIN);
 356                 break;
 357         case I915_PARAM_CMD_PARSER_VERSION:
 358                 value = i915_cmd_parser_get_version(dev_priv);
 359                 break;
 360         case I915_PARAM_SUBSLICE_TOTAL:
 361                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 362                 if (!value)
 363                         return -ENODEV;
 364                 break;
 365         case I915_PARAM_EU_TOTAL:
 366                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 367                 if (!value)
 368                         return -ENODEV;
 369                 break;
 370         case I915_PARAM_HAS_GPU_RESET:
 371                 value = i915_modparams.enable_hangcheck &&
 372                         intel_has_gpu_reset(dev_priv);
 373                 if (value && intel_has_reset_engine(dev_priv))
 374                         value = 2;
 375                 break;
 376         case I915_PARAM_HAS_RESOURCE_STREAMER:
 377                 value = HAS_RESOURCE_STREAMER(dev_priv);
 378                 break;
 379         case I915_PARAM_HAS_POOLED_EU:
 380                 value = HAS_POOLED_EU(dev_priv);
 381                 break;
 382         case I915_PARAM_MIN_EU_IN_POOL:
 383                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 384                 break;
 385         case I915_PARAM_HUC_STATUS:
 386                 value = intel_huc_check_status(&dev_priv->huc);
 387                 if (value < 0)
 388                         return value;
 389                 break;
 390         case I915_PARAM_MMAP_GTT_VERSION:
 391                 /* Though we've started our numbering from 1, and so class all
 392                  * earlier versions as 0, in effect their value is undefined as
 393                  * the ioctl will report EINVAL for the unknown param!
 394                  */
 395                 value = i915_gem_mmap_gtt_version();
 396                 break;
 397         case I915_PARAM_HAS_SCHEDULER:
 398                 value = dev_priv->caps.scheduler;
 399                 break;
 400
 401         case I915_PARAM_MMAP_VERSION:
 402                 /* Remember to bump this if the version changes! */
 403         case I915_PARAM_HAS_GEM:
 404         case I915_PARAM_HAS_PAGEFLIPPING:
 405         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 406         case I915_PARAM_HAS_RELAXED_FENCING:
 407         case I915_PARAM_HAS_COHERENT_RINGS:
 408         case I915_PARAM_HAS_RELAXED_DELTA:
 409         case I915_PARAM_HAS_GEN7_SOL_RESET:
 410         case I915_PARAM_HAS_WAIT_TIMEOUT:
 411         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 412         case I915_PARAM_HAS_PINNED_BATCHES:
 413         case I915_PARAM_HAS_EXEC_NO_RELOC:
 414         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 415         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 416         case I915_PARAM_HAS_EXEC_SOFTPIN:
 417         case I915_PARAM_HAS_EXEC_ASYNC:
 418         case I915_PARAM_HAS_EXEC_FENCE:
 419         case I915_PARAM_HAS_EXEC_CAPTURE:
 420         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 421         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 422                 /* For the time being all of these are always true;
 423                  * if some supported hardware does not have one of these
 424                  * features this value needs to be provided from
 425                  * INTEL_INFO(), a feature macro, or similar.
 426                  */
 427                 value = 1;
 428                 break;
 429         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 430                 value = intel_engines_has_context_isolation(dev_priv);
 431                 break;
 432         case I915_PARAM_SLICE_MASK:
 433                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 434                 if (!value)
 435                         return -ENODEV;
 436                 break;
 437         case I915_PARAM_SUBSLICE_MASK:
 438                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 439                 if (!value)
 440                         return -ENODEV;
 441                 break;
 442         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 443                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 444                 break;
 445         default:
 446                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 447                 return -EINVAL;
 448         }
 449
 450         if (put_user(value, param->value))
 451                 return -EFAULT;
 452
 453         return 0;
 454 }
 455
 456 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 457 {
 458         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 459
 460         dev_priv->bridge_dev =
 461                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 462         if (!dev_priv->bridge_dev) {
 463                 DRM_ERROR("bridge device not found\n");
 464                 return -1;
 465         }
 466         return 0;
 467 }
 468
 469 /* Allocate space for the MCH regs if needed, return nonzero on error */
 470 static int
 471 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 472 {
 473         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 474         u32 temp_lo, temp_hi = 0;
 475         u64 mchbar_addr;
 476         int ret;
 477
 478         if (INTEL_GEN(dev_priv) >= 4)
 479                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 480         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 481         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 482
 483         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 484 #ifdef CONFIG_PNP
 485         if (mchbar_addr &&
 486             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 487                 return 0;
 488 #endif
 489
 490         /* Get some space for it */
 491         dev_priv->mch_res.name = "i915 MCHBAR";
 492         dev_priv->mch_res.flags = IORESOURCE_MEM;
 493         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 494                                      &dev_priv->mch_res,
 495                                      MCHBAR_SIZE, MCHBAR_SIZE,
 496                                      PCIBIOS_MIN_MEM,
 497                                      0, pcibios_align_resource,
 498                                      dev_priv->bridge_dev);
 499         if (ret) {
 500                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 501                 dev_priv->mch_res.start = 0;
 502                 return ret;
 503         }
 504
 505         if (INTEL_GEN(dev_priv) >= 4)
 506                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 507                                        upper_32_bits(dev_priv->mch_res.start));
 508
 509         pci_write_config_dword(dev_priv->bridge_dev, reg,
 510                                lower_32_bits(dev_priv->mch_res.start));
 511         return 0;
 512 }
 513
 514 /* Setup MCHBAR if possible, return true if we should disable it again */
 515 static void
 516 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 517 {
 518         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 519         u32 temp;
 520         bool enabled;
 521
 522         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 523                 return;
 524
 525         dev_priv->mchbar_need_disable = false;
 526
 527         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 528                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 529                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 530         } else {
 531                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 532                 enabled = temp & 1;
 533         }
 534
 535         /* If it's already enabled, don't have to do anything */
 536         if (enabled)
 537                 return;
 538
 539         if (intel_alloc_mchbar_resource(dev_priv))
 540                 return;
 541
 542         dev_priv->mchbar_need_disable = true;
 543
 544         /* Space is allocated or reserved, so enable it. */
 545         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 546                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 547                                        temp | DEVEN_MCHBAR_EN);
 548         } else {
 549                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 550                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 551         }
 552 }
 553
 554 static void
 555 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 556 {
 557         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 558
 559         if (dev_priv->mchbar_need_disable) {
 560                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 561                         u32 deven_val;
 562
 563                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 564                                               &deven_val);
 565                         deven_val &= ~DEVEN_MCHBAR_EN;
 566                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 567                                                deven_val);
 568                 } else {
 569                         u32 mchbar_val;
 570
 571                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 572                                               &mchbar_val);
 573                         mchbar_val &= ~1;
 574                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 575                                                mchbar_val);
 576                 }
 577         }
 578
 579         if (dev_priv->mch_res.start)
 580                 release_resource(&dev_priv->mch_res);
 581 }
 582
 583 /* true = enable decode, false = disable decoder */
 584 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 585 {
 586         struct drm_i915_private *dev_priv = cookie;
 587
 588         intel_modeset_vga_set_state(dev_priv, state);
 589         if (state)
 590                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 591                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 592         else
 593                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 594 }
 595
 596 static int i915_resume_switcheroo(struct drm_device *dev);
 597 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 598
 599 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 600 {
 601         struct drm_device *dev = pci_get_drvdata(pdev);
 602         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 603
 604         if (state == VGA_SWITCHEROO_ON) {
 605                 pr_info("switched on\n");
 606                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 607                 /* i915 resume handler doesn't set to D0 */
 608                 pci_set_power_state(pdev, PCI_D0);
 609                 i915_resume_switcheroo(dev);
 610                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 611         } else {
 612                 pr_info("switched off\n");
 613                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 614                 i915_suspend_switcheroo(dev, pmm);
 615                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 616         }
 617 }
 618
 619 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 620 {
 621         struct drm_device *dev = pci_get_drvdata(pdev);
 622
 623         /*
 624          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 625          * locking inversion with the driver load path. And the access here is
 626          * completely racy anyway. So don't bother with locking for now.
 627          */
 628         return dev->open_count == 0;
 629 }
 630
 631 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 632         .set_gpu_state = i915_switcheroo_set_state,
 633         .reprobe = NULL,
 634         .can_switch = i915_switcheroo_can_switch,
 635 };
 636
 637 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 638 {
 639         /* Flush any outstanding unpin_work. */
 640         i915_gem_drain_workqueue(dev_priv);
 641
 642         mutex_lock(&dev_priv->drm.struct_mutex);
 643         intel_uc_fini_hw(dev_priv);
 644         intel_uc_fini(dev_priv);
 645         i915_gem_cleanup_engines(dev_priv);
 646         i915_gem_contexts_fini(dev_priv);
 647         mutex_unlock(&dev_priv->drm.struct_mutex);
 648
 649         intel_uc_fini_misc(dev_priv);
 650         i915_gem_cleanup_userptr(dev_priv);
 651
 652         i915_gem_drain_freed_objects(dev_priv);
 653
 654         WARN_ON(!list_empty(&dev_priv->contexts.list));
 655 }
 656
 657 static int i915_load_modeset_init(struct drm_device *dev)
 658 {
 659         struct drm_i915_private *dev_priv = to_i915(dev);
 660         struct pci_dev *pdev = dev_priv->drm.pdev;
 661         int ret;
 662
 663         if (i915_inject_load_failure())
 664                 return -ENODEV;
 665
 666         intel_bios_init(dev_priv);
 667
 668         /* If we have > 1 VGA cards, then we need to arbitrate access
 669          * to the common VGA resources.
 670          *
 671          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 672          * then we do not take part in VGA arbitration and the
 673          * vga_client_register() fails with -ENODEV.
 674          */
 675         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 676         if (ret && ret != -ENODEV)
 677                 goto out;
 678
 679         intel_register_dsm_handler();
 680
 681         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 682         if (ret)
 683                 goto cleanup_vga_client;
 684
 685         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 686         intel_update_rawclk(dev_priv);
 687
 688         intel_power_domains_init_hw(dev_priv, false);
 689
 690         intel_csr_ucode_init(dev_priv);
 691
 692         ret = intel_irq_install(dev_priv);
 693         if (ret)
 694                 goto cleanup_csr;
 695
 696         intel_setup_gmbus(dev_priv);
 697
 698         /* Important: The output setup functions called by modeset_init need
 699          * working irqs for e.g. gmbus and dp aux transfers. */
 700         ret = intel_modeset_init(dev);
 701         if (ret)
 702                 goto cleanup_irq;
 703
 704         ret = i915_gem_init(dev_priv);
 705         if (ret)
 706                 goto cleanup_irq;
 707
 708         intel_setup_overlay(dev_priv);
 709
 710         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 711                 return 0;
 712
 713         ret = intel_fbdev_init(dev);
 714         if (ret)
 715                 goto cleanup_gem;
 716
 717         /* Only enable hotplug handling once the fbdev is fully set up. */
 718         intel_hpd_init(dev_priv);
 719
 720         return 0;
 721
 722 cleanup_gem:
 723         if (i915_gem_suspend(dev_priv))
 724                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 725         i915_gem_fini(dev_priv);
 726 cleanup_irq:
 727         drm_irq_uninstall(dev);
 728         intel_teardown_gmbus(dev_priv);
 729 cleanup_csr:
 730         intel_csr_ucode_fini(dev_priv);
 731         intel_power_domains_fini(dev_priv);
 732         vga_switcheroo_unregister_client(pdev);
 733 cleanup_vga_client:
 734         vga_client_register(pdev, NULL, NULL, NULL);
 735 out:
 736         return ret;
 737 }
 738
 739 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 740 {
 741         struct apertures_struct *ap;
 742         struct pci_dev *pdev = dev_priv->drm.pdev;
 743         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 744         bool primary;
 745         int ret;
 746
 747         ap = alloc_apertures(1);
 748         if (!ap)
 749                 return -ENOMEM;
 750
 751         ap->ranges[0].base = ggtt->gmadr.start;
 752         ap->ranges[0].size = ggtt->mappable_end;
 753
 754         primary =
 755                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 756
 757         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 758
 759         kfree(ap);
 760
 761         return ret;
 762 }
 763
 764 #if !defined(CONFIG_VGA_CONSOLE)
 765 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 766 {
 767         return 0;
 768 }
 769 #elif !defined(CONFIG_DUMMY_CONSOLE)
 770 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 771 {
 772         return -ENODEV;
 773 }
 774 #else
 775 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 776 {
 777         int ret = 0;
 778
 779         DRM_INFO("Replacing VGA console driver\n");
 780
 781         console_lock();
 782         if (con_is_bound(&vga_con))
 783                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 784         if (ret == 0) {
 785                 ret = do_unregister_con_driver(&vga_con);
 786
 787                 /* Ignore "already unregistered". */
 788                 if (ret == -ENODEV)
 789                         ret = 0;
 790         }
 791         console_unlock();
 792
 793         return ret;
 794 }
 795 #endif
 796
 797 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 798 {
 799         /*
 800          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 801          * CHV x1 PHY (DP/HDMI D)
 802          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 803          */
 804         if (IS_CHERRYVIEW(dev_priv)) {
 805                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 806                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 807         } else if (IS_VALLEYVIEW(dev_priv)) {
 808                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 809         }
 810 }
 811
 812 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 813 {
 814         /*
 815          * The i915 workqueue is primarily used for batched retirement of
 816          * requests (and thus managing bo) once the task has been completed
 817          * by the GPU. i915_retire_requests() is called directly when we
 818          * need high-priority retirement, such as waiting for an explicit
 819          * bo.
 820          *
 821          * It is also used for periodic low-priority events, such as
 822          * idle-timers and recording error state.
 823          *
 824          * All tasks on the workqueue are expected to acquire the dev mutex
 825          * so there is no point in running more than one instance of the
 826          * workqueue at any time.  Use an ordered one.
 827          */
 828         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 829         if (dev_priv->wq == NULL)
 830                 goto out_err;
 831
 832         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 833         if (dev_priv->hotplug.dp_wq == NULL)
 834                 goto out_free_wq;
 835
 836         return 0;
 837
 838 out_free_wq:
 839         destroy_workqueue(dev_priv->wq);
 840 out_err:
 841         DRM_ERROR("Failed to allocate workqueues.\n");
 842
 843         return -ENOMEM;
 844 }
 845
 846 static void i915_engines_cleanup(struct drm_i915_private *i915)
 847 {
 848         struct intel_engine_cs *engine;
 849         enum intel_engine_id id;
 850
 851         for_each_engine(engine, i915, id)
 852                 kfree(engine);
 853 }
 854
 855 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 856 {
 857         destroy_workqueue(dev_priv->hotplug.dp_wq);
 858         destroy_workqueue(dev_priv->wq);
 859 }
 860
 861 /*
 862  * We don't keep the workarounds for pre-production hardware, so we expect our
 863  * driver to fail on these machines in one way or another. A little warning on
 864  * dmesg may help both the user and the bug triagers.
 865  *
 866  * Our policy for removing pre-production workarounds is to keep the
 867  * current gen workarounds as a guide to the bring-up of the next gen
 868  * (workarounds have a habit of persisting!). Anything older than that
 869  * should be removed along with the complications they introduce.
 870  */
 871 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 872 {
 873         bool pre = false;
 874
 875         pre |= IS_HSW_EARLY_SDV(dev_priv);
 876         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 877         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 878
 879         if (pre) {
 880                 DRM_ERROR("This is a pre-production stepping. "
 881                           "It may not be fully functional.\n");
 882                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 883         }
 884 }
 885
 886 /**
 887  * i915_driver_init_early - setup state not requiring device access
 888  * @dev_priv: device private
 889  * @ent: the matching pci_device_id
 890  *
 891  * Initialize everything that is a "SW-only" state, that is state not
 892  * requiring accessing the device or exposing the driver via kernel internal
 893  * or userspace interfaces. Example steps belonging here: lock initialization,
 894  * system memory allocation, setting up device specific attributes and
 895  * function hooks not requiring accessing the device.
 896  */
 897 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 898                                   const struct pci_device_id *ent)
 899 {
 900         const struct intel_device_info *match_info =
 901                 (struct intel_device_info *)ent->driver_data;
 902         struct intel_device_info *device_info;
 903         int ret = 0;
 904
 905         if (i915_inject_load_failure())
 906                 return -ENODEV;
 907
 908         /* Setup the write-once "constant" device info */
 909         device_info = mkwrite_device_info(dev_priv);
 910         memcpy(device_info, match_info, sizeof(*device_info));
 911         device_info->device_id = dev_priv->drm.pdev->device;
 912
 913         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 914                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 915         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 916         spin_lock_init(&dev_priv->irq_lock);
 917         spin_lock_init(&dev_priv->gpu_error.lock);
 918         mutex_init(&dev_priv->backlight_lock);
 919         spin_lock_init(&dev_priv->uncore.lock);
 920
 921         mutex_init(&dev_priv->sb_lock);
 922         mutex_init(&dev_priv->modeset_restore_lock);
 923         mutex_init(&dev_priv->av_mutex);
 924         mutex_init(&dev_priv->wm.wm_mutex);
 925         mutex_init(&dev_priv->pps_mutex);
 926
 927         i915_memcpy_init_early(dev_priv);
 928
 929         ret = i915_workqueues_init(dev_priv);
 930         if (ret < 0)
 931                 goto err_engines;
 932
 933         ret = i915_gem_init_early(dev_priv);
 934         if (ret < 0)
 935                 goto err_workqueues;
 936
 937         /* This must be called before any calls to HAS_PCH_* */
 938         intel_detect_pch(dev_priv);
 939
 940         intel_wopcm_init_early(&dev_priv->wopcm);
 941         intel_uc_init_early(dev_priv);
 942         intel_pm_setup(dev_priv);
 943         intel_init_dpio(dev_priv);
 944         intel_power_domains_init(dev_priv);
 945         intel_irq_init(dev_priv);
 946         intel_hangcheck_init(dev_priv);
 947         intel_init_display_hooks(dev_priv);
 948         intel_init_clock_gating_hooks(dev_priv);
 949         intel_init_audio_hooks(dev_priv);
 950         intel_display_crc_init(dev_priv);
 951
 952         intel_detect_preproduction_hw(dev_priv);
 953
 954         return 0;
 955
 956 err_workqueues:
 957         i915_workqueues_cleanup(dev_priv);
 958 err_engines:
 959         i915_engines_cleanup(dev_priv);
 960         return ret;
 961 }
 962
 963 /**
 964  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 965  * @dev_priv: device private
 966  */
 967 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 968 {
 969         intel_irq_fini(dev_priv);
 970         intel_uc_cleanup_early(dev_priv);
 971         i915_gem_cleanup_early(dev_priv);
 972         i915_workqueues_cleanup(dev_priv);
 973         i915_engines_cleanup(dev_priv);
 974 }
 975
 976 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 977 {
 978         struct pci_dev *pdev = dev_priv->drm.pdev;
 979         int mmio_bar;
 980         int mmio_size;
 981
 982         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 983         /*
 984          * Before gen4, the registers and the GTT are behind different BARs.
 985          * However, from gen4 onwards, the registers and the GTT are shared
 986          * in the same BAR, so we want to restrict this ioremap from
 987          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 988          * the register BAR remains the same size for all the earlier
 989          * generations up to Ironlake.
 990          */
 991         if (INTEL_GEN(dev_priv) < 5)
 992                 mmio_size = 512 * 1024;
 993         else
 994                 mmio_size = 2 * 1024 * 1024;
 995         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 996         if (dev_priv->regs == NULL) {
 997                 DRM_ERROR("failed to map registers\n");
 998
 999                 return -EIO;
1000         }
1001
1002         /* Try to make sure MCHBAR is enabled before poking at it */
1003         intel_setup_mchbar(dev_priv);
1004
1005         return 0;
1006 }
1007
1008 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
1009 {
1010         struct pci_dev *pdev = dev_priv->drm.pdev;
1011
1012         intel_teardown_mchbar(dev_priv);
1013         pci_iounmap(pdev, dev_priv->regs);
1014 }
1015
1016 /**
1017  * i915_driver_init_mmio - setup device MMIO
1018  * @dev_priv: device private
1019  *
1020  * Setup minimal device state necessary for MMIO accesses later in the
1021  * initialization sequence. The setup here should avoid any other device-wide
1022  * side effects or exposing the driver via kernel internal or user space
1023  * interfaces.
1024  */
1025 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1026 {
1027         int ret;
1028
1029         if (i915_inject_load_failure())
1030                 return -ENODEV;
1031
1032         if (i915_get_bridge_dev(dev_priv))
1033                 return -EIO;
1034
1035         ret = i915_mmio_setup(dev_priv);
1036         if (ret < 0)
1037                 goto err_bridge;
1038
1039         intel_uncore_init(dev_priv);
1040
1041         intel_device_info_init_mmio(dev_priv);
1042
1043         intel_uncore_prune(dev_priv);
1044
1045         intel_uc_init_mmio(dev_priv);
1046
1047         ret = intel_engines_init_mmio(dev_priv);
1048         if (ret)
1049                 goto err_uncore;
1050
1051         i915_gem_init_mmio(dev_priv);
1052
1053         return 0;
1054
1055 err_uncore:
1056         intel_uncore_fini(dev_priv);
1057 err_bridge:
1058         pci_dev_put(dev_priv->bridge_dev);
1059
1060         return ret;
1061 }
1062
1063 /**
1064  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1065  * @dev_priv: device private
1066  */
1067 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1068 {
1069         intel_uncore_fini(dev_priv);
1070         i915_mmio_cleanup(dev_priv);
1071         pci_dev_put(dev_priv->bridge_dev);
1072 }
1073
1074 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1075 {
1076         /*
1077          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1078          * user's requested state against the hardware/driver capabilities.  We
1079          * do this now so that we can print out any log messages once rather
1080          * than every time we check intel_enable_ppgtt().
1081          */
1082         i915_modparams.enable_ppgtt =
1083                 intel_sanitize_enable_ppgtt(dev_priv,
1084                                             i915_modparams.enable_ppgtt);
1085         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1086
1087         intel_gvt_sanitize_options(dev_priv);
1088 }
1089
1090 /**
1091  * i915_driver_init_hw - setup state requiring device access
1092  * @dev_priv: device private
1093  *
1094  * Setup state that requires accessing the device, but doesn't require
1095  * exposing the driver via kernel internal or userspace interfaces.
1096  */
1097 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1098 {
1099         struct pci_dev *pdev = dev_priv->drm.pdev;
1100         int ret;
1101
1102         if (i915_inject_load_failure())
1103                 return -ENODEV;
1104
1105         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1106
1107         intel_sanitize_options(dev_priv);
1108
1109         i915_perf_init(dev_priv);
1110
1111         ret = i915_ggtt_probe_hw(dev_priv);
1112         if (ret)
1113                 goto err_perf;
1114
1115         /*
1116          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1117          * otherwise the vga fbdev driver falls over.
1118          */
1119         ret = i915_kick_out_firmware_fb(dev_priv);
1120         if (ret) {
1121                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1122                 goto err_ggtt;
1123         }
1124
1125         ret = i915_kick_out_vgacon(dev_priv);
1126         if (ret) {
1127                 DRM_ERROR("failed to remove conflicting VGA console\n");
1128                 goto err_ggtt;
1129         }
1130
1131         ret = i915_ggtt_init_hw(dev_priv);
1132         if (ret)
1133                 goto err_ggtt;
1134
1135         ret = i915_ggtt_enable_hw(dev_priv);
1136         if (ret) {
1137                 DRM_ERROR("failed to enable GGTT\n");
1138                 goto err_ggtt;
1139         }
1140
1141         pci_set_master(pdev);
1142
1143         /* overlay on gen2 is broken and can't address above 1G */
1144         if (IS_GEN2(dev_priv)) {
1145                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1146                 if (ret) {
1147                         DRM_ERROR("failed to set DMA mask\n");
1148
1149                         goto err_ggtt;
1150                 }
1151         }
1152
1153         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1154          * using 32bit addressing, overwriting memory if HWS is located
1155          * above 4GB.
1156          *
1157          * The documentation also mentions an issue with undefined
1158          * behaviour if any general state is accessed within a page above 4GB,
1159          * which also needs to be handled carefully.
1160          */
1161         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1162                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1163
1164                 if (ret) {
1165                         DRM_ERROR("failed to set DMA mask\n");
1166
1167                         goto err_ggtt;
1168                 }
1169         }
1170
1171         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1172                            PM_QOS_DEFAULT_VALUE);
1173
1174         intel_uncore_sanitize(dev_priv);
1175
1176         intel_opregion_setup(dev_priv);
1177
1178         i915_gem_load_init_fences(dev_priv);
1179
1180         /* On the 945G/GM, the chipset reports the MSI capability on the
1181          * integrated graphics even though the support isn't actually there
1182          * according to the published specs.  It doesn't appear to function
1183          * correctly in testing on 945G.
1184          * This may be a side effect of MSI having been made available for PEG
1185          * and the registers being closely associated.
1186          *
1187          * According to chipset errata, on the 965GM, MSI interrupts may
1188          * be lost or delayed, and was defeatured. MSI interrupts seem to
1189          * get lost on g4x as well, and interrupt delivery seems to stay
1190          * properly dead afterwards. So we'll just disable them for all
1191          * pre-gen5 chipsets.
1192          */
1193         if (INTEL_GEN(dev_priv) >= 5) {
1194                 if (pci_enable_msi(pdev) < 0)
1195                         DRM_DEBUG_DRIVER("can't enable MSI");
1196         }
1197
1198         ret = intel_gvt_init(dev_priv);
1199         if (ret)
1200                 goto err_ggtt;
1201
1202         return 0;
1203
1204 err_ggtt:
1205         i915_ggtt_cleanup_hw(dev_priv);
1206 err_perf:
1207         i915_perf_fini(dev_priv);
1208         return ret;
1209 }
1210
1211 /**
1212  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1213  * @dev_priv: device private
1214  */
1215 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1216 {
1217         struct pci_dev *pdev = dev_priv->drm.pdev;
1218
1219         i915_perf_fini(dev_priv);
1220
1221         if (pdev->msi_enabled)
1222                 pci_disable_msi(pdev);
1223
1224         pm_qos_remove_request(&dev_priv->pm_qos);
1225         i915_ggtt_cleanup_hw(dev_priv);
1226 }
1227
1228 /**
1229  * i915_driver_register - register the driver with the rest of the system
1230  * @dev_priv: device private
1231  *
1232  * Perform any steps necessary to make the driver available via kernel
1233  * internal or userspace interfaces.
1234  */
1235 static void i915_driver_register(struct drm_i915_private *dev_priv)
1236 {
1237         struct drm_device *dev = &dev_priv->drm;
1238
1239         i915_gem_shrinker_register(dev_priv);
1240         i915_pmu_register(dev_priv);
1241
1242         /*
1243          * Notify a valid surface after modesetting,
1244          * when running inside a VM.
1245          */
1246         if (intel_vgpu_active(dev_priv))
1247                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1248
1249         /* Reveal our presence to userspace */
1250         if (drm_dev_register(dev, 0) == 0) {
1251                 i915_debugfs_register(dev_priv);
1252                 i915_setup_sysfs(dev_priv);
1253
1254                 /* Depends on sysfs having been initialized */
1255                 i915_perf_register(dev_priv);
1256         } else
1257                 DRM_ERROR("Failed to register driver for userspace access!\n");
1258
1259         if (INTEL_INFO(dev_priv)->num_pipes) {
1260                 /* Must be done after probing outputs */
1261                 intel_opregion_register(dev_priv);
1262                 acpi_video_register();
1263         }
1264
1265         if (IS_GEN5(dev_priv))
1266                 intel_gpu_ips_init(dev_priv);
1267
1268         intel_audio_init(dev_priv);
1269
1270         /*
1271          * Some ports require correctly set-up hpd registers for detection to
1272          * work properly (leading to ghost connected connector status), e.g. VGA
1273          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1274          * irqs are fully enabled. We do it last so that the async config
1275          * cannot run before the connectors are registered.
1276          */
1277         intel_fbdev_initial_config_async(dev);
1278
1279         /*
1280          * We need to coordinate the hotplugs with the asynchronous fbdev
1281          * configuration, for which we use the fbdev->async_cookie.
1282          */
1283         if (INTEL_INFO(dev_priv)->num_pipes)
1284                 drm_kms_helper_poll_init(dev);
1285 }
1286
1287 /**
1288  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1289  * @dev_priv: device private
1290  */
1291 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1292 {
1293         intel_fbdev_unregister(dev_priv);
1294         intel_audio_deinit(dev_priv);
1295
1296         /*
1297          * After flushing the fbdev (incl. a late async config which will
1298          * have delayed queuing of a hotplug event), then flush the hotplug
1299          * events.
1300          */
1301         drm_kms_helper_poll_fini(&dev_priv->drm);
1302
1303         intel_gpu_ips_teardown();
1304         acpi_video_unregister();
1305         intel_opregion_unregister(dev_priv);
1306
1307         i915_perf_unregister(dev_priv);
1308         i915_pmu_unregister(dev_priv);
1309
1310         i915_teardown_sysfs(dev_priv);
1311         drm_dev_unregister(&dev_priv->drm);
1312
1313         i915_gem_shrinker_unregister(dev_priv);
1314 }
1315
1316 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1317 {
1318         if (drm_debug & DRM_UT_DRIVER) {
1319                 struct drm_printer p = drm_debug_printer("i915 device info:");
1320
1321                 intel_device_info_dump(&dev_priv->info, &p);
1322                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1323         }
1324
1325         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1326                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1327         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1328                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1329 }
1330
1331 /**
1332  * i915_driver_load - setup chip and create an initial config
1333  * @pdev: PCI device
1334  * @ent: matching PCI ID entry
1335  *
1336  * The driver load routine has to do several things:
1337  *   - drive output discovery via intel_modeset_init()
1338  *   - initialize the memory manager
1339  *   - allocate initial config memory
1340  *   - setup the DRM framebuffer with the allocated memory
1341  */
1342 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1343 {
1344         const struct intel_device_info *match_info =
1345                 (struct intel_device_info *)ent->driver_data;
1346         struct drm_i915_private *dev_priv;
1347         int ret;
1348
1349         /* Enable nuclear pageflip on ILK+ */
1350         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1351                 driver.driver_features &= ~DRIVER_ATOMIC;
1352
1353         ret = -ENOMEM;
1354         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1355         if (dev_priv)
1356                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1357         if (ret) {
1358                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1359                 goto out_free;
1360         }
1361
1362         dev_priv->drm.pdev = pdev;
1363         dev_priv->drm.dev_private = dev_priv;
1364
1365         ret = pci_enable_device(pdev);
1366         if (ret)
1367                 goto out_fini;
1368
1369         pci_set_drvdata(pdev, &dev_priv->drm);
1370         /*
1371          * Disable the system suspend direct complete optimization, which can
1372          * leave the device suspended skipping the driver's suspend handlers
1373          * if the device was already runtime suspended. This is needed due to
1374          * the difference in our runtime and system suspend sequence and
1375          * becaue the HDA driver may require us to enable the audio power
1376          * domain during system suspend.
1377          */
1378         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1379
1380         ret = i915_driver_init_early(dev_priv, ent);
1381         if (ret < 0)
1382                 goto out_pci_disable;
1383
1384         intel_runtime_pm_get(dev_priv);
1385
1386         ret = i915_driver_init_mmio(dev_priv);
1387         if (ret < 0)
1388                 goto out_runtime_pm_put;
1389
1390         ret = i915_driver_init_hw(dev_priv);
1391         if (ret < 0)
1392                 goto out_cleanup_mmio;
1393
1394         /*
1395          * TODO: move the vblank init and parts of modeset init steps into one
1396          * of the i915_driver_init_/i915_driver_register functions according
1397          * to the role/effect of the given init step.
1398          */
1399         if (INTEL_INFO(dev_priv)->num_pipes) {
1400                 ret = drm_vblank_init(&dev_priv->drm,
1401                                       INTEL_INFO(dev_priv)->num_pipes);
1402                 if (ret)
1403                         goto out_cleanup_hw;
1404         }
1405
1406         ret = i915_load_modeset_init(&dev_priv->drm);
1407         if (ret < 0)
1408                 goto out_cleanup_hw;
1409
1410         i915_driver_register(dev_priv);
1411
1412         intel_runtime_pm_enable(dev_priv);
1413
1414         intel_init_ipc(dev_priv);
1415
1416         intel_runtime_pm_put(dev_priv);
1417
1418         i915_welcome_messages(dev_priv);
1419
1420         return 0;
1421
1422 out_cleanup_hw:
1423         i915_driver_cleanup_hw(dev_priv);
1424 out_cleanup_mmio:
1425         i915_driver_cleanup_mmio(dev_priv);
1426 out_runtime_pm_put:
1427         intel_runtime_pm_put(dev_priv);
1428         i915_driver_cleanup_early(dev_priv);
1429 out_pci_disable:
1430         pci_disable_device(pdev);
1431 out_fini:
1432         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1433         drm_dev_fini(&dev_priv->drm);
1434 out_free:
1435         kfree(dev_priv);
1436         return ret;
1437 }
1438
1439 void i915_driver_unload(struct drm_device *dev)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(dev);
1442         struct pci_dev *pdev = dev_priv->drm.pdev;
1443
1444         i915_driver_unregister(dev_priv);
1445
1446         if (i915_gem_suspend(dev_priv))
1447                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1448
1449         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1450
1451         drm_atomic_helper_shutdown(dev);
1452
1453         intel_gvt_cleanup(dev_priv);
1454
1455         intel_modeset_cleanup(dev);
1456
1457         intel_bios_cleanup(dev_priv);
1458
1459         vga_switcheroo_unregister_client(pdev);
1460         vga_client_register(pdev, NULL, NULL, NULL);
1461
1462         intel_csr_ucode_fini(dev_priv);
1463
1464         /* Free error state after interrupts are fully disabled. */
1465         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1466         i915_reset_error_state(dev_priv);
1467
1468         i915_gem_fini(dev_priv);
1469         intel_fbc_cleanup_cfb(dev_priv);
1470
1471         intel_power_domains_fini(dev_priv);
1472
1473         i915_driver_cleanup_hw(dev_priv);
1474         i915_driver_cleanup_mmio(dev_priv);
1475
1476         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1477 }
1478
1479 static void i915_driver_release(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = to_i915(dev);
1482
1483         i915_driver_cleanup_early(dev_priv);
1484         drm_dev_fini(&dev_priv->drm);
1485
1486         kfree(dev_priv);
1487 }
1488
1489 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1490 {
1491         struct drm_i915_private *i915 = to_i915(dev);
1492         int ret;
1493
1494         ret = i915_gem_open(i915, file);
1495         if (ret)
1496                 return ret;
1497
1498         return 0;
1499 }
1500
1501 /**
1502  * i915_driver_lastclose - clean up after all DRM clients have exited
1503  * @dev: DRM device
1504  *
1505  * Take care of cleaning up after all DRM clients have exited.  In the
1506  * mode setting case, we want to restore the kernel's initial mode (just
1507  * in case the last client left us in a bad state).
1508  *
1509  * Additionally, in the non-mode setting case, we'll tear down the GTT
1510  * and DMA structures, since the kernel won't be using them, and clea
1511  * up any GEM state.
1512  */
1513 static void i915_driver_lastclose(struct drm_device *dev)
1514 {
1515         intel_fbdev_restore_mode(dev);
1516         vga_switcheroo_process_delayed_switch();
1517 }
1518
1519 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1520 {
1521         struct drm_i915_file_private *file_priv = file->driver_priv;
1522
1523         mutex_lock(&dev->struct_mutex);
1524         i915_gem_context_close(file);
1525         i915_gem_release(dev, file);
1526         mutex_unlock(&dev->struct_mutex);
1527
1528         kfree(file_priv);
1529 }
1530
1531 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1532 {
1533         struct drm_device *dev = &dev_priv->drm;
1534         struct intel_encoder *encoder;
1535
1536         drm_modeset_lock_all(dev);
1537         for_each_intel_encoder(dev, encoder)
1538                 if (encoder->suspend)
1539                         encoder->suspend(encoder);
1540         drm_modeset_unlock_all(dev);
1541 }
1542
1543 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1544                               bool rpm_resume);
1545 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1546
1547 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1548 {
1549 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1550         if (acpi_target_system_state() < ACPI_STATE_S3)
1551                 return true;
1552 #endif
1553         return false;
1554 }
1555
1556 static int i915_drm_suspend(struct drm_device *dev)
1557 {
1558         struct drm_i915_private *dev_priv = to_i915(dev);
1559         struct pci_dev *pdev = dev_priv->drm.pdev;
1560         pci_power_t opregion_target_state;
1561         int error;
1562
1563         /* ignore lid events during suspend */
1564         mutex_lock(&dev_priv->modeset_restore_lock);
1565         dev_priv->modeset_restore = MODESET_SUSPENDED;
1566         mutex_unlock(&dev_priv->modeset_restore_lock);
1567
1568         disable_rpm_wakeref_asserts(dev_priv);
1569
1570         /* We do a lot of poking in a lot of registers, make sure they work
1571          * properly. */
1572         intel_display_set_init_power(dev_priv, true);
1573
1574         drm_kms_helper_poll_disable(dev);
1575
1576         pci_save_state(pdev);
1577
1578         error = i915_gem_suspend(dev_priv);
1579         if (error) {
1580                 dev_err(&pdev->dev,
1581                         "GEM idle failed, resume might fail\n");
1582                 goto out;
1583         }
1584
1585         intel_display_suspend(dev);
1586
1587         intel_dp_mst_suspend(dev);
1588
1589         intel_runtime_pm_disable_interrupts(dev_priv);
1590         intel_hpd_cancel_work(dev_priv);
1591
1592         intel_suspend_encoders(dev_priv);
1593
1594         intel_suspend_hw(dev_priv);
1595
1596         i915_gem_suspend_gtt_mappings(dev_priv);
1597
1598         i915_save_state(dev_priv);
1599
1600         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1601         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1602
1603         intel_uncore_suspend(dev_priv);
1604         intel_opregion_unregister(dev_priv);
1605
1606         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1607
1608         dev_priv->suspend_count++;
1609
1610         intel_csr_ucode_suspend(dev_priv);
1611
1612 out:
1613         enable_rpm_wakeref_asserts(dev_priv);
1614
1615         return error;
1616 }
1617
1618 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(dev);
1621         struct pci_dev *pdev = dev_priv->drm.pdev;
1622         int ret;
1623
1624         disable_rpm_wakeref_asserts(dev_priv);
1625
1626         intel_display_set_init_power(dev_priv, false);
1627
1628         /*
1629          * In case of firmware assisted context save/restore don't manually
1630          * deinit the power domains. This also means the CSR/DMC firmware will
1631          * stay active, it will power down any HW resources as required and
1632          * also enable deeper system power states that would be blocked if the
1633          * firmware was inactive.
1634          */
1635         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1636             dev_priv->csr.dmc_payload == NULL) {
1637                 intel_power_domains_suspend(dev_priv);
1638                 dev_priv->power_domains_suspended = true;
1639         }
1640
1641         ret = 0;
1642         if (IS_GEN9_LP(dev_priv))
1643                 bxt_enable_dc9(dev_priv);
1644         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1645                 hsw_enable_pc8(dev_priv);
1646         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1647                 ret = vlv_suspend_complete(dev_priv);
1648
1649         if (ret) {
1650                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1651                 if (dev_priv->power_domains_suspended) {
1652                         intel_power_domains_init_hw(dev_priv, true);
1653                         dev_priv->power_domains_suspended = false;
1654                 }
1655
1656                 goto out;
1657         }
1658
1659         pci_disable_device(pdev);
1660         /*
1661          * During hibernation on some platforms the BIOS may try to access
1662          * the device even though it's already in D3 and hang the machine. So
1663          * leave the device in D0 on those platforms and hope the BIOS will
1664          * power down the device properly. The issue was seen on multiple old
1665          * GENs with different BIOS vendors, so having an explicit blacklist
1666          * is inpractical; apply the workaround on everything pre GEN6. The
1667          * platforms where the issue was seen:
1668          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1669          * Fujitsu FSC S7110
1670          * Acer Aspire 1830T
1671          */
1672         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1673                 pci_set_power_state(pdev, PCI_D3hot);
1674
1675 out:
1676         enable_rpm_wakeref_asserts(dev_priv);
1677
1678         return ret;
1679 }
1680
1681 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1682 {
1683         int error;
1684
1685         if (!dev) {
1686                 DRM_ERROR("dev: %p\n", dev);
1687                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1688                 return -ENODEV;
1689         }
1690
1691         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1692                          state.event != PM_EVENT_FREEZE))
1693                 return -EINVAL;
1694
1695         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1696                 return 0;
1697
1698         error = i915_drm_suspend(dev);
1699         if (error)
1700                 return error;
1701
1702         return i915_drm_suspend_late(dev, false);
1703 }
1704
1705 static int i915_drm_resume(struct drm_device *dev)
1706 {
1707         struct drm_i915_private *dev_priv = to_i915(dev);
1708         int ret;
1709
1710         disable_rpm_wakeref_asserts(dev_priv);
1711         intel_sanitize_gt_powersave(dev_priv);
1712
1713         ret = i915_ggtt_enable_hw(dev_priv);
1714         if (ret)
1715                 DRM_ERROR("failed to re-enable GGTT\n");
1716
1717         intel_csr_ucode_resume(dev_priv);
1718
1719         i915_restore_state(dev_priv);
1720         intel_pps_unlock_regs_wa(dev_priv);
1721         intel_opregion_setup(dev_priv);
1722
1723         intel_init_pch_refclk(dev_priv);
1724
1725         /*
1726          * Interrupts have to be enabled before any batches are run. If not the
1727          * GPU will hang. i915_gem_init_hw() will initiate batches to
1728          * update/restore the context.
1729          *
1730          * drm_mode_config_reset() needs AUX interrupts.
1731          *
1732          * Modeset enabling in intel_modeset_init_hw() also needs working
1733          * interrupts.
1734          */
1735         intel_runtime_pm_enable_interrupts(dev_priv);
1736
1737         drm_mode_config_reset(dev);
1738
1739         i915_gem_resume(dev_priv);
1740
1741         intel_modeset_init_hw(dev);
1742         intel_init_clock_gating(dev_priv);
1743
1744         spin_lock_irq(&dev_priv->irq_lock);
1745         if (dev_priv->display.hpd_irq_setup)
1746                 dev_priv->display.hpd_irq_setup(dev_priv);
1747         spin_unlock_irq(&dev_priv->irq_lock);
1748
1749         intel_dp_mst_resume(dev);
1750
1751         intel_display_resume(dev);
1752
1753         drm_kms_helper_poll_enable(dev);
1754
1755         /*
1756          * ... but also need to make sure that hotplug processing
1757          * doesn't cause havoc. Like in the driver load code we don't
1758          * bother with the tiny race here where we might loose hotplug
1759          * notifications.
1760          * */
1761         intel_hpd_init(dev_priv);
1762
1763         intel_opregion_register(dev_priv);
1764
1765         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1766
1767         mutex_lock(&dev_priv->modeset_restore_lock);
1768         dev_priv->modeset_restore = MODESET_DONE;
1769         mutex_unlock(&dev_priv->modeset_restore_lock);
1770
1771         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1772
1773         enable_rpm_wakeref_asserts(dev_priv);
1774
1775         return 0;
1776 }
1777
1778 static int i915_drm_resume_early(struct drm_device *dev)
1779 {
1780         struct drm_i915_private *dev_priv = to_i915(dev);
1781         struct pci_dev *pdev = dev_priv->drm.pdev;
1782         int ret;
1783
1784         /*
1785          * We have a resume ordering issue with the snd-hda driver also
1786          * requiring our device to be power up. Due to the lack of a
1787          * parent/child relationship we currently solve this with an early
1788          * resume hook.
1789          *
1790          * FIXME: This should be solved with a special hdmi sink device or
1791          * similar so that power domains can be employed.
1792          */
1793
1794         /*
1795          * Note that we need to set the power state explicitly, since we
1796          * powered off the device during freeze and the PCI core won't power
1797          * it back up for us during thaw. Powering off the device during
1798          * freeze is not a hard requirement though, and during the
1799          * suspend/resume phases the PCI core makes sure we get here with the
1800          * device powered on. So in case we change our freeze logic and keep
1801          * the device powered we can also remove the following set power state
1802          * call.
1803          */
1804         ret = pci_set_power_state(pdev, PCI_D0);
1805         if (ret) {
1806                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1807                 goto out;
1808         }
1809
1810         /*
1811          * Note that pci_enable_device() first enables any parent bridge
1812          * device and only then sets the power state for this device. The
1813          * bridge enabling is a nop though, since bridge devices are resumed
1814          * first. The order of enabling power and enabling the device is
1815          * imposed by the PCI core as described above, so here we preserve the
1816          * same order for the freeze/thaw phases.
1817          *
1818          * TODO: eventually we should remove pci_disable_device() /
1819          * pci_enable_enable_device() from suspend/resume. Due to how they
1820          * depend on the device enable refcount we can't anyway depend on them
1821          * disabling/enabling the device.
1822          */
1823         if (pci_enable_device(pdev)) {
1824                 ret = -EIO;
1825                 goto out;
1826         }
1827
1828         pci_set_master(pdev);
1829
1830         disable_rpm_wakeref_asserts(dev_priv);
1831
1832         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1833                 ret = vlv_resume_prepare(dev_priv, false);
1834         if (ret)
1835                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1836                           ret);
1837
1838         intel_uncore_resume_early(dev_priv);
1839
1840         if (IS_GEN9_LP(dev_priv)) {
1841                 gen9_sanitize_dc_state(dev_priv);
1842                 bxt_disable_dc9(dev_priv);
1843         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1844                 hsw_disable_pc8(dev_priv);
1845         }
1846
1847         intel_uncore_sanitize(dev_priv);
1848
1849         if (dev_priv->power_domains_suspended)
1850                 intel_power_domains_init_hw(dev_priv, true);
1851         else
1852                 intel_display_set_init_power(dev_priv, true);
1853
1854         i915_gem_sanitize(dev_priv);
1855
1856         enable_rpm_wakeref_asserts(dev_priv);
1857
1858 out:
1859         dev_priv->power_domains_suspended = false;
1860
1861         return ret;
1862 }
1863
1864 static int i915_resume_switcheroo(struct drm_device *dev)
1865 {
1866         int ret;
1867
1868         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1869                 return 0;
1870
1871         ret = i915_drm_resume_early(dev);
1872         if (ret)
1873                 return ret;
1874
1875         return i915_drm_resume(dev);
1876 }
1877
1878 /**
1879  * i915_reset - reset chip after a hang
1880  * @i915: #drm_i915_private to reset
1881  * @stalled_mask: mask of the stalled engines with the guilty requests
1882  * @reason: user error message for why we are resetting
1883  *
1884  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1885  * on failure.
1886  *
1887  * Caller must hold the struct_mutex.
1888  *
1889  * Procedure is fairly simple:
1890  *   - reset the chip using the reset reg
1891  *   - re-init context state
1892  *   - re-init hardware status page
1893  *   - re-init ring buffer
1894  *   - re-init interrupt state
1895  *   - re-init display
1896  */
1897 void i915_reset(struct drm_i915_private *i915,
1898                 unsigned int stalled_mask,
1899                 const char *reason)
1900 {
1901         struct i915_gpu_error *error = &i915->gpu_error;
1902         int ret;
1903         int i;
1904
1905         GEM_TRACE("flags=%lx\n", error->flags);
1906
1907         might_sleep();
1908         lockdep_assert_held(&i915->drm.struct_mutex);
1909         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1910
1911         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1912                 return;
1913
1914         /* Clear any previous failed attempts at recovery. Time to try again. */
1915         if (!i915_gem_unset_wedged(i915))
1916                 goto wakeup;
1917
1918         if (reason)
1919                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1920         error->reset_count++;
1921
1922         disable_irq(i915->drm.irq);
1923         ret = i915_gem_reset_prepare(i915);
1924         if (ret) {
1925                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1926                 goto taint;
1927         }
1928
1929         if (!intel_has_gpu_reset(i915)) {
1930                 if (i915_modparams.reset)
1931                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1932                 else
1933                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1934                 goto error;
1935         }
1936
1937         for (i = 0; i < 3; i++) {
1938                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1939                 if (ret == 0)
1940                         break;
1941
1942                 msleep(100);
1943         }
1944         if (ret) {
1945                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1946                 goto taint;
1947         }
1948
1949         /* Ok, now get things going again... */
1950
1951         /*
1952          * Everything depends on having the GTT running, so we need to start
1953          * there.
1954          */
1955         ret = i915_ggtt_enable_hw(i915);
1956         if (ret) {
1957                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1958                           ret);
1959                 goto error;
1960         }
1961
1962         i915_gem_reset(i915, stalled_mask);
1963         intel_overlay_reset(i915);
1964
1965         /*
1966          * Next we need to restore the context, but we don't use those
1967          * yet either...
1968          *
1969          * Ring buffer needs to be re-initialized in the KMS case, or if X
1970          * was running at the time of the reset (i.e. we weren't VT
1971          * switched away).
1972          */
1973         ret = i915_gem_init_hw(i915);
1974         if (ret) {
1975                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1976                           ret);
1977                 goto error;
1978         }
1979
1980         i915_queue_hangcheck(i915);
1981
1982 finish:
1983         i915_gem_reset_finish(i915);
1984         enable_irq(i915->drm.irq);
1985
1986 wakeup:
1987         clear_bit(I915_RESET_HANDOFF, &error->flags);
1988         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1989         return;
1990
1991 taint:
1992         /*
1993          * History tells us that if we cannot reset the GPU now, we
1994          * never will. This then impacts everything that is run
1995          * subsequently. On failing the reset, we mark the driver
1996          * as wedged, preventing further execution on the GPU.
1997          * We also want to go one step further and add a taint to the
1998          * kernel so that any subsequent faults can be traced back to
1999          * this failure. This is important for CI, where if the
2000          * GPU/driver fails we would like to reboot and restart testing
2001          * rather than continue on into oblivion. For everyone else,
2002          * the system should still plod along, but they have been warned!
2003          */
2004         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2005 error:
2006         i915_gem_set_wedged(i915);
2007         i915_retire_requests(i915);
2008         goto finish;
2009 }
2010
2011 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2012                                         struct intel_engine_cs *engine)
2013 {
2014         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2015 }
2016
2017 /**
2018  * i915_reset_engine - reset GPU engine to recover from a hang
2019  * @engine: engine to reset
2020  * @msg: reason for GPU reset; or NULL for no dev_notice()
2021  *
2022  * Reset a specific GPU engine. Useful if a hang is detected.
2023  * Returns zero on successful reset or otherwise an error code.
2024  *
2025  * Procedure is:
2026  *  - identifies the request that caused the hang and it is dropped
2027  *  - reset engine (which will force the engine to idle)
2028  *  - re-init/configure engine
2029  */
2030 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2031 {
2032         struct i915_gpu_error *error = &engine->i915->gpu_error;
2033         struct i915_request *active_request;
2034         int ret;
2035
2036         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2037         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2038
2039         active_request = i915_gem_reset_prepare_engine(engine);
2040         if (IS_ERR_OR_NULL(active_request)) {
2041                 /* Either the previous reset failed, or we pardon the reset. */
2042                 ret = PTR_ERR(active_request);
2043                 goto out;
2044         }
2045
2046         if (msg)
2047                 dev_notice(engine->i915->drm.dev,
2048                            "Resetting %s for %s\n", engine->name, msg);
2049         error->reset_engine_count[engine->id]++;
2050
2051         if (!engine->i915->guc.execbuf_client)
2052                 ret = intel_gt_reset_engine(engine->i915, engine);
2053         else
2054                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2055         if (ret) {
2056                 /* If we fail here, we expect to fallback to a global reset */
2057                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2058                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2059                                  engine->name, ret);
2060                 goto out;
2061         }
2062
2063         /*
2064          * The request that caused the hang is stuck on elsp, we know the
2065          * active request and can drop it, adjust head to skip the offending
2066          * request to resume executing remaining requests in the queue.
2067          */
2068         i915_gem_reset_engine(engine, active_request, true);
2069
2070         /*
2071          * The engine and its registers (and workarounds in case of render)
2072          * have been reset to their default values. Follow the init_ring
2073          * process to program RING_MODE, HWSP and re-enable submission.
2074          */
2075         ret = engine->init_hw(engine);
2076         if (ret)
2077                 goto out;
2078
2079 out:
2080         i915_gem_reset_finish_engine(engine);
2081         return ret;
2082 }
2083
2084 static int i915_pm_suspend(struct device *kdev)
2085 {
2086         struct pci_dev *pdev = to_pci_dev(kdev);
2087         struct drm_device *dev = pci_get_drvdata(pdev);
2088
2089         if (!dev) {
2090                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2091                 return -ENODEV;
2092         }
2093
2094         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2095                 return 0;
2096
2097         return i915_drm_suspend(dev);
2098 }
2099
2100 static int i915_pm_suspend_late(struct device *kdev)
2101 {
2102         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2103
2104         /*
2105          * We have a suspend ordering issue with the snd-hda driver also
2106          * requiring our device to be power up. Due to the lack of a
2107          * parent/child relationship we currently solve this with an late
2108          * suspend hook.
2109          *
2110          * FIXME: This should be solved with a special hdmi sink device or
2111          * similar so that power domains can be employed.
2112          */
2113         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2114                 return 0;
2115
2116         return i915_drm_suspend_late(dev, false);
2117 }
2118
2119 static int i915_pm_poweroff_late(struct device *kdev)
2120 {
2121         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2122
2123         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2124                 return 0;
2125
2126         return i915_drm_suspend_late(dev, true);
2127 }
2128
2129 static int i915_pm_resume_early(struct device *kdev)
2130 {
2131         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2132
2133         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2134                 return 0;
2135
2136         return i915_drm_resume_early(dev);
2137 }
2138
2139 static int i915_pm_resume(struct device *kdev)
2140 {
2141         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2142
2143         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2144                 return 0;
2145
2146         return i915_drm_resume(dev);
2147 }
2148
2149 /* freeze: before creating the hibernation_image */
2150 static int i915_pm_freeze(struct device *kdev)
2151 {
2152         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2153         int ret;
2154
2155         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2156                 ret = i915_drm_suspend(dev);
2157                 if (ret)
2158                         return ret;
2159         }
2160
2161         ret = i915_gem_freeze(kdev_to_i915(kdev));
2162         if (ret)
2163                 return ret;
2164
2165         return 0;
2166 }
2167
2168 static int i915_pm_freeze_late(struct device *kdev)
2169 {
2170         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2171         int ret;
2172
2173         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2174                 ret = i915_drm_suspend_late(dev, true);
2175                 if (ret)
2176                         return ret;
2177         }
2178
2179         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2180         if (ret)
2181                 return ret;
2182
2183         return 0;
2184 }
2185
2186 /* thaw: called after creating the hibernation image, but before turning off. */
2187 static int i915_pm_thaw_early(struct device *kdev)
2188 {
2189         return i915_pm_resume_early(kdev);
2190 }
2191
2192 static int i915_pm_thaw(struct device *kdev)
2193 {
2194         return i915_pm_resume(kdev);
2195 }
2196
2197 /* restore: called after loading the hibernation image. */
2198 static int i915_pm_restore_early(struct device *kdev)
2199 {
2200         return i915_pm_resume_early(kdev);
2201 }
2202
2203 static int i915_pm_restore(struct device *kdev)
2204 {
2205         return i915_pm_resume(kdev);
2206 }
2207
2208 /*
2209  * Save all Gunit registers that may be lost after a D3 and a subsequent
2210  * S0i[R123] transition. The list of registers needing a save/restore is
2211  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2212  * registers in the following way:
2213  * - Driver: saved/restored by the driver
2214  * - Punit : saved/restored by the Punit firmware
2215  * - No, w/o marking: no need to save/restore, since the register is R/O or
2216  *                    used internally by the HW in a way that doesn't depend
2217  *                    keeping the content across a suspend/resume.
2218  * - Debug : used for debugging
2219  *
2220  * We save/restore all registers marked with 'Driver', with the following
2221  * exceptions:
2222  * - Registers out of use, including also registers marked with 'Debug'.
2223  *   These have no effect on the driver's operation, so we don't save/restore
2224  *   them to reduce the overhead.
2225  * - Registers that are fully setup by an initialization function called from
2226  *   the resume path. For example many clock gating and RPS/RC6 registers.
2227  * - Registers that provide the right functionality with their reset defaults.
2228  *
2229  * TODO: Except for registers that based on the above 3 criteria can be safely
2230  * ignored, we save/restore all others, practically treating the HW context as
2231  * a black-box for the driver. Further investigation is needed to reduce the
2232  * saved/restored registers even further, by following the same 3 criteria.
2233  */
2234 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2235 {
2236         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2237         int i;
2238
2239         /* GAM 0x4000-0x4770 */
2240         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2241         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2242         s->arb_mode             = I915_READ(ARB_MODE);
2243         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2244         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2245
2246         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2247                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2248
2249         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2250         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2251
2252         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2253         s->ecochk               = I915_READ(GAM_ECOCHK);
2254         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2255         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2256
2257         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2258
2259         /* MBC 0x9024-0x91D0, 0x8500 */
2260         s->g3dctl               = I915_READ(VLV_G3DCTL);
2261         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2262         s->mbctl                = I915_READ(GEN6_MBCTL);
2263
2264         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2265         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2266         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2267         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2268         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2269         s->rstctl               = I915_READ(GEN6_RSTCTL);
2270         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2271
2272         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2273         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2274         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2275         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2276         s->ecobus               = I915_READ(ECOBUS);
2277         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2278         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2279         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2280         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2281         s->rcedata              = I915_READ(VLV_RCEDATA);
2282         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2283
2284         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2285         s->gt_imr               = I915_READ(GTIMR);
2286         s->gt_ier               = I915_READ(GTIER);
2287         s->pm_imr               = I915_READ(GEN6_PMIMR);
2288         s->pm_ier               = I915_READ(GEN6_PMIER);
2289
2290         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2291                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2292
2293         /* GT SA CZ domain, 0x100000-0x138124 */
2294         s->tilectl              = I915_READ(TILECTL);
2295         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2296         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2297         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2298         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2299
2300         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2301         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2302         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2303         s->pcbr                 = I915_READ(VLV_PCBR);
2304         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2305
2306         /*
2307          * Not saving any of:
2308          * DFT,         0x9800-0x9EC0
2309          * SARB,        0xB000-0xB1FC
2310          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2311          * PCI CFG
2312          */
2313 }
2314
2315 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2316 {
2317         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2318         u32 val;
2319         int i;
2320
2321         /* GAM 0x4000-0x4770 */
2322         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2323         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2324         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2325         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2326         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2327
2328         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2329                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2330
2331         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2332         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2333
2334         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2335         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2336         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2337         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2338
2339         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2340
2341         /* MBC 0x9024-0x91D0, 0x8500 */
2342         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2343         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2344         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2345
2346         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2347         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2348         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2349         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2350         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2351         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2352         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2353
2354         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2355         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2356         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2357         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2358         I915_WRITE(ECOBUS,              s->ecobus);
2359         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2360         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2361         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2362         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2363         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2364         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2365
2366         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2367         I915_WRITE(GTIMR,               s->gt_imr);
2368         I915_WRITE(GTIER,               s->gt_ier);
2369         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2370         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2371
2372         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2373                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2374
2375         /* GT SA CZ domain, 0x100000-0x138124 */
2376         I915_WRITE(TILECTL,                     s->tilectl);
2377         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2378         /*
2379          * Preserve the GT allow wake and GFX force clock bit, they are not
2380          * be restored, as they are used to control the s0ix suspend/resume
2381          * sequence by the caller.
2382          */
2383         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2384         val &= VLV_GTLC_ALLOWWAKEREQ;
2385         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2386         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2387
2388         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2389         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2390         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2391         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2392
2393         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2394
2395         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2396         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2397         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2398         I915_WRITE(VLV_PCBR,                    s->pcbr);
2399         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2400 }
2401
2402 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2403                                   u32 mask, u32 val)
2404 {
2405         /* The HW does not like us polling for PW_STATUS frequently, so
2406          * use the sleeping loop rather than risk the busy spin within
2407          * intel_wait_for_register().
2408          *
2409          * Transitioning between RC6 states should be at most 2ms (see
2410          * valleyview_enable_rps) so use a 3ms timeout.
2411          */
2412         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2413                         3);
2414 }
2415
2416 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2417 {
2418         u32 val;
2419         int err;
2420
2421         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2422         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2423         if (force_on)
2424                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2425         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2426
2427         if (!force_on)
2428                 return 0;
2429
2430         err = intel_wait_for_register(dev_priv,
2431                                       VLV_GTLC_SURVIVABILITY_REG,
2432                                       VLV_GFX_CLK_STATUS_BIT,
2433                                       VLV_GFX_CLK_STATUS_BIT,
2434                                       20);
2435         if (err)
2436                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2437                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2438
2439         return err;
2440 }
2441
2442 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2443 {
2444         u32 mask;
2445         u32 val;
2446         int err;
2447
2448         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2449         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2450         if (allow)
2451                 val |= VLV_GTLC_ALLOWWAKEREQ;
2452         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2453         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2454
2455         mask = VLV_GTLC_ALLOWWAKEACK;
2456         val = allow ? mask : 0;
2457
2458         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2459         if (err)
2460                 DRM_ERROR("timeout disabling GT waking\n");
2461
2462         return err;
2463 }
2464
2465 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2466                                   bool wait_for_on)
2467 {
2468         u32 mask;
2469         u32 val;
2470
2471         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2472         val = wait_for_on ? mask : 0;
2473
2474         /*
2475          * RC6 transitioning can be delayed up to 2 msec (see
2476          * valleyview_enable_rps), use 3 msec for safety.
2477          *
2478          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2479          * reset and we are trying to force the machine to sleep.
2480          */
2481         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2482                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2483                                  onoff(wait_for_on));
2484 }
2485
2486 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2487 {
2488         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2489                 return;
2490
2491         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2492         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2493 }
2494
2495 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2496 {
2497         u32 mask;
2498         int err;
2499
2500         /*
2501          * Bspec defines the following GT well on flags as debug only, so
2502          * don't treat them as hard failures.
2503          */
2504         vlv_wait_for_gt_wells(dev_priv, false);
2505
2506         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2507         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2508
2509         vlv_check_no_gt_access(dev_priv);
2510
2511         err = vlv_force_gfx_clock(dev_priv, true);
2512         if (err)
2513                 goto err1;
2514
2515         err = vlv_allow_gt_wake(dev_priv, false);
2516         if (err)
2517                 goto err2;
2518
2519         if (!IS_CHERRYVIEW(dev_priv))
2520                 vlv_save_gunit_s0ix_state(dev_priv);
2521
2522         err = vlv_force_gfx_clock(dev_priv, false);
2523         if (err)
2524                 goto err2;
2525
2526         return 0;
2527
2528 err2:
2529         /* For safety always re-enable waking and disable gfx clock forcing */
2530         vlv_allow_gt_wake(dev_priv, true);
2531 err1:
2532         vlv_force_gfx_clock(dev_priv, false);
2533
2534         return err;
2535 }
2536
2537 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2538                                 bool rpm_resume)
2539 {
2540         int err;
2541         int ret;
2542
2543         /*
2544          * If any of the steps fail just try to continue, that's the best we
2545          * can do at this point. Return the first error code (which will also
2546          * leave RPM permanently disabled).
2547          */
2548         ret = vlv_force_gfx_clock(dev_priv, true);
2549
2550         if (!IS_CHERRYVIEW(dev_priv))
2551                 vlv_restore_gunit_s0ix_state(dev_priv);
2552
2553         err = vlv_allow_gt_wake(dev_priv, true);
2554         if (!ret)
2555                 ret = err;
2556
2557         err = vlv_force_gfx_clock(dev_priv, false);
2558         if (!ret)
2559                 ret = err;
2560
2561         vlv_check_no_gt_access(dev_priv);
2562
2563         if (rpm_resume)
2564                 intel_init_clock_gating(dev_priv);
2565
2566         return ret;
2567 }
2568
2569 static int intel_runtime_suspend(struct device *kdev)
2570 {
2571         struct pci_dev *pdev = to_pci_dev(kdev);
2572         struct drm_device *dev = pci_get_drvdata(pdev);
2573         struct drm_i915_private *dev_priv = to_i915(dev);
2574         int ret;
2575
2576         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2577                 return -ENODEV;
2578
2579         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2580                 return -ENODEV;
2581
2582         DRM_DEBUG_KMS("Suspending device\n");
2583
2584         disable_rpm_wakeref_asserts(dev_priv);
2585
2586         /*
2587          * We are safe here against re-faults, since the fault handler takes
2588          * an RPM reference.
2589          */
2590         i915_gem_runtime_suspend(dev_priv);
2591
2592         intel_uc_suspend(dev_priv);
2593
2594         intel_runtime_pm_disable_interrupts(dev_priv);
2595
2596         intel_uncore_suspend(dev_priv);
2597
2598         ret = 0;
2599         if (IS_GEN9_LP(dev_priv)) {
2600                 bxt_display_core_uninit(dev_priv);
2601                 bxt_enable_dc9(dev_priv);
2602         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2603                 hsw_enable_pc8(dev_priv);
2604         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2605                 ret = vlv_suspend_complete(dev_priv);
2606         }
2607
2608         if (ret) {
2609                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2610                 intel_uncore_runtime_resume(dev_priv);
2611
2612                 intel_runtime_pm_enable_interrupts(dev_priv);
2613
2614                 intel_uc_resume(dev_priv);
2615
2616                 i915_gem_init_swizzling(dev_priv);
2617                 i915_gem_restore_fences(dev_priv);
2618
2619                 enable_rpm_wakeref_asserts(dev_priv);
2620
2621                 return ret;
2622         }
2623
2624         enable_rpm_wakeref_asserts(dev_priv);
2625         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2626
2627         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2628                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2629
2630         dev_priv->runtime_pm.suspended = true;
2631
2632         /*
2633          * FIXME: We really should find a document that references the arguments
2634          * used below!
2635          */
2636         if (IS_BROADWELL(dev_priv)) {
2637                 /*
2638                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2639                  * being detected, and the call we do at intel_runtime_resume()
2640                  * won't be able to restore them. Since PCI_D3hot matches the
2641                  * actual specification and appears to be working, use it.
2642                  */
2643                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2644         } else {
2645                 /*
2646                  * current versions of firmware which depend on this opregion
2647                  * notification have repurposed the D1 definition to mean
2648                  * "runtime suspended" vs. what you would normally expect (D3)
2649                  * to distinguish it from notifications that might be sent via
2650                  * the suspend path.
2651                  */
2652                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2653         }
2654
2655         assert_forcewakes_inactive(dev_priv);
2656
2657         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2658                 intel_hpd_poll_init(dev_priv);
2659
2660         DRM_DEBUG_KMS("Device suspended\n");
2661         return 0;
2662 }
2663
2664 static int intel_runtime_resume(struct device *kdev)
2665 {
2666         struct pci_dev *pdev = to_pci_dev(kdev);
2667         struct drm_device *dev = pci_get_drvdata(pdev);
2668         struct drm_i915_private *dev_priv = to_i915(dev);
2669         int ret = 0;
2670
2671         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2672                 return -ENODEV;
2673
2674         DRM_DEBUG_KMS("Resuming device\n");
2675
2676         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2677         disable_rpm_wakeref_asserts(dev_priv);
2678
2679         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2680         dev_priv->runtime_pm.suspended = false;
2681         if (intel_uncore_unclaimed_mmio(dev_priv))
2682                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2683
2684         if (IS_GEN9_LP(dev_priv)) {
2685                 bxt_disable_dc9(dev_priv);
2686                 bxt_display_core_init(dev_priv, true);
2687                 if (dev_priv->csr.dmc_payload &&
2688                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2689                         gen9_enable_dc5(dev_priv);
2690         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2691                 hsw_disable_pc8(dev_priv);
2692         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2693                 ret = vlv_resume_prepare(dev_priv, true);
2694         }
2695
2696         intel_uncore_runtime_resume(dev_priv);
2697
2698         intel_runtime_pm_enable_interrupts(dev_priv);
2699
2700         intel_uc_resume(dev_priv);
2701
2702         /*
2703          * No point of rolling back things in case of an error, as the best
2704          * we can do is to hope that things will still work (and disable RPM).
2705          */
2706         i915_gem_init_swizzling(dev_priv);
2707         i915_gem_restore_fences(dev_priv);
2708
2709         /*
2710          * On VLV/CHV display interrupts are part of the display
2711          * power well, so hpd is reinitialized from there. For
2712          * everyone else do it here.
2713          */
2714         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2715                 intel_hpd_init(dev_priv);
2716
2717         intel_enable_ipc(dev_priv);
2718
2719         enable_rpm_wakeref_asserts(dev_priv);
2720
2721         if (ret)
2722                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2723         else
2724                 DRM_DEBUG_KMS("Device resumed\n");
2725
2726         return ret;
2727 }
2728
2729 const struct dev_pm_ops i915_pm_ops = {
2730         /*
2731          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2732          * PMSG_RESUME]
2733          */
2734         .suspend = i915_pm_suspend,
2735         .suspend_late = i915_pm_suspend_late,
2736         .resume_early = i915_pm_resume_early,
2737         .resume = i915_pm_resume,
2738
2739         /*
2740          * S4 event handlers
2741          * @freeze, @freeze_late    : called (1) before creating the
2742          *                            hibernation image [PMSG_FREEZE] and
2743          *                            (2) after rebooting, before restoring
2744          *                            the image [PMSG_QUIESCE]
2745          * @thaw, @thaw_early       : called (1) after creating the hibernation
2746          *                            image, before writing it [PMSG_THAW]
2747          *                            and (2) after failing to create or
2748          *                            restore the image [PMSG_RECOVER]
2749          * @poweroff, @poweroff_late: called after writing the hibernation
2750          *                            image, before rebooting [PMSG_HIBERNATE]
2751          * @restore, @restore_early : called after rebooting and restoring the
2752          *                            hibernation image [PMSG_RESTORE]
2753          */
2754         .freeze = i915_pm_freeze,
2755         .freeze_late = i915_pm_freeze_late,
2756         .thaw_early = i915_pm_thaw_early,
2757         .thaw = i915_pm_thaw,
2758         .poweroff = i915_pm_suspend,
2759         .poweroff_late = i915_pm_poweroff_late,
2760         .restore_early = i915_pm_restore_early,
2761         .restore = i915_pm_restore,
2762
2763         /* S0ix (via runtime suspend) event handlers */
2764         .runtime_suspend = intel_runtime_suspend,
2765         .runtime_resume = intel_runtime_resume,
2766 };
2767
2768 static const struct vm_operations_struct i915_gem_vm_ops = {
2769         .fault = i915_gem_fault,
2770         .open = drm_gem_vm_open,
2771         .close = drm_gem_vm_close,
2772 };
2773
2774 static const struct file_operations i915_driver_fops = {
2775         .owner = THIS_MODULE,
2776         .open = drm_open,
2777         .release = drm_release,
2778         .unlocked_ioctl = drm_ioctl,
2779         .mmap = drm_gem_mmap,
2780         .poll = drm_poll,
2781         .read = drm_read,
2782         .compat_ioctl = i915_compat_ioctl,
2783         .llseek = noop_llseek,
2784 };
2785
2786 static int
2787 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2788                           struct drm_file *file)
2789 {
2790         return -ENODEV;
2791 }
2792
2793 static const struct drm_ioctl_desc i915_ioctls[] = {
2794         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2795         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2796         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2797         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2798         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2799         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2800         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2801         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2802         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2803         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2804         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2805         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2806         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2807         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2808         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2809         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2810         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2811         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2812         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2813         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2814         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2815         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2816         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2818         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2819         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2820         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2821         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2822         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2823         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2824         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2825         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2826         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2832         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2837         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2838         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2844         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2848         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2849         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2850 };
2851
2852 static struct drm_driver driver = {
2853         /* Don't use MTRRs here; the Xserver or userspace app should
2854          * deal with them for Intel hardware.
2855          */
2856         .driver_features =
2857             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2858             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2859         .release = i915_driver_release,
2860         .open = i915_driver_open,
2861         .lastclose = i915_driver_lastclose,
2862         .postclose = i915_driver_postclose,
2863
2864         .gem_close_object = i915_gem_close_object,
2865         .gem_free_object_unlocked = i915_gem_free_object,
2866         .gem_vm_ops = &i915_gem_vm_ops,
2867
2868         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2869         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2870         .gem_prime_export = i915_gem_prime_export,
2871         .gem_prime_import = i915_gem_prime_import,
2872
2873         .dumb_create = i915_gem_dumb_create,
2874         .dumb_map_offset = i915_gem_mmap_gtt,
2875         .ioctls = i915_ioctls,
2876         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2877         .fops = &i915_driver_fops,
2878         .name = DRIVER_NAME,
2879         .desc = DRIVER_DESC,
2880         .date = DRIVER_DATE,
2881         .major = DRIVER_MAJOR,
2882         .minor = DRIVER_MINOR,
2883         .patchlevel = DRIVER_PATCHLEVEL,
2884 };
2885
2886 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2887 #include "selftests/mock_drm.c"
2888 #endif