drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/drm_atomic_helper.h>
  47 #include <drm/i915_drm.h>
  48
  49 #include "i915_drv.h"
  50 #include "i915_trace.h"
  51 #include "i915_pmu.h"
  52 #include "i915_query.h"
  53 #include "i915_vgpu.h"
  54 #include "intel_drv.h"
  55 #include "intel_uc.h"
  56
  57 static struct drm_driver driver;
  58
  59 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  60 static unsigned int i915_load_fail_count;
  61
  62 bool __i915_inject_load_failure(const char *func, int line)
  63 {
  64         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  65                 return false;
  66
  67         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  68                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  69                          i915_modparams.inject_load_failure, func, line);
  70                 i915_modparams.inject_load_failure = 0;
  71                 return true;
  72         }
  73
  74         return false;
  75 }
  76
  77 bool i915_error_injected(void)
  78 {
  79         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  80 }
  81
  82 #endif
  83
  84 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  85 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  86                     "providing the dmesg log by booting with drm.debug=0xf"
  87
  88 void
  89 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  90               const char *fmt, ...)
  91 {
  92         static bool shown_bug_once;
  93         struct device *kdev = dev_priv->drm.dev;
  94         bool is_error = level[1] <= KERN_ERR[1];
  95         bool is_debug = level[1] == KERN_DEBUG[1];
  96         struct va_format vaf;
  97         va_list args;
  98
  99         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 100                 return;
 101
 102         va_start(args, fmt);
 103
 104         vaf.fmt = fmt;
 105         vaf.va = &args;
 106
 107         if (is_error)
 108                 dev_printk(level, kdev, "%pV", &vaf);
 109         else
 110                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 111                            __builtin_return_address(0), &vaf);
 112
 113         va_end(args);
 114
 115         if (is_error && !shown_bug_once) {
 116                 /*
 117                  * Ask the user to file a bug report for the error, except
 118                  * if they may have caused the bug by fiddling with unsafe
 119                  * module parameters.
 120                  */
 121                 if (!test_taint(TAINT_USER))
 122                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 123                 shown_bug_once = true;
 124         }
 125 }
 126
 127 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 128 static enum intel_pch
 129 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 130 {
 131         switch (id) {
 132         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 133                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 134                 WARN_ON(!IS_GEN5(dev_priv));
 135                 return PCH_IBX;
 136         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 137                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 138                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 139                 return PCH_CPT;
 140         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 141                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 142                 WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv));
 143                 /* PantherPoint is CPT compatible */
 144                 return PCH_CPT;
 145         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 146                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 147                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 148                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 149                 return PCH_LPT;
 150         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 151                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 152                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 153                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 154                 return PCH_LPT;
 155         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 156                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 157                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 158                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 159                 /* WildcatPoint is LPT compatible */
 160                 return PCH_LPT;
 161         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 162                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 163                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 164                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 165                 /* WildcatPoint is LPT compatible */
 166                 return PCH_LPT;
 167         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 168                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 169                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 170                 return PCH_SPT;
 171         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 172                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 173                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 174                 return PCH_SPT;
 175         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 176                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 177                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 178                         !IS_COFFEELAKE(dev_priv));
 179                 return PCH_KBP;
 180         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 181                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 182                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 183                 return PCH_CNP;
 184         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 185                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 186                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 187                 return PCH_CNP;
 188         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 189                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 190                 WARN_ON(!IS_ICELAKE(dev_priv));
 191                 return PCH_ICP;
 192         default:
 193                 return PCH_NONE;
 194         }
 195 }
 196
 197 static bool intel_is_virt_pch(unsigned short id,
 198                               unsigned short svendor, unsigned short sdevice)
 199 {
 200         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 201                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 202                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 203                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 204                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 205 }
 206
 207 static unsigned short
 208 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 209 {
 210         unsigned short id = 0;
 211
 212         /*
 213          * In a virtualized passthrough environment we can be in a
 214          * setup where the ISA bridge is not able to be passed through.
 215          * In this case, a south bridge can be emulated and we have to
 216          * make an educated guess as to which PCH is really there.
 217          */
 218
 219         if (IS_GEN5(dev_priv))
 220                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 221         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
 222                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 223         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 224                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 225         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 226                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 227         else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
 228                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 229         else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
 230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 231         else if (IS_ICELAKE(dev_priv))
 232                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 233
 234         if (id)
 235                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 236         else
 237                 DRM_DEBUG_KMS("Assuming no PCH\n");
 238
 239         return id;
 240 }
 241
 242 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 243 {
 244         struct pci_dev *pch = NULL;
 245
 246         /*
 247          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 248          * make graphics device passthrough work easy for VMM, that only
 249          * need to expose ISA bridge to let driver know the real hardware
 250          * underneath. This is a requirement from virtualization team.
 251          *
 252          * In some virtualized environments (e.g. XEN), there is irrelevant
 253          * ISA bridge in the system. To work reliably, we should scan trhough
 254          * all the ISA bridge devices and check for the first match, instead
 255          * of only checking the first one.
 256          */
 257         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 258                 unsigned short id;
 259                 enum intel_pch pch_type;
 260
 261                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 262                         continue;
 263
 264                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 265
 266                 pch_type = intel_pch_type(dev_priv, id);
 267                 if (pch_type != PCH_NONE) {
 268                         dev_priv->pch_type = pch_type;
 269                         dev_priv->pch_id = id;
 270                         break;
 271                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 272                                          pch->subsystem_device)) {
 273                         id = intel_virt_detect_pch(dev_priv);
 274                         pch_type = intel_pch_type(dev_priv, id);
 275
 276                         /* Sanity check virtual PCH id */
 277                         if (WARN_ON(id && pch_type == PCH_NONE))
 278                                 id = 0;
 279
 280                         dev_priv->pch_type = pch_type;
 281                         dev_priv->pch_id = id;
 282                         break;
 283                 }
 284         }
 285
 286         /*
 287          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 288          * display.
 289          */
 290         if (pch && INTEL_INFO(dev_priv)->num_pipes == 0) {
 291                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 292                 dev_priv->pch_type = PCH_NOP;
 293                 dev_priv->pch_id = 0;
 294         }
 295
 296         if (!pch)
 297                 DRM_DEBUG_KMS("No PCH found.\n");
 298
 299         pci_dev_put(pch);
 300 }
 301
 302 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 303                                struct drm_file *file_priv)
 304 {
 305         struct drm_i915_private *dev_priv = to_i915(dev);
 306         struct pci_dev *pdev = dev_priv->drm.pdev;
 307         drm_i915_getparam_t *param = data;
 308         int value;
 309
 310         switch (param->param) {
 311         case I915_PARAM_IRQ_ACTIVE:
 312         case I915_PARAM_ALLOW_BATCHBUFFER:
 313         case I915_PARAM_LAST_DISPATCH:
 314         case I915_PARAM_HAS_EXEC_CONSTANTS:
 315                 /* Reject all old ums/dri params. */
 316                 return -ENODEV;
 317         case I915_PARAM_CHIPSET_ID:
 318                 value = pdev->device;
 319                 break;
 320         case I915_PARAM_REVISION:
 321                 value = pdev->revision;
 322                 break;
 323         case I915_PARAM_NUM_FENCES_AVAIL:
 324                 value = dev_priv->num_fence_regs;
 325                 break;
 326         case I915_PARAM_HAS_OVERLAY:
 327                 value = dev_priv->overlay ? 1 : 0;
 328                 break;
 329         case I915_PARAM_HAS_BSD:
 330                 value = !!dev_priv->engine[VCS];
 331                 break;
 332         case I915_PARAM_HAS_BLT:
 333                 value = !!dev_priv->engine[BCS];
 334                 break;
 335         case I915_PARAM_HAS_VEBOX:
 336                 value = !!dev_priv->engine[VECS];
 337                 break;
 338         case I915_PARAM_HAS_BSD2:
 339                 value = !!dev_priv->engine[VCS2];
 340                 break;
 341         case I915_PARAM_HAS_LLC:
 342                 value = HAS_LLC(dev_priv);
 343                 break;
 344         case I915_PARAM_HAS_WT:
 345                 value = HAS_WT(dev_priv);
 346                 break;
 347         case I915_PARAM_HAS_ALIASING_PPGTT:
 348                 value = USES_PPGTT(dev_priv);
 349                 break;
 350         case I915_PARAM_HAS_SEMAPHORES:
 351                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
 352                 break;
 353         case I915_PARAM_HAS_SECURE_BATCHES:
 354                 value = capable(CAP_SYS_ADMIN);
 355                 break;
 356         case I915_PARAM_CMD_PARSER_VERSION:
 357                 value = i915_cmd_parser_get_version(dev_priv);
 358                 break;
 359         case I915_PARAM_SUBSLICE_TOTAL:
 360                 value = sseu_subslice_total(&INTEL_INFO(dev_priv)->sseu);
 361                 if (!value)
 362                         return -ENODEV;
 363                 break;
 364         case I915_PARAM_EU_TOTAL:
 365                 value = INTEL_INFO(dev_priv)->sseu.eu_total;
 366                 if (!value)
 367                         return -ENODEV;
 368                 break;
 369         case I915_PARAM_HAS_GPU_RESET:
 370                 value = i915_modparams.enable_hangcheck &&
 371                         intel_has_gpu_reset(dev_priv);
 372                 if (value && intel_has_reset_engine(dev_priv))
 373                         value = 2;
 374                 break;
 375         case I915_PARAM_HAS_RESOURCE_STREAMER:
 376                 value = HAS_RESOURCE_STREAMER(dev_priv);
 377                 break;
 378         case I915_PARAM_HAS_POOLED_EU:
 379                 value = HAS_POOLED_EU(dev_priv);
 380                 break;
 381         case I915_PARAM_MIN_EU_IN_POOL:
 382                 value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
 383                 break;
 384         case I915_PARAM_HUC_STATUS:
 385                 value = intel_huc_check_status(&dev_priv->huc);
 386                 if (value < 0)
 387                         return value;
 388                 break;
 389         case I915_PARAM_MMAP_GTT_VERSION:
 390                 /* Though we've started our numbering from 1, and so class all
 391                  * earlier versions as 0, in effect their value is undefined as
 392                  * the ioctl will report EINVAL for the unknown param!
 393                  */
 394                 value = i915_gem_mmap_gtt_version();
 395                 break;
 396         case I915_PARAM_HAS_SCHEDULER:
 397                 value = dev_priv->caps.scheduler;
 398                 break;
 399
 400         case I915_PARAM_MMAP_VERSION:
 401                 /* Remember to bump this if the version changes! */
 402         case I915_PARAM_HAS_GEM:
 403         case I915_PARAM_HAS_PAGEFLIPPING:
 404         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 405         case I915_PARAM_HAS_RELAXED_FENCING:
 406         case I915_PARAM_HAS_COHERENT_RINGS:
 407         case I915_PARAM_HAS_RELAXED_DELTA:
 408         case I915_PARAM_HAS_GEN7_SOL_RESET:
 409         case I915_PARAM_HAS_WAIT_TIMEOUT:
 410         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 411         case I915_PARAM_HAS_PINNED_BATCHES:
 412         case I915_PARAM_HAS_EXEC_NO_RELOC:
 413         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 414         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 415         case I915_PARAM_HAS_EXEC_SOFTPIN:
 416         case I915_PARAM_HAS_EXEC_ASYNC:
 417         case I915_PARAM_HAS_EXEC_FENCE:
 418         case I915_PARAM_HAS_EXEC_CAPTURE:
 419         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 420         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 421                 /* For the time being all of these are always true;
 422                  * if some supported hardware does not have one of these
 423                  * features this value needs to be provided from
 424                  * INTEL_INFO(), a feature macro, or similar.
 425                  */
 426                 value = 1;
 427                 break;
 428         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 429                 value = intel_engines_has_context_isolation(dev_priv);
 430                 break;
 431         case I915_PARAM_SLICE_MASK:
 432                 value = INTEL_INFO(dev_priv)->sseu.slice_mask;
 433                 if (!value)
 434                         return -ENODEV;
 435                 break;
 436         case I915_PARAM_SUBSLICE_MASK:
 437                 value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 438                 if (!value)
 439                         return -ENODEV;
 440                 break;
 441         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 442                 value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz;
 443                 break;
 444         case I915_PARAM_MMAP_GTT_COHERENT:
 445                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 446                 break;
 447         default:
 448                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 449                 return -EINVAL;
 450         }
 451
 452         if (put_user(value, param->value))
 453                 return -EFAULT;
 454
 455         return 0;
 456 }
 457
 458 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 459 {
 460         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 461
 462         dev_priv->bridge_dev =
 463                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 464         if (!dev_priv->bridge_dev) {
 465                 DRM_ERROR("bridge device not found\n");
 466                 return -1;
 467         }
 468         return 0;
 469 }
 470
 471 /* Allocate space for the MCH regs if needed, return nonzero on error */
 472 static int
 473 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 474 {
 475         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 476         u32 temp_lo, temp_hi = 0;
 477         u64 mchbar_addr;
 478         int ret;
 479
 480         if (INTEL_GEN(dev_priv) >= 4)
 481                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 482         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 483         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 484
 485         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 486 #ifdef CONFIG_PNP
 487         if (mchbar_addr &&
 488             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 489                 return 0;
 490 #endif
 491
 492         /* Get some space for it */
 493         dev_priv->mch_res.name = "i915 MCHBAR";
 494         dev_priv->mch_res.flags = IORESOURCE_MEM;
 495         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 496                                      &dev_priv->mch_res,
 497                                      MCHBAR_SIZE, MCHBAR_SIZE,
 498                                      PCIBIOS_MIN_MEM,
 499                                      0, pcibios_align_resource,
 500                                      dev_priv->bridge_dev);
 501         if (ret) {
 502                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 503                 dev_priv->mch_res.start = 0;
 504                 return ret;
 505         }
 506
 507         if (INTEL_GEN(dev_priv) >= 4)
 508                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 509                                        upper_32_bits(dev_priv->mch_res.start));
 510
 511         pci_write_config_dword(dev_priv->bridge_dev, reg,
 512                                lower_32_bits(dev_priv->mch_res.start));
 513         return 0;
 514 }
 515
 516 /* Setup MCHBAR if possible, return true if we should disable it again */
 517 static void
 518 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 519 {
 520         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 521         u32 temp;
 522         bool enabled;
 523
 524         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 525                 return;
 526
 527         dev_priv->mchbar_need_disable = false;
 528
 529         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 530                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 531                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 532         } else {
 533                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 534                 enabled = temp & 1;
 535         }
 536
 537         /* If it's already enabled, don't have to do anything */
 538         if (enabled)
 539                 return;
 540
 541         if (intel_alloc_mchbar_resource(dev_priv))
 542                 return;
 543
 544         dev_priv->mchbar_need_disable = true;
 545
 546         /* Space is allocated or reserved, so enable it. */
 547         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 548                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 549                                        temp | DEVEN_MCHBAR_EN);
 550         } else {
 551                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 552                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 553         }
 554 }
 555
 556 static void
 557 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 558 {
 559         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 560
 561         if (dev_priv->mchbar_need_disable) {
 562                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 563                         u32 deven_val;
 564
 565                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 566                                               &deven_val);
 567                         deven_val &= ~DEVEN_MCHBAR_EN;
 568                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 569                                                deven_val);
 570                 } else {
 571                         u32 mchbar_val;
 572
 573                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 574                                               &mchbar_val);
 575                         mchbar_val &= ~1;
 576                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 577                                                mchbar_val);
 578                 }
 579         }
 580
 581         if (dev_priv->mch_res.start)
 582                 release_resource(&dev_priv->mch_res);
 583 }
 584
 585 /* true = enable decode, false = disable decoder */
 586 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 587 {
 588         struct drm_i915_private *dev_priv = cookie;
 589
 590         intel_modeset_vga_set_state(dev_priv, state);
 591         if (state)
 592                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 593                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 594         else
 595                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 596 }
 597
 598 static int i915_resume_switcheroo(struct drm_device *dev);
 599 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 600
 601 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 602 {
 603         struct drm_device *dev = pci_get_drvdata(pdev);
 604         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 605
 606         if (state == VGA_SWITCHEROO_ON) {
 607                 pr_info("switched on\n");
 608                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 609                 /* i915 resume handler doesn't set to D0 */
 610                 pci_set_power_state(pdev, PCI_D0);
 611                 i915_resume_switcheroo(dev);
 612                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 613         } else {
 614                 pr_info("switched off\n");
 615                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 616                 i915_suspend_switcheroo(dev, pmm);
 617                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 618         }
 619 }
 620
 621 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 622 {
 623         struct drm_device *dev = pci_get_drvdata(pdev);
 624
 625         /*
 626          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 627          * locking inversion with the driver load path. And the access here is
 628          * completely racy anyway. So don't bother with locking for now.
 629          */
 630         return dev->open_count == 0;
 631 }
 632
 633 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 634         .set_gpu_state = i915_switcheroo_set_state,
 635         .reprobe = NULL,
 636         .can_switch = i915_switcheroo_can_switch,
 637 };
 638
 639 static int i915_load_modeset_init(struct drm_device *dev)
 640 {
 641         struct drm_i915_private *dev_priv = to_i915(dev);
 642         struct pci_dev *pdev = dev_priv->drm.pdev;
 643         int ret;
 644
 645         if (i915_inject_load_failure())
 646                 return -ENODEV;
 647
 648         intel_bios_init(dev_priv);
 649
 650         /* If we have > 1 VGA cards, then we need to arbitrate access
 651          * to the common VGA resources.
 652          *
 653          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 654          * then we do not take part in VGA arbitration and the
 655          * vga_client_register() fails with -ENODEV.
 656          */
 657         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 658         if (ret && ret != -ENODEV)
 659                 goto out;
 660
 661         intel_register_dsm_handler();
 662
 663         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 664         if (ret)
 665                 goto cleanup_vga_client;
 666
 667         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 668         intel_update_rawclk(dev_priv);
 669
 670         intel_power_domains_init_hw(dev_priv, false);
 671
 672         intel_csr_ucode_init(dev_priv);
 673
 674         ret = intel_irq_install(dev_priv);
 675         if (ret)
 676                 goto cleanup_csr;
 677
 678         intel_setup_gmbus(dev_priv);
 679
 680         /* Important: The output setup functions called by modeset_init need
 681          * working irqs for e.g. gmbus and dp aux transfers. */
 682         ret = intel_modeset_init(dev);
 683         if (ret)
 684                 goto cleanup_irq;
 685
 686         ret = i915_gem_init(dev_priv);
 687         if (ret)
 688                 goto cleanup_modeset;
 689
 690         intel_setup_overlay(dev_priv);
 691
 692         if (INTEL_INFO(dev_priv)->num_pipes == 0)
 693                 return 0;
 694
 695         ret = intel_fbdev_init(dev);
 696         if (ret)
 697                 goto cleanup_gem;
 698
 699         /* Only enable hotplug handling once the fbdev is fully set up. */
 700         intel_hpd_init(dev_priv);
 701
 702         return 0;
 703
 704 cleanup_gem:
 705         if (i915_gem_suspend(dev_priv))
 706                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 707         i915_gem_fini(dev_priv);
 708 cleanup_modeset:
 709         intel_modeset_cleanup(dev);
 710 cleanup_irq:
 711         drm_irq_uninstall(dev);
 712         intel_teardown_gmbus(dev_priv);
 713 cleanup_csr:
 714         intel_csr_ucode_fini(dev_priv);
 715         intel_power_domains_fini(dev_priv);
 716         vga_switcheroo_unregister_client(pdev);
 717 cleanup_vga_client:
 718         vga_client_register(pdev, NULL, NULL, NULL);
 719 out:
 720         return ret;
 721 }
 722
 723 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 724 {
 725         struct apertures_struct *ap;
 726         struct pci_dev *pdev = dev_priv->drm.pdev;
 727         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 728         bool primary;
 729         int ret;
 730
 731         ap = alloc_apertures(1);
 732         if (!ap)
 733                 return -ENOMEM;
 734
 735         ap->ranges[0].base = ggtt->gmadr.start;
 736         ap->ranges[0].size = ggtt->mappable_end;
 737
 738         primary =
 739                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 740
 741         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 742
 743         kfree(ap);
 744
 745         return ret;
 746 }
 747
 748 #if !defined(CONFIG_VGA_CONSOLE)
 749 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 750 {
 751         return 0;
 752 }
 753 #elif !defined(CONFIG_DUMMY_CONSOLE)
 754 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 755 {
 756         return -ENODEV;
 757 }
 758 #else
 759 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 760 {
 761         int ret = 0;
 762
 763         DRM_INFO("Replacing VGA console driver\n");
 764
 765         console_lock();
 766         if (con_is_bound(&vga_con))
 767                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 768         if (ret == 0) {
 769                 ret = do_unregister_con_driver(&vga_con);
 770
 771                 /* Ignore "already unregistered". */
 772                 if (ret == -ENODEV)
 773                         ret = 0;
 774         }
 775         console_unlock();
 776
 777         return ret;
 778 }
 779 #endif
 780
 781 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 782 {
 783         /*
 784          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 785          * CHV x1 PHY (DP/HDMI D)
 786          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 787          */
 788         if (IS_CHERRYVIEW(dev_priv)) {
 789                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 790                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 791         } else if (IS_VALLEYVIEW(dev_priv)) {
 792                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 793         }
 794 }
 795
 796 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 797 {
 798         /*
 799          * The i915 workqueue is primarily used for batched retirement of
 800          * requests (and thus managing bo) once the task has been completed
 801          * by the GPU. i915_retire_requests() is called directly when we
 802          * need high-priority retirement, such as waiting for an explicit
 803          * bo.
 804          *
 805          * It is also used for periodic low-priority events, such as
 806          * idle-timers and recording error state.
 807          *
 808          * All tasks on the workqueue are expected to acquire the dev mutex
 809          * so there is no point in running more than one instance of the
 810          * workqueue at any time.  Use an ordered one.
 811          */
 812         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 813         if (dev_priv->wq == NULL)
 814                 goto out_err;
 815
 816         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 817         if (dev_priv->hotplug.dp_wq == NULL)
 818                 goto out_free_wq;
 819
 820         return 0;
 821
 822 out_free_wq:
 823         destroy_workqueue(dev_priv->wq);
 824 out_err:
 825         DRM_ERROR("Failed to allocate workqueues.\n");
 826
 827         return -ENOMEM;
 828 }
 829
 830 static void i915_engines_cleanup(struct drm_i915_private *i915)
 831 {
 832         struct intel_engine_cs *engine;
 833         enum intel_engine_id id;
 834
 835         for_each_engine(engine, i915, id)
 836                 kfree(engine);
 837 }
 838
 839 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 840 {
 841         destroy_workqueue(dev_priv->hotplug.dp_wq);
 842         destroy_workqueue(dev_priv->wq);
 843 }
 844
 845 /*
 846  * We don't keep the workarounds for pre-production hardware, so we expect our
 847  * driver to fail on these machines in one way or another. A little warning on
 848  * dmesg may help both the user and the bug triagers.
 849  *
 850  * Our policy for removing pre-production workarounds is to keep the
 851  * current gen workarounds as a guide to the bring-up of the next gen
 852  * (workarounds have a habit of persisting!). Anything older than that
 853  * should be removed along with the complications they introduce.
 854  */
 855 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 856 {
 857         bool pre = false;
 858
 859         pre |= IS_HSW_EARLY_SDV(dev_priv);
 860         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 861         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 862
 863         if (pre) {
 864                 DRM_ERROR("This is a pre-production stepping. "
 865                           "It may not be fully functional.\n");
 866                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 867         }
 868 }
 869
 870 /**
 871  * i915_driver_init_early - setup state not requiring device access
 872  * @dev_priv: device private
 873  * @ent: the matching pci_device_id
 874  *
 875  * Initialize everything that is a "SW-only" state, that is state not
 876  * requiring accessing the device or exposing the driver via kernel internal
 877  * or userspace interfaces. Example steps belonging here: lock initialization,
 878  * system memory allocation, setting up device specific attributes and
 879  * function hooks not requiring accessing the device.
 880  */
 881 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 882                                   const struct pci_device_id *ent)
 883 {
 884         const struct intel_device_info *match_info =
 885                 (struct intel_device_info *)ent->driver_data;
 886         struct intel_device_info *device_info;
 887         int ret = 0;
 888
 889         if (i915_inject_load_failure())
 890                 return -ENODEV;
 891
 892         /* Setup the write-once "constant" device info */
 893         device_info = mkwrite_device_info(dev_priv);
 894         memcpy(device_info, match_info, sizeof(*device_info));
 895         device_info->device_id = dev_priv->drm.pdev->device;
 896
 897         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
 898                      sizeof(device_info->platform_mask) * BITS_PER_BYTE);
 899         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 900         spin_lock_init(&dev_priv->irq_lock);
 901         spin_lock_init(&dev_priv->gpu_error.lock);
 902         mutex_init(&dev_priv->backlight_lock);
 903         spin_lock_init(&dev_priv->uncore.lock);
 904
 905         mutex_init(&dev_priv->sb_lock);
 906         mutex_init(&dev_priv->av_mutex);
 907         mutex_init(&dev_priv->wm.wm_mutex);
 908         mutex_init(&dev_priv->pps_mutex);
 909
 910         i915_memcpy_init_early(dev_priv);
 911
 912         ret = i915_workqueues_init(dev_priv);
 913         if (ret < 0)
 914                 goto err_engines;
 915
 916         ret = i915_gem_init_early(dev_priv);
 917         if (ret < 0)
 918                 goto err_workqueues;
 919
 920         /* This must be called before any calls to HAS_PCH_* */
 921         intel_detect_pch(dev_priv);
 922
 923         intel_wopcm_init_early(&dev_priv->wopcm);
 924         intel_uc_init_early(dev_priv);
 925         intel_pm_setup(dev_priv);
 926         intel_init_dpio(dev_priv);
 927         intel_power_domains_init(dev_priv);
 928         intel_irq_init(dev_priv);
 929         intel_hangcheck_init(dev_priv);
 930         intel_init_display_hooks(dev_priv);
 931         intel_init_clock_gating_hooks(dev_priv);
 932         intel_init_audio_hooks(dev_priv);
 933         intel_display_crc_init(dev_priv);
 934
 935         intel_detect_preproduction_hw(dev_priv);
 936
 937         return 0;
 938
 939 err_workqueues:
 940         i915_workqueues_cleanup(dev_priv);
 941 err_engines:
 942         i915_engines_cleanup(dev_priv);
 943         return ret;
 944 }
 945
 946 /**
 947  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 948  * @dev_priv: device private
 949  */
 950 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 951 {
 952         intel_irq_fini(dev_priv);
 953         intel_uc_cleanup_early(dev_priv);
 954         i915_gem_cleanup_early(dev_priv);
 955         i915_workqueues_cleanup(dev_priv);
 956         i915_engines_cleanup(dev_priv);
 957 }
 958
 959 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 960 {
 961         struct pci_dev *pdev = dev_priv->drm.pdev;
 962         int mmio_bar;
 963         int mmio_size;
 964
 965         mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
 966         /*
 967          * Before gen4, the registers and the GTT are behind different BARs.
 968          * However, from gen4 onwards, the registers and the GTT are shared
 969          * in the same BAR, so we want to restrict this ioremap from
 970          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 971          * the register BAR remains the same size for all the earlier
 972          * generations up to Ironlake.
 973          */
 974         if (INTEL_GEN(dev_priv) < 5)
 975                 mmio_size = 512 * 1024;
 976         else
 977                 mmio_size = 2 * 1024 * 1024;
 978         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 979         if (dev_priv->regs == NULL) {
 980                 DRM_ERROR("failed to map registers\n");
 981
 982                 return -EIO;
 983         }
 984
 985         /* Try to make sure MCHBAR is enabled before poking at it */
 986         intel_setup_mchbar(dev_priv);
 987
 988         return 0;
 989 }
 990
 991 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 992 {
 993         struct pci_dev *pdev = dev_priv->drm.pdev;
 994
 995         intel_teardown_mchbar(dev_priv);
 996         pci_iounmap(pdev, dev_priv->regs);
 997 }
 998
 999 /**
1000  * i915_driver_init_mmio - setup device MMIO
1001  * @dev_priv: device private
1002  *
1003  * Setup minimal device state necessary for MMIO accesses later in the
1004  * initialization sequence. The setup here should avoid any other device-wide
1005  * side effects or exposing the driver via kernel internal or user space
1006  * interfaces.
1007  */
1008 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1009 {
1010         int ret;
1011
1012         if (i915_inject_load_failure())
1013                 return -ENODEV;
1014
1015         if (i915_get_bridge_dev(dev_priv))
1016                 return -EIO;
1017
1018         ret = i915_mmio_setup(dev_priv);
1019         if (ret < 0)
1020                 goto err_bridge;
1021
1022         intel_uncore_init(dev_priv);
1023
1024         intel_device_info_init_mmio(dev_priv);
1025
1026         intel_uncore_prune(dev_priv);
1027
1028         intel_uc_init_mmio(dev_priv);
1029
1030         ret = intel_engines_init_mmio(dev_priv);
1031         if (ret)
1032                 goto err_uncore;
1033
1034         i915_gem_init_mmio(dev_priv);
1035
1036         return 0;
1037
1038 err_uncore:
1039         intel_uncore_fini(dev_priv);
1040 err_bridge:
1041         pci_dev_put(dev_priv->bridge_dev);
1042
1043         return ret;
1044 }
1045
1046 /**
1047  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1048  * @dev_priv: device private
1049  */
1050 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1051 {
1052         intel_uncore_fini(dev_priv);
1053         i915_mmio_cleanup(dev_priv);
1054         pci_dev_put(dev_priv->bridge_dev);
1055 }
1056
1057 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1058 {
1059         /*
1060          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1061          * user's requested state against the hardware/driver capabilities.  We
1062          * do this now so that we can print out any log messages once rather
1063          * than every time we check intel_enable_ppgtt().
1064          */
1065         i915_modparams.enable_ppgtt =
1066                 intel_sanitize_enable_ppgtt(dev_priv,
1067                                             i915_modparams.enable_ppgtt);
1068         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
1069
1070         intel_gvt_sanitize_options(dev_priv);
1071 }
1072
1073 /**
1074  * i915_driver_init_hw - setup state requiring device access
1075  * @dev_priv: device private
1076  *
1077  * Setup state that requires accessing the device, but doesn't require
1078  * exposing the driver via kernel internal or userspace interfaces.
1079  */
1080 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1081 {
1082         struct pci_dev *pdev = dev_priv->drm.pdev;
1083         int ret;
1084
1085         if (i915_inject_load_failure())
1086                 return -ENODEV;
1087
1088         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
1089
1090         intel_sanitize_options(dev_priv);
1091
1092         i915_perf_init(dev_priv);
1093
1094         ret = i915_ggtt_probe_hw(dev_priv);
1095         if (ret)
1096                 goto err_perf;
1097
1098         /*
1099          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1100          * otherwise the vga fbdev driver falls over.
1101          */
1102         ret = i915_kick_out_firmware_fb(dev_priv);
1103         if (ret) {
1104                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1105                 goto err_ggtt;
1106         }
1107
1108         ret = i915_kick_out_vgacon(dev_priv);
1109         if (ret) {
1110                 DRM_ERROR("failed to remove conflicting VGA console\n");
1111                 goto err_ggtt;
1112         }
1113
1114         ret = i915_ggtt_init_hw(dev_priv);
1115         if (ret)
1116                 goto err_ggtt;
1117
1118         ret = i915_ggtt_enable_hw(dev_priv);
1119         if (ret) {
1120                 DRM_ERROR("failed to enable GGTT\n");
1121                 goto err_ggtt;
1122         }
1123
1124         pci_set_master(pdev);
1125
1126         /* overlay on gen2 is broken and can't address above 1G */
1127         if (IS_GEN2(dev_priv)) {
1128                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1129                 if (ret) {
1130                         DRM_ERROR("failed to set DMA mask\n");
1131
1132                         goto err_ggtt;
1133                 }
1134         }
1135
1136         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1137          * using 32bit addressing, overwriting memory if HWS is located
1138          * above 4GB.
1139          *
1140          * The documentation also mentions an issue with undefined
1141          * behaviour if any general state is accessed within a page above 4GB,
1142          * which also needs to be handled carefully.
1143          */
1144         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1145                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1146
1147                 if (ret) {
1148                         DRM_ERROR("failed to set DMA mask\n");
1149
1150                         goto err_ggtt;
1151                 }
1152         }
1153
1154         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1155                            PM_QOS_DEFAULT_VALUE);
1156
1157         intel_uncore_sanitize(dev_priv);
1158
1159         i915_gem_load_init_fences(dev_priv);
1160
1161         /* On the 945G/GM, the chipset reports the MSI capability on the
1162          * integrated graphics even though the support isn't actually there
1163          * according to the published specs.  It doesn't appear to function
1164          * correctly in testing on 945G.
1165          * This may be a side effect of MSI having been made available for PEG
1166          * and the registers being closely associated.
1167          *
1168          * According to chipset errata, on the 965GM, MSI interrupts may
1169          * be lost or delayed, and was defeatured. MSI interrupts seem to
1170          * get lost on g4x as well, and interrupt delivery seems to stay
1171          * properly dead afterwards. So we'll just disable them for all
1172          * pre-gen5 chipsets.
1173          *
1174          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1175          * interrupts even when in MSI mode. This results in spurious
1176          * interrupt warnings if the legacy irq no. is shared with another
1177          * device. The kernel then disables that interrupt source and so
1178          * prevents the other device from working properly.
1179          */
1180         if (INTEL_GEN(dev_priv) >= 5) {
1181                 if (pci_enable_msi(pdev) < 0)
1182                         DRM_DEBUG_DRIVER("can't enable MSI");
1183         }
1184
1185         ret = intel_gvt_init(dev_priv);
1186         if (ret)
1187                 goto err_msi;
1188
1189         intel_opregion_setup(dev_priv);
1190
1191         return 0;
1192
1193 err_msi:
1194         if (pdev->msi_enabled)
1195                 pci_disable_msi(pdev);
1196         pm_qos_remove_request(&dev_priv->pm_qos);
1197 err_ggtt:
1198         i915_ggtt_cleanup_hw(dev_priv);
1199 err_perf:
1200         i915_perf_fini(dev_priv);
1201         return ret;
1202 }
1203
1204 /**
1205  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1206  * @dev_priv: device private
1207  */
1208 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1209 {
1210         struct pci_dev *pdev = dev_priv->drm.pdev;
1211
1212         i915_perf_fini(dev_priv);
1213
1214         if (pdev->msi_enabled)
1215                 pci_disable_msi(pdev);
1216
1217         pm_qos_remove_request(&dev_priv->pm_qos);
1218         i915_ggtt_cleanup_hw(dev_priv);
1219 }
1220
1221 /**
1222  * i915_driver_register - register the driver with the rest of the system
1223  * @dev_priv: device private
1224  *
1225  * Perform any steps necessary to make the driver available via kernel
1226  * internal or userspace interfaces.
1227  */
1228 static void i915_driver_register(struct drm_i915_private *dev_priv)
1229 {
1230         struct drm_device *dev = &dev_priv->drm;
1231
1232         i915_gem_shrinker_register(dev_priv);
1233         i915_pmu_register(dev_priv);
1234
1235         /*
1236          * Notify a valid surface after modesetting,
1237          * when running inside a VM.
1238          */
1239         if (intel_vgpu_active(dev_priv))
1240                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1241
1242         /* Reveal our presence to userspace */
1243         if (drm_dev_register(dev, 0) == 0) {
1244                 i915_debugfs_register(dev_priv);
1245                 i915_setup_sysfs(dev_priv);
1246
1247                 /* Depends on sysfs having been initialized */
1248                 i915_perf_register(dev_priv);
1249         } else
1250                 DRM_ERROR("Failed to register driver for userspace access!\n");
1251
1252         if (INTEL_INFO(dev_priv)->num_pipes) {
1253                 /* Must be done after probing outputs */
1254                 intel_opregion_register(dev_priv);
1255                 acpi_video_register();
1256         }
1257
1258         if (IS_GEN5(dev_priv))
1259                 intel_gpu_ips_init(dev_priv);
1260
1261         intel_audio_init(dev_priv);
1262
1263         /*
1264          * Some ports require correctly set-up hpd registers for detection to
1265          * work properly (leading to ghost connected connector status), e.g. VGA
1266          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1267          * irqs are fully enabled. We do it last so that the async config
1268          * cannot run before the connectors are registered.
1269          */
1270         intel_fbdev_initial_config_async(dev);
1271
1272         /*
1273          * We need to coordinate the hotplugs with the asynchronous fbdev
1274          * configuration, for which we use the fbdev->async_cookie.
1275          */
1276         if (INTEL_INFO(dev_priv)->num_pipes)
1277                 drm_kms_helper_poll_init(dev);
1278 }
1279
1280 /**
1281  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1282  * @dev_priv: device private
1283  */
1284 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1285 {
1286         intel_fbdev_unregister(dev_priv);
1287         intel_audio_deinit(dev_priv);
1288
1289         /*
1290          * After flushing the fbdev (incl. a late async config which will
1291          * have delayed queuing of a hotplug event), then flush the hotplug
1292          * events.
1293          */
1294         drm_kms_helper_poll_fini(&dev_priv->drm);
1295
1296         intel_gpu_ips_teardown();
1297         acpi_video_unregister();
1298         intel_opregion_unregister(dev_priv);
1299
1300         i915_perf_unregister(dev_priv);
1301         i915_pmu_unregister(dev_priv);
1302
1303         i915_teardown_sysfs(dev_priv);
1304         drm_dev_unregister(&dev_priv->drm);
1305
1306         i915_gem_shrinker_unregister(dev_priv);
1307 }
1308
1309 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1310 {
1311         if (drm_debug & DRM_UT_DRIVER) {
1312                 struct drm_printer p = drm_debug_printer("i915 device info:");
1313
1314                 intel_device_info_dump(&dev_priv->info, &p);
1315                 intel_device_info_dump_runtime(&dev_priv->info, &p);
1316         }
1317
1318         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1319                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1320         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1321                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1322 }
1323
1324 /**
1325  * i915_driver_load - setup chip and create an initial config
1326  * @pdev: PCI device
1327  * @ent: matching PCI ID entry
1328  *
1329  * The driver load routine has to do several things:
1330  *   - drive output discovery via intel_modeset_init()
1331  *   - initialize the memory manager
1332  *   - allocate initial config memory
1333  *   - setup the DRM framebuffer with the allocated memory
1334  */
1335 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1336 {
1337         const struct intel_device_info *match_info =
1338                 (struct intel_device_info *)ent->driver_data;
1339         struct drm_i915_private *dev_priv;
1340         int ret;
1341
1342         /* Enable nuclear pageflip on ILK+ */
1343         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1344                 driver.driver_features &= ~DRIVER_ATOMIC;
1345
1346         ret = -ENOMEM;
1347         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1348         if (dev_priv)
1349                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1350         if (ret) {
1351                 DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
1352                 goto out_free;
1353         }
1354
1355         dev_priv->drm.pdev = pdev;
1356         dev_priv->drm.dev_private = dev_priv;
1357
1358         ret = pci_enable_device(pdev);
1359         if (ret)
1360                 goto out_fini;
1361
1362         pci_set_drvdata(pdev, &dev_priv->drm);
1363         /*
1364          * Disable the system suspend direct complete optimization, which can
1365          * leave the device suspended skipping the driver's suspend handlers
1366          * if the device was already runtime suspended. This is needed due to
1367          * the difference in our runtime and system suspend sequence and
1368          * becaue the HDA driver may require us to enable the audio power
1369          * domain during system suspend.
1370          */
1371         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
1372
1373         ret = i915_driver_init_early(dev_priv, ent);
1374         if (ret < 0)
1375                 goto out_pci_disable;
1376
1377         intel_runtime_pm_get(dev_priv);
1378
1379         ret = i915_driver_init_mmio(dev_priv);
1380         if (ret < 0)
1381                 goto out_runtime_pm_put;
1382
1383         ret = i915_driver_init_hw(dev_priv);
1384         if (ret < 0)
1385                 goto out_cleanup_mmio;
1386
1387         /*
1388          * TODO: move the vblank init and parts of modeset init steps into one
1389          * of the i915_driver_init_/i915_driver_register functions according
1390          * to the role/effect of the given init step.
1391          */
1392         if (INTEL_INFO(dev_priv)->num_pipes) {
1393                 ret = drm_vblank_init(&dev_priv->drm,
1394                                       INTEL_INFO(dev_priv)->num_pipes);
1395                 if (ret)
1396                         goto out_cleanup_hw;
1397         }
1398
1399         ret = i915_load_modeset_init(&dev_priv->drm);
1400         if (ret < 0)
1401                 goto out_cleanup_hw;
1402
1403         i915_driver_register(dev_priv);
1404
1405         intel_runtime_pm_enable(dev_priv);
1406
1407         intel_init_ipc(dev_priv);
1408
1409         intel_runtime_pm_put(dev_priv);
1410
1411         i915_welcome_messages(dev_priv);
1412
1413         return 0;
1414
1415 out_cleanup_hw:
1416         i915_driver_cleanup_hw(dev_priv);
1417 out_cleanup_mmio:
1418         i915_driver_cleanup_mmio(dev_priv);
1419 out_runtime_pm_put:
1420         intel_runtime_pm_put(dev_priv);
1421         i915_driver_cleanup_early(dev_priv);
1422 out_pci_disable:
1423         pci_disable_device(pdev);
1424 out_fini:
1425         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1426         drm_dev_fini(&dev_priv->drm);
1427 out_free:
1428         kfree(dev_priv);
1429         pci_set_drvdata(pdev, NULL);
1430         return ret;
1431 }
1432
1433 void i915_driver_unload(struct drm_device *dev)
1434 {
1435         struct drm_i915_private *dev_priv = to_i915(dev);
1436         struct pci_dev *pdev = dev_priv->drm.pdev;
1437
1438         i915_driver_unregister(dev_priv);
1439
1440         if (i915_gem_suspend(dev_priv))
1441                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1442
1443         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1444
1445         drm_atomic_helper_shutdown(dev);
1446
1447         intel_gvt_cleanup(dev_priv);
1448
1449         intel_modeset_cleanup(dev);
1450
1451         intel_bios_cleanup(dev_priv);
1452
1453         vga_switcheroo_unregister_client(pdev);
1454         vga_client_register(pdev, NULL, NULL, NULL);
1455
1456         intel_csr_ucode_fini(dev_priv);
1457
1458         /* Free error state after interrupts are fully disabled. */
1459         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1460         i915_reset_error_state(dev_priv);
1461
1462         i915_gem_fini(dev_priv);
1463         intel_fbc_cleanup_cfb(dev_priv);
1464
1465         intel_power_domains_fini(dev_priv);
1466
1467         i915_driver_cleanup_hw(dev_priv);
1468         i915_driver_cleanup_mmio(dev_priv);
1469
1470         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1471 }
1472
1473 static void i915_driver_release(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = to_i915(dev);
1476
1477         i915_driver_cleanup_early(dev_priv);
1478         drm_dev_fini(&dev_priv->drm);
1479
1480         kfree(dev_priv);
1481 }
1482
1483 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1484 {
1485         struct drm_i915_private *i915 = to_i915(dev);
1486         int ret;
1487
1488         ret = i915_gem_open(i915, file);
1489         if (ret)
1490                 return ret;
1491
1492         return 0;
1493 }
1494
1495 /**
1496  * i915_driver_lastclose - clean up after all DRM clients have exited
1497  * @dev: DRM device
1498  *
1499  * Take care of cleaning up after all DRM clients have exited.  In the
1500  * mode setting case, we want to restore the kernel's initial mode (just
1501  * in case the last client left us in a bad state).
1502  *
1503  * Additionally, in the non-mode setting case, we'll tear down the GTT
1504  * and DMA structures, since the kernel won't be using them, and clea
1505  * up any GEM state.
1506  */
1507 static void i915_driver_lastclose(struct drm_device *dev)
1508 {
1509         intel_fbdev_restore_mode(dev);
1510         vga_switcheroo_process_delayed_switch();
1511 }
1512
1513 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1514 {
1515         struct drm_i915_file_private *file_priv = file->driver_priv;
1516
1517         mutex_lock(&dev->struct_mutex);
1518         i915_gem_context_close(file);
1519         i915_gem_release(dev, file);
1520         mutex_unlock(&dev->struct_mutex);
1521
1522         kfree(file_priv);
1523 }
1524
1525 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1526 {
1527         struct drm_device *dev = &dev_priv->drm;
1528         struct intel_encoder *encoder;
1529
1530         drm_modeset_lock_all(dev);
1531         for_each_intel_encoder(dev, encoder)
1532                 if (encoder->suspend)
1533                         encoder->suspend(encoder);
1534         drm_modeset_unlock_all(dev);
1535 }
1536
1537 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1538                               bool rpm_resume);
1539 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1540
1541 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1542 {
1543 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1544         if (acpi_target_system_state() < ACPI_STATE_S3)
1545                 return true;
1546 #endif
1547         return false;
1548 }
1549
1550 static int i915_drm_prepare(struct drm_device *dev)
1551 {
1552         struct drm_i915_private *i915 = to_i915(dev);
1553         int err;
1554
1555         /*
1556          * NB intel_display_suspend() may issue new requests after we've
1557          * ostensibly marked the GPU as ready-to-sleep here. We need to
1558          * split out that work and pull it forward so that after point,
1559          * the GPU is not woken again.
1560          */
1561         err = i915_gem_suspend(i915);
1562         if (err)
1563                 dev_err(&i915->drm.pdev->dev,
1564                         "GEM idle failed, suspend/resume might fail\n");
1565
1566         return err;
1567 }
1568
1569 static int i915_drm_suspend(struct drm_device *dev)
1570 {
1571         struct drm_i915_private *dev_priv = to_i915(dev);
1572         struct pci_dev *pdev = dev_priv->drm.pdev;
1573         pci_power_t opregion_target_state;
1574
1575         disable_rpm_wakeref_asserts(dev_priv);
1576
1577         /* We do a lot of poking in a lot of registers, make sure they work
1578          * properly. */
1579         intel_display_set_init_power(dev_priv, true);
1580
1581         drm_kms_helper_poll_disable(dev);
1582
1583         pci_save_state(pdev);
1584
1585         intel_display_suspend(dev);
1586
1587         intel_dp_mst_suspend(dev_priv);
1588
1589         intel_runtime_pm_disable_interrupts(dev_priv);
1590         intel_hpd_cancel_work(dev_priv);
1591
1592         intel_suspend_encoders(dev_priv);
1593
1594         intel_suspend_hw(dev_priv);
1595
1596         i915_gem_suspend_gtt_mappings(dev_priv);
1597
1598         i915_save_state(dev_priv);
1599
1600         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1601         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1602
1603         intel_opregion_unregister(dev_priv);
1604
1605         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1606
1607         dev_priv->suspend_count++;
1608
1609         intel_csr_ucode_suspend(dev_priv);
1610
1611         enable_rpm_wakeref_asserts(dev_priv);
1612
1613         return 0;
1614 }
1615
1616 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1617 {
1618         struct drm_i915_private *dev_priv = to_i915(dev);
1619         struct pci_dev *pdev = dev_priv->drm.pdev;
1620         int ret;
1621
1622         disable_rpm_wakeref_asserts(dev_priv);
1623
1624         i915_gem_suspend_late(dev_priv);
1625
1626         intel_display_set_init_power(dev_priv, false);
1627         intel_uncore_suspend(dev_priv);
1628
1629         /*
1630          * In case of firmware assisted context save/restore don't manually
1631          * deinit the power domains. This also means the CSR/DMC firmware will
1632          * stay active, it will power down any HW resources as required and
1633          * also enable deeper system power states that would be blocked if the
1634          * firmware was inactive.
1635          */
1636         if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
1637             dev_priv->csr.dmc_payload == NULL) {
1638                 intel_power_domains_suspend(dev_priv);
1639                 dev_priv->power_domains_suspended = true;
1640         }
1641
1642         ret = 0;
1643         if (IS_GEN9_LP(dev_priv))
1644                 bxt_enable_dc9(dev_priv);
1645         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1646                 hsw_enable_pc8(dev_priv);
1647         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1648                 ret = vlv_suspend_complete(dev_priv);
1649
1650         if (ret) {
1651                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1652                 if (dev_priv->power_domains_suspended) {
1653                         intel_power_domains_init_hw(dev_priv, true);
1654                         dev_priv->power_domains_suspended = false;
1655                 }
1656
1657                 goto out;
1658         }
1659
1660         pci_disable_device(pdev);
1661         /*
1662          * During hibernation on some platforms the BIOS may try to access
1663          * the device even though it's already in D3 and hang the machine. So
1664          * leave the device in D0 on those platforms and hope the BIOS will
1665          * power down the device properly. The issue was seen on multiple old
1666          * GENs with different BIOS vendors, so having an explicit blacklist
1667          * is inpractical; apply the workaround on everything pre GEN6. The
1668          * platforms where the issue was seen:
1669          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1670          * Fujitsu FSC S7110
1671          * Acer Aspire 1830T
1672          */
1673         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1674                 pci_set_power_state(pdev, PCI_D3hot);
1675
1676 out:
1677         enable_rpm_wakeref_asserts(dev_priv);
1678
1679         return ret;
1680 }
1681
1682 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1683 {
1684         int error;
1685
1686         if (!dev) {
1687                 DRM_ERROR("dev: %p\n", dev);
1688                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1689                 return -ENODEV;
1690         }
1691
1692         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1693                          state.event != PM_EVENT_FREEZE))
1694                 return -EINVAL;
1695
1696         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1697                 return 0;
1698
1699         error = i915_drm_suspend(dev);
1700         if (error)
1701                 return error;
1702
1703         return i915_drm_suspend_late(dev, false);
1704 }
1705
1706 static int i915_drm_resume(struct drm_device *dev)
1707 {
1708         struct drm_i915_private *dev_priv = to_i915(dev);
1709         int ret;
1710
1711         disable_rpm_wakeref_asserts(dev_priv);
1712         intel_sanitize_gt_powersave(dev_priv);
1713
1714         i915_gem_sanitize(dev_priv);
1715
1716         ret = i915_ggtt_enable_hw(dev_priv);
1717         if (ret)
1718                 DRM_ERROR("failed to re-enable GGTT\n");
1719
1720         intel_csr_ucode_resume(dev_priv);
1721
1722         i915_restore_state(dev_priv);
1723         intel_pps_unlock_regs_wa(dev_priv);
1724         intel_opregion_setup(dev_priv);
1725
1726         intel_init_pch_refclk(dev_priv);
1727
1728         /*
1729          * Interrupts have to be enabled before any batches are run. If not the
1730          * GPU will hang. i915_gem_init_hw() will initiate batches to
1731          * update/restore the context.
1732          *
1733          * drm_mode_config_reset() needs AUX interrupts.
1734          *
1735          * Modeset enabling in intel_modeset_init_hw() also needs working
1736          * interrupts.
1737          */
1738         intel_runtime_pm_enable_interrupts(dev_priv);
1739
1740         drm_mode_config_reset(dev);
1741
1742         i915_gem_resume(dev_priv);
1743
1744         intel_modeset_init_hw(dev);
1745         intel_init_clock_gating(dev_priv);
1746
1747         spin_lock_irq(&dev_priv->irq_lock);
1748         if (dev_priv->display.hpd_irq_setup)
1749                 dev_priv->display.hpd_irq_setup(dev_priv);
1750         spin_unlock_irq(&dev_priv->irq_lock);
1751
1752         intel_dp_mst_resume(dev_priv);
1753
1754         intel_display_resume(dev);
1755
1756         drm_kms_helper_poll_enable(dev);
1757
1758         /*
1759          * ... but also need to make sure that hotplug processing
1760          * doesn't cause havoc. Like in the driver load code we don't
1761          * bother with the tiny race here where we might loose hotplug
1762          * notifications.
1763          * */
1764         intel_hpd_init(dev_priv);
1765
1766         intel_opregion_register(dev_priv);
1767
1768         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1769
1770         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1771
1772         enable_rpm_wakeref_asserts(dev_priv);
1773
1774         return 0;
1775 }
1776
1777 static int i915_drm_resume_early(struct drm_device *dev)
1778 {
1779         struct drm_i915_private *dev_priv = to_i915(dev);
1780         struct pci_dev *pdev = dev_priv->drm.pdev;
1781         int ret;
1782
1783         /*
1784          * We have a resume ordering issue with the snd-hda driver also
1785          * requiring our device to be power up. Due to the lack of a
1786          * parent/child relationship we currently solve this with an early
1787          * resume hook.
1788          *
1789          * FIXME: This should be solved with a special hdmi sink device or
1790          * similar so that power domains can be employed.
1791          */
1792
1793         /*
1794          * Note that we need to set the power state explicitly, since we
1795          * powered off the device during freeze and the PCI core won't power
1796          * it back up for us during thaw. Powering off the device during
1797          * freeze is not a hard requirement though, and during the
1798          * suspend/resume phases the PCI core makes sure we get here with the
1799          * device powered on. So in case we change our freeze logic and keep
1800          * the device powered we can also remove the following set power state
1801          * call.
1802          */
1803         ret = pci_set_power_state(pdev, PCI_D0);
1804         if (ret) {
1805                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1806                 goto out;
1807         }
1808
1809         /*
1810          * Note that pci_enable_device() first enables any parent bridge
1811          * device and only then sets the power state for this device. The
1812          * bridge enabling is a nop though, since bridge devices are resumed
1813          * first. The order of enabling power and enabling the device is
1814          * imposed by the PCI core as described above, so here we preserve the
1815          * same order for the freeze/thaw phases.
1816          *
1817          * TODO: eventually we should remove pci_disable_device() /
1818          * pci_enable_enable_device() from suspend/resume. Due to how they
1819          * depend on the device enable refcount we can't anyway depend on them
1820          * disabling/enabling the device.
1821          */
1822         if (pci_enable_device(pdev)) {
1823                 ret = -EIO;
1824                 goto out;
1825         }
1826
1827         pci_set_master(pdev);
1828
1829         disable_rpm_wakeref_asserts(dev_priv);
1830
1831         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1832                 ret = vlv_resume_prepare(dev_priv, false);
1833         if (ret)
1834                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1835                           ret);
1836
1837         intel_uncore_resume_early(dev_priv);
1838
1839         if (IS_GEN9_LP(dev_priv)) {
1840                 gen9_sanitize_dc_state(dev_priv);
1841                 bxt_disable_dc9(dev_priv);
1842         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1843                 hsw_disable_pc8(dev_priv);
1844         }
1845
1846         intel_uncore_sanitize(dev_priv);
1847
1848         if (dev_priv->power_domains_suspended)
1849                 intel_power_domains_init_hw(dev_priv, true);
1850         else
1851                 intel_display_set_init_power(dev_priv, true);
1852
1853         intel_engines_sanitize(dev_priv);
1854
1855         enable_rpm_wakeref_asserts(dev_priv);
1856
1857 out:
1858         dev_priv->power_domains_suspended = false;
1859
1860         return ret;
1861 }
1862
1863 static int i915_resume_switcheroo(struct drm_device *dev)
1864 {
1865         int ret;
1866
1867         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1868                 return 0;
1869
1870         ret = i915_drm_resume_early(dev);
1871         if (ret)
1872                 return ret;
1873
1874         return i915_drm_resume(dev);
1875 }
1876
1877 /**
1878  * i915_reset - reset chip after a hang
1879  * @i915: #drm_i915_private to reset
1880  * @stalled_mask: mask of the stalled engines with the guilty requests
1881  * @reason: user error message for why we are resetting
1882  *
1883  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1884  * on failure.
1885  *
1886  * Caller must hold the struct_mutex.
1887  *
1888  * Procedure is fairly simple:
1889  *   - reset the chip using the reset reg
1890  *   - re-init context state
1891  *   - re-init hardware status page
1892  *   - re-init ring buffer
1893  *   - re-init interrupt state
1894  *   - re-init display
1895  */
1896 void i915_reset(struct drm_i915_private *i915,
1897                 unsigned int stalled_mask,
1898                 const char *reason)
1899 {
1900         struct i915_gpu_error *error = &i915->gpu_error;
1901         int ret;
1902         int i;
1903
1904         GEM_TRACE("flags=%lx\n", error->flags);
1905
1906         might_sleep();
1907         lockdep_assert_held(&i915->drm.struct_mutex);
1908         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
1909
1910         if (!test_bit(I915_RESET_HANDOFF, &error->flags))
1911                 return;
1912
1913         /* Clear any previous failed attempts at recovery. Time to try again. */
1914         if (!i915_gem_unset_wedged(i915))
1915                 goto wakeup;
1916
1917         if (reason)
1918                 dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1919         error->reset_count++;
1920
1921         disable_irq(i915->drm.irq);
1922         ret = i915_gem_reset_prepare(i915);
1923         if (ret) {
1924                 dev_err(i915->drm.dev, "GPU recovery failed\n");
1925                 goto taint;
1926         }
1927
1928         if (!intel_has_gpu_reset(i915)) {
1929                 if (i915_modparams.reset)
1930                         dev_err(i915->drm.dev, "GPU reset not supported\n");
1931                 else
1932                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1933                 goto error;
1934         }
1935
1936         for (i = 0; i < 3; i++) {
1937                 ret = intel_gpu_reset(i915, ALL_ENGINES);
1938                 if (ret == 0)
1939                         break;
1940
1941                 msleep(100);
1942         }
1943         if (ret) {
1944                 dev_err(i915->drm.dev, "Failed to reset chip\n");
1945                 goto taint;
1946         }
1947
1948         /* Ok, now get things going again... */
1949
1950         /*
1951          * Everything depends on having the GTT running, so we need to start
1952          * there.
1953          */
1954         ret = i915_ggtt_enable_hw(i915);
1955         if (ret) {
1956                 DRM_ERROR("Failed to re-enable GGTT following reset (%d)\n",
1957                           ret);
1958                 goto error;
1959         }
1960
1961         i915_gem_reset(i915, stalled_mask);
1962         intel_overlay_reset(i915);
1963
1964         /*
1965          * Next we need to restore the context, but we don't use those
1966          * yet either...
1967          *
1968          * Ring buffer needs to be re-initialized in the KMS case, or if X
1969          * was running at the time of the reset (i.e. we weren't VT
1970          * switched away).
1971          */
1972         ret = i915_gem_init_hw(i915);
1973         if (ret) {
1974                 DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1975                           ret);
1976                 goto error;
1977         }
1978
1979         i915_queue_hangcheck(i915);
1980
1981 finish:
1982         i915_gem_reset_finish(i915);
1983         enable_irq(i915->drm.irq);
1984
1985 wakeup:
1986         clear_bit(I915_RESET_HANDOFF, &error->flags);
1987         wake_up_bit(&error->flags, I915_RESET_HANDOFF);
1988         return;
1989
1990 taint:
1991         /*
1992          * History tells us that if we cannot reset the GPU now, we
1993          * never will. This then impacts everything that is run
1994          * subsequently. On failing the reset, we mark the driver
1995          * as wedged, preventing further execution on the GPU.
1996          * We also want to go one step further and add a taint to the
1997          * kernel so that any subsequent faults can be traced back to
1998          * this failure. This is important for CI, where if the
1999          * GPU/driver fails we would like to reboot and restart testing
2000          * rather than continue on into oblivion. For everyone else,
2001          * the system should still plod along, but they have been warned!
2002          */
2003         add_taint(TAINT_WARN, LOCKDEP_STILL_OK);
2004 error:
2005         i915_gem_set_wedged(i915);
2006         i915_retire_requests(i915);
2007         goto finish;
2008 }
2009
2010 static inline int intel_gt_reset_engine(struct drm_i915_private *dev_priv,
2011                                         struct intel_engine_cs *engine)
2012 {
2013         return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
2014 }
2015
2016 /**
2017  * i915_reset_engine - reset GPU engine to recover from a hang
2018  * @engine: engine to reset
2019  * @msg: reason for GPU reset; or NULL for no dev_notice()
2020  *
2021  * Reset a specific GPU engine. Useful if a hang is detected.
2022  * Returns zero on successful reset or otherwise an error code.
2023  *
2024  * Procedure is:
2025  *  - identifies the request that caused the hang and it is dropped
2026  *  - reset engine (which will force the engine to idle)
2027  *  - re-init/configure engine
2028  */
2029 int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
2030 {
2031         struct i915_gpu_error *error = &engine->i915->gpu_error;
2032         struct i915_request *active_request;
2033         int ret;
2034
2035         GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
2036         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
2037
2038         active_request = i915_gem_reset_prepare_engine(engine);
2039         if (IS_ERR_OR_NULL(active_request)) {
2040                 /* Either the previous reset failed, or we pardon the reset. */
2041                 ret = PTR_ERR(active_request);
2042                 goto out;
2043         }
2044
2045         if (msg)
2046                 dev_notice(engine->i915->drm.dev,
2047                            "Resetting %s for %s\n", engine->name, msg);
2048         error->reset_engine_count[engine->id]++;
2049
2050         if (!engine->i915->guc.execbuf_client)
2051                 ret = intel_gt_reset_engine(engine->i915, engine);
2052         else
2053                 ret = intel_guc_reset_engine(&engine->i915->guc, engine);
2054         if (ret) {
2055                 /* If we fail here, we expect to fallback to a global reset */
2056                 DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
2057                                  engine->i915->guc.execbuf_client ? "GuC " : "",
2058                                  engine->name, ret);
2059                 goto out;
2060         }
2061
2062         /*
2063          * The request that caused the hang is stuck on elsp, we know the
2064          * active request and can drop it, adjust head to skip the offending
2065          * request to resume executing remaining requests in the queue.
2066          */
2067         i915_gem_reset_engine(engine, active_request, true);
2068
2069         /*
2070          * The engine and its registers (and workarounds in case of render)
2071          * have been reset to their default values. Follow the init_ring
2072          * process to program RING_MODE, HWSP and re-enable submission.
2073          */
2074         ret = engine->init_hw(engine);
2075         if (ret)
2076                 goto out;
2077
2078 out:
2079         i915_gem_reset_finish_engine(engine);
2080         return ret;
2081 }
2082
2083 static int i915_pm_prepare(struct device *kdev)
2084 {
2085         struct pci_dev *pdev = to_pci_dev(kdev);
2086         struct drm_device *dev = pci_get_drvdata(pdev);
2087
2088         if (!dev) {
2089                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2090                 return -ENODEV;
2091         }
2092
2093         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2094                 return 0;
2095
2096         return i915_drm_prepare(dev);
2097 }
2098
2099 static int i915_pm_suspend(struct device *kdev)
2100 {
2101         struct pci_dev *pdev = to_pci_dev(kdev);
2102         struct drm_device *dev = pci_get_drvdata(pdev);
2103
2104         if (!dev) {
2105                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2106                 return -ENODEV;
2107         }
2108
2109         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2110                 return 0;
2111
2112         return i915_drm_suspend(dev);
2113 }
2114
2115 static int i915_pm_suspend_late(struct device *kdev)
2116 {
2117         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2118
2119         /*
2120          * We have a suspend ordering issue with the snd-hda driver also
2121          * requiring our device to be power up. Due to the lack of a
2122          * parent/child relationship we currently solve this with an late
2123          * suspend hook.
2124          *
2125          * FIXME: This should be solved with a special hdmi sink device or
2126          * similar so that power domains can be employed.
2127          */
2128         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2129                 return 0;
2130
2131         return i915_drm_suspend_late(dev, false);
2132 }
2133
2134 static int i915_pm_poweroff_late(struct device *kdev)
2135 {
2136         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2137
2138         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2139                 return 0;
2140
2141         return i915_drm_suspend_late(dev, true);
2142 }
2143
2144 static int i915_pm_resume_early(struct device *kdev)
2145 {
2146         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2147
2148         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2149                 return 0;
2150
2151         return i915_drm_resume_early(dev);
2152 }
2153
2154 static int i915_pm_resume(struct device *kdev)
2155 {
2156         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2157
2158         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2159                 return 0;
2160
2161         return i915_drm_resume(dev);
2162 }
2163
2164 /* freeze: before creating the hibernation_image */
2165 static int i915_pm_freeze(struct device *kdev)
2166 {
2167         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2168         int ret;
2169
2170         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2171                 ret = i915_drm_suspend(dev);
2172                 if (ret)
2173                         return ret;
2174         }
2175
2176         ret = i915_gem_freeze(kdev_to_i915(kdev));
2177         if (ret)
2178                 return ret;
2179
2180         return 0;
2181 }
2182
2183 static int i915_pm_freeze_late(struct device *kdev)
2184 {
2185         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2186         int ret;
2187
2188         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2189                 ret = i915_drm_suspend_late(dev, true);
2190                 if (ret)
2191                         return ret;
2192         }
2193
2194         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2195         if (ret)
2196                 return ret;
2197
2198         return 0;
2199 }
2200
2201 /* thaw: called after creating the hibernation image, but before turning off. */
2202 static int i915_pm_thaw_early(struct device *kdev)
2203 {
2204         return i915_pm_resume_early(kdev);
2205 }
2206
2207 static int i915_pm_thaw(struct device *kdev)
2208 {
2209         return i915_pm_resume(kdev);
2210 }
2211
2212 /* restore: called after loading the hibernation image. */
2213 static int i915_pm_restore_early(struct device *kdev)
2214 {
2215         return i915_pm_resume_early(kdev);
2216 }
2217
2218 static int i915_pm_restore(struct device *kdev)
2219 {
2220         return i915_pm_resume(kdev);
2221 }
2222
2223 /*
2224  * Save all Gunit registers that may be lost after a D3 and a subsequent
2225  * S0i[R123] transition. The list of registers needing a save/restore is
2226  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2227  * registers in the following way:
2228  * - Driver: saved/restored by the driver
2229  * - Punit : saved/restored by the Punit firmware
2230  * - No, w/o marking: no need to save/restore, since the register is R/O or
2231  *                    used internally by the HW in a way that doesn't depend
2232  *                    keeping the content across a suspend/resume.
2233  * - Debug : used for debugging
2234  *
2235  * We save/restore all registers marked with 'Driver', with the following
2236  * exceptions:
2237  * - Registers out of use, including also registers marked with 'Debug'.
2238  *   These have no effect on the driver's operation, so we don't save/restore
2239  *   them to reduce the overhead.
2240  * - Registers that are fully setup by an initialization function called from
2241  *   the resume path. For example many clock gating and RPS/RC6 registers.
2242  * - Registers that provide the right functionality with their reset defaults.
2243  *
2244  * TODO: Except for registers that based on the above 3 criteria can be safely
2245  * ignored, we save/restore all others, practically treating the HW context as
2246  * a black-box for the driver. Further investigation is needed to reduce the
2247  * saved/restored registers even further, by following the same 3 criteria.
2248  */
2249 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2250 {
2251         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2252         int i;
2253
2254         /* GAM 0x4000-0x4770 */
2255         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2256         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2257         s->arb_mode             = I915_READ(ARB_MODE);
2258         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2259         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2260
2261         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2262                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2263
2264         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2265         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2266
2267         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2268         s->ecochk               = I915_READ(GAM_ECOCHK);
2269         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2270         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2271
2272         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2273
2274         /* MBC 0x9024-0x91D0, 0x8500 */
2275         s->g3dctl               = I915_READ(VLV_G3DCTL);
2276         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2277         s->mbctl                = I915_READ(GEN6_MBCTL);
2278
2279         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2280         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2281         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2282         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2283         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2284         s->rstctl               = I915_READ(GEN6_RSTCTL);
2285         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2286
2287         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2288         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2289         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2290         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2291         s->ecobus               = I915_READ(ECOBUS);
2292         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2293         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2294         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2295         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2296         s->rcedata              = I915_READ(VLV_RCEDATA);
2297         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2298
2299         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2300         s->gt_imr               = I915_READ(GTIMR);
2301         s->gt_ier               = I915_READ(GTIER);
2302         s->pm_imr               = I915_READ(GEN6_PMIMR);
2303         s->pm_ier               = I915_READ(GEN6_PMIER);
2304
2305         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2306                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2307
2308         /* GT SA CZ domain, 0x100000-0x138124 */
2309         s->tilectl              = I915_READ(TILECTL);
2310         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2311         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2312         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2313         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2314
2315         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2316         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2317         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2318         s->pcbr                 = I915_READ(VLV_PCBR);
2319         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2320
2321         /*
2322          * Not saving any of:
2323          * DFT,         0x9800-0x9EC0
2324          * SARB,        0xB000-0xB1FC
2325          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2326          * PCI CFG
2327          */
2328 }
2329
2330 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2331 {
2332         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2333         u32 val;
2334         int i;
2335
2336         /* GAM 0x4000-0x4770 */
2337         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2338         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2339         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2340         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2341         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2342
2343         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2344                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2345
2346         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2347         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2348
2349         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2350         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2351         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2352         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2353
2354         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2355
2356         /* MBC 0x9024-0x91D0, 0x8500 */
2357         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2358         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2359         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2360
2361         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2362         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2363         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2364         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2365         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2366         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2367         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2368
2369         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2370         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2371         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2372         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2373         I915_WRITE(ECOBUS,              s->ecobus);
2374         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2375         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2376         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2377         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2378         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2379         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2380
2381         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2382         I915_WRITE(GTIMR,               s->gt_imr);
2383         I915_WRITE(GTIER,               s->gt_ier);
2384         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2385         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2386
2387         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2388                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2389
2390         /* GT SA CZ domain, 0x100000-0x138124 */
2391         I915_WRITE(TILECTL,                     s->tilectl);
2392         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2393         /*
2394          * Preserve the GT allow wake and GFX force clock bit, they are not
2395          * be restored, as they are used to control the s0ix suspend/resume
2396          * sequence by the caller.
2397          */
2398         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2399         val &= VLV_GTLC_ALLOWWAKEREQ;
2400         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2401         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2402
2403         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2404         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2405         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2406         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2407
2408         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2409
2410         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2411         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2412         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2413         I915_WRITE(VLV_PCBR,                    s->pcbr);
2414         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2415 }
2416
2417 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2418                                   u32 mask, u32 val)
2419 {
2420         /* The HW does not like us polling for PW_STATUS frequently, so
2421          * use the sleeping loop rather than risk the busy spin within
2422          * intel_wait_for_register().
2423          *
2424          * Transitioning between RC6 states should be at most 2ms (see
2425          * valleyview_enable_rps) so use a 3ms timeout.
2426          */
2427         return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS) & mask) == val,
2428                         3);
2429 }
2430
2431 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2432 {
2433         u32 val;
2434         int err;
2435
2436         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2437         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2438         if (force_on)
2439                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2440         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2441
2442         if (!force_on)
2443                 return 0;
2444
2445         err = intel_wait_for_register(dev_priv,
2446                                       VLV_GTLC_SURVIVABILITY_REG,
2447                                       VLV_GFX_CLK_STATUS_BIT,
2448                                       VLV_GFX_CLK_STATUS_BIT,
2449                                       20);
2450         if (err)
2451                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2452                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2453
2454         return err;
2455 }
2456
2457 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2458 {
2459         u32 mask;
2460         u32 val;
2461         int err;
2462
2463         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2464         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2465         if (allow)
2466                 val |= VLV_GTLC_ALLOWWAKEREQ;
2467         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2468         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2469
2470         mask = VLV_GTLC_ALLOWWAKEACK;
2471         val = allow ? mask : 0;
2472
2473         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2474         if (err)
2475                 DRM_ERROR("timeout disabling GT waking\n");
2476
2477         return err;
2478 }
2479
2480 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2481                                   bool wait_for_on)
2482 {
2483         u32 mask;
2484         u32 val;
2485
2486         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2487         val = wait_for_on ? mask : 0;
2488
2489         /*
2490          * RC6 transitioning can be delayed up to 2 msec (see
2491          * valleyview_enable_rps), use 3 msec for safety.
2492          *
2493          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2494          * reset and we are trying to force the machine to sleep.
2495          */
2496         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2497                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2498                                  onoff(wait_for_on));
2499 }
2500
2501 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2502 {
2503         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2504                 return;
2505
2506         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2507         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2508 }
2509
2510 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2511 {
2512         u32 mask;
2513         int err;
2514
2515         /*
2516          * Bspec defines the following GT well on flags as debug only, so
2517          * don't treat them as hard failures.
2518          */
2519         vlv_wait_for_gt_wells(dev_priv, false);
2520
2521         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2522         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2523
2524         vlv_check_no_gt_access(dev_priv);
2525
2526         err = vlv_force_gfx_clock(dev_priv, true);
2527         if (err)
2528                 goto err1;
2529
2530         err = vlv_allow_gt_wake(dev_priv, false);
2531         if (err)
2532                 goto err2;
2533
2534         if (!IS_CHERRYVIEW(dev_priv))
2535                 vlv_save_gunit_s0ix_state(dev_priv);
2536
2537         err = vlv_force_gfx_clock(dev_priv, false);
2538         if (err)
2539                 goto err2;
2540
2541         return 0;
2542
2543 err2:
2544         /* For safety always re-enable waking and disable gfx clock forcing */
2545         vlv_allow_gt_wake(dev_priv, true);
2546 err1:
2547         vlv_force_gfx_clock(dev_priv, false);
2548
2549         return err;
2550 }
2551
2552 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2553                                 bool rpm_resume)
2554 {
2555         int err;
2556         int ret;
2557
2558         /*
2559          * If any of the steps fail just try to continue, that's the best we
2560          * can do at this point. Return the first error code (which will also
2561          * leave RPM permanently disabled).
2562          */
2563         ret = vlv_force_gfx_clock(dev_priv, true);
2564
2565         if (!IS_CHERRYVIEW(dev_priv))
2566                 vlv_restore_gunit_s0ix_state(dev_priv);
2567
2568         err = vlv_allow_gt_wake(dev_priv, true);
2569         if (!ret)
2570                 ret = err;
2571
2572         err = vlv_force_gfx_clock(dev_priv, false);
2573         if (!ret)
2574                 ret = err;
2575
2576         vlv_check_no_gt_access(dev_priv);
2577
2578         if (rpm_resume)
2579                 intel_init_clock_gating(dev_priv);
2580
2581         return ret;
2582 }
2583
2584 static int intel_runtime_suspend(struct device *kdev)
2585 {
2586         struct pci_dev *pdev = to_pci_dev(kdev);
2587         struct drm_device *dev = pci_get_drvdata(pdev);
2588         struct drm_i915_private *dev_priv = to_i915(dev);
2589         int ret;
2590
2591         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2592                 return -ENODEV;
2593
2594         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2595                 return -ENODEV;
2596
2597         DRM_DEBUG_KMS("Suspending device\n");
2598
2599         disable_rpm_wakeref_asserts(dev_priv);
2600
2601         /*
2602          * We are safe here against re-faults, since the fault handler takes
2603          * an RPM reference.
2604          */
2605         i915_gem_runtime_suspend(dev_priv);
2606
2607         intel_uc_suspend(dev_priv);
2608
2609         intel_runtime_pm_disable_interrupts(dev_priv);
2610
2611         intel_uncore_suspend(dev_priv);
2612
2613         ret = 0;
2614         if (IS_GEN9_LP(dev_priv)) {
2615                 bxt_display_core_uninit(dev_priv);
2616                 bxt_enable_dc9(dev_priv);
2617         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2618                 hsw_enable_pc8(dev_priv);
2619         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2620                 ret = vlv_suspend_complete(dev_priv);
2621         }
2622
2623         if (ret) {
2624                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2625                 intel_uncore_runtime_resume(dev_priv);
2626
2627                 intel_runtime_pm_enable_interrupts(dev_priv);
2628
2629                 intel_uc_resume(dev_priv);
2630
2631                 i915_gem_init_swizzling(dev_priv);
2632                 i915_gem_restore_fences(dev_priv);
2633
2634                 enable_rpm_wakeref_asserts(dev_priv);
2635
2636                 return ret;
2637         }
2638
2639         enable_rpm_wakeref_asserts(dev_priv);
2640         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2641
2642         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2643                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2644
2645         dev_priv->runtime_pm.suspended = true;
2646
2647         /*
2648          * FIXME: We really should find a document that references the arguments
2649          * used below!
2650          */
2651         if (IS_BROADWELL(dev_priv)) {
2652                 /*
2653                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2654                  * being detected, and the call we do at intel_runtime_resume()
2655                  * won't be able to restore them. Since PCI_D3hot matches the
2656                  * actual specification and appears to be working, use it.
2657                  */
2658                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2659         } else {
2660                 /*
2661                  * current versions of firmware which depend on this opregion
2662                  * notification have repurposed the D1 definition to mean
2663                  * "runtime suspended" vs. what you would normally expect (D3)
2664                  * to distinguish it from notifications that might be sent via
2665                  * the suspend path.
2666                  */
2667                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2668         }
2669
2670         assert_forcewakes_inactive(dev_priv);
2671
2672         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2673                 intel_hpd_poll_init(dev_priv);
2674
2675         DRM_DEBUG_KMS("Device suspended\n");
2676         return 0;
2677 }
2678
2679 static int intel_runtime_resume(struct device *kdev)
2680 {
2681         struct pci_dev *pdev = to_pci_dev(kdev);
2682         struct drm_device *dev = pci_get_drvdata(pdev);
2683         struct drm_i915_private *dev_priv = to_i915(dev);
2684         int ret = 0;
2685
2686         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2687                 return -ENODEV;
2688
2689         DRM_DEBUG_KMS("Resuming device\n");
2690
2691         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2692         disable_rpm_wakeref_asserts(dev_priv);
2693
2694         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2695         dev_priv->runtime_pm.suspended = false;
2696         if (intel_uncore_unclaimed_mmio(dev_priv))
2697                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2698
2699         if (IS_GEN9_LP(dev_priv)) {
2700                 bxt_disable_dc9(dev_priv);
2701                 bxt_display_core_init(dev_priv, true);
2702                 if (dev_priv->csr.dmc_payload &&
2703                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2704                         gen9_enable_dc5(dev_priv);
2705         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2706                 hsw_disable_pc8(dev_priv);
2707         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2708                 ret = vlv_resume_prepare(dev_priv, true);
2709         }
2710
2711         intel_uncore_runtime_resume(dev_priv);
2712
2713         intel_runtime_pm_enable_interrupts(dev_priv);
2714
2715         intel_uc_resume(dev_priv);
2716
2717         /*
2718          * No point of rolling back things in case of an error, as the best
2719          * we can do is to hope that things will still work (and disable RPM).
2720          */
2721         i915_gem_init_swizzling(dev_priv);
2722         i915_gem_restore_fences(dev_priv);
2723
2724         /*
2725          * On VLV/CHV display interrupts are part of the display
2726          * power well, so hpd is reinitialized from there. For
2727          * everyone else do it here.
2728          */
2729         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2730                 intel_hpd_init(dev_priv);
2731
2732         intel_enable_ipc(dev_priv);
2733
2734         enable_rpm_wakeref_asserts(dev_priv);
2735
2736         if (ret)
2737                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2738         else
2739                 DRM_DEBUG_KMS("Device resumed\n");
2740
2741         return ret;
2742 }
2743
2744 const struct dev_pm_ops i915_pm_ops = {
2745         /*
2746          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2747          * PMSG_RESUME]
2748          */
2749         .prepare = i915_pm_prepare,
2750         .suspend = i915_pm_suspend,
2751         .suspend_late = i915_pm_suspend_late,
2752         .resume_early = i915_pm_resume_early,
2753         .resume = i915_pm_resume,
2754
2755         /*
2756          * S4 event handlers
2757          * @freeze, @freeze_late    : called (1) before creating the
2758          *                            hibernation image [PMSG_FREEZE] and
2759          *                            (2) after rebooting, before restoring
2760          *                            the image [PMSG_QUIESCE]
2761          * @thaw, @thaw_early       : called (1) after creating the hibernation
2762          *                            image, before writing it [PMSG_THAW]
2763          *                            and (2) after failing to create or
2764          *                            restore the image [PMSG_RECOVER]
2765          * @poweroff, @poweroff_late: called after writing the hibernation
2766          *                            image, before rebooting [PMSG_HIBERNATE]
2767          * @restore, @restore_early : called after rebooting and restoring the
2768          *                            hibernation image [PMSG_RESTORE]
2769          */
2770         .freeze = i915_pm_freeze,
2771         .freeze_late = i915_pm_freeze_late,
2772         .thaw_early = i915_pm_thaw_early,
2773         .thaw = i915_pm_thaw,
2774         .poweroff = i915_pm_suspend,
2775         .poweroff_late = i915_pm_poweroff_late,
2776         .restore_early = i915_pm_restore_early,
2777         .restore = i915_pm_restore,
2778
2779         /* S0ix (via runtime suspend) event handlers */
2780         .runtime_suspend = intel_runtime_suspend,
2781         .runtime_resume = intel_runtime_resume,
2782 };
2783
2784 static const struct vm_operations_struct i915_gem_vm_ops = {
2785         .fault = i915_gem_fault,
2786         .open = drm_gem_vm_open,
2787         .close = drm_gem_vm_close,
2788 };
2789
2790 static const struct file_operations i915_driver_fops = {
2791         .owner = THIS_MODULE,
2792         .open = drm_open,
2793         .release = drm_release,
2794         .unlocked_ioctl = drm_ioctl,
2795         .mmap = drm_gem_mmap,
2796         .poll = drm_poll,
2797         .read = drm_read,
2798         .compat_ioctl = i915_compat_ioctl,
2799         .llseek = noop_llseek,
2800 };
2801
2802 static int
2803 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2804                           struct drm_file *file)
2805 {
2806         return -ENODEV;
2807 }
2808
2809 static const struct drm_ioctl_desc i915_ioctls[] = {
2810         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2811         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2812         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2813         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2814         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2815         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2816         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2817         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2818         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2819         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2820         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2821         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2822         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2823         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2824         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2825         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2826         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2827         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2828         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2829         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2830         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2831         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2832         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2833         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2834         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2835         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2836         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2837         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2838         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2839         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2840         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2841         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2842         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2843         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2844         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2845         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2846         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2847         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2848         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2849         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2850         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2851         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2852         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2853         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2854         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2855         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2856         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2857         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2858         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2859         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2860         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2861         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2862         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2863         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2864         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2865         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2866 };
2867
2868 static struct drm_driver driver = {
2869         /* Don't use MTRRs here; the Xserver or userspace app should
2870          * deal with them for Intel hardware.
2871          */
2872         .driver_features =
2873             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2874             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2875         .release = i915_driver_release,
2876         .open = i915_driver_open,
2877         .lastclose = i915_driver_lastclose,
2878         .postclose = i915_driver_postclose,
2879
2880         .gem_close_object = i915_gem_close_object,
2881         .gem_free_object_unlocked = i915_gem_free_object,
2882         .gem_vm_ops = &i915_gem_vm_ops,
2883
2884         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2885         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2886         .gem_prime_export = i915_gem_prime_export,
2887         .gem_prime_import = i915_gem_prime_import,
2888
2889         .dumb_create = i915_gem_dumb_create,
2890         .dumb_map_offset = i915_gem_mmap_gtt,
2891         .ioctls = i915_ioctls,
2892         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2893         .fops = &i915_driver_fops,
2894         .name = DRIVER_NAME,
2895         .desc = DRIVER_DESC,
2896         .date = DRIVER_DATE,
2897         .major = DRIVER_MAJOR,
2898         .minor = DRIVER_MINOR,
2899         .patchlevel = DRIVER_PATCHLEVEL,
2900 };
2901
2902 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2903 #include "selftests/mock_drm.c"
2904 #endif