drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pnp.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/slab.h>
  42
  43 /**
  44  * Sets up the hardware status page for devices that need a physical address
  45  * in the register.
  46  */
  47 static int i915_init_phys_hws(struct drm_device *dev)
  48 {
  49         drm_i915_private_t *dev_priv = dev->dev_private;
  50         /* Program Hardware Status Page */
  51         dev_priv->status_page_dmah =
  52                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  53
  54         if (!dev_priv->status_page_dmah) {
  55                 DRM_ERROR("Can not allocate hardware status page\n");
  56                 return -ENOMEM;
  57         }
  58         dev_priv->render_ring.status_page.page_addr
  59                 = dev_priv->status_page_dmah->vaddr;
  60         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  61
  62         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  63
  64         if (IS_I965G(dev))
  65                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  66                                              0xf0;
  67
  68         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  69         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  70         return 0;
  71 }
  72
  73 /**
  74  * Frees the hardware status page, whether it's a physical address or a virtual
  75  * address set up by the X Server.
  76  */
  77 static void i915_free_hws(struct drm_device *dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         if (dev_priv->status_page_dmah) {
  81                 drm_pci_free(dev, dev_priv->status_page_dmah);
  82                 dev_priv->status_page_dmah = NULL;
  83         }
  84
  85         if (dev_priv->render_ring.status_page.gfx_addr) {
  86                 dev_priv->render_ring.status_page.gfx_addr = 0;
  87                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  88         }
  89
  90         /* Need to rewrite hardware status page */
  91         I915_WRITE(HWS_PGA, 0x1ffff000);
  92 }
  93
  94 void i915_kernel_lost_context(struct drm_device * dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         struct drm_i915_master_private *master_priv;
  98         struct intel_ring_buffer *ring = &dev_priv->render_ring;
  99
 100         /*
 101          * We should never lose context on the ring with modesetting
 102          * as we don't expose it to userspace
 103          */
 104         if (drm_core_check_feature(dev, DRIVER_MODESET))
 105                 return;
 106
 107         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 108         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 109         ring->space = ring->head - (ring->tail + 8);
 110         if (ring->space < 0)
 111                 ring->space += ring->size;
 112
 113         if (!dev->primary->master)
 114                 return;
 115
 116         master_priv = dev->primary->master->driver_priv;
 117         if (ring->head == ring->tail && master_priv->sarea_priv)
 118                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 119 }
 120
 121 static int i915_dma_cleanup(struct drm_device * dev)
 122 {
 123         drm_i915_private_t *dev_priv = dev->dev_private;
 124         /* Make sure interrupts are disabled here because the uninstall ioctl
 125          * may not have been called from userspace and after dev_private
 126          * is freed, it's too late.
 127          */
 128         if (dev->irq_enabled)
 129                 drm_irq_uninstall(dev);
 130
 131         mutex_lock(&dev->struct_mutex);
 132         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 133         if (HAS_BSD(dev))
 134                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 135         mutex_unlock(&dev->struct_mutex);
 136
 137         /* Clear the HWS virtual address at teardown */
 138         if (I915_NEED_GFX_HWS(dev))
 139                 i915_free_hws(dev);
 140
 141         return 0;
 142 }
 143
 144 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 145 {
 146         drm_i915_private_t *dev_priv = dev->dev_private;
 147         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 148
 149         master_priv->sarea = drm_getsarea(dev);
 150         if (master_priv->sarea) {
 151                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 152                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 153         } else {
 154                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 155         }
 156
 157         if (init->ring_size != 0) {
 158                 if (dev_priv->render_ring.gem_object != NULL) {
 159                         i915_dma_cleanup(dev);
 160                         DRM_ERROR("Client tried to initialize ringbuffer in "
 161                                   "GEM mode\n");
 162                         return -EINVAL;
 163                 }
 164
 165                 dev_priv->render_ring.size = init->ring_size;
 166
 167                 dev_priv->render_ring.map.offset = init->ring_start;
 168                 dev_priv->render_ring.map.size = init->ring_size;
 169                 dev_priv->render_ring.map.type = 0;
 170                 dev_priv->render_ring.map.flags = 0;
 171                 dev_priv->render_ring.map.mtrr = 0;
 172
 173                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 174
 175                 if (dev_priv->render_ring.map.handle == NULL) {
 176                         i915_dma_cleanup(dev);
 177                         DRM_ERROR("can not ioremap virtual address for"
 178                                   " ring buffer\n");
 179                         return -ENOMEM;
 180                 }
 181         }
 182
 183         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 184
 185         dev_priv->cpp = init->cpp;
 186         dev_priv->back_offset = init->back_offset;
 187         dev_priv->front_offset = init->front_offset;
 188         dev_priv->current_page = 0;
 189         if (master_priv->sarea_priv)
 190                 master_priv->sarea_priv->pf_current_page = 0;
 191
 192         /* Allow hardware batchbuffers unless told otherwise.
 193          */
 194         dev_priv->allow_batchbuffer = 1;
 195
 196         return 0;
 197 }
 198
 199 static int i915_dma_resume(struct drm_device * dev)
 200 {
 201         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 202
 203         struct intel_ring_buffer *ring;
 204         DRM_DEBUG_DRIVER("%s\n", __func__);
 205
 206         ring = &dev_priv->render_ring;
 207
 208         if (ring->map.handle == NULL) {
 209                 DRM_ERROR("can not ioremap virtual address for"
 210                           " ring buffer\n");
 211                 return -ENOMEM;
 212         }
 213
 214         /* Program Hardware Status Page */
 215         if (!ring->status_page.page_addr) {
 216                 DRM_ERROR("Can not find hardware status page\n");
 217                 return -EINVAL;
 218         }
 219         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 220                                 ring->status_page.page_addr);
 221         if (ring->status_page.gfx_addr != 0)
 222                 ring->setup_status_page(dev, ring);
 223         else
 224                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 225
 226         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 227
 228         return 0;
 229 }
 230
 231 static int i915_dma_init(struct drm_device *dev, void *data,
 232                          struct drm_file *file_priv)
 233 {
 234         drm_i915_init_t *init = data;
 235         int retcode = 0;
 236
 237         switch (init->func) {
 238         case I915_INIT_DMA:
 239                 retcode = i915_initialize(dev, init);
 240                 break;
 241         case I915_CLEANUP_DMA:
 242                 retcode = i915_dma_cleanup(dev);
 243                 break;
 244         case I915_RESUME_DMA:
 245                 retcode = i915_dma_resume(dev);
 246                 break;
 247         default:
 248                 retcode = -EINVAL;
 249                 break;
 250         }
 251
 252         return retcode;
 253 }
 254
 255 /* Implement basically the same security restrictions as hardware does
 256  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 257  *
 258  * Most of the calculations below involve calculating the size of a
 259  * particular instruction.  It's important to get the size right as
 260  * that tells us where the next instruction to check is.  Any illegal
 261  * instruction detected will be given a size of zero, which is a
 262  * signal to abort the rest of the buffer.
 263  */
 264 static int do_validate_cmd(int cmd)
 265 {
 266         switch (((cmd >> 29) & 0x7)) {
 267         case 0x0:
 268                 switch ((cmd >> 23) & 0x3f) {
 269                 case 0x0:
 270                         return 1;       /* MI_NOOP */
 271                 case 0x4:
 272                         return 1;       /* MI_FLUSH */
 273                 default:
 274                         return 0;       /* disallow everything else */
 275                 }
 276                 break;
 277         case 0x1:
 278                 return 0;       /* reserved */
 279         case 0x2:
 280                 return (cmd & 0xff) + 2;        /* 2d commands */
 281         case 0x3:
 282                 if (((cmd >> 24) & 0x1f) <= 0x18)
 283                         return 1;
 284
 285                 switch ((cmd >> 24) & 0x1f) {
 286                 case 0x1c:
 287                         return 1;
 288                 case 0x1d:
 289                         switch ((cmd >> 16) & 0xff) {
 290                         case 0x3:
 291                                 return (cmd & 0x1f) + 2;
 292                         case 0x4:
 293                                 return (cmd & 0xf) + 2;
 294                         default:
 295                                 return (cmd & 0xffff) + 2;
 296                         }
 297                 case 0x1e:
 298                         if (cmd & (1 << 23))
 299                                 return (cmd & 0xffff) + 1;
 300                         else
 301                                 return 1;
 302                 case 0x1f:
 303                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 304                                 return (cmd & 0x1ffff) + 2;
 305                         else if (cmd & (1 << 17))       /* indirect random */
 306                                 if ((cmd & 0xffff) == 0)
 307                                         return 0;       /* unknown length, too hard */
 308                                 else
 309                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 310                         else
 311                                 return 2;       /* indirect sequential */
 312                 default:
 313                         return 0;
 314                 }
 315         default:
 316                 return 0;
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int validate_cmd(int cmd)
 323 {
 324         int ret = do_validate_cmd(cmd);
 325
 326 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 327
 328         return ret;
 329 }
 330
 331 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 332 {
 333         drm_i915_private_t *dev_priv = dev->dev_private;
 334         int i;
 335
 336         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 337                 return -EINVAL;
 338
 339         BEGIN_LP_RING((dwords+1)&~1);
 340
 341         for (i = 0; i < dwords;) {
 342                 int cmd, sz;
 343
 344                 cmd = buffer[i];
 345
 346                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 347                         return -EINVAL;
 348
 349                 OUT_RING(cmd);
 350
 351                 while (++i, --sz) {
 352                         OUT_RING(buffer[i]);
 353                 }
 354         }
 355
 356         if (dwords & 1)
 357                 OUT_RING(0);
 358
 359         ADVANCE_LP_RING();
 360
 361         return 0;
 362 }
 363
 364 int
 365 i915_emit_box(struct drm_device *dev,
 366               struct drm_clip_rect *boxes,
 367               int i, int DR1, int DR4)
 368 {
 369         struct drm_clip_rect box = boxes[i];
 370
 371         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 372                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 373                           box.x1, box.y1, box.x2, box.y2);
 374                 return -EINVAL;
 375         }
 376
 377         if (IS_I965G(dev)) {
 378                 BEGIN_LP_RING(4);
 379                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 380                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 381                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 382                 OUT_RING(DR4);
 383                 ADVANCE_LP_RING();
 384         } else {
 385                 BEGIN_LP_RING(6);
 386                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 387                 OUT_RING(DR1);
 388                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 389                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 390                 OUT_RING(DR4);
 391                 OUT_RING(0);
 392                 ADVANCE_LP_RING();
 393         }
 394
 395         return 0;
 396 }
 397
 398 /* XXX: Emitting the counter should really be moved to part of the IRQ
 399  * emit. For now, do it in both places:
 400  */
 401
 402 static void i915_emit_breadcrumb(struct drm_device *dev)
 403 {
 404         drm_i915_private_t *dev_priv = dev->dev_private;
 405         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 406
 407         dev_priv->counter++;
 408         if (dev_priv->counter > 0x7FFFFFFFUL)
 409                 dev_priv->counter = 0;
 410         if (master_priv->sarea_priv)
 411                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 412
 413         BEGIN_LP_RING(4);
 414         OUT_RING(MI_STORE_DWORD_INDEX);
 415         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 416         OUT_RING(dev_priv->counter);
 417         OUT_RING(0);
 418         ADVANCE_LP_RING();
 419 }
 420
 421 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 422                                    drm_i915_cmdbuffer_t *cmd,
 423                                    struct drm_clip_rect *cliprects,
 424                                    void *cmdbuf)
 425 {
 426         int nbox = cmd->num_cliprects;
 427         int i = 0, count, ret;
 428
 429         if (cmd->sz & 0x3) {
 430                 DRM_ERROR("alignment");
 431                 return -EINVAL;
 432         }
 433
 434         i915_kernel_lost_context(dev);
 435
 436         count = nbox ? nbox : 1;
 437
 438         for (i = 0; i < count; i++) {
 439                 if (i < nbox) {
 440                         ret = i915_emit_box(dev, cliprects, i,
 441                                             cmd->DR1, cmd->DR4);
 442                         if (ret)
 443                                 return ret;
 444                 }
 445
 446                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 447                 if (ret)
 448                         return ret;
 449         }
 450
 451         i915_emit_breadcrumb(dev);
 452         return 0;
 453 }
 454
 455 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 456                                      drm_i915_batchbuffer_t * batch,
 457                                      struct drm_clip_rect *cliprects)
 458 {
 459         int nbox = batch->num_cliprects;
 460         int i = 0, count;
 461
 462         if ((batch->start | batch->used) & 0x7) {
 463                 DRM_ERROR("alignment");
 464                 return -EINVAL;
 465         }
 466
 467         i915_kernel_lost_context(dev);
 468
 469         count = nbox ? nbox : 1;
 470
 471         for (i = 0; i < count; i++) {
 472                 if (i < nbox) {
 473                         int ret = i915_emit_box(dev, cliprects, i,
 474                                                 batch->DR1, batch->DR4);
 475                         if (ret)
 476                                 return ret;
 477                 }
 478
 479                 if (!IS_I830(dev) && !IS_845G(dev)) {
 480                         BEGIN_LP_RING(2);
 481                         if (IS_I965G(dev)) {
 482                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 483                                 OUT_RING(batch->start);
 484                         } else {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 486                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 487                         }
 488                         ADVANCE_LP_RING();
 489                 } else {
 490                         BEGIN_LP_RING(4);
 491                         OUT_RING(MI_BATCH_BUFFER);
 492                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 493                         OUT_RING(batch->start + batch->used - 4);
 494                         OUT_RING(0);
 495                         ADVANCE_LP_RING();
 496                 }
 497         }
 498
 499         i915_emit_breadcrumb(dev);
 500
 501         return 0;
 502 }
 503
 504 static int i915_dispatch_flip(struct drm_device * dev)
 505 {
 506         drm_i915_private_t *dev_priv = dev->dev_private;
 507         struct drm_i915_master_private *master_priv =
 508                 dev->primary->master->driver_priv;
 509
 510         if (!master_priv->sarea_priv)
 511                 return -EINVAL;
 512
 513         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 514                           __func__,
 515                          dev_priv->current_page,
 516                          master_priv->sarea_priv->pf_current_page);
 517
 518         i915_kernel_lost_context(dev);
 519
 520         BEGIN_LP_RING(2);
 521         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 522         OUT_RING(0);
 523         ADVANCE_LP_RING();
 524
 525         BEGIN_LP_RING(6);
 526         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 527         OUT_RING(0);
 528         if (dev_priv->current_page == 0) {
 529                 OUT_RING(dev_priv->back_offset);
 530                 dev_priv->current_page = 1;
 531         } else {
 532                 OUT_RING(dev_priv->front_offset);
 533                 dev_priv->current_page = 0;
 534         }
 535         OUT_RING(0);
 536         ADVANCE_LP_RING();
 537
 538         BEGIN_LP_RING(2);
 539         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 540         OUT_RING(0);
 541         ADVANCE_LP_RING();
 542
 543         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 544
 545         BEGIN_LP_RING(4);
 546         OUT_RING(MI_STORE_DWORD_INDEX);
 547         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 548         OUT_RING(dev_priv->counter);
 549         OUT_RING(0);
 550         ADVANCE_LP_RING();
 551
 552         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 553         return 0;
 554 }
 555
 556 static int i915_quiescent(struct drm_device * dev)
 557 {
 558         drm_i915_private_t *dev_priv = dev->dev_private;
 559
 560         i915_kernel_lost_context(dev);
 561         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 562                                       dev_priv->render_ring.size - 8);
 563 }
 564
 565 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 566                             struct drm_file *file_priv)
 567 {
 568         int ret;
 569
 570         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 571
 572         mutex_lock(&dev->struct_mutex);
 573         ret = i915_quiescent(dev);
 574         mutex_unlock(&dev->struct_mutex);
 575
 576         return ret;
 577 }
 578
 579 static int i915_batchbuffer(struct drm_device *dev, void *data,
 580                             struct drm_file *file_priv)
 581 {
 582         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 583         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 584         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 585             master_priv->sarea_priv;
 586         drm_i915_batchbuffer_t *batch = data;
 587         int ret;
 588         struct drm_clip_rect *cliprects = NULL;
 589
 590         if (!dev_priv->allow_batchbuffer) {
 591                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 592                 return -EINVAL;
 593         }
 594
 595         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 596                         batch->start, batch->used, batch->num_cliprects);
 597
 598         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 599
 600         if (batch->num_cliprects < 0)
 601                 return -EINVAL;
 602
 603         if (batch->num_cliprects) {
 604                 cliprects = kcalloc(batch->num_cliprects,
 605                                     sizeof(struct drm_clip_rect),
 606                                     GFP_KERNEL);
 607                 if (cliprects == NULL)
 608                         return -ENOMEM;
 609
 610                 ret = copy_from_user(cliprects, batch->cliprects,
 611                                      batch->num_cliprects *
 612                                      sizeof(struct drm_clip_rect));
 613                 if (ret != 0)
 614                         goto fail_free;
 615         }
 616
 617         mutex_lock(&dev->struct_mutex);
 618         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 619         mutex_unlock(&dev->struct_mutex);
 620
 621         if (sarea_priv)
 622                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 623
 624 fail_free:
 625         kfree(cliprects);
 626
 627         return ret;
 628 }
 629
 630 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 631                           struct drm_file *file_priv)
 632 {
 633         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 634         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 635         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 636             master_priv->sarea_priv;
 637         drm_i915_cmdbuffer_t *cmdbuf = data;
 638         struct drm_clip_rect *cliprects = NULL;
 639         void *batch_data;
 640         int ret;
 641
 642         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 643                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 644
 645         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 646
 647         if (cmdbuf->num_cliprects < 0)
 648                 return -EINVAL;
 649
 650         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 651         if (batch_data == NULL)
 652                 return -ENOMEM;
 653
 654         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 655         if (ret != 0)
 656                 goto fail_batch_free;
 657
 658         if (cmdbuf->num_cliprects) {
 659                 cliprects = kcalloc(cmdbuf->num_cliprects,
 660                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 661                 if (cliprects == NULL) {
 662                         ret = -ENOMEM;
 663                         goto fail_batch_free;
 664                 }
 665
 666                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 667                                      cmdbuf->num_cliprects *
 668                                      sizeof(struct drm_clip_rect));
 669                 if (ret != 0)
 670                         goto fail_clip_free;
 671         }
 672
 673         mutex_lock(&dev->struct_mutex);
 674         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 675         mutex_unlock(&dev->struct_mutex);
 676         if (ret) {
 677                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 678                 goto fail_clip_free;
 679         }
 680
 681         if (sarea_priv)
 682                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 683
 684 fail_clip_free:
 685         kfree(cliprects);
 686 fail_batch_free:
 687         kfree(batch_data);
 688
 689         return ret;
 690 }
 691
 692 static int i915_flip_bufs(struct drm_device *dev, void *data,
 693                           struct drm_file *file_priv)
 694 {
 695         int ret;
 696
 697         DRM_DEBUG_DRIVER("%s\n", __func__);
 698
 699         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 700
 701         mutex_lock(&dev->struct_mutex);
 702         ret = i915_dispatch_flip(dev);
 703         mutex_unlock(&dev->struct_mutex);
 704
 705         return ret;
 706 }
 707
 708 static int i915_getparam(struct drm_device *dev, void *data,
 709                          struct drm_file *file_priv)
 710 {
 711         drm_i915_private_t *dev_priv = dev->dev_private;
 712         drm_i915_getparam_t *param = data;
 713         int value;
 714
 715         if (!dev_priv) {
 716                 DRM_ERROR("called with no initialization\n");
 717                 return -EINVAL;
 718         }
 719
 720         switch (param->param) {
 721         case I915_PARAM_IRQ_ACTIVE:
 722                 value = dev->pdev->irq ? 1 : 0;
 723                 break;
 724         case I915_PARAM_ALLOW_BATCHBUFFER:
 725                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 726                 break;
 727         case I915_PARAM_LAST_DISPATCH:
 728                 value = READ_BREADCRUMB(dev_priv);
 729                 break;
 730         case I915_PARAM_CHIPSET_ID:
 731                 value = dev->pci_device;
 732                 break;
 733         case I915_PARAM_HAS_GEM:
 734                 value = dev_priv->has_gem;
 735                 break;
 736         case I915_PARAM_NUM_FENCES_AVAIL:
 737                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 738                 break;
 739         case I915_PARAM_HAS_OVERLAY:
 740                 value = dev_priv->overlay ? 1 : 0;
 741                 break;
 742         case I915_PARAM_HAS_PAGEFLIPPING:
 743                 value = 1;
 744                 break;
 745         case I915_PARAM_HAS_EXECBUF2:
 746                 /* depends on GEM */
 747                 value = dev_priv->has_gem;
 748                 break;
 749         case I915_PARAM_HAS_BSD:
 750                 value = HAS_BSD(dev);
 751                 break;
 752         default:
 753                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 754                                  param->param);
 755                 return -EINVAL;
 756         }
 757
 758         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 759                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 760                 return -EFAULT;
 761         }
 762
 763         return 0;
 764 }
 765
 766 static int i915_setparam(struct drm_device *dev, void *data,
 767                          struct drm_file *file_priv)
 768 {
 769         drm_i915_private_t *dev_priv = dev->dev_private;
 770         drm_i915_setparam_t *param = data;
 771
 772         if (!dev_priv) {
 773                 DRM_ERROR("called with no initialization\n");
 774                 return -EINVAL;
 775         }
 776
 777         switch (param->param) {
 778         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 779                 break;
 780         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 781                 dev_priv->tex_lru_log_granularity = param->value;
 782                 break;
 783         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 784                 dev_priv->allow_batchbuffer = param->value;
 785                 break;
 786         case I915_SETPARAM_NUM_USED_FENCES:
 787                 if (param->value > dev_priv->num_fence_regs ||
 788                     param->value < 0)
 789                         return -EINVAL;
 790                 /* Userspace can use first N regs */
 791                 dev_priv->fence_reg_start = param->value;
 792                 break;
 793         default:
 794                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 795                                         param->param);
 796                 return -EINVAL;
 797         }
 798
 799         return 0;
 800 }
 801
 802 static int i915_set_status_page(struct drm_device *dev, void *data,
 803                                 struct drm_file *file_priv)
 804 {
 805         drm_i915_private_t *dev_priv = dev->dev_private;
 806         drm_i915_hws_addr_t *hws = data;
 807         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 808
 809         if (!I915_NEED_GFX_HWS(dev))
 810                 return -EINVAL;
 811
 812         if (!dev_priv) {
 813                 DRM_ERROR("called with no initialization\n");
 814                 return -EINVAL;
 815         }
 816
 817         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 818                 WARN(1, "tried to set status page when mode setting active\n");
 819                 return 0;
 820         }
 821
 822         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 823
 824         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 825
 826         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 827         dev_priv->hws_map.size = 4*1024;
 828         dev_priv->hws_map.type = 0;
 829         dev_priv->hws_map.flags = 0;
 830         dev_priv->hws_map.mtrr = 0;
 831
 832         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 833         if (dev_priv->hws_map.handle == NULL) {
 834                 i915_dma_cleanup(dev);
 835                 ring->status_page.gfx_addr = 0;
 836                 DRM_ERROR("can not ioremap virtual address for"
 837                                 " G33 hw status page\n");
 838                 return -ENOMEM;
 839         }
 840         ring->status_page.page_addr = dev_priv->hws_map.handle;
 841         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 842         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 843
 844         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 845                          ring->status_page.gfx_addr);
 846         DRM_DEBUG_DRIVER("load hws at %p\n",
 847                          ring->status_page.page_addr);
 848         return 0;
 849 }
 850
 851 static int i915_get_bridge_dev(struct drm_device *dev)
 852 {
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854
 855         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 856         if (!dev_priv->bridge_dev) {
 857                 DRM_ERROR("bridge device not found\n");
 858                 return -1;
 859         }
 860         return 0;
 861 }
 862
 863 #define MCHBAR_I915 0x44
 864 #define MCHBAR_I965 0x48
 865 #define MCHBAR_SIZE (4*4096)
 866
 867 #define DEVEN_REG 0x54
 868 #define   DEVEN_MCHBAR_EN (1 << 28)
 869
 870 /* Allocate space for the MCH regs if needed, return nonzero on error */
 871 static int
 872 intel_alloc_mchbar_resource(struct drm_device *dev)
 873 {
 874         drm_i915_private_t *dev_priv = dev->dev_private;
 875         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 876         u32 temp_lo, temp_hi = 0;
 877         u64 mchbar_addr;
 878         int ret = 0;
 879
 880         if (IS_I965G(dev))
 881                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 882         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 883         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 884
 885         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 886 #ifdef CONFIG_PNP
 887         if (mchbar_addr &&
 888             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 889                 ret = 0;
 890                 goto out;
 891         }
 892 #endif
 893
 894         /* Get some space for it */
 895         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 896                                      MCHBAR_SIZE, MCHBAR_SIZE,
 897                                      PCIBIOS_MIN_MEM,
 898                                      0,   pcibios_align_resource,
 899                                      dev_priv->bridge_dev);
 900         if (ret) {
 901                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 902                 dev_priv->mch_res.start = 0;
 903                 goto out;
 904         }
 905
 906         if (IS_I965G(dev))
 907                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 908                                        upper_32_bits(dev_priv->mch_res.start));
 909
 910         pci_write_config_dword(dev_priv->bridge_dev, reg,
 911                                lower_32_bits(dev_priv->mch_res.start));
 912 out:
 913         return ret;
 914 }
 915
 916 /* Setup MCHBAR if possible, return true if we should disable it again */
 917 static void
 918 intel_setup_mchbar(struct drm_device *dev)
 919 {
 920         drm_i915_private_t *dev_priv = dev->dev_private;
 921         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 922         u32 temp;
 923         bool enabled;
 924
 925         dev_priv->mchbar_need_disable = false;
 926
 927         if (IS_I915G(dev) || IS_I915GM(dev)) {
 928                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 929                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 930         } else {
 931                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 932                 enabled = temp & 1;
 933         }
 934
 935         /* If it's already enabled, don't have to do anything */
 936         if (enabled)
 937                 return;
 938
 939         if (intel_alloc_mchbar_resource(dev))
 940                 return;
 941
 942         dev_priv->mchbar_need_disable = true;
 943
 944         /* Space is allocated or reserved, so enable it. */
 945         if (IS_I915G(dev) || IS_I915GM(dev)) {
 946                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 947                                        temp | DEVEN_MCHBAR_EN);
 948         } else {
 949                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 950                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 951         }
 952 }
 953
 954 static void
 955 intel_teardown_mchbar(struct drm_device *dev)
 956 {
 957         drm_i915_private_t *dev_priv = dev->dev_private;
 958         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 959         u32 temp;
 960
 961         if (dev_priv->mchbar_need_disable) {
 962                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 963                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 964                         temp &= ~DEVEN_MCHBAR_EN;
 965                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 966                 } else {
 967                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 968                         temp &= ~1;
 969                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 970                 }
 971         }
 972
 973         if (dev_priv->mch_res.start)
 974                 release_resource(&dev_priv->mch_res);
 975 }
 976
 977 /**
 978  * i915_probe_agp - get AGP bootup configuration
 979  * @pdev: PCI device
 980  * @aperture_size: returns AGP aperture configured size
 981  * @preallocated_size: returns size of BIOS preallocated AGP space
 982  *
 983  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 984  * some RAM for the framebuffer at early boot.  This code figures out
 985  * how much was set aside so we can use it for our own purposes.
 986  */
 987 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 988                           uint32_t *preallocated_size,
 989                           uint32_t *start)
 990 {
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         u16 tmp = 0;
 993         unsigned long overhead;
 994         unsigned long stolen;
 995
 996         /* Get the fb aperture size and "stolen" memory amount. */
 997         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
 998
 999         *aperture_size = 1024 * 1024;
1000         *preallocated_size = 1024 * 1024;
1001
1002         switch (dev->pdev->device) {
1003         case PCI_DEVICE_ID_INTEL_82830_CGC:
1004         case PCI_DEVICE_ID_INTEL_82845G_IG:
1005         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1006         case PCI_DEVICE_ID_INTEL_82865_IG:
1007                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1008                         *aperture_size *= 64;
1009                 else
1010                         *aperture_size *= 128;
1011                 break;
1012         default:
1013                 /* 9xx supports large sizes, just look at the length */
1014                 *aperture_size = pci_resource_len(dev->pdev, 2);
1015                 break;
1016         }
1017
1018         /*
1019          * Some of the preallocated space is taken by the GTT
1020          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1021          */
1022         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1023                 overhead = 4096;
1024         else
1025                 overhead = (*aperture_size / 1024) + 4096;
1026
1027         if (IS_GEN6(dev)) {
1028                 /* SNB has memory control reg at 0x50.w */
1029                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1030
1031                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1032                 case INTEL_855_GMCH_GMS_DISABLED:
1033                         DRM_ERROR("video memory is disabled\n");
1034                         return -1;
1035                 case SNB_GMCH_GMS_STOLEN_32M:
1036                         stolen = 32 * 1024 * 1024;
1037                         break;
1038                 case SNB_GMCH_GMS_STOLEN_64M:
1039                         stolen = 64 * 1024 * 1024;
1040                         break;
1041                 case SNB_GMCH_GMS_STOLEN_96M:
1042                         stolen = 96 * 1024 * 1024;
1043                         break;
1044                 case SNB_GMCH_GMS_STOLEN_128M:
1045                         stolen = 128 * 1024 * 1024;
1046                         break;
1047                 case SNB_GMCH_GMS_STOLEN_160M:
1048                         stolen = 160 * 1024 * 1024;
1049                         break;
1050                 case SNB_GMCH_GMS_STOLEN_192M:
1051                         stolen = 192 * 1024 * 1024;
1052                         break;
1053                 case SNB_GMCH_GMS_STOLEN_224M:
1054                         stolen = 224 * 1024 * 1024;
1055                         break;
1056                 case SNB_GMCH_GMS_STOLEN_256M:
1057                         stolen = 256 * 1024 * 1024;
1058                         break;
1059                 case SNB_GMCH_GMS_STOLEN_288M:
1060                         stolen = 288 * 1024 * 1024;
1061                         break;
1062                 case SNB_GMCH_GMS_STOLEN_320M:
1063                         stolen = 320 * 1024 * 1024;
1064                         break;
1065                 case SNB_GMCH_GMS_STOLEN_352M:
1066                         stolen = 352 * 1024 * 1024;
1067                         break;
1068                 case SNB_GMCH_GMS_STOLEN_384M:
1069                         stolen = 384 * 1024 * 1024;
1070                         break;
1071                 case SNB_GMCH_GMS_STOLEN_416M:
1072                         stolen = 416 * 1024 * 1024;
1073                         break;
1074                 case SNB_GMCH_GMS_STOLEN_448M:
1075                         stolen = 448 * 1024 * 1024;
1076                         break;
1077                 case SNB_GMCH_GMS_STOLEN_480M:
1078                         stolen = 480 * 1024 * 1024;
1079                         break;
1080                 case SNB_GMCH_GMS_STOLEN_512M:
1081                         stolen = 512 * 1024 * 1024;
1082                         break;
1083                 default:
1084                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1085                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1086                         return -1;
1087                 }
1088         } else {
1089                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1090                 case INTEL_855_GMCH_GMS_DISABLED:
1091                         DRM_ERROR("video memory is disabled\n");
1092                         return -1;
1093                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1094                         stolen = 1 * 1024 * 1024;
1095                         break;
1096                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1097                         stolen = 4 * 1024 * 1024;
1098                         break;
1099                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1100                         stolen = 8 * 1024 * 1024;
1101                         break;
1102                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1103                         stolen = 16 * 1024 * 1024;
1104                         break;
1105                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1106                         stolen = 32 * 1024 * 1024;
1107                         break;
1108                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1109                         stolen = 48 * 1024 * 1024;
1110                         break;
1111                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1112                         stolen = 64 * 1024 * 1024;
1113                         break;
1114                 case INTEL_GMCH_GMS_STOLEN_128M:
1115                         stolen = 128 * 1024 * 1024;
1116                         break;
1117                 case INTEL_GMCH_GMS_STOLEN_256M:
1118                         stolen = 256 * 1024 * 1024;
1119                         break;
1120                 case INTEL_GMCH_GMS_STOLEN_96M:
1121                         stolen = 96 * 1024 * 1024;
1122                         break;
1123                 case INTEL_GMCH_GMS_STOLEN_160M:
1124                         stolen = 160 * 1024 * 1024;
1125                         break;
1126                 case INTEL_GMCH_GMS_STOLEN_224M:
1127                         stolen = 224 * 1024 * 1024;
1128                         break;
1129                 case INTEL_GMCH_GMS_STOLEN_352M:
1130                         stolen = 352 * 1024 * 1024;
1131                         break;
1132                 default:
1133                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1134                                   tmp & INTEL_GMCH_GMS_MASK);
1135                         return -1;
1136                 }
1137         }
1138
1139         *preallocated_size = stolen - overhead;
1140         *start = overhead;
1141
1142         return 0;
1143 }
1144
1145 #define PTE_ADDRESS_MASK                0xfffff000
1146 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1147 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1148 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1149 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1150 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1151 #define PTE_VALID                       (1 << 0)
1152
1153 /**
1154  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1155  * @dev: drm device
1156  * @gtt_addr: address to translate
1157  *
1158  * Some chip functions require allocations from stolen space but need the
1159  * physical address of the memory in question.  We use this routine
1160  * to get a physical address suitable for register programming from a given
1161  * GTT address.
1162  */
1163 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1164                                       unsigned long gtt_addr)
1165 {
1166         unsigned long *gtt;
1167         unsigned long entry, phys;
1168         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1169         int gtt_offset, gtt_size;
1170
1171         if (IS_I965G(dev)) {
1172                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1173                         gtt_offset = 2*1024*1024;
1174                         gtt_size = 2*1024*1024;
1175                 } else {
1176                         gtt_offset = 512*1024;
1177                         gtt_size = 512*1024;
1178                 }
1179         } else {
1180                 gtt_bar = 3;
1181                 gtt_offset = 0;
1182                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1183         }
1184
1185         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1186                          gtt_size);
1187         if (!gtt) {
1188                 DRM_ERROR("ioremap of GTT failed\n");
1189                 return 0;
1190         }
1191
1192         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1193
1194         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1195
1196         /* Mask out these reserved bits on this hardware. */
1197         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1198             IS_I945G(dev) || IS_I945GM(dev)) {
1199                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1200         }
1201
1202         /* If it's not a mapping type we know, then bail. */
1203         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1204             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1205                 iounmap(gtt);
1206                 return 0;
1207         }
1208
1209         if (!(entry & PTE_VALID)) {
1210                 DRM_ERROR("bad GTT entry in stolen space\n");
1211                 iounmap(gtt);
1212                 return 0;
1213         }
1214
1215         iounmap(gtt);
1216
1217         phys =(entry & PTE_ADDRESS_MASK) |
1218                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1219
1220         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1221
1222         return phys;
1223 }
1224
1225 static void i915_warn_stolen(struct drm_device *dev)
1226 {
1227         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1228         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1229 }
1230
1231 static void i915_setup_compression(struct drm_device *dev, int size)
1232 {
1233         struct drm_i915_private *dev_priv = dev->dev_private;
1234         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1235         unsigned long cfb_base;
1236         unsigned long ll_base = 0;
1237
1238         /* Leave 1M for line length buffer & misc. */
1239         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1240         if (!compressed_fb) {
1241                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1242                 i915_warn_stolen(dev);
1243                 return;
1244         }
1245
1246         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1247         if (!compressed_fb) {
1248                 i915_warn_stolen(dev);
1249                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1250                 return;
1251         }
1252
1253         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1254         if (!cfb_base) {
1255                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1256                 drm_mm_put_block(compressed_fb);
1257         }
1258
1259         if (!IS_GM45(dev)) {
1260                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1261                                                     4096, 0);
1262                 if (!compressed_llb) {
1263                         i915_warn_stolen(dev);
1264                         return;
1265                 }
1266
1267                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1268                 if (!compressed_llb) {
1269                         i915_warn_stolen(dev);
1270                         return;
1271                 }
1272
1273                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1274                 if (!ll_base) {
1275                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1276                         drm_mm_put_block(compressed_fb);
1277                         drm_mm_put_block(compressed_llb);
1278                 }
1279         }
1280
1281         dev_priv->cfb_size = size;
1282
1283         intel_disable_fbc(dev);
1284         dev_priv->compressed_fb = compressed_fb;
1285
1286         if (IS_GM45(dev)) {
1287                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1288         } else {
1289                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1290                 I915_WRITE(FBC_LL_BASE, ll_base);
1291                 dev_priv->compressed_llb = compressed_llb;
1292         }
1293
1294         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1295                   ll_base, size >> 20);
1296 }
1297
1298 static void i915_cleanup_compression(struct drm_device *dev)
1299 {
1300         struct drm_i915_private *dev_priv = dev->dev_private;
1301
1302         drm_mm_put_block(dev_priv->compressed_fb);
1303         if (!IS_GM45(dev))
1304                 drm_mm_put_block(dev_priv->compressed_llb);
1305 }
1306
1307 /* true = enable decode, false = disable decoder */
1308 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1309 {
1310         struct drm_device *dev = cookie;
1311
1312         intel_modeset_vga_set_state(dev, state);
1313         if (state)
1314                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1315                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1316         else
1317                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1318 }
1319
1320 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1321 {
1322         struct drm_device *dev = pci_get_drvdata(pdev);
1323         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1324         if (state == VGA_SWITCHEROO_ON) {
1325                 printk(KERN_INFO "i915: switched on\n");
1326                 /* i915 resume handler doesn't set to D0 */
1327                 pci_set_power_state(dev->pdev, PCI_D0);
1328                 i915_resume(dev);
1329                 drm_kms_helper_poll_enable(dev);
1330         } else {
1331                 printk(KERN_ERR "i915: switched off\n");
1332                 drm_kms_helper_poll_disable(dev);
1333                 i915_suspend(dev, pmm);
1334         }
1335 }
1336
1337 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1338 {
1339         struct drm_device *dev = pci_get_drvdata(pdev);
1340         bool can_switch;
1341
1342         spin_lock(&dev->count_lock);
1343         can_switch = (dev->open_count == 0);
1344         spin_unlock(&dev->count_lock);
1345         return can_switch;
1346 }
1347
1348 static int i915_load_modeset_init(struct drm_device *dev,
1349                                   unsigned long prealloc_start,
1350                                   unsigned long prealloc_size,
1351                                   unsigned long agp_size)
1352 {
1353         struct drm_i915_private *dev_priv = dev->dev_private;
1354         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1355         int ret = 0;
1356
1357         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1358                 0xff000000;
1359
1360         /* Basic memrange allocator for stolen space (aka vram) */
1361         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1362         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1363
1364         /* We're off and running w/KMS */
1365         dev_priv->mm.suspended = 0;
1366
1367         /* Let GEM Manage from end of prealloc space to end of aperture.
1368          *
1369          * However, leave one page at the end still bound to the scratch page.
1370          * There are a number of places where the hardware apparently
1371          * prefetches past the end of the object, and we've seen multiple
1372          * hangs with the GPU head pointer stuck in a batchbuffer bound
1373          * at the last page of the aperture.  One page should be enough to
1374          * keep any prefetching inside of the aperture.
1375          */
1376         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1377
1378         mutex_lock(&dev->struct_mutex);
1379         ret = i915_gem_init_ringbuffer(dev);
1380         mutex_unlock(&dev->struct_mutex);
1381         if (ret)
1382                 goto out;
1383
1384         /* Try to set up FBC with a reasonable compressed buffer size */
1385         if (I915_HAS_FBC(dev) && i915_powersave) {
1386                 int cfb_size;
1387
1388                 /* Try to get an 8M buffer... */
1389                 if (prealloc_size > (9*1024*1024))
1390                         cfb_size = 8*1024*1024;
1391                 else /* fall back to 7/8 of the stolen space */
1392                         cfb_size = prealloc_size * 7 / 8;
1393                 i915_setup_compression(dev, cfb_size);
1394         }
1395
1396         /* Allow hardware batchbuffers unless told otherwise.
1397          */
1398         dev_priv->allow_batchbuffer = 1;
1399
1400         ret = intel_init_bios(dev);
1401         if (ret)
1402                 DRM_INFO("failed to find VBIOS tables\n");
1403
1404         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1405         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1406         if (ret)
1407                 goto cleanup_ringbuffer;
1408
1409         ret = vga_switcheroo_register_client(dev->pdev,
1410                                              i915_switcheroo_set_state,
1411                                              i915_switcheroo_can_switch);
1412         if (ret)
1413                 goto cleanup_vga_client;
1414
1415         /* IIR "flip pending" bit means done if this bit is set */
1416         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1417                 dev_priv->flip_pending_is_done = true;
1418
1419         intel_modeset_init(dev);
1420
1421         ret = drm_irq_install(dev);
1422         if (ret)
1423                 goto cleanup_vga_switcheroo;
1424
1425         /* Always safe in the mode setting case. */
1426         /* FIXME: do pre/post-mode set stuff in core KMS code */
1427         dev->vblank_disable_allowed = 1;
1428
1429         /*
1430          * Initialize the hardware status page IRQ location.
1431          */
1432
1433         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1434
1435         ret = intel_fbdev_init(dev);
1436         if (ret)
1437                 goto cleanup_irq;
1438
1439         drm_kms_helper_poll_init(dev);
1440         return 0;
1441
1442 cleanup_irq:
1443         drm_irq_uninstall(dev);
1444 cleanup_vga_switcheroo:
1445         vga_switcheroo_unregister_client(dev->pdev);
1446 cleanup_vga_client:
1447         vga_client_register(dev->pdev, NULL, NULL, NULL);
1448 cleanup_ringbuffer:
1449         mutex_lock(&dev->struct_mutex);
1450         i915_gem_cleanup_ringbuffer(dev);
1451         mutex_unlock(&dev->struct_mutex);
1452 out:
1453         return ret;
1454 }
1455
1456 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1457 {
1458         struct drm_i915_master_private *master_priv;
1459
1460         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1461         if (!master_priv)
1462                 return -ENOMEM;
1463
1464         master->driver_priv = master_priv;
1465         return 0;
1466 }
1467
1468 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1469 {
1470         struct drm_i915_master_private *master_priv = master->driver_priv;
1471
1472         if (!master_priv)
1473                 return;
1474
1475         kfree(master_priv);
1476
1477         master->driver_priv = NULL;
1478 }
1479
1480 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1481 {
1482         drm_i915_private_t *dev_priv = dev->dev_private;
1483         u32 tmp;
1484
1485         tmp = I915_READ(CLKCFG);
1486
1487         switch (tmp & CLKCFG_FSB_MASK) {
1488         case CLKCFG_FSB_533:
1489                 dev_priv->fsb_freq = 533; /* 133*4 */
1490                 break;
1491         case CLKCFG_FSB_800:
1492                 dev_priv->fsb_freq = 800; /* 200*4 */
1493                 break;
1494         case CLKCFG_FSB_667:
1495                 dev_priv->fsb_freq =  667; /* 167*4 */
1496                 break;
1497         case CLKCFG_FSB_400:
1498                 dev_priv->fsb_freq = 400; /* 100*4 */
1499                 break;
1500         }
1501
1502         switch (tmp & CLKCFG_MEM_MASK) {
1503         case CLKCFG_MEM_533:
1504                 dev_priv->mem_freq = 533;
1505                 break;
1506         case CLKCFG_MEM_667:
1507                 dev_priv->mem_freq = 667;
1508                 break;
1509         case CLKCFG_MEM_800:
1510                 dev_priv->mem_freq = 800;
1511                 break;
1512         }
1513
1514         /* detect pineview DDR3 setting */
1515         tmp = I915_READ(CSHRDDR3CTL);
1516         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1517 }
1518
1519 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1520 {
1521         drm_i915_private_t *dev_priv = dev->dev_private;
1522         u16 ddrpll, csipll;
1523
1524         ddrpll = I915_READ16(DDRMPLL1);
1525         csipll = I915_READ16(CSIPLL0);
1526
1527         switch (ddrpll & 0xff) {
1528         case 0xc:
1529                 dev_priv->mem_freq = 800;
1530                 break;
1531         case 0x10:
1532                 dev_priv->mem_freq = 1066;
1533                 break;
1534         case 0x14:
1535                 dev_priv->mem_freq = 1333;
1536                 break;
1537         case 0x18:
1538                 dev_priv->mem_freq = 1600;
1539                 break;
1540         default:
1541                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1542                                  ddrpll & 0xff);
1543                 dev_priv->mem_freq = 0;
1544                 break;
1545         }
1546
1547         dev_priv->r_t = dev_priv->mem_freq;
1548
1549         switch (csipll & 0x3ff) {
1550         case 0x00c:
1551                 dev_priv->fsb_freq = 3200;
1552                 break;
1553         case 0x00e:
1554                 dev_priv->fsb_freq = 3733;
1555                 break;
1556         case 0x010:
1557                 dev_priv->fsb_freq = 4266;
1558                 break;
1559         case 0x012:
1560                 dev_priv->fsb_freq = 4800;
1561                 break;
1562         case 0x014:
1563                 dev_priv->fsb_freq = 5333;
1564                 break;
1565         case 0x016:
1566                 dev_priv->fsb_freq = 5866;
1567                 break;
1568         case 0x018:
1569                 dev_priv->fsb_freq = 6400;
1570                 break;
1571         default:
1572                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1573                                  csipll & 0x3ff);
1574                 dev_priv->fsb_freq = 0;
1575                 break;
1576         }
1577
1578         if (dev_priv->fsb_freq == 3200) {
1579                 dev_priv->c_m = 0;
1580         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1581                 dev_priv->c_m = 1;
1582         } else {
1583                 dev_priv->c_m = 2;
1584         }
1585 }
1586
1587 struct v_table {
1588         u8 vid;
1589         unsigned long vd; /* in .1 mil */
1590         unsigned long vm; /* in .1 mil */
1591         u8 pvid;
1592 };
1593
1594 static struct v_table v_table[] = {
1595         { 0, 16125, 15000, 0x7f, },
1596         { 1, 16000, 14875, 0x7e, },
1597         { 2, 15875, 14750, 0x7d, },
1598         { 3, 15750, 14625, 0x7c, },
1599         { 4, 15625, 14500, 0x7b, },
1600         { 5, 15500, 14375, 0x7a, },
1601         { 6, 15375, 14250, 0x79, },
1602         { 7, 15250, 14125, 0x78, },
1603         { 8, 15125, 14000, 0x77, },
1604         { 9, 15000, 13875, 0x76, },
1605         { 10, 14875, 13750, 0x75, },
1606         { 11, 14750, 13625, 0x74, },
1607         { 12, 14625, 13500, 0x73, },
1608         { 13, 14500, 13375, 0x72, },
1609         { 14, 14375, 13250, 0x71, },
1610         { 15, 14250, 13125, 0x70, },
1611         { 16, 14125, 13000, 0x6f, },
1612         { 17, 14000, 12875, 0x6e, },
1613         { 18, 13875, 12750, 0x6d, },
1614         { 19, 13750, 12625, 0x6c, },
1615         { 20, 13625, 12500, 0x6b, },
1616         { 21, 13500, 12375, 0x6a, },
1617         { 22, 13375, 12250, 0x69, },
1618         { 23, 13250, 12125, 0x68, },
1619         { 24, 13125, 12000, 0x67, },
1620         { 25, 13000, 11875, 0x66, },
1621         { 26, 12875, 11750, 0x65, },
1622         { 27, 12750, 11625, 0x64, },
1623         { 28, 12625, 11500, 0x63, },
1624         { 29, 12500, 11375, 0x62, },
1625         { 30, 12375, 11250, 0x61, },
1626         { 31, 12250, 11125, 0x60, },
1627         { 32, 12125, 11000, 0x5f, },
1628         { 33, 12000, 10875, 0x5e, },
1629         { 34, 11875, 10750, 0x5d, },
1630         { 35, 11750, 10625, 0x5c, },
1631         { 36, 11625, 10500, 0x5b, },
1632         { 37, 11500, 10375, 0x5a, },
1633         { 38, 11375, 10250, 0x59, },
1634         { 39, 11250, 10125, 0x58, },
1635         { 40, 11125, 10000, 0x57, },
1636         { 41, 11000, 9875, 0x56, },
1637         { 42, 10875, 9750, 0x55, },
1638         { 43, 10750, 9625, 0x54, },
1639         { 44, 10625, 9500, 0x53, },
1640         { 45, 10500, 9375, 0x52, },
1641         { 46, 10375, 9250, 0x51, },
1642         { 47, 10250, 9125, 0x50, },
1643         { 48, 10125, 9000, 0x4f, },
1644         { 49, 10000, 8875, 0x4e, },
1645         { 50, 9875, 8750, 0x4d, },
1646         { 51, 9750, 8625, 0x4c, },
1647         { 52, 9625, 8500, 0x4b, },
1648         { 53, 9500, 8375, 0x4a, },
1649         { 54, 9375, 8250, 0x49, },
1650         { 55, 9250, 8125, 0x48, },
1651         { 56, 9125, 8000, 0x47, },
1652         { 57, 9000, 7875, 0x46, },
1653         { 58, 8875, 7750, 0x45, },
1654         { 59, 8750, 7625, 0x44, },
1655         { 60, 8625, 7500, 0x43, },
1656         { 61, 8500, 7375, 0x42, },
1657         { 62, 8375, 7250, 0x41, },
1658         { 63, 8250, 7125, 0x40, },
1659         { 64, 8125, 7000, 0x3f, },
1660         { 65, 8000, 6875, 0x3e, },
1661         { 66, 7875, 6750, 0x3d, },
1662         { 67, 7750, 6625, 0x3c, },
1663         { 68, 7625, 6500, 0x3b, },
1664         { 69, 7500, 6375, 0x3a, },
1665         { 70, 7375, 6250, 0x39, },
1666         { 71, 7250, 6125, 0x38, },
1667         { 72, 7125, 6000, 0x37, },
1668         { 73, 7000, 5875, 0x36, },
1669         { 74, 6875, 5750, 0x35, },
1670         { 75, 6750, 5625, 0x34, },
1671         { 76, 6625, 5500, 0x33, },
1672         { 77, 6500, 5375, 0x32, },
1673         { 78, 6375, 5250, 0x31, },
1674         { 79, 6250, 5125, 0x30, },
1675         { 80, 6125, 5000, 0x2f, },
1676         { 81, 6000, 4875, 0x2e, },
1677         { 82, 5875, 4750, 0x2d, },
1678         { 83, 5750, 4625, 0x2c, },
1679         { 84, 5625, 4500, 0x2b, },
1680         { 85, 5500, 4375, 0x2a, },
1681         { 86, 5375, 4250, 0x29, },
1682         { 87, 5250, 4125, 0x28, },
1683         { 88, 5125, 4000, 0x27, },
1684         { 89, 5000, 3875, 0x26, },
1685         { 90, 4875, 3750, 0x25, },
1686         { 91, 4750, 3625, 0x24, },
1687         { 92, 4625, 3500, 0x23, },
1688         { 93, 4500, 3375, 0x22, },
1689         { 94, 4375, 3250, 0x21, },
1690         { 95, 4250, 3125, 0x20, },
1691         { 96, 4125, 3000, 0x1f, },
1692         { 97, 4125, 3000, 0x1e, },
1693         { 98, 4125, 3000, 0x1d, },
1694         { 99, 4125, 3000, 0x1c, },
1695         { 100, 4125, 3000, 0x1b, },
1696         { 101, 4125, 3000, 0x1a, },
1697         { 102, 4125, 3000, 0x19, },
1698         { 103, 4125, 3000, 0x18, },
1699         { 104, 4125, 3000, 0x17, },
1700         { 105, 4125, 3000, 0x16, },
1701         { 106, 4125, 3000, 0x15, },
1702         { 107, 4125, 3000, 0x14, },
1703         { 108, 4125, 3000, 0x13, },
1704         { 109, 4125, 3000, 0x12, },
1705         { 110, 4125, 3000, 0x11, },
1706         { 111, 4125, 3000, 0x10, },
1707         { 112, 4125, 3000, 0x0f, },
1708         { 113, 4125, 3000, 0x0e, },
1709         { 114, 4125, 3000, 0x0d, },
1710         { 115, 4125, 3000, 0x0c, },
1711         { 116, 4125, 3000, 0x0b, },
1712         { 117, 4125, 3000, 0x0a, },
1713         { 118, 4125, 3000, 0x09, },
1714         { 119, 4125, 3000, 0x08, },
1715         { 120, 1125, 0, 0x07, },
1716         { 121, 1000, 0, 0x06, },
1717         { 122, 875, 0, 0x05, },
1718         { 123, 750, 0, 0x04, },
1719         { 124, 625, 0, 0x03, },
1720         { 125, 500, 0, 0x02, },
1721         { 126, 375, 0, 0x01, },
1722         { 127, 0, 0, 0x00, },
1723 };
1724
1725 struct cparams {
1726         int i;
1727         int t;
1728         int m;
1729         int c;
1730 };
1731
1732 static struct cparams cparams[] = {
1733         { 1, 1333, 301, 28664 },
1734         { 1, 1066, 294, 24460 },
1735         { 1, 800, 294, 25192 },
1736         { 0, 1333, 276, 27605 },
1737         { 0, 1066, 276, 27605 },
1738         { 0, 800, 231, 23784 },
1739 };
1740
1741 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1742 {
1743         u64 total_count, diff, ret;
1744         u32 count1, count2, count3, m = 0, c = 0;
1745         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1746         int i;
1747
1748         diff1 = now - dev_priv->last_time1;
1749
1750         count1 = I915_READ(DMIEC);
1751         count2 = I915_READ(DDREC);
1752         count3 = I915_READ(CSIEC);
1753
1754         total_count = count1 + count2 + count3;
1755
1756         /* FIXME: handle per-counter overflow */
1757         if (total_count < dev_priv->last_count1) {
1758                 diff = ~0UL - dev_priv->last_count1;
1759                 diff += total_count;
1760         } else {
1761                 diff = total_count - dev_priv->last_count1;
1762         }
1763
1764         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1765                 if (cparams[i].i == dev_priv->c_m &&
1766                     cparams[i].t == dev_priv->r_t) {
1767                         m = cparams[i].m;
1768                         c = cparams[i].c;
1769                         break;
1770                 }
1771         }
1772
1773         div_u64(diff, diff1);
1774         ret = ((m * diff) + c);
1775         div_u64(ret, 10);
1776
1777         dev_priv->last_count1 = total_count;
1778         dev_priv->last_time1 = now;
1779
1780         return ret;
1781 }
1782
1783 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1784 {
1785         unsigned long m, x, b;
1786         u32 tsfs;
1787
1788         tsfs = I915_READ(TSFS);
1789
1790         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1791         x = I915_READ8(TR1);
1792
1793         b = tsfs & TSFS_INTR_MASK;
1794
1795         return ((m * x) / 127) - b;
1796 }
1797
1798 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1799 {
1800         unsigned long val = 0;
1801         int i;
1802
1803         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1804                 if (v_table[i].pvid == pxvid) {
1805                         if (IS_MOBILE(dev_priv->dev))
1806                                 val = v_table[i].vm;
1807                         else
1808                                 val = v_table[i].vd;
1809                 }
1810         }
1811
1812         return val;
1813 }
1814
1815 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1816 {
1817         struct timespec now, diff1;
1818         u64 diff;
1819         unsigned long diffms;
1820         u32 count;
1821
1822         getrawmonotonic(&now);
1823         diff1 = timespec_sub(now, dev_priv->last_time2);
1824
1825         /* Don't divide by 0 */
1826         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1827         if (!diffms)
1828                 return;
1829
1830         count = I915_READ(GFXEC);
1831
1832         if (count < dev_priv->last_count2) {
1833                 diff = ~0UL - dev_priv->last_count2;
1834                 diff += count;
1835         } else {
1836                 diff = count - dev_priv->last_count2;
1837         }
1838
1839         dev_priv->last_count2 = count;
1840         dev_priv->last_time2 = now;
1841
1842         /* More magic constants... */
1843         diff = diff * 1181;
1844         div_u64(diff, diffms * 10);
1845         dev_priv->gfx_power = diff;
1846 }
1847
1848 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1849 {
1850         unsigned long t, corr, state1, corr2, state2;
1851         u32 pxvid, ext_v;
1852
1853         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1854         pxvid = (pxvid >> 24) & 0x7f;
1855         ext_v = pvid_to_extvid(dev_priv, pxvid);
1856
1857         state1 = ext_v;
1858
1859         t = i915_mch_val(dev_priv);
1860
1861         /* Revel in the empirically derived constants */
1862
1863         /* Correction factor in 1/100000 units */
1864         if (t > 80)
1865                 corr = ((t * 2349) + 135940);
1866         else if (t >= 50)
1867                 corr = ((t * 964) + 29317);
1868         else /* < 50 */
1869                 corr = ((t * 301) + 1004);
1870
1871         corr = corr * ((150142 * state1) / 10000 - 78642);
1872         corr /= 100000;
1873         corr2 = (corr * dev_priv->corr);
1874
1875         state2 = (corr2 * state1) / 10000;
1876         state2 /= 100; /* convert to mW */
1877
1878         i915_update_gfx_val(dev_priv);
1879
1880         return dev_priv->gfx_power + state2;
1881 }
1882
1883 /* Global for IPS driver to get at the current i915 device */
1884 static struct drm_i915_private *i915_mch_dev;
1885 /*
1886  * Lock protecting IPS related data structures
1887  *   - i915_mch_dev
1888  *   - dev_priv->max_delay
1889  *   - dev_priv->min_delay
1890  *   - dev_priv->fmax
1891  *   - dev_priv->gpu_busy
1892  */
1893 DEFINE_SPINLOCK(mchdev_lock);
1894
1895 /**
1896  * i915_read_mch_val - return value for IPS use
1897  *
1898  * Calculate and return a value for the IPS driver to use when deciding whether
1899  * we have thermal and power headroom to increase CPU or GPU power budget.
1900  */
1901 unsigned long i915_read_mch_val(void)
1902 {
1903         struct drm_i915_private *dev_priv;
1904         unsigned long chipset_val, graphics_val, ret = 0;
1905
1906         spin_lock(&mchdev_lock);
1907         if (!i915_mch_dev)
1908                 goto out_unlock;
1909         dev_priv = i915_mch_dev;
1910
1911         chipset_val = i915_chipset_val(dev_priv);
1912         graphics_val = i915_gfx_val(dev_priv);
1913
1914         ret = chipset_val + graphics_val;
1915
1916 out_unlock:
1917         spin_unlock(&mchdev_lock);
1918
1919         return ret;
1920 }
1921 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1922
1923 /**
1924  * i915_gpu_raise - raise GPU frequency limit
1925  *
1926  * Raise the limit; IPS indicates we have thermal headroom.
1927  */
1928 bool i915_gpu_raise(void)
1929 {
1930         struct drm_i915_private *dev_priv;
1931         bool ret = true;
1932
1933         spin_lock(&mchdev_lock);
1934         if (!i915_mch_dev) {
1935                 ret = false;
1936                 goto out_unlock;
1937         }
1938         dev_priv = i915_mch_dev;
1939
1940         if (dev_priv->max_delay > dev_priv->fmax)
1941                 dev_priv->max_delay--;
1942
1943 out_unlock:
1944         spin_unlock(&mchdev_lock);
1945
1946         return ret;
1947 }
1948 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1949
1950 /**
1951  * i915_gpu_lower - lower GPU frequency limit
1952  *
1953  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1954  * frequency maximum.
1955  */
1956 bool i915_gpu_lower(void)
1957 {
1958         struct drm_i915_private *dev_priv;
1959         bool ret = true;
1960
1961         spin_lock(&mchdev_lock);
1962         if (!i915_mch_dev) {
1963                 ret = false;
1964                 goto out_unlock;
1965         }
1966         dev_priv = i915_mch_dev;
1967
1968         if (dev_priv->max_delay < dev_priv->min_delay)
1969                 dev_priv->max_delay++;
1970
1971 out_unlock:
1972         spin_unlock(&mchdev_lock);
1973
1974         return ret;
1975 }
1976 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1977
1978 /**
1979  * i915_gpu_busy - indicate GPU business to IPS
1980  *
1981  * Tell the IPS driver whether or not the GPU is busy.
1982  */
1983 bool i915_gpu_busy(void)
1984 {
1985         struct drm_i915_private *dev_priv;
1986         bool ret = false;
1987
1988         spin_lock(&mchdev_lock);
1989         if (!i915_mch_dev)
1990                 goto out_unlock;
1991         dev_priv = i915_mch_dev;
1992
1993         ret = dev_priv->busy;
1994
1995 out_unlock:
1996         spin_unlock(&mchdev_lock);
1997
1998         return ret;
1999 }
2000 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2001
2002 /**
2003  * i915_gpu_turbo_disable - disable graphics turbo
2004  *
2005  * Disable graphics turbo by resetting the max frequency and setting the
2006  * current frequency to the default.
2007  */
2008 bool i915_gpu_turbo_disable(void)
2009 {
2010         struct drm_i915_private *dev_priv;
2011         bool ret = true;
2012
2013         spin_lock(&mchdev_lock);
2014         if (!i915_mch_dev) {
2015                 ret = false;
2016                 goto out_unlock;
2017         }
2018         dev_priv = i915_mch_dev;
2019
2020         dev_priv->max_delay = dev_priv->fstart;
2021
2022         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2023                 ret = false;
2024
2025 out_unlock:
2026         spin_unlock(&mchdev_lock);
2027
2028         return ret;
2029 }
2030 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2031
2032 /**
2033  * i915_driver_load - setup chip and create an initial config
2034  * @dev: DRM device
2035  * @flags: startup flags
2036  *
2037  * The driver load routine has to do several things:
2038  *   - drive output discovery via intel_modeset_init()
2039  *   - initialize the memory manager
2040  *   - allocate initial config memory
2041  *   - setup the DRM framebuffer with the allocated memory
2042  */
2043 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2044 {
2045         struct drm_i915_private *dev_priv;
2046         resource_size_t base, size;
2047         int ret = 0, mmio_bar;
2048         uint32_t agp_size, prealloc_size, prealloc_start;
2049         /* i915 has 4 more counters */
2050         dev->counters += 4;
2051         dev->types[6] = _DRM_STAT_IRQ;
2052         dev->types[7] = _DRM_STAT_PRIMARY;
2053         dev->types[8] = _DRM_STAT_SECONDARY;
2054         dev->types[9] = _DRM_STAT_DMA;
2055
2056         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2057         if (dev_priv == NULL)
2058                 return -ENOMEM;
2059
2060         dev->dev_private = (void *)dev_priv;
2061         dev_priv->dev = dev;
2062         dev_priv->info = (struct intel_device_info *) flags;
2063
2064         /* Add register map (needed for suspend/resume) */
2065         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2066         base = drm_get_resource_start(dev, mmio_bar);
2067         size = drm_get_resource_len(dev, mmio_bar);
2068
2069         if (i915_get_bridge_dev(dev)) {
2070                 ret = -EIO;
2071                 goto free_priv;
2072         }
2073
2074         dev_priv->regs = ioremap(base, size);
2075         if (!dev_priv->regs) {
2076                 DRM_ERROR("failed to map registers\n");
2077                 ret = -EIO;
2078                 goto put_bridge;
2079         }
2080
2081         dev_priv->mm.gtt_mapping =
2082                 io_mapping_create_wc(dev->agp->base,
2083                                      dev->agp->agp_info.aper_size * 1024*1024);
2084         if (dev_priv->mm.gtt_mapping == NULL) {
2085                 ret = -EIO;
2086                 goto out_rmmap;
2087         }
2088
2089         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2090          * one would think, because the kernel disables PAT on first
2091          * generation Core chips because WC PAT gets overridden by a UC
2092          * MTRR if present.  Even if a UC MTRR isn't present.
2093          */
2094         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2095                                          dev->agp->agp_info.aper_size *
2096                                          1024 * 1024,
2097                                          MTRR_TYPE_WRCOMB, 1);
2098         if (dev_priv->mm.gtt_mtrr < 0) {
2099                 DRM_INFO("MTRR allocation failed.  Graphics "
2100                          "performance may suffer.\n");
2101         }
2102
2103         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2104         if (ret)
2105                 goto out_iomapfree;
2106
2107         dev_priv->wq = create_singlethread_workqueue("i915");
2108         if (dev_priv->wq == NULL) {
2109                 DRM_ERROR("Failed to create our workqueue.\n");
2110                 ret = -ENOMEM;
2111                 goto out_iomapfree;
2112         }
2113
2114         /* enable GEM by default */
2115         dev_priv->has_gem = 1;
2116
2117         if (prealloc_size > agp_size * 3 / 4) {
2118                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2119                           "memory stolen.\n",
2120                           prealloc_size / 1024, agp_size / 1024);
2121                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2122                           "updating the BIOS to fix).\n");
2123                 dev_priv->has_gem = 0;
2124         }
2125
2126         if (dev_priv->has_gem == 0 &&
2127             drm_core_check_feature(dev, DRIVER_MODESET)) {
2128                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2129                 ret = -ENODEV;
2130                 goto out_iomapfree;
2131         }
2132
2133         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2134         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2135         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2136                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2137                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2138         }
2139
2140         /* Try to make sure MCHBAR is enabled before poking at it */
2141         intel_setup_mchbar(dev);
2142
2143         i915_gem_load(dev);
2144
2145         /* Init HWS */
2146         if (!I915_NEED_GFX_HWS(dev)) {
2147                 ret = i915_init_phys_hws(dev);
2148                 if (ret != 0)
2149                         goto out_workqueue_free;
2150         }
2151
2152         if (IS_PINEVIEW(dev))
2153                 i915_pineview_get_mem_freq(dev);
2154         else if (IS_IRONLAKE(dev))
2155                 i915_ironlake_get_mem_freq(dev);
2156
2157         /* On the 945G/GM, the chipset reports the MSI capability on the
2158          * integrated graphics even though the support isn't actually there
2159          * according to the published specs.  It doesn't appear to function
2160          * correctly in testing on 945G.
2161          * This may be a side effect of MSI having been made available for PEG
2162          * and the registers being closely associated.
2163          *
2164          * According to chipset errata, on the 965GM, MSI interrupts may
2165          * be lost or delayed, but we use them anyways to avoid
2166          * stuck interrupts on some machines.
2167          */
2168         if (!IS_I945G(dev) && !IS_I945GM(dev))
2169                 pci_enable_msi(dev->pdev);
2170
2171         spin_lock_init(&dev_priv->user_irq_lock);
2172         spin_lock_init(&dev_priv->error_lock);
2173         dev_priv->trace_irq_seqno = 0;
2174
2175         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2176
2177         if (ret) {
2178                 (void) i915_driver_unload(dev);
2179                 return ret;
2180         }
2181
2182         /* Start out suspended */
2183         dev_priv->mm.suspended = 1;
2184
2185         intel_detect_pch(dev);
2186
2187         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2188                 ret = i915_load_modeset_init(dev, prealloc_start,
2189                                              prealloc_size, agp_size);
2190                 if (ret < 0) {
2191                         DRM_ERROR("failed to init modeset\n");
2192                         goto out_workqueue_free;
2193                 }
2194         }
2195
2196         /* Must be done after probing outputs */
2197         intel_opregion_init(dev, 0);
2198
2199         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2200                     (unsigned long) dev);
2201
2202         spin_lock(&mchdev_lock);
2203         i915_mch_dev = dev_priv;
2204         dev_priv->mchdev_lock = &mchdev_lock;
2205         spin_unlock(&mchdev_lock);
2206
2207         return 0;
2208
2209 out_workqueue_free:
2210         destroy_workqueue(dev_priv->wq);
2211 out_iomapfree:
2212         io_mapping_free(dev_priv->mm.gtt_mapping);
2213 out_rmmap:
2214         iounmap(dev_priv->regs);
2215 put_bridge:
2216         pci_dev_put(dev_priv->bridge_dev);
2217 free_priv:
2218         kfree(dev_priv);
2219         return ret;
2220 }
2221
2222 int i915_driver_unload(struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225
2226         i915_destroy_error_state(dev);
2227
2228         spin_lock(&mchdev_lock);
2229         i915_mch_dev = NULL;
2230         spin_unlock(&mchdev_lock);
2231
2232         destroy_workqueue(dev_priv->wq);
2233         del_timer_sync(&dev_priv->hangcheck_timer);
2234
2235         io_mapping_free(dev_priv->mm.gtt_mapping);
2236         if (dev_priv->mm.gtt_mtrr >= 0) {
2237                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2238                          dev->agp->agp_info.aper_size * 1024 * 1024);
2239                 dev_priv->mm.gtt_mtrr = -1;
2240         }
2241
2242         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2243                 intel_modeset_cleanup(dev);
2244
2245                 /*
2246                  * free the memory space allocated for the child device
2247                  * config parsed from VBT
2248                  */
2249                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2250                         kfree(dev_priv->child_dev);
2251                         dev_priv->child_dev = NULL;
2252                         dev_priv->child_dev_num = 0;
2253                 }
2254                 drm_irq_uninstall(dev);
2255                 vga_switcheroo_unregister_client(dev->pdev);
2256                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2257         }
2258
2259         if (dev->pdev->msi_enabled)
2260                 pci_disable_msi(dev->pdev);
2261
2262         if (dev_priv->regs != NULL)
2263                 iounmap(dev_priv->regs);
2264
2265         intel_opregion_free(dev, 0);
2266
2267         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2268                 i915_gem_free_all_phys_object(dev);
2269
2270                 mutex_lock(&dev->struct_mutex);
2271                 i915_gem_cleanup_ringbuffer(dev);
2272                 mutex_unlock(&dev->struct_mutex);
2273                 if (I915_HAS_FBC(dev) && i915_powersave)
2274                         i915_cleanup_compression(dev);
2275                 drm_mm_takedown(&dev_priv->vram);
2276                 i915_gem_lastclose(dev);
2277
2278                 intel_cleanup_overlay(dev);
2279         }
2280
2281         intel_teardown_mchbar(dev);
2282
2283         pci_dev_put(dev_priv->bridge_dev);
2284         kfree(dev->dev_private);
2285
2286         return 0;
2287 }
2288
2289 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2290 {
2291         struct drm_i915_file_private *i915_file_priv;
2292
2293         DRM_DEBUG_DRIVER("\n");
2294         i915_file_priv = (struct drm_i915_file_private *)
2295             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2296
2297         if (!i915_file_priv)
2298                 return -ENOMEM;
2299
2300         file_priv->driver_priv = i915_file_priv;
2301
2302         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2303
2304         return 0;
2305 }
2306
2307 /**
2308  * i915_driver_lastclose - clean up after all DRM clients have exited
2309  * @dev: DRM device
2310  *
2311  * Take care of cleaning up after all DRM clients have exited.  In the
2312  * mode setting case, we want to restore the kernel's initial mode (just
2313  * in case the last client left us in a bad state).
2314  *
2315  * Additionally, in the non-mode setting case, we'll tear down the AGP
2316  * and DMA structures, since the kernel won't be using them, and clea
2317  * up any GEM state.
2318  */
2319 void i915_driver_lastclose(struct drm_device * dev)
2320 {
2321         drm_i915_private_t *dev_priv = dev->dev_private;
2322
2323         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2324                 drm_fb_helper_restore();
2325                 vga_switcheroo_process_delayed_switch();
2326                 return;
2327         }
2328
2329         i915_gem_lastclose(dev);
2330
2331         if (dev_priv->agp_heap)
2332                 i915_mem_takedown(&(dev_priv->agp_heap));
2333
2334         i915_dma_cleanup(dev);
2335 }
2336
2337 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2338 {
2339         drm_i915_private_t *dev_priv = dev->dev_private;
2340         i915_gem_release(dev, file_priv);
2341         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2342                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2343 }
2344
2345 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2346 {
2347         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2348
2349         kfree(i915_file_priv);
2350 }
2351
2352 struct drm_ioctl_desc i915_ioctls[] = {
2353         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2354         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2355         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2356         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2357         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2358         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2359         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2360         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2361         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2362         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2363         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2364         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2365         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2366         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2367         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
2368         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2369         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2370         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2371         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2372         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2373         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2374         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2375         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2376         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2377         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2378         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2379         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2380         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2381         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2382         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2383         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2384         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2385         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2386         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2387         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2388         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2389         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2390         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2391         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2392         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2393 };
2394
2395 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2396
2397 /**
2398  * Determine if the device really is AGP or not.
2399  *
2400  * All Intel graphics chipsets are treated as AGP, even if they are really
2401  * PCI-e.
2402  *
2403  * \param dev   The device to be tested.
2404  *
2405  * \returns
2406  * A value of 1 is always retured to indictate every i9x5 is AGP.
2407  */
2408 int i915_driver_device_is_agp(struct drm_device * dev)
2409 {
2410         return 1;
2411 }