Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38 #include <linux/acpi.h>
39 #include <linux/pnp.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/slab.h>
42
43 /**
44  * Sets up the hardware status page for devices that need a physical address
45  * in the register.
46  */
47 static int i915_init_phys_hws(struct drm_device *dev)
48 {
49         drm_i915_private_t *dev_priv = dev->dev_private;
50         /* Program Hardware Status Page */
51         dev_priv->status_page_dmah =
52                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
53
54         if (!dev_priv->status_page_dmah) {
55                 DRM_ERROR("Can not allocate hardware status page\n");
56                 return -ENOMEM;
57         }
58         dev_priv->render_ring.status_page.page_addr
59                 = dev_priv->status_page_dmah->vaddr;
60         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
61
62         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
63
64         if (IS_I965G(dev))
65                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
66                                              0xf0;
67
68         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
69         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
70         return 0;
71 }
72
73 /**
74  * Frees the hardware status page, whether it's a physical address or a virtual
75  * address set up by the X Server.
76  */
77 static void i915_free_hws(struct drm_device *dev)
78 {
79         drm_i915_private_t *dev_priv = dev->dev_private;
80         if (dev_priv->status_page_dmah) {
81                 drm_pci_free(dev, dev_priv->status_page_dmah);
82                 dev_priv->status_page_dmah = NULL;
83         }
84
85         if (dev_priv->render_ring.status_page.gfx_addr) {
86                 dev_priv->render_ring.status_page.gfx_addr = 0;
87                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
88         }
89
90         /* Need to rewrite hardware status page */
91         I915_WRITE(HWS_PGA, 0x1ffff000);
92 }
93
94 void i915_kernel_lost_context(struct drm_device * dev)
95 {
96         drm_i915_private_t *dev_priv = dev->dev_private;
97         struct drm_i915_master_private *master_priv;
98         struct intel_ring_buffer *ring = &dev_priv->render_ring;
99
100         /*
101          * We should never lose context on the ring with modesetting
102          * as we don't expose it to userspace
103          */
104         if (drm_core_check_feature(dev, DRIVER_MODESET))
105                 return;
106
107         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
108         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
109         ring->space = ring->head - (ring->tail + 8);
110         if (ring->space < 0)
111                 ring->space += ring->size;
112
113         if (!dev->primary->master)
114                 return;
115
116         master_priv = dev->primary->master->driver_priv;
117         if (ring->head == ring->tail && master_priv->sarea_priv)
118                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
119 }
120
121 static int i915_dma_cleanup(struct drm_device * dev)
122 {
123         drm_i915_private_t *dev_priv = dev->dev_private;
124         /* Make sure interrupts are disabled here because the uninstall ioctl
125          * may not have been called from userspace and after dev_private
126          * is freed, it's too late.
127          */
128         if (dev->irq_enabled)
129                 drm_irq_uninstall(dev);
130
131         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
132         if (HAS_BSD(dev))
133                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
134
135         /* Clear the HWS virtual address at teardown */
136         if (I915_NEED_GFX_HWS(dev))
137                 i915_free_hws(dev);
138
139         return 0;
140 }
141
142 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
143 {
144         drm_i915_private_t *dev_priv = dev->dev_private;
145         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
146
147         master_priv->sarea = drm_getsarea(dev);
148         if (master_priv->sarea) {
149                 master_priv->sarea_priv = (drm_i915_sarea_t *)
150                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
151         } else {
152                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
153         }
154
155         if (init->ring_size != 0) {
156                 if (dev_priv->render_ring.gem_object != NULL) {
157                         i915_dma_cleanup(dev);
158                         DRM_ERROR("Client tried to initialize ringbuffer in "
159                                   "GEM mode\n");
160                         return -EINVAL;
161                 }
162
163                 dev_priv->render_ring.size = init->ring_size;
164
165                 dev_priv->render_ring.map.offset = init->ring_start;
166                 dev_priv->render_ring.map.size = init->ring_size;
167                 dev_priv->render_ring.map.type = 0;
168                 dev_priv->render_ring.map.flags = 0;
169                 dev_priv->render_ring.map.mtrr = 0;
170
171                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
172
173                 if (dev_priv->render_ring.map.handle == NULL) {
174                         i915_dma_cleanup(dev);
175                         DRM_ERROR("can not ioremap virtual address for"
176                                   " ring buffer\n");
177                         return -ENOMEM;
178                 }
179         }
180
181         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
182
183         dev_priv->cpp = init->cpp;
184         dev_priv->back_offset = init->back_offset;
185         dev_priv->front_offset = init->front_offset;
186         dev_priv->current_page = 0;
187         if (master_priv->sarea_priv)
188                 master_priv->sarea_priv->pf_current_page = 0;
189
190         /* Allow hardware batchbuffers unless told otherwise.
191          */
192         dev_priv->allow_batchbuffer = 1;
193
194         return 0;
195 }
196
197 static int i915_dma_resume(struct drm_device * dev)
198 {
199         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200
201         struct intel_ring_buffer *ring;
202         DRM_DEBUG_DRIVER("%s\n", __func__);
203
204         ring = &dev_priv->render_ring;
205
206         if (ring->map.handle == NULL) {
207                 DRM_ERROR("can not ioremap virtual address for"
208                           " ring buffer\n");
209                 return -ENOMEM;
210         }
211
212         /* Program Hardware Status Page */
213         if (!ring->status_page.page_addr) {
214                 DRM_ERROR("Can not find hardware status page\n");
215                 return -EINVAL;
216         }
217         DRM_DEBUG_DRIVER("hw status page @ %p\n",
218                                 ring->status_page.page_addr);
219         if (ring->status_page.gfx_addr != 0)
220                 ring->setup_status_page(dev, ring);
221         else
222                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
223
224         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
225
226         return 0;
227 }
228
229 static int i915_dma_init(struct drm_device *dev, void *data,
230                          struct drm_file *file_priv)
231 {
232         drm_i915_init_t *init = data;
233         int retcode = 0;
234
235         switch (init->func) {
236         case I915_INIT_DMA:
237                 retcode = i915_initialize(dev, init);
238                 break;
239         case I915_CLEANUP_DMA:
240                 retcode = i915_dma_cleanup(dev);
241                 break;
242         case I915_RESUME_DMA:
243                 retcode = i915_dma_resume(dev);
244                 break;
245         default:
246                 retcode = -EINVAL;
247                 break;
248         }
249
250         return retcode;
251 }
252
253 /* Implement basically the same security restrictions as hardware does
254  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
255  *
256  * Most of the calculations below involve calculating the size of a
257  * particular instruction.  It's important to get the size right as
258  * that tells us where the next instruction to check is.  Any illegal
259  * instruction detected will be given a size of zero, which is a
260  * signal to abort the rest of the buffer.
261  */
262 static int do_validate_cmd(int cmd)
263 {
264         switch (((cmd >> 29) & 0x7)) {
265         case 0x0:
266                 switch ((cmd >> 23) & 0x3f) {
267                 case 0x0:
268                         return 1;       /* MI_NOOP */
269                 case 0x4:
270                         return 1;       /* MI_FLUSH */
271                 default:
272                         return 0;       /* disallow everything else */
273                 }
274                 break;
275         case 0x1:
276                 return 0;       /* reserved */
277         case 0x2:
278                 return (cmd & 0xff) + 2;        /* 2d commands */
279         case 0x3:
280                 if (((cmd >> 24) & 0x1f) <= 0x18)
281                         return 1;
282
283                 switch ((cmd >> 24) & 0x1f) {
284                 case 0x1c:
285                         return 1;
286                 case 0x1d:
287                         switch ((cmd >> 16) & 0xff) {
288                         case 0x3:
289                                 return (cmd & 0x1f) + 2;
290                         case 0x4:
291                                 return (cmd & 0xf) + 2;
292                         default:
293                                 return (cmd & 0xffff) + 2;
294                         }
295                 case 0x1e:
296                         if (cmd & (1 << 23))
297                                 return (cmd & 0xffff) + 1;
298                         else
299                                 return 1;
300                 case 0x1f:
301                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
302                                 return (cmd & 0x1ffff) + 2;
303                         else if (cmd & (1 << 17))       /* indirect random */
304                                 if ((cmd & 0xffff) == 0)
305                                         return 0;       /* unknown length, too hard */
306                                 else
307                                         return (((cmd & 0xffff) + 1) / 2) + 1;
308                         else
309                                 return 2;       /* indirect sequential */
310                 default:
311                         return 0;
312                 }
313         default:
314                 return 0;
315         }
316
317         return 0;
318 }
319
320 static int validate_cmd(int cmd)
321 {
322         int ret = do_validate_cmd(cmd);
323
324 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
325
326         return ret;
327 }
328
329 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
330 {
331         drm_i915_private_t *dev_priv = dev->dev_private;
332         int i;
333
334         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
335                 return -EINVAL;
336
337         BEGIN_LP_RING((dwords+1)&~1);
338
339         for (i = 0; i < dwords;) {
340                 int cmd, sz;
341
342                 cmd = buffer[i];
343
344                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
345                         return -EINVAL;
346
347                 OUT_RING(cmd);
348
349                 while (++i, --sz) {
350                         OUT_RING(buffer[i]);
351                 }
352         }
353
354         if (dwords & 1)
355                 OUT_RING(0);
356
357         ADVANCE_LP_RING();
358
359         return 0;
360 }
361
362 int
363 i915_emit_box(struct drm_device *dev,
364               struct drm_clip_rect *boxes,
365               int i, int DR1, int DR4)
366 {
367         struct drm_clip_rect box = boxes[i];
368
369         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
370                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
371                           box.x1, box.y1, box.x2, box.y2);
372                 return -EINVAL;
373         }
374
375         if (IS_I965G(dev)) {
376                 BEGIN_LP_RING(4);
377                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
378                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
379                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
380                 OUT_RING(DR4);
381                 ADVANCE_LP_RING();
382         } else {
383                 BEGIN_LP_RING(6);
384                 OUT_RING(GFX_OP_DRAWRECT_INFO);
385                 OUT_RING(DR1);
386                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
387                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
388                 OUT_RING(DR4);
389                 OUT_RING(0);
390                 ADVANCE_LP_RING();
391         }
392
393         return 0;
394 }
395
396 /* XXX: Emitting the counter should really be moved to part of the IRQ
397  * emit. For now, do it in both places:
398  */
399
400 static void i915_emit_breadcrumb(struct drm_device *dev)
401 {
402         drm_i915_private_t *dev_priv = dev->dev_private;
403         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
404
405         dev_priv->counter++;
406         if (dev_priv->counter > 0x7FFFFFFFUL)
407                 dev_priv->counter = 0;
408         if (master_priv->sarea_priv)
409                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
410
411         BEGIN_LP_RING(4);
412         OUT_RING(MI_STORE_DWORD_INDEX);
413         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
414         OUT_RING(dev_priv->counter);
415         OUT_RING(0);
416         ADVANCE_LP_RING();
417 }
418
419 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
420                                    drm_i915_cmdbuffer_t *cmd,
421                                    struct drm_clip_rect *cliprects,
422                                    void *cmdbuf)
423 {
424         int nbox = cmd->num_cliprects;
425         int i = 0, count, ret;
426
427         if (cmd->sz & 0x3) {
428                 DRM_ERROR("alignment");
429                 return -EINVAL;
430         }
431
432         i915_kernel_lost_context(dev);
433
434         count = nbox ? nbox : 1;
435
436         for (i = 0; i < count; i++) {
437                 if (i < nbox) {
438                         ret = i915_emit_box(dev, cliprects, i,
439                                             cmd->DR1, cmd->DR4);
440                         if (ret)
441                                 return ret;
442                 }
443
444                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
445                 if (ret)
446                         return ret;
447         }
448
449         i915_emit_breadcrumb(dev);
450         return 0;
451 }
452
453 static int i915_dispatch_batchbuffer(struct drm_device * dev,
454                                      drm_i915_batchbuffer_t * batch,
455                                      struct drm_clip_rect *cliprects)
456 {
457         int nbox = batch->num_cliprects;
458         int i = 0, count;
459
460         if ((batch->start | batch->used) & 0x7) {
461                 DRM_ERROR("alignment");
462                 return -EINVAL;
463         }
464
465         i915_kernel_lost_context(dev);
466
467         count = nbox ? nbox : 1;
468
469         for (i = 0; i < count; i++) {
470                 if (i < nbox) {
471                         int ret = i915_emit_box(dev, cliprects, i,
472                                                 batch->DR1, batch->DR4);
473                         if (ret)
474                                 return ret;
475                 }
476
477                 if (!IS_I830(dev) && !IS_845G(dev)) {
478                         BEGIN_LP_RING(2);
479                         if (IS_I965G(dev)) {
480                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
481                                 OUT_RING(batch->start);
482                         } else {
483                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
484                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
485                         }
486                         ADVANCE_LP_RING();
487                 } else {
488                         BEGIN_LP_RING(4);
489                         OUT_RING(MI_BATCH_BUFFER);
490                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
491                         OUT_RING(batch->start + batch->used - 4);
492                         OUT_RING(0);
493                         ADVANCE_LP_RING();
494                 }
495         }
496
497         i915_emit_breadcrumb(dev);
498
499         return 0;
500 }
501
502 static int i915_dispatch_flip(struct drm_device * dev)
503 {
504         drm_i915_private_t *dev_priv = dev->dev_private;
505         struct drm_i915_master_private *master_priv =
506                 dev->primary->master->driver_priv;
507
508         if (!master_priv->sarea_priv)
509                 return -EINVAL;
510
511         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
512                           __func__,
513                          dev_priv->current_page,
514                          master_priv->sarea_priv->pf_current_page);
515
516         i915_kernel_lost_context(dev);
517
518         BEGIN_LP_RING(2);
519         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
520         OUT_RING(0);
521         ADVANCE_LP_RING();
522
523         BEGIN_LP_RING(6);
524         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
525         OUT_RING(0);
526         if (dev_priv->current_page == 0) {
527                 OUT_RING(dev_priv->back_offset);
528                 dev_priv->current_page = 1;
529         } else {
530                 OUT_RING(dev_priv->front_offset);
531                 dev_priv->current_page = 0;
532         }
533         OUT_RING(0);
534         ADVANCE_LP_RING();
535
536         BEGIN_LP_RING(2);
537         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
538         OUT_RING(0);
539         ADVANCE_LP_RING();
540
541         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
542
543         BEGIN_LP_RING(4);
544         OUT_RING(MI_STORE_DWORD_INDEX);
545         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
546         OUT_RING(dev_priv->counter);
547         OUT_RING(0);
548         ADVANCE_LP_RING();
549
550         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
551         return 0;
552 }
553
554 static int i915_quiescent(struct drm_device * dev)
555 {
556         drm_i915_private_t *dev_priv = dev->dev_private;
557
558         i915_kernel_lost_context(dev);
559         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
560                                       dev_priv->render_ring.size - 8);
561 }
562
563 static int i915_flush_ioctl(struct drm_device *dev, void *data,
564                             struct drm_file *file_priv)
565 {
566         int ret;
567
568         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
569
570         mutex_lock(&dev->struct_mutex);
571         ret = i915_quiescent(dev);
572         mutex_unlock(&dev->struct_mutex);
573
574         return ret;
575 }
576
577 static int i915_batchbuffer(struct drm_device *dev, void *data,
578                             struct drm_file *file_priv)
579 {
580         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
581         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
582         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
583             master_priv->sarea_priv;
584         drm_i915_batchbuffer_t *batch = data;
585         int ret;
586         struct drm_clip_rect *cliprects = NULL;
587
588         if (!dev_priv->allow_batchbuffer) {
589                 DRM_ERROR("Batchbuffer ioctl disabled\n");
590                 return -EINVAL;
591         }
592
593         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
594                         batch->start, batch->used, batch->num_cliprects);
595
596         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
597
598         if (batch->num_cliprects < 0)
599                 return -EINVAL;
600
601         if (batch->num_cliprects) {
602                 cliprects = kcalloc(batch->num_cliprects,
603                                     sizeof(struct drm_clip_rect),
604                                     GFP_KERNEL);
605                 if (cliprects == NULL)
606                         return -ENOMEM;
607
608                 ret = copy_from_user(cliprects, batch->cliprects,
609                                      batch->num_cliprects *
610                                      sizeof(struct drm_clip_rect));
611                 if (ret != 0)
612                         goto fail_free;
613         }
614
615         mutex_lock(&dev->struct_mutex);
616         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
617         mutex_unlock(&dev->struct_mutex);
618
619         if (sarea_priv)
620                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
621
622 fail_free:
623         kfree(cliprects);
624
625         return ret;
626 }
627
628 static int i915_cmdbuffer(struct drm_device *dev, void *data,
629                           struct drm_file *file_priv)
630 {
631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
632         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
633         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
634             master_priv->sarea_priv;
635         drm_i915_cmdbuffer_t *cmdbuf = data;
636         struct drm_clip_rect *cliprects = NULL;
637         void *batch_data;
638         int ret;
639
640         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
641                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
642
643         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
644
645         if (cmdbuf->num_cliprects < 0)
646                 return -EINVAL;
647
648         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
649         if (batch_data == NULL)
650                 return -ENOMEM;
651
652         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
653         if (ret != 0)
654                 goto fail_batch_free;
655
656         if (cmdbuf->num_cliprects) {
657                 cliprects = kcalloc(cmdbuf->num_cliprects,
658                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
659                 if (cliprects == NULL) {
660                         ret = -ENOMEM;
661                         goto fail_batch_free;
662                 }
663
664                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
665                                      cmdbuf->num_cliprects *
666                                      sizeof(struct drm_clip_rect));
667                 if (ret != 0)
668                         goto fail_clip_free;
669         }
670
671         mutex_lock(&dev->struct_mutex);
672         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
673         mutex_unlock(&dev->struct_mutex);
674         if (ret) {
675                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
676                 goto fail_clip_free;
677         }
678
679         if (sarea_priv)
680                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
681
682 fail_clip_free:
683         kfree(cliprects);
684 fail_batch_free:
685         kfree(batch_data);
686
687         return ret;
688 }
689
690 static int i915_flip_bufs(struct drm_device *dev, void *data,
691                           struct drm_file *file_priv)
692 {
693         int ret;
694
695         DRM_DEBUG_DRIVER("%s\n", __func__);
696
697         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
698
699         mutex_lock(&dev->struct_mutex);
700         ret = i915_dispatch_flip(dev);
701         mutex_unlock(&dev->struct_mutex);
702
703         return ret;
704 }
705
706 static int i915_getparam(struct drm_device *dev, void *data,
707                          struct drm_file *file_priv)
708 {
709         drm_i915_private_t *dev_priv = dev->dev_private;
710         drm_i915_getparam_t *param = data;
711         int value;
712
713         if (!dev_priv) {
714                 DRM_ERROR("called with no initialization\n");
715                 return -EINVAL;
716         }
717
718         switch (param->param) {
719         case I915_PARAM_IRQ_ACTIVE:
720                 value = dev->pdev->irq ? 1 : 0;
721                 break;
722         case I915_PARAM_ALLOW_BATCHBUFFER:
723                 value = dev_priv->allow_batchbuffer ? 1 : 0;
724                 break;
725         case I915_PARAM_LAST_DISPATCH:
726                 value = READ_BREADCRUMB(dev_priv);
727                 break;
728         case I915_PARAM_CHIPSET_ID:
729                 value = dev->pci_device;
730                 break;
731         case I915_PARAM_HAS_GEM:
732                 value = dev_priv->has_gem;
733                 break;
734         case I915_PARAM_NUM_FENCES_AVAIL:
735                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
736                 break;
737         case I915_PARAM_HAS_OVERLAY:
738                 value = dev_priv->overlay ? 1 : 0;
739                 break;
740         case I915_PARAM_HAS_PAGEFLIPPING:
741                 value = 1;
742                 break;
743         case I915_PARAM_HAS_EXECBUF2:
744                 /* depends on GEM */
745                 value = dev_priv->has_gem;
746                 break;
747         case I915_PARAM_HAS_BSD:
748                 value = HAS_BSD(dev);
749                 break;
750         default:
751                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
752                                  param->param);
753                 return -EINVAL;
754         }
755
756         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
757                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
758                 return -EFAULT;
759         }
760
761         return 0;
762 }
763
764 static int i915_setparam(struct drm_device *dev, void *data,
765                          struct drm_file *file_priv)
766 {
767         drm_i915_private_t *dev_priv = dev->dev_private;
768         drm_i915_setparam_t *param = data;
769
770         if (!dev_priv) {
771                 DRM_ERROR("called with no initialization\n");
772                 return -EINVAL;
773         }
774
775         switch (param->param) {
776         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
777                 break;
778         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
779                 dev_priv->tex_lru_log_granularity = param->value;
780                 break;
781         case I915_SETPARAM_ALLOW_BATCHBUFFER:
782                 dev_priv->allow_batchbuffer = param->value;
783                 break;
784         case I915_SETPARAM_NUM_USED_FENCES:
785                 if (param->value > dev_priv->num_fence_regs ||
786                     param->value < 0)
787                         return -EINVAL;
788                 /* Userspace can use first N regs */
789                 dev_priv->fence_reg_start = param->value;
790                 break;
791         default:
792                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
793                                         param->param);
794                 return -EINVAL;
795         }
796
797         return 0;
798 }
799
800 static int i915_set_status_page(struct drm_device *dev, void *data,
801                                 struct drm_file *file_priv)
802 {
803         drm_i915_private_t *dev_priv = dev->dev_private;
804         drm_i915_hws_addr_t *hws = data;
805         struct intel_ring_buffer *ring = &dev_priv->render_ring;
806
807         if (!I915_NEED_GFX_HWS(dev))
808                 return -EINVAL;
809
810         if (!dev_priv) {
811                 DRM_ERROR("called with no initialization\n");
812                 return -EINVAL;
813         }
814
815         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
816                 WARN(1, "tried to set status page when mode setting active\n");
817                 return 0;
818         }
819
820         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
821
822         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
823
824         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
825         dev_priv->hws_map.size = 4*1024;
826         dev_priv->hws_map.type = 0;
827         dev_priv->hws_map.flags = 0;
828         dev_priv->hws_map.mtrr = 0;
829
830         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
831         if (dev_priv->hws_map.handle == NULL) {
832                 i915_dma_cleanup(dev);
833                 ring->status_page.gfx_addr = 0;
834                 DRM_ERROR("can not ioremap virtual address for"
835                                 " G33 hw status page\n");
836                 return -ENOMEM;
837         }
838         ring->status_page.page_addr = dev_priv->hws_map.handle;
839         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
840         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
841
842         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
843                          ring->status_page.gfx_addr);
844         DRM_DEBUG_DRIVER("load hws at %p\n",
845                          ring->status_page.page_addr);
846         return 0;
847 }
848
849 static int i915_get_bridge_dev(struct drm_device *dev)
850 {
851         struct drm_i915_private *dev_priv = dev->dev_private;
852
853         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
854         if (!dev_priv->bridge_dev) {
855                 DRM_ERROR("bridge device not found\n");
856                 return -1;
857         }
858         return 0;
859 }
860
861 #define MCHBAR_I915 0x44
862 #define MCHBAR_I965 0x48
863 #define MCHBAR_SIZE (4*4096)
864
865 #define DEVEN_REG 0x54
866 #define   DEVEN_MCHBAR_EN (1 << 28)
867
868 /* Allocate space for the MCH regs if needed, return nonzero on error */
869 static int
870 intel_alloc_mchbar_resource(struct drm_device *dev)
871 {
872         drm_i915_private_t *dev_priv = dev->dev_private;
873         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
874         u32 temp_lo, temp_hi = 0;
875         u64 mchbar_addr;
876         int ret = 0;
877
878         if (IS_I965G(dev))
879                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
880         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
881         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
882
883         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
884 #ifdef CONFIG_PNP
885         if (mchbar_addr &&
886             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
887                 ret = 0;
888                 goto out;
889         }
890 #endif
891
892         /* Get some space for it */
893         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
894                                      MCHBAR_SIZE, MCHBAR_SIZE,
895                                      PCIBIOS_MIN_MEM,
896                                      0,   pcibios_align_resource,
897                                      dev_priv->bridge_dev);
898         if (ret) {
899                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
900                 dev_priv->mch_res.start = 0;
901                 goto out;
902         }
903
904         if (IS_I965G(dev))
905                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
906                                        upper_32_bits(dev_priv->mch_res.start));
907
908         pci_write_config_dword(dev_priv->bridge_dev, reg,
909                                lower_32_bits(dev_priv->mch_res.start));
910 out:
911         return ret;
912 }
913
914 /* Setup MCHBAR if possible, return true if we should disable it again */
915 static void
916 intel_setup_mchbar(struct drm_device *dev)
917 {
918         drm_i915_private_t *dev_priv = dev->dev_private;
919         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
920         u32 temp;
921         bool enabled;
922
923         dev_priv->mchbar_need_disable = false;
924
925         if (IS_I915G(dev) || IS_I915GM(dev)) {
926                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
927                 enabled = !!(temp & DEVEN_MCHBAR_EN);
928         } else {
929                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
930                 enabled = temp & 1;
931         }
932
933         /* If it's already enabled, don't have to do anything */
934         if (enabled)
935                 return;
936
937         if (intel_alloc_mchbar_resource(dev))
938                 return;
939
940         dev_priv->mchbar_need_disable = true;
941
942         /* Space is allocated or reserved, so enable it. */
943         if (IS_I915G(dev) || IS_I915GM(dev)) {
944                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
945                                        temp | DEVEN_MCHBAR_EN);
946         } else {
947                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
948                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
949         }
950 }
951
952 static void
953 intel_teardown_mchbar(struct drm_device *dev)
954 {
955         drm_i915_private_t *dev_priv = dev->dev_private;
956         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
957         u32 temp;
958
959         if (dev_priv->mchbar_need_disable) {
960                 if (IS_I915G(dev) || IS_I915GM(dev)) {
961                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
962                         temp &= ~DEVEN_MCHBAR_EN;
963                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
964                 } else {
965                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
966                         temp &= ~1;
967                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
968                 }
969         }
970
971         if (dev_priv->mch_res.start)
972                 release_resource(&dev_priv->mch_res);
973 }
974
975 /**
976  * i915_probe_agp - get AGP bootup configuration
977  * @pdev: PCI device
978  * @aperture_size: returns AGP aperture configured size
979  * @preallocated_size: returns size of BIOS preallocated AGP space
980  *
981  * Since Intel integrated graphics are UMA, the BIOS has to set aside
982  * some RAM for the framebuffer at early boot.  This code figures out
983  * how much was set aside so we can use it for our own purposes.
984  */
985 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
986                           uint32_t *preallocated_size,
987                           uint32_t *start)
988 {
989         struct drm_i915_private *dev_priv = dev->dev_private;
990         u16 tmp = 0;
991         unsigned long overhead;
992         unsigned long stolen;
993
994         /* Get the fb aperture size and "stolen" memory amount. */
995         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
996
997         *aperture_size = 1024 * 1024;
998         *preallocated_size = 1024 * 1024;
999
1000         switch (dev->pdev->device) {
1001         case PCI_DEVICE_ID_INTEL_82830_CGC:
1002         case PCI_DEVICE_ID_INTEL_82845G_IG:
1003         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1004         case PCI_DEVICE_ID_INTEL_82865_IG:
1005                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1006                         *aperture_size *= 64;
1007                 else
1008                         *aperture_size *= 128;
1009                 break;
1010         default:
1011                 /* 9xx supports large sizes, just look at the length */
1012                 *aperture_size = pci_resource_len(dev->pdev, 2);
1013                 break;
1014         }
1015
1016         /*
1017          * Some of the preallocated space is taken by the GTT
1018          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1019          */
1020         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1021                 overhead = 4096;
1022         else
1023                 overhead = (*aperture_size / 1024) + 4096;
1024
1025         if (IS_GEN6(dev)) {
1026                 /* SNB has memory control reg at 0x50.w */
1027                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1028
1029                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1030                 case INTEL_855_GMCH_GMS_DISABLED:
1031                         DRM_ERROR("video memory is disabled\n");
1032                         return -1;
1033                 case SNB_GMCH_GMS_STOLEN_32M:
1034                         stolen = 32 * 1024 * 1024;
1035                         break;
1036                 case SNB_GMCH_GMS_STOLEN_64M:
1037                         stolen = 64 * 1024 * 1024;
1038                         break;
1039                 case SNB_GMCH_GMS_STOLEN_96M:
1040                         stolen = 96 * 1024 * 1024;
1041                         break;
1042                 case SNB_GMCH_GMS_STOLEN_128M:
1043                         stolen = 128 * 1024 * 1024;
1044                         break;
1045                 case SNB_GMCH_GMS_STOLEN_160M:
1046                         stolen = 160 * 1024 * 1024;
1047                         break;
1048                 case SNB_GMCH_GMS_STOLEN_192M:
1049                         stolen = 192 * 1024 * 1024;
1050                         break;
1051                 case SNB_GMCH_GMS_STOLEN_224M:
1052                         stolen = 224 * 1024 * 1024;
1053                         break;
1054                 case SNB_GMCH_GMS_STOLEN_256M:
1055                         stolen = 256 * 1024 * 1024;
1056                         break;
1057                 case SNB_GMCH_GMS_STOLEN_288M:
1058                         stolen = 288 * 1024 * 1024;
1059                         break;
1060                 case SNB_GMCH_GMS_STOLEN_320M:
1061                         stolen = 320 * 1024 * 1024;
1062                         break;
1063                 case SNB_GMCH_GMS_STOLEN_352M:
1064                         stolen = 352 * 1024 * 1024;
1065                         break;
1066                 case SNB_GMCH_GMS_STOLEN_384M:
1067                         stolen = 384 * 1024 * 1024;
1068                         break;
1069                 case SNB_GMCH_GMS_STOLEN_416M:
1070                         stolen = 416 * 1024 * 1024;
1071                         break;
1072                 case SNB_GMCH_GMS_STOLEN_448M:
1073                         stolen = 448 * 1024 * 1024;
1074                         break;
1075                 case SNB_GMCH_GMS_STOLEN_480M:
1076                         stolen = 480 * 1024 * 1024;
1077                         break;
1078                 case SNB_GMCH_GMS_STOLEN_512M:
1079                         stolen = 512 * 1024 * 1024;
1080                         break;
1081                 default:
1082                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1083                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1084                         return -1;
1085                 }
1086         } else {
1087                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1088                 case INTEL_855_GMCH_GMS_DISABLED:
1089                         DRM_ERROR("video memory is disabled\n");
1090                         return -1;
1091                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1092                         stolen = 1 * 1024 * 1024;
1093                         break;
1094                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1095                         stolen = 4 * 1024 * 1024;
1096                         break;
1097                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1098                         stolen = 8 * 1024 * 1024;
1099                         break;
1100                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1101                         stolen = 16 * 1024 * 1024;
1102                         break;
1103                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1104                         stolen = 32 * 1024 * 1024;
1105                         break;
1106                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1107                         stolen = 48 * 1024 * 1024;
1108                         break;
1109                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1110                         stolen = 64 * 1024 * 1024;
1111                         break;
1112                 case INTEL_GMCH_GMS_STOLEN_128M:
1113                         stolen = 128 * 1024 * 1024;
1114                         break;
1115                 case INTEL_GMCH_GMS_STOLEN_256M:
1116                         stolen = 256 * 1024 * 1024;
1117                         break;
1118                 case INTEL_GMCH_GMS_STOLEN_96M:
1119                         stolen = 96 * 1024 * 1024;
1120                         break;
1121                 case INTEL_GMCH_GMS_STOLEN_160M:
1122                         stolen = 160 * 1024 * 1024;
1123                         break;
1124                 case INTEL_GMCH_GMS_STOLEN_224M:
1125                         stolen = 224 * 1024 * 1024;
1126                         break;
1127                 case INTEL_GMCH_GMS_STOLEN_352M:
1128                         stolen = 352 * 1024 * 1024;
1129                         break;
1130                 default:
1131                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1132                                   tmp & INTEL_GMCH_GMS_MASK);
1133                         return -1;
1134                 }
1135         }
1136
1137         *preallocated_size = stolen - overhead;
1138         *start = overhead;
1139
1140         return 0;
1141 }
1142
1143 #define PTE_ADDRESS_MASK                0xfffff000
1144 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1145 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1146 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1147 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1148 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1149 #define PTE_VALID                       (1 << 0)
1150
1151 /**
1152  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1153  * @dev: drm device
1154  * @gtt_addr: address to translate
1155  *
1156  * Some chip functions require allocations from stolen space but need the
1157  * physical address of the memory in question.  We use this routine
1158  * to get a physical address suitable for register programming from a given
1159  * GTT address.
1160  */
1161 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1162                                       unsigned long gtt_addr)
1163 {
1164         unsigned long *gtt;
1165         unsigned long entry, phys;
1166         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1167         int gtt_offset, gtt_size;
1168
1169         if (IS_I965G(dev)) {
1170                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1171                         gtt_offset = 2*1024*1024;
1172                         gtt_size = 2*1024*1024;
1173                 } else {
1174                         gtt_offset = 512*1024;
1175                         gtt_size = 512*1024;
1176                 }
1177         } else {
1178                 gtt_bar = 3;
1179                 gtt_offset = 0;
1180                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1181         }
1182
1183         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1184                          gtt_size);
1185         if (!gtt) {
1186                 DRM_ERROR("ioremap of GTT failed\n");
1187                 return 0;
1188         }
1189
1190         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1191
1192         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1193
1194         /* Mask out these reserved bits on this hardware. */
1195         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1196             IS_I945G(dev) || IS_I945GM(dev)) {
1197                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1198         }
1199
1200         /* If it's not a mapping type we know, then bail. */
1201         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1202             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1203                 iounmap(gtt);
1204                 return 0;
1205         }
1206
1207         if (!(entry & PTE_VALID)) {
1208                 DRM_ERROR("bad GTT entry in stolen space\n");
1209                 iounmap(gtt);
1210                 return 0;
1211         }
1212
1213         iounmap(gtt);
1214
1215         phys =(entry & PTE_ADDRESS_MASK) |
1216                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1217
1218         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1219
1220         return phys;
1221 }
1222
1223 static void i915_warn_stolen(struct drm_device *dev)
1224 {
1225         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1226         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1227 }
1228
1229 static void i915_setup_compression(struct drm_device *dev, int size)
1230 {
1231         struct drm_i915_private *dev_priv = dev->dev_private;
1232         struct drm_mm_node *compressed_fb, *compressed_llb;
1233         unsigned long cfb_base;
1234         unsigned long ll_base = 0;
1235
1236         /* Leave 1M for line length buffer & misc. */
1237         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1238         if (!compressed_fb) {
1239                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1240                 i915_warn_stolen(dev);
1241                 return;
1242         }
1243
1244         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1245         if (!compressed_fb) {
1246                 i915_warn_stolen(dev);
1247                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1248                 return;
1249         }
1250
1251         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1252         if (!cfb_base) {
1253                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1254                 drm_mm_put_block(compressed_fb);
1255         }
1256
1257         if (!IS_GM45(dev)) {
1258                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1259                                                     4096, 0);
1260                 if (!compressed_llb) {
1261                         i915_warn_stolen(dev);
1262                         return;
1263                 }
1264
1265                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1266                 if (!compressed_llb) {
1267                         i915_warn_stolen(dev);
1268                         return;
1269                 }
1270
1271                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1272                 if (!ll_base) {
1273                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1274                         drm_mm_put_block(compressed_fb);
1275                         drm_mm_put_block(compressed_llb);
1276                 }
1277         }
1278
1279         dev_priv->cfb_size = size;
1280
1281         intel_disable_fbc(dev);
1282         dev_priv->compressed_fb = compressed_fb;
1283
1284         if (IS_GM45(dev)) {
1285                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1286         } else {
1287                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1288                 I915_WRITE(FBC_LL_BASE, ll_base);
1289                 dev_priv->compressed_llb = compressed_llb;
1290         }
1291
1292         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1293                   ll_base, size >> 20);
1294 }
1295
1296 static void i915_cleanup_compression(struct drm_device *dev)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299
1300         drm_mm_put_block(dev_priv->compressed_fb);
1301         if (!IS_GM45(dev))
1302                 drm_mm_put_block(dev_priv->compressed_llb);
1303 }
1304
1305 /* true = enable decode, false = disable decoder */
1306 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1307 {
1308         struct drm_device *dev = cookie;
1309
1310         intel_modeset_vga_set_state(dev, state);
1311         if (state)
1312                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1313                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1314         else
1315                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1316 }
1317
1318 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1319 {
1320         struct drm_device *dev = pci_get_drvdata(pdev);
1321         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1322         if (state == VGA_SWITCHEROO_ON) {
1323                 printk(KERN_INFO "i915: switched on\n");
1324                 /* i915 resume handler doesn't set to D0 */
1325                 pci_set_power_state(dev->pdev, PCI_D0);
1326                 i915_resume(dev);
1327                 drm_kms_helper_poll_enable(dev);
1328         } else {
1329                 printk(KERN_ERR "i915: switched off\n");
1330                 drm_kms_helper_poll_disable(dev);
1331                 i915_suspend(dev, pmm);
1332         }
1333 }
1334
1335 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1336 {
1337         struct drm_device *dev = pci_get_drvdata(pdev);
1338         bool can_switch;
1339
1340         spin_lock(&dev->count_lock);
1341         can_switch = (dev->open_count == 0);
1342         spin_unlock(&dev->count_lock);
1343         return can_switch;
1344 }
1345
1346 static int i915_load_modeset_init(struct drm_device *dev,
1347                                   unsigned long prealloc_start,
1348                                   unsigned long prealloc_size,
1349                                   unsigned long agp_size)
1350 {
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1353         int ret = 0;
1354
1355         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1356                 0xff000000;
1357
1358         /* Basic memrange allocator for stolen space (aka vram) */
1359         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1360         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1361
1362         /* We're off and running w/KMS */
1363         dev_priv->mm.suspended = 0;
1364
1365         /* Let GEM Manage from end of prealloc space to end of aperture.
1366          *
1367          * However, leave one page at the end still bound to the scratch page.
1368          * There are a number of places where the hardware apparently
1369          * prefetches past the end of the object, and we've seen multiple
1370          * hangs with the GPU head pointer stuck in a batchbuffer bound
1371          * at the last page of the aperture.  One page should be enough to
1372          * keep any prefetching inside of the aperture.
1373          */
1374         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1375
1376         mutex_lock(&dev->struct_mutex);
1377         ret = i915_gem_init_ringbuffer(dev);
1378         mutex_unlock(&dev->struct_mutex);
1379         if (ret)
1380                 goto out;
1381
1382         /* Try to set up FBC with a reasonable compressed buffer size */
1383         if (I915_HAS_FBC(dev) && i915_powersave) {
1384                 int cfb_size;
1385
1386                 /* Try to get an 8M buffer... */
1387                 if (prealloc_size > (9*1024*1024))
1388                         cfb_size = 8*1024*1024;
1389                 else /* fall back to 7/8 of the stolen space */
1390                         cfb_size = prealloc_size * 7 / 8;
1391                 i915_setup_compression(dev, cfb_size);
1392         }
1393
1394         /* Allow hardware batchbuffers unless told otherwise.
1395          */
1396         dev_priv->allow_batchbuffer = 1;
1397
1398         ret = intel_init_bios(dev);
1399         if (ret)
1400                 DRM_INFO("failed to find VBIOS tables\n");
1401
1402         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1403         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1404         if (ret)
1405                 goto destroy_ringbuffer;
1406
1407         ret = vga_switcheroo_register_client(dev->pdev,
1408                                              i915_switcheroo_set_state,
1409                                              i915_switcheroo_can_switch);
1410         if (ret)
1411                 goto destroy_ringbuffer;
1412
1413         intel_modeset_init(dev);
1414
1415         ret = drm_irq_install(dev);
1416         if (ret)
1417                 goto destroy_ringbuffer;
1418
1419         /* Always safe in the mode setting case. */
1420         /* FIXME: do pre/post-mode set stuff in core KMS code */
1421         dev->vblank_disable_allowed = 1;
1422
1423         /*
1424          * Initialize the hardware status page IRQ location.
1425          */
1426
1427         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1428
1429         intel_fbdev_init(dev);
1430         drm_kms_helper_poll_init(dev);
1431         return 0;
1432
1433 destroy_ringbuffer:
1434         mutex_lock(&dev->struct_mutex);
1435         i915_gem_cleanup_ringbuffer(dev);
1436         mutex_unlock(&dev->struct_mutex);
1437 out:
1438         return ret;
1439 }
1440
1441 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1442 {
1443         struct drm_i915_master_private *master_priv;
1444
1445         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1446         if (!master_priv)
1447                 return -ENOMEM;
1448
1449         master->driver_priv = master_priv;
1450         return 0;
1451 }
1452
1453 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1454 {
1455         struct drm_i915_master_private *master_priv = master->driver_priv;
1456
1457         if (!master_priv)
1458                 return;
1459
1460         kfree(master_priv);
1461
1462         master->driver_priv = NULL;
1463 }
1464
1465 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1466 {
1467         drm_i915_private_t *dev_priv = dev->dev_private;
1468         u32 tmp;
1469
1470         tmp = I915_READ(CLKCFG);
1471
1472         switch (tmp & CLKCFG_FSB_MASK) {
1473         case CLKCFG_FSB_533:
1474                 dev_priv->fsb_freq = 533; /* 133*4 */
1475                 break;
1476         case CLKCFG_FSB_800:
1477                 dev_priv->fsb_freq = 800; /* 200*4 */
1478                 break;
1479         case CLKCFG_FSB_667:
1480                 dev_priv->fsb_freq =  667; /* 167*4 */
1481                 break;
1482         case CLKCFG_FSB_400:
1483                 dev_priv->fsb_freq = 400; /* 100*4 */
1484                 break;
1485         }
1486
1487         switch (tmp & CLKCFG_MEM_MASK) {
1488         case CLKCFG_MEM_533:
1489                 dev_priv->mem_freq = 533;
1490                 break;
1491         case CLKCFG_MEM_667:
1492                 dev_priv->mem_freq = 667;
1493                 break;
1494         case CLKCFG_MEM_800:
1495                 dev_priv->mem_freq = 800;
1496                 break;
1497         }
1498
1499         /* detect pineview DDR3 setting */
1500         tmp = I915_READ(CSHRDDR3CTL);
1501         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1502 }
1503
1504 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1505 {
1506         drm_i915_private_t *dev_priv = dev->dev_private;
1507         u16 ddrpll, csipll;
1508
1509         ddrpll = I915_READ16(DDRMPLL1);
1510         csipll = I915_READ16(CSIPLL0);
1511
1512         switch (ddrpll & 0xff) {
1513         case 0xc:
1514                 dev_priv->mem_freq = 800;
1515                 break;
1516         case 0x10:
1517                 dev_priv->mem_freq = 1066;
1518                 break;
1519         case 0x14:
1520                 dev_priv->mem_freq = 1333;
1521                 break;
1522         case 0x18:
1523                 dev_priv->mem_freq = 1600;
1524                 break;
1525         default:
1526                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1527                                  ddrpll & 0xff);
1528                 dev_priv->mem_freq = 0;
1529                 break;
1530         }
1531
1532         dev_priv->r_t = dev_priv->mem_freq;
1533
1534         switch (csipll & 0x3ff) {
1535         case 0x00c:
1536                 dev_priv->fsb_freq = 3200;
1537                 break;
1538         case 0x00e:
1539                 dev_priv->fsb_freq = 3733;
1540                 break;
1541         case 0x010:
1542                 dev_priv->fsb_freq = 4266;
1543                 break;
1544         case 0x012:
1545                 dev_priv->fsb_freq = 4800;
1546                 break;
1547         case 0x014:
1548                 dev_priv->fsb_freq = 5333;
1549                 break;
1550         case 0x016:
1551                 dev_priv->fsb_freq = 5866;
1552                 break;
1553         case 0x018:
1554                 dev_priv->fsb_freq = 6400;
1555                 break;
1556         default:
1557                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1558                                  csipll & 0x3ff);
1559                 dev_priv->fsb_freq = 0;
1560                 break;
1561         }
1562
1563         if (dev_priv->fsb_freq == 3200) {
1564                 dev_priv->c_m = 0;
1565         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1566                 dev_priv->c_m = 1;
1567         } else {
1568                 dev_priv->c_m = 2;
1569         }
1570 }
1571
1572 struct v_table {
1573         u8 vid;
1574         unsigned long vd; /* in .1 mil */
1575         unsigned long vm; /* in .1 mil */
1576         u8 pvid;
1577 };
1578
1579 static struct v_table v_table[] = {
1580         { 0, 16125, 15000, 0x7f, },
1581         { 1, 16000, 14875, 0x7e, },
1582         { 2, 15875, 14750, 0x7d, },
1583         { 3, 15750, 14625, 0x7c, },
1584         { 4, 15625, 14500, 0x7b, },
1585         { 5, 15500, 14375, 0x7a, },
1586         { 6, 15375, 14250, 0x79, },
1587         { 7, 15250, 14125, 0x78, },
1588         { 8, 15125, 14000, 0x77, },
1589         { 9, 15000, 13875, 0x76, },
1590         { 10, 14875, 13750, 0x75, },
1591         { 11, 14750, 13625, 0x74, },
1592         { 12, 14625, 13500, 0x73, },
1593         { 13, 14500, 13375, 0x72, },
1594         { 14, 14375, 13250, 0x71, },
1595         { 15, 14250, 13125, 0x70, },
1596         { 16, 14125, 13000, 0x6f, },
1597         { 17, 14000, 12875, 0x6e, },
1598         { 18, 13875, 12750, 0x6d, },
1599         { 19, 13750, 12625, 0x6c, },
1600         { 20, 13625, 12500, 0x6b, },
1601         { 21, 13500, 12375, 0x6a, },
1602         { 22, 13375, 12250, 0x69, },
1603         { 23, 13250, 12125, 0x68, },
1604         { 24, 13125, 12000, 0x67, },
1605         { 25, 13000, 11875, 0x66, },
1606         { 26, 12875, 11750, 0x65, },
1607         { 27, 12750, 11625, 0x64, },
1608         { 28, 12625, 11500, 0x63, },
1609         { 29, 12500, 11375, 0x62, },
1610         { 30, 12375, 11250, 0x61, },
1611         { 31, 12250, 11125, 0x60, },
1612         { 32, 12125, 11000, 0x5f, },
1613         { 33, 12000, 10875, 0x5e, },
1614         { 34, 11875, 10750, 0x5d, },
1615         { 35, 11750, 10625, 0x5c, },
1616         { 36, 11625, 10500, 0x5b, },
1617         { 37, 11500, 10375, 0x5a, },
1618         { 38, 11375, 10250, 0x59, },
1619         { 39, 11250, 10125, 0x58, },
1620         { 40, 11125, 10000, 0x57, },
1621         { 41, 11000, 9875, 0x56, },
1622         { 42, 10875, 9750, 0x55, },
1623         { 43, 10750, 9625, 0x54, },
1624         { 44, 10625, 9500, 0x53, },
1625         { 45, 10500, 9375, 0x52, },
1626         { 46, 10375, 9250, 0x51, },
1627         { 47, 10250, 9125, 0x50, },
1628         { 48, 10125, 9000, 0x4f, },
1629         { 49, 10000, 8875, 0x4e, },
1630         { 50, 9875, 8750, 0x4d, },
1631         { 51, 9750, 8625, 0x4c, },
1632         { 52, 9625, 8500, 0x4b, },
1633         { 53, 9500, 8375, 0x4a, },
1634         { 54, 9375, 8250, 0x49, },
1635         { 55, 9250, 8125, 0x48, },
1636         { 56, 9125, 8000, 0x47, },
1637         { 57, 9000, 7875, 0x46, },
1638         { 58, 8875, 7750, 0x45, },
1639         { 59, 8750, 7625, 0x44, },
1640         { 60, 8625, 7500, 0x43, },
1641         { 61, 8500, 7375, 0x42, },
1642         { 62, 8375, 7250, 0x41, },
1643         { 63, 8250, 7125, 0x40, },
1644         { 64, 8125, 7000, 0x3f, },
1645         { 65, 8000, 6875, 0x3e, },
1646         { 66, 7875, 6750, 0x3d, },
1647         { 67, 7750, 6625, 0x3c, },
1648         { 68, 7625, 6500, 0x3b, },
1649         { 69, 7500, 6375, 0x3a, },
1650         { 70, 7375, 6250, 0x39, },
1651         { 71, 7250, 6125, 0x38, },
1652         { 72, 7125, 6000, 0x37, },
1653         { 73, 7000, 5875, 0x36, },
1654         { 74, 6875, 5750, 0x35, },
1655         { 75, 6750, 5625, 0x34, },
1656         { 76, 6625, 5500, 0x33, },
1657         { 77, 6500, 5375, 0x32, },
1658         { 78, 6375, 5250, 0x31, },
1659         { 79, 6250, 5125, 0x30, },
1660         { 80, 6125, 5000, 0x2f, },
1661         { 81, 6000, 4875, 0x2e, },
1662         { 82, 5875, 4750, 0x2d, },
1663         { 83, 5750, 4625, 0x2c, },
1664         { 84, 5625, 4500, 0x2b, },
1665         { 85, 5500, 4375, 0x2a, },
1666         { 86, 5375, 4250, 0x29, },
1667         { 87, 5250, 4125, 0x28, },
1668         { 88, 5125, 4000, 0x27, },
1669         { 89, 5000, 3875, 0x26, },
1670         { 90, 4875, 3750, 0x25, },
1671         { 91, 4750, 3625, 0x24, },
1672         { 92, 4625, 3500, 0x23, },
1673         { 93, 4500, 3375, 0x22, },
1674         { 94, 4375, 3250, 0x21, },
1675         { 95, 4250, 3125, 0x20, },
1676         { 96, 4125, 3000, 0x1f, },
1677         { 97, 4125, 3000, 0x1e, },
1678         { 98, 4125, 3000, 0x1d, },
1679         { 99, 4125, 3000, 0x1c, },
1680         { 100, 4125, 3000, 0x1b, },
1681         { 101, 4125, 3000, 0x1a, },
1682         { 102, 4125, 3000, 0x19, },
1683         { 103, 4125, 3000, 0x18, },
1684         { 104, 4125, 3000, 0x17, },
1685         { 105, 4125, 3000, 0x16, },
1686         { 106, 4125, 3000, 0x15, },
1687         { 107, 4125, 3000, 0x14, },
1688         { 108, 4125, 3000, 0x13, },
1689         { 109, 4125, 3000, 0x12, },
1690         { 110, 4125, 3000, 0x11, },
1691         { 111, 4125, 3000, 0x10, },
1692         { 112, 4125, 3000, 0x0f, },
1693         { 113, 4125, 3000, 0x0e, },
1694         { 114, 4125, 3000, 0x0d, },
1695         { 115, 4125, 3000, 0x0c, },
1696         { 116, 4125, 3000, 0x0b, },
1697         { 117, 4125, 3000, 0x0a, },
1698         { 118, 4125, 3000, 0x09, },
1699         { 119, 4125, 3000, 0x08, },
1700         { 120, 1125, 0, 0x07, },
1701         { 121, 1000, 0, 0x06, },
1702         { 122, 875, 0, 0x05, },
1703         { 123, 750, 0, 0x04, },
1704         { 124, 625, 0, 0x03, },
1705         { 125, 500, 0, 0x02, },
1706         { 126, 375, 0, 0x01, },
1707         { 127, 0, 0, 0x00, },
1708 };
1709
1710 struct cparams {
1711         int i;
1712         int t;
1713         int m;
1714         int c;
1715 };
1716
1717 static struct cparams cparams[] = {
1718         { 1, 1333, 301, 28664 },
1719         { 1, 1066, 294, 24460 },
1720         { 1, 800, 294, 25192 },
1721         { 0, 1333, 276, 27605 },
1722         { 0, 1066, 276, 27605 },
1723         { 0, 800, 231, 23784 },
1724 };
1725
1726 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1727 {
1728         u64 total_count, diff, ret;
1729         u32 count1, count2, count3, m = 0, c = 0;
1730         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1731         int i;
1732
1733         diff1 = now - dev_priv->last_time1;
1734
1735         count1 = I915_READ(DMIEC);
1736         count2 = I915_READ(DDREC);
1737         count3 = I915_READ(CSIEC);
1738
1739         total_count = count1 + count2 + count3;
1740
1741         /* FIXME: handle per-counter overflow */
1742         if (total_count < dev_priv->last_count1) {
1743                 diff = ~0UL - dev_priv->last_count1;
1744                 diff += total_count;
1745         } else {
1746                 diff = total_count - dev_priv->last_count1;
1747         }
1748
1749         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1750                 if (cparams[i].i == dev_priv->c_m &&
1751                     cparams[i].t == dev_priv->r_t) {
1752                         m = cparams[i].m;
1753                         c = cparams[i].c;
1754                         break;
1755                 }
1756         }
1757
1758         div_u64(diff, diff1);
1759         ret = ((m * diff) + c);
1760         div_u64(ret, 10);
1761
1762         dev_priv->last_count1 = total_count;
1763         dev_priv->last_time1 = now;
1764
1765         return ret;
1766 }
1767
1768 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1769 {
1770         unsigned long m, x, b;
1771         u32 tsfs;
1772
1773         tsfs = I915_READ(TSFS);
1774
1775         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1776         x = I915_READ8(TR1);
1777
1778         b = tsfs & TSFS_INTR_MASK;
1779
1780         return ((m * x) / 127) - b;
1781 }
1782
1783 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1784 {
1785         unsigned long val = 0;
1786         int i;
1787
1788         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1789                 if (v_table[i].pvid == pxvid) {
1790                         if (IS_MOBILE(dev_priv->dev))
1791                                 val = v_table[i].vm;
1792                         else
1793                                 val = v_table[i].vd;
1794                 }
1795         }
1796
1797         return val;
1798 }
1799
1800 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1801 {
1802         struct timespec now, diff1;
1803         u64 diff;
1804         unsigned long diffms;
1805         u32 count;
1806
1807         getrawmonotonic(&now);
1808         diff1 = timespec_sub(now, dev_priv->last_time2);
1809
1810         /* Don't divide by 0 */
1811         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1812         if (!diffms)
1813                 return;
1814
1815         count = I915_READ(GFXEC);
1816
1817         if (count < dev_priv->last_count2) {
1818                 diff = ~0UL - dev_priv->last_count2;
1819                 diff += count;
1820         } else {
1821                 diff = count - dev_priv->last_count2;
1822         }
1823
1824         dev_priv->last_count2 = count;
1825         dev_priv->last_time2 = now;
1826
1827         /* More magic constants... */
1828         diff = diff * 1181;
1829         div_u64(diff, diffms * 10);
1830         dev_priv->gfx_power = diff;
1831 }
1832
1833 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1834 {
1835         unsigned long t, corr, state1, corr2, state2;
1836         u32 pxvid, ext_v;
1837
1838         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1839         pxvid = (pxvid >> 24) & 0x7f;
1840         ext_v = pvid_to_extvid(dev_priv, pxvid);
1841
1842         state1 = ext_v;
1843
1844         t = i915_mch_val(dev_priv);
1845
1846         /* Revel in the empirically derived constants */
1847
1848         /* Correction factor in 1/100000 units */
1849         if (t > 80)
1850                 corr = ((t * 2349) + 135940);
1851         else if (t >= 50)
1852                 corr = ((t * 964) + 29317);
1853         else /* < 50 */
1854                 corr = ((t * 301) + 1004);
1855
1856         corr = corr * ((150142 * state1) / 10000 - 78642);
1857         corr /= 100000;
1858         corr2 = (corr * dev_priv->corr);
1859
1860         state2 = (corr2 * state1) / 10000;
1861         state2 /= 100; /* convert to mW */
1862
1863         i915_update_gfx_val(dev_priv);
1864
1865         return dev_priv->gfx_power + state2;
1866 }
1867
1868 /* Global for IPS driver to get at the current i915 device */
1869 static struct drm_i915_private *i915_mch_dev;
1870 /*
1871  * Lock protecting IPS related data structures
1872  *   - i915_mch_dev
1873  *   - dev_priv->max_delay
1874  *   - dev_priv->min_delay
1875  *   - dev_priv->fmax
1876  *   - dev_priv->gpu_busy
1877  */
1878 DEFINE_SPINLOCK(mchdev_lock);
1879
1880 /**
1881  * i915_read_mch_val - return value for IPS use
1882  *
1883  * Calculate and return a value for the IPS driver to use when deciding whether
1884  * we have thermal and power headroom to increase CPU or GPU power budget.
1885  */
1886 unsigned long i915_read_mch_val(void)
1887 {
1888         struct drm_i915_private *dev_priv;
1889         unsigned long chipset_val, graphics_val, ret = 0;
1890
1891         spin_lock(&mchdev_lock);
1892         if (!i915_mch_dev)
1893                 goto out_unlock;
1894         dev_priv = i915_mch_dev;
1895
1896         chipset_val = i915_chipset_val(dev_priv);
1897         graphics_val = i915_gfx_val(dev_priv);
1898
1899         ret = chipset_val + graphics_val;
1900
1901 out_unlock:
1902         spin_unlock(&mchdev_lock);
1903
1904         return ret;
1905 }
1906 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1907
1908 /**
1909  * i915_gpu_raise - raise GPU frequency limit
1910  *
1911  * Raise the limit; IPS indicates we have thermal headroom.
1912  */
1913 bool i915_gpu_raise(void)
1914 {
1915         struct drm_i915_private *dev_priv;
1916         bool ret = true;
1917
1918         spin_lock(&mchdev_lock);
1919         if (!i915_mch_dev) {
1920                 ret = false;
1921                 goto out_unlock;
1922         }
1923         dev_priv = i915_mch_dev;
1924
1925         if (dev_priv->max_delay > dev_priv->fmax)
1926                 dev_priv->max_delay--;
1927
1928 out_unlock:
1929         spin_unlock(&mchdev_lock);
1930
1931         return ret;
1932 }
1933 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1934
1935 /**
1936  * i915_gpu_lower - lower GPU frequency limit
1937  *
1938  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1939  * frequency maximum.
1940  */
1941 bool i915_gpu_lower(void)
1942 {
1943         struct drm_i915_private *dev_priv;
1944         bool ret = true;
1945
1946         spin_lock(&mchdev_lock);
1947         if (!i915_mch_dev) {
1948                 ret = false;
1949                 goto out_unlock;
1950         }
1951         dev_priv = i915_mch_dev;
1952
1953         if (dev_priv->max_delay < dev_priv->min_delay)
1954                 dev_priv->max_delay++;
1955
1956 out_unlock:
1957         spin_unlock(&mchdev_lock);
1958
1959         return ret;
1960 }
1961 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1962
1963 /**
1964  * i915_gpu_busy - indicate GPU business to IPS
1965  *
1966  * Tell the IPS driver whether or not the GPU is busy.
1967  */
1968 bool i915_gpu_busy(void)
1969 {
1970         struct drm_i915_private *dev_priv;
1971         bool ret = false;
1972
1973         spin_lock(&mchdev_lock);
1974         if (!i915_mch_dev)
1975                 goto out_unlock;
1976         dev_priv = i915_mch_dev;
1977
1978         ret = dev_priv->busy;
1979
1980 out_unlock:
1981         spin_unlock(&mchdev_lock);
1982
1983         return ret;
1984 }
1985 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1986
1987 /**
1988  * i915_gpu_turbo_disable - disable graphics turbo
1989  *
1990  * Disable graphics turbo by resetting the max frequency and setting the
1991  * current frequency to the default.
1992  */
1993 bool i915_gpu_turbo_disable(void)
1994 {
1995         struct drm_i915_private *dev_priv;
1996         bool ret = true;
1997
1998         spin_lock(&mchdev_lock);
1999         if (!i915_mch_dev) {
2000                 ret = false;
2001                 goto out_unlock;
2002         }
2003         dev_priv = i915_mch_dev;
2004
2005         dev_priv->max_delay = dev_priv->fstart;
2006
2007         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2008                 ret = false;
2009
2010 out_unlock:
2011         spin_unlock(&mchdev_lock);
2012
2013         return ret;
2014 }
2015 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2016
2017 /**
2018  * i915_driver_load - setup chip and create an initial config
2019  * @dev: DRM device
2020  * @flags: startup flags
2021  *
2022  * The driver load routine has to do several things:
2023  *   - drive output discovery via intel_modeset_init()
2024  *   - initialize the memory manager
2025  *   - allocate initial config memory
2026  *   - setup the DRM framebuffer with the allocated memory
2027  */
2028 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2029 {
2030         struct drm_i915_private *dev_priv;
2031         resource_size_t base, size;
2032         int ret = 0, mmio_bar;
2033         uint32_t agp_size, prealloc_size, prealloc_start;
2034         /* i915 has 4 more counters */
2035         dev->counters += 4;
2036         dev->types[6] = _DRM_STAT_IRQ;
2037         dev->types[7] = _DRM_STAT_PRIMARY;
2038         dev->types[8] = _DRM_STAT_SECONDARY;
2039         dev->types[9] = _DRM_STAT_DMA;
2040
2041         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2042         if (dev_priv == NULL)
2043                 return -ENOMEM;
2044
2045         dev->dev_private = (void *)dev_priv;
2046         dev_priv->dev = dev;
2047         dev_priv->info = (struct intel_device_info *) flags;
2048
2049         /* Add register map (needed for suspend/resume) */
2050         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2051         base = drm_get_resource_start(dev, mmio_bar);
2052         size = drm_get_resource_len(dev, mmio_bar);
2053
2054         if (i915_get_bridge_dev(dev)) {
2055                 ret = -EIO;
2056                 goto free_priv;
2057         }
2058
2059         dev_priv->regs = ioremap(base, size);
2060         if (!dev_priv->regs) {
2061                 DRM_ERROR("failed to map registers\n");
2062                 ret = -EIO;
2063                 goto put_bridge;
2064         }
2065
2066         dev_priv->mm.gtt_mapping =
2067                 io_mapping_create_wc(dev->agp->base,
2068                                      dev->agp->agp_info.aper_size * 1024*1024);
2069         if (dev_priv->mm.gtt_mapping == NULL) {
2070                 ret = -EIO;
2071                 goto out_rmmap;
2072         }
2073
2074         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2075          * one would think, because the kernel disables PAT on first
2076          * generation Core chips because WC PAT gets overridden by a UC
2077          * MTRR if present.  Even if a UC MTRR isn't present.
2078          */
2079         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2080                                          dev->agp->agp_info.aper_size *
2081                                          1024 * 1024,
2082                                          MTRR_TYPE_WRCOMB, 1);
2083         if (dev_priv->mm.gtt_mtrr < 0) {
2084                 DRM_INFO("MTRR allocation failed.  Graphics "
2085                          "performance may suffer.\n");
2086         }
2087
2088         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2089         if (ret)
2090                 goto out_iomapfree;
2091
2092         dev_priv->wq = create_singlethread_workqueue("i915");
2093         if (dev_priv->wq == NULL) {
2094                 DRM_ERROR("Failed to create our workqueue.\n");
2095                 ret = -ENOMEM;
2096                 goto out_iomapfree;
2097         }
2098
2099         /* enable GEM by default */
2100         dev_priv->has_gem = 1;
2101
2102         if (prealloc_size > agp_size * 3 / 4) {
2103                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2104                           "memory stolen.\n",
2105                           prealloc_size / 1024, agp_size / 1024);
2106                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2107                           "updating the BIOS to fix).\n");
2108                 dev_priv->has_gem = 0;
2109         }
2110
2111         if (dev_priv->has_gem == 0 &&
2112             drm_core_check_feature(dev, DRIVER_MODESET)) {
2113                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2114                 ret = -ENODEV;
2115                 goto out_iomapfree;
2116         }
2117
2118         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2119         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2120         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2121                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2122                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2123         }
2124
2125         /* Try to make sure MCHBAR is enabled before poking at it */
2126         intel_setup_mchbar(dev);
2127
2128         i915_gem_load(dev);
2129
2130         /* Init HWS */
2131         if (!I915_NEED_GFX_HWS(dev)) {
2132                 ret = i915_init_phys_hws(dev);
2133                 if (ret != 0)
2134                         goto out_workqueue_free;
2135         }
2136
2137         if (IS_PINEVIEW(dev))
2138                 i915_pineview_get_mem_freq(dev);
2139         else if (IS_IRONLAKE(dev))
2140                 i915_ironlake_get_mem_freq(dev);
2141
2142         /* On the 945G/GM, the chipset reports the MSI capability on the
2143          * integrated graphics even though the support isn't actually there
2144          * according to the published specs.  It doesn't appear to function
2145          * correctly in testing on 945G.
2146          * This may be a side effect of MSI having been made available for PEG
2147          * and the registers being closely associated.
2148          *
2149          * According to chipset errata, on the 965GM, MSI interrupts may
2150          * be lost or delayed, but we use them anyways to avoid
2151          * stuck interrupts on some machines.
2152          */
2153         if (!IS_I945G(dev) && !IS_I945GM(dev))
2154                 pci_enable_msi(dev->pdev);
2155
2156         spin_lock_init(&dev_priv->user_irq_lock);
2157         spin_lock_init(&dev_priv->error_lock);
2158         dev_priv->trace_irq_seqno = 0;
2159
2160         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2161
2162         if (ret) {
2163                 (void) i915_driver_unload(dev);
2164                 return ret;
2165         }
2166
2167         /* Start out suspended */
2168         dev_priv->mm.suspended = 1;
2169
2170         intel_detect_pch(dev);
2171
2172         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2173                 ret = i915_load_modeset_init(dev, prealloc_start,
2174                                              prealloc_size, agp_size);
2175                 if (ret < 0) {
2176                         DRM_ERROR("failed to init modeset\n");
2177                         goto out_workqueue_free;
2178                 }
2179         }
2180
2181         /* Must be done after probing outputs */
2182         intel_opregion_init(dev, 0);
2183
2184         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2185                     (unsigned long) dev);
2186
2187         spin_lock(&mchdev_lock);
2188         i915_mch_dev = dev_priv;
2189         dev_priv->mchdev_lock = &mchdev_lock;
2190         spin_unlock(&mchdev_lock);
2191
2192         return 0;
2193
2194 out_workqueue_free:
2195         destroy_workqueue(dev_priv->wq);
2196 out_iomapfree:
2197         io_mapping_free(dev_priv->mm.gtt_mapping);
2198 out_rmmap:
2199         iounmap(dev_priv->regs);
2200 put_bridge:
2201         pci_dev_put(dev_priv->bridge_dev);
2202 free_priv:
2203         kfree(dev_priv);
2204         return ret;
2205 }
2206
2207 int i915_driver_unload(struct drm_device *dev)
2208 {
2209         struct drm_i915_private *dev_priv = dev->dev_private;
2210
2211         i915_destroy_error_state(dev);
2212
2213         spin_lock(&mchdev_lock);
2214         i915_mch_dev = NULL;
2215         spin_unlock(&mchdev_lock);
2216
2217         destroy_workqueue(dev_priv->wq);
2218         del_timer_sync(&dev_priv->hangcheck_timer);
2219
2220         io_mapping_free(dev_priv->mm.gtt_mapping);
2221         if (dev_priv->mm.gtt_mtrr >= 0) {
2222                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2223                          dev->agp->agp_info.aper_size * 1024 * 1024);
2224                 dev_priv->mm.gtt_mtrr = -1;
2225         }
2226
2227         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2228                 intel_modeset_cleanup(dev);
2229
2230                 /*
2231                  * free the memory space allocated for the child device
2232                  * config parsed from VBT
2233                  */
2234                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2235                         kfree(dev_priv->child_dev);
2236                         dev_priv->child_dev = NULL;
2237                         dev_priv->child_dev_num = 0;
2238                 }
2239                 drm_irq_uninstall(dev);
2240                 vga_switcheroo_unregister_client(dev->pdev);
2241                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2242         }
2243
2244         if (dev->pdev->msi_enabled)
2245                 pci_disable_msi(dev->pdev);
2246
2247         if (dev_priv->regs != NULL)
2248                 iounmap(dev_priv->regs);
2249
2250         intel_opregion_free(dev, 0);
2251
2252         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2253                 i915_gem_free_all_phys_object(dev);
2254
2255                 mutex_lock(&dev->struct_mutex);
2256                 i915_gem_cleanup_ringbuffer(dev);
2257                 mutex_unlock(&dev->struct_mutex);
2258                 if (I915_HAS_FBC(dev) && i915_powersave)
2259                         i915_cleanup_compression(dev);
2260                 drm_mm_takedown(&dev_priv->vram);
2261                 i915_gem_lastclose(dev);
2262
2263                 intel_cleanup_overlay(dev);
2264         }
2265
2266         intel_teardown_mchbar(dev);
2267
2268         pci_dev_put(dev_priv->bridge_dev);
2269         kfree(dev->dev_private);
2270
2271         return 0;
2272 }
2273
2274 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2275 {
2276         struct drm_i915_file_private *i915_file_priv;
2277
2278         DRM_DEBUG_DRIVER("\n");
2279         i915_file_priv = (struct drm_i915_file_private *)
2280             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2281
2282         if (!i915_file_priv)
2283                 return -ENOMEM;
2284
2285         file_priv->driver_priv = i915_file_priv;
2286
2287         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2288
2289         return 0;
2290 }
2291
2292 /**
2293  * i915_driver_lastclose - clean up after all DRM clients have exited
2294  * @dev: DRM device
2295  *
2296  * Take care of cleaning up after all DRM clients have exited.  In the
2297  * mode setting case, we want to restore the kernel's initial mode (just
2298  * in case the last client left us in a bad state).
2299  *
2300  * Additionally, in the non-mode setting case, we'll tear down the AGP
2301  * and DMA structures, since the kernel won't be using them, and clea
2302  * up any GEM state.
2303  */
2304 void i915_driver_lastclose(struct drm_device * dev)
2305 {
2306         drm_i915_private_t *dev_priv = dev->dev_private;
2307
2308         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2309                 drm_fb_helper_restore();
2310                 vga_switcheroo_process_delayed_switch();
2311                 return;
2312         }
2313
2314         i915_gem_lastclose(dev);
2315
2316         if (dev_priv->agp_heap)
2317                 i915_mem_takedown(&(dev_priv->agp_heap));
2318
2319         i915_dma_cleanup(dev);
2320 }
2321
2322 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2323 {
2324         drm_i915_private_t *dev_priv = dev->dev_private;
2325         i915_gem_release(dev, file_priv);
2326         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2327                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2328 }
2329
2330 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2331 {
2332         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2333
2334         kfree(i915_file_priv);
2335 }
2336
2337 struct drm_ioctl_desc i915_ioctls[] = {
2338         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2339         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2340         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2341         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2342         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2343         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2344         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2345         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2346         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2347         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2348         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2349         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2350         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2351         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2352         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
2353         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2354         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2355         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2356         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2357         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2358         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2359         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2360         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2361         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2362         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2363         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2364         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2365         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2366         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2367         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2368         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2369         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2370         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2371         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2372         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2373         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2374         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2375         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2376         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2377         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2378 };
2379
2380 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2381
2382 /**
2383  * Determine if the device really is AGP or not.
2384  *
2385  * All Intel graphics chipsets are treated as AGP, even if they are really
2386  * PCI-e.
2387  *
2388  * \param dev   The device to be tested.
2389  *
2390  * \returns
2391  * A value of 1 is always retured to indictate every i9x5 is AGP.
2392  */
2393 int i915_driver_device_is_agp(struct drm_device * dev)
2394 {
2395         return 1;
2396 }