drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139         enum intel_engine_id id;
 140
 141         lockdep_assert_held(&obj->base.dev->struct_mutex);
 142
 143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    get_active_flag(obj),
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    get_pin_mapped_flag(obj),
 150                    obj->base.size / 1024,
 151                    obj->base.read_domains,
 152                    obj->base.write_domain);
 153         for_each_engine_id(engine, dev_priv, id)
 154                 seq_printf(m, "%x ",
 155                            i915_gem_active_get_seqno(&obj->last_read[id],
 156                                                      &obj->base.dev->struct_mutex));
 157         seq_printf(m, "] %x %s%s%s",
 158                    i915_gem_active_get_seqno(&obj->last_write,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(dev_priv, obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 173                 if (!drm_mm_node_allocated(&vma->node))
 174                         continue;
 175
 176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 178                            vma->node.start, vma->node.size);
 179                 if (i915_vma_is_ggtt(vma))
 180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 181                 if (vma->fence)
 182                         seq_printf(m, " , fence: %d%s",
 183                                    vma->fence->id,
 184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 185                 seq_puts(m, ")");
 186         }
 187         if (obj->stolen)
 188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 189         if (obj->pin_display || obj->fault_mappable) {
 190                 char s[3], *t = s;
 191                 if (obj->pin_display)
 192                         *t++ = 'p';
 193                 if (obj->fault_mappable)
 194                         *t++ = 'f';
 195                 *t = '\0';
 196                 seq_printf(m, " (%s mappable)", s);
 197         }
 198
 199         engine = i915_gem_active_get_engine(&obj->last_write,
 200                                             &dev_priv->drm.struct_mutex);
 201         if (engine)
 202                 seq_printf(m, " (%s)", engine->name);
 203
 204         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 205         if (frontbuffer_bits)
 206                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 207 }
 208
 209 static int obj_rank_by_stolen(void *priv,
 210                               struct list_head *A, struct list_head *B)
 211 {
 212         struct drm_i915_gem_object *a =
 213                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 214         struct drm_i915_gem_object *b =
 215                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 216
 217         if (a->stolen->start < b->stolen->start)
 218                 return -1;
 219         if (a->stolen->start > b->stolen->start)
 220                 return 1;
 221         return 0;
 222 }
 223
 224 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 225 {
 226         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 227         struct drm_device *dev = &dev_priv->drm;
 228         struct drm_i915_gem_object *obj;
 229         u64 total_obj_size, total_gtt_size;
 230         LIST_HEAD(stolen);
 231         int count, ret;
 232
 233         ret = mutex_lock_interruptible(&dev->struct_mutex);
 234         if (ret)
 235                 return ret;
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 239                 if (obj->stolen == NULL)
 240                         continue;
 241
 242                 list_add(&obj->obj_exec_link, &stolen);
 243
 244                 total_obj_size += obj->base.size;
 245                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 246                 count++;
 247         }
 248         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 249                 if (obj->stolen == NULL)
 250                         continue;
 251
 252                 list_add(&obj->obj_exec_link, &stolen);
 253
 254                 total_obj_size += obj->base.size;
 255                 count++;
 256         }
 257         list_sort(NULL, &stolen, obj_rank_by_stolen);
 258         seq_puts(m, "Stolen:\n");
 259         while (!list_empty(&stolen)) {
 260                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 261                 seq_puts(m, "   ");
 262                 describe_obj(m, obj);
 263                 seq_putc(m, '\n');
 264                 list_del_init(&obj->obj_exec_link);
 265         }
 266         mutex_unlock(&dev->struct_mutex);
 267
 268         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 269                    count, total_obj_size, total_gtt_size);
 270         return 0;
 271 }
 272
 273 struct file_stats {
 274         struct drm_i915_file_private *file_priv;
 275         unsigned long count;
 276         u64 total, unbound;
 277         u64 global, shared;
 278         u64 active, inactive;
 279 };
 280
 281 static int per_file_stats(int id, void *ptr, void *data)
 282 {
 283         struct drm_i915_gem_object *obj = ptr;
 284         struct file_stats *stats = data;
 285         struct i915_vma *vma;
 286
 287         stats->count++;
 288         stats->total += obj->base.size;
 289         if (!obj->bind_count)
 290                 stats->unbound += obj->base.size;
 291         if (obj->base.name || obj->base.dma_buf)
 292                 stats->shared += obj->base.size;
 293
 294         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 295                 if (!drm_mm_node_allocated(&vma->node))
 296                         continue;
 297
 298                 if (i915_vma_is_ggtt(vma)) {
 299                         stats->global += vma->node.size;
 300                 } else {
 301                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 302
 303                         if (ppgtt->base.file != stats->file_priv)
 304                                 continue;
 305                 }
 306
 307                 if (i915_vma_is_active(vma))
 308                         stats->active += vma->node.size;
 309                 else
 310                         stats->inactive += vma->node.size;
 311         }
 312
 313         return 0;
 314 }
 315
 316 #define print_file_stats(m, name, stats) do { \
 317         if (stats.count) \
 318                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 319                            name, \
 320                            stats.count, \
 321                            stats.total, \
 322                            stats.active, \
 323                            stats.inactive, \
 324                            stats.global, \
 325                            stats.shared, \
 326                            stats.unbound); \
 327 } while (0)
 328
 329 static void print_batch_pool_stats(struct seq_file *m,
 330                                    struct drm_i915_private *dev_priv)
 331 {
 332         struct drm_i915_gem_object *obj;
 333         struct file_stats stats;
 334         struct intel_engine_cs *engine;
 335         int j;
 336
 337         memset(&stats, 0, sizeof(stats));
 338
 339         for_each_engine(engine, dev_priv) {
 340                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 341                         list_for_each_entry(obj,
 342                                             &engine->batch_pool.cache_list[j],
 343                                             batch_pool_link)
 344                                 per_file_stats(0, obj, &stats);
 345                 }
 346         }
 347
 348         print_file_stats(m, "[k]batch pool", stats);
 349 }
 350
 351 static int per_file_ctx_stats(int id, void *ptr, void *data)
 352 {
 353         struct i915_gem_context *ctx = ptr;
 354         int n;
 355
 356         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 357                 if (ctx->engine[n].state)
 358                         per_file_stats(0, ctx->engine[n].state->obj, data);
 359                 if (ctx->engine[n].ring)
 360                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 361         }
 362
 363         return 0;
 364 }
 365
 366 static void print_context_stats(struct seq_file *m,
 367                                 struct drm_i915_private *dev_priv)
 368 {
 369         struct drm_device *dev = &dev_priv->drm;
 370         struct file_stats stats;
 371         struct drm_file *file;
 372
 373         memset(&stats, 0, sizeof(stats));
 374
 375         mutex_lock(&dev->struct_mutex);
 376         if (dev_priv->kernel_context)
 377                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 378
 379         list_for_each_entry(file, &dev->filelist, lhead) {
 380                 struct drm_i915_file_private *fpriv = file->driver_priv;
 381                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 382         }
 383         mutex_unlock(&dev->struct_mutex);
 384
 385         print_file_stats(m, "[k]contexts", stats);
 386 }
 387
 388 static int i915_gem_object_info(struct seq_file *m, void *data)
 389 {
 390         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 391         struct drm_device *dev = &dev_priv->drm;
 392         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 393         u32 count, mapped_count, purgeable_count, dpy_count;
 394         u64 size, mapped_size, purgeable_size, dpy_size;
 395         struct drm_i915_gem_object *obj;
 396         struct drm_file *file;
 397         int ret;
 398
 399         ret = mutex_lock_interruptible(&dev->struct_mutex);
 400         if (ret)
 401                 return ret;
 402
 403         seq_printf(m, "%u objects, %zu bytes\n",
 404                    dev_priv->mm.object_count,
 405                    dev_priv->mm.object_memory);
 406
 407         size = count = 0;
 408         mapped_size = mapped_count = 0;
 409         purgeable_size = purgeable_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 411                 size += obj->base.size;
 412                 ++count;
 413
 414                 if (obj->madv == I915_MADV_DONTNEED) {
 415                         purgeable_size += obj->base.size;
 416                         ++purgeable_count;
 417                 }
 418
 419                 if (obj->mapping) {
 420                         mapped_count++;
 421                         mapped_size += obj->base.size;
 422                 }
 423         }
 424         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 425
 426         size = count = dpy_size = dpy_count = 0;
 427         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 428                 size += obj->base.size;
 429                 ++count;
 430
 431                 if (obj->pin_display) {
 432                         dpy_size += obj->base.size;
 433                         ++dpy_count;
 434                 }
 435
 436                 if (obj->madv == I915_MADV_DONTNEED) {
 437                         purgeable_size += obj->base.size;
 438                         ++purgeable_count;
 439                 }
 440
 441                 if (obj->mapping) {
 442                         mapped_count++;
 443                         mapped_size += obj->base.size;
 444                 }
 445         }
 446         seq_printf(m, "%u bound objects, %llu bytes\n",
 447                    count, size);
 448         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 449                    purgeable_count, purgeable_size);
 450         seq_printf(m, "%u mapped objects, %llu bytes\n",
 451                    mapped_count, mapped_size);
 452         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 453                    dpy_count, dpy_size);
 454
 455         seq_printf(m, "%llu [%llu] gtt total\n",
 456                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 457
 458         seq_putc(m, '\n');
 459         print_batch_pool_stats(m, dev_priv);
 460         mutex_unlock(&dev->struct_mutex);
 461
 462         mutex_lock(&dev->filelist_mutex);
 463         print_context_stats(m, dev_priv);
 464         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 465                 struct file_stats stats;
 466                 struct drm_i915_file_private *file_priv = file->driver_priv;
 467                 struct drm_i915_gem_request *request;
 468                 struct task_struct *task;
 469
 470                 memset(&stats, 0, sizeof(stats));
 471                 stats.file_priv = file->driver_priv;
 472                 spin_lock(&file->table_lock);
 473                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 474                 spin_unlock(&file->table_lock);
 475                 /*
 476                  * Although we have a valid reference on file->pid, that does
 477                  * not guarantee that the task_struct who called get_pid() is
 478                  * still alive (e.g. get_pid(current) => fork() => exit()).
 479                  * Therefore, we need to protect this ->comm access using RCU.
 480                  */
 481                 mutex_lock(&dev->struct_mutex);
 482                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 483                                                    struct drm_i915_gem_request,
 484                                                    client_list);
 485                 rcu_read_lock();
 486                 task = pid_task(request && request->ctx->pid ?
 487                                 request->ctx->pid : file->pid,
 488                                 PIDTYPE_PID);
 489                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 490                 rcu_read_unlock();
 491                 mutex_unlock(&dev->struct_mutex);
 492         }
 493         mutex_unlock(&dev->filelist_mutex);
 494
 495         return 0;
 496 }
 497
 498 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 499 {
 500         struct drm_info_node *node = m->private;
 501         struct drm_i915_private *dev_priv = node_to_i915(node);
 502         struct drm_device *dev = &dev_priv->drm;
 503         bool show_pin_display_only = !!node->info_ent->data;
 504         struct drm_i915_gem_object *obj;
 505         u64 total_obj_size, total_gtt_size;
 506         int count, ret;
 507
 508         ret = mutex_lock_interruptible(&dev->struct_mutex);
 509         if (ret)
 510                 return ret;
 511
 512         total_obj_size = total_gtt_size = count = 0;
 513         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 514                 if (show_pin_display_only && !obj->pin_display)
 515                         continue;
 516
 517                 seq_puts(m, "   ");
 518                 describe_obj(m, obj);
 519                 seq_putc(m, '\n');
 520                 total_obj_size += obj->base.size;
 521                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 522                 count++;
 523         }
 524
 525         mutex_unlock(&dev->struct_mutex);
 526
 527         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 528                    count, total_obj_size, total_gtt_size);
 529
 530         return 0;
 531 }
 532
 533 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 534 {
 535         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 536         struct drm_device *dev = &dev_priv->drm;
 537         struct intel_crtc *crtc;
 538         int ret;
 539
 540         ret = mutex_lock_interruptible(&dev->struct_mutex);
 541         if (ret)
 542                 return ret;
 543
 544         for_each_intel_crtc(dev, crtc) {
 545                 const char pipe = pipe_name(crtc->pipe);
 546                 const char plane = plane_name(crtc->plane);
 547                 struct intel_flip_work *work;
 548
 549                 spin_lock_irq(&dev->event_lock);
 550                 work = crtc->flip_work;
 551                 if (work == NULL) {
 552                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 553                                    pipe, plane);
 554                 } else {
 555                         u32 pending;
 556                         u32 addr;
 557
 558                         pending = atomic_read(&work->pending);
 559                         if (pending) {
 560                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 561                                            pipe, plane);
 562                         } else {
 563                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 564                                            pipe, plane);
 565                         }
 566                         if (work->flip_queued_req) {
 567                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 568
 569                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 570                                            engine->name,
 571                                            i915_gem_request_get_seqno(work->flip_queued_req),
 572                                            dev_priv->next_seqno,
 573                                            intel_engine_get_seqno(engine),
 574                                            i915_gem_request_completed(work->flip_queued_req));
 575                         } else
 576                                 seq_printf(m, "Flip not associated with any ring\n");
 577                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 578                                    work->flip_queued_vblank,
 579                                    work->flip_ready_vblank,
 580                                    intel_crtc_get_vblank_counter(crtc));
 581                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 582
 583                         if (INTEL_GEN(dev_priv) >= 4)
 584                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 585                         else
 586                                 addr = I915_READ(DSPADDR(crtc->plane));
 587                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 588
 589                         if (work->pending_flip_obj) {
 590                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 591                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 592                         }
 593                 }
 594                 spin_unlock_irq(&dev->event_lock);
 595         }
 596
 597         mutex_unlock(&dev->struct_mutex);
 598
 599         return 0;
 600 }
 601
 602 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 603 {
 604         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 605         struct drm_device *dev = &dev_priv->drm;
 606         struct drm_i915_gem_object *obj;
 607         struct intel_engine_cs *engine;
 608         int total = 0;
 609         int ret, j;
 610
 611         ret = mutex_lock_interruptible(&dev->struct_mutex);
 612         if (ret)
 613                 return ret;
 614
 615         for_each_engine(engine, dev_priv) {
 616                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 617                         int count;
 618
 619                         count = 0;
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link)
 623                                 count++;
 624                         seq_printf(m, "%s cache[%d]: %d objects\n",
 625                                    engine->name, j, count);
 626
 627                         list_for_each_entry(obj,
 628                                             &engine->batch_pool.cache_list[j],
 629                                             batch_pool_link) {
 630                                 seq_puts(m, "   ");
 631                                 describe_obj(m, obj);
 632                                 seq_putc(m, '\n');
 633                         }
 634
 635                         total += count;
 636                 }
 637         }
 638
 639         seq_printf(m, "total: %d\n", total);
 640
 641         mutex_unlock(&dev->struct_mutex);
 642
 643         return 0;
 644 }
 645
 646 static void print_request(struct seq_file *m,
 647                           struct drm_i915_gem_request *rq,
 648                           const char *prefix)
 649 {
 650         struct pid *pid = rq->ctx->pid;
 651         struct task_struct *task;
 652
 653         rcu_read_lock();
 654         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 655         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 656                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 657                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 658                    task ? task->comm : "<unknown>",
 659                    task ? task->pid : -1);
 660         rcu_read_unlock();
 661 }
 662
 663 static int i915_gem_request_info(struct seq_file *m, void *data)
 664 {
 665         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 666         struct drm_device *dev = &dev_priv->drm;
 667         struct intel_engine_cs *engine;
 668         struct drm_i915_gem_request *req;
 669         int ret, any;
 670
 671         ret = mutex_lock_interruptible(&dev->struct_mutex);
 672         if (ret)
 673                 return ret;
 674
 675         any = 0;
 676         for_each_engine(engine, dev_priv) {
 677                 int count;
 678
 679                 count = 0;
 680                 list_for_each_entry(req, &engine->request_list, link)
 681                         count++;
 682                 if (count == 0)
 683                         continue;
 684
 685                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 686                 list_for_each_entry(req, &engine->request_list, link)
 687                         print_request(m, req, "    ");
 688
 689                 any++;
 690         }
 691         mutex_unlock(&dev->struct_mutex);
 692
 693         if (any == 0)
 694                 seq_puts(m, "No requests\n");
 695
 696         return 0;
 697 }
 698
 699 static void i915_ring_seqno_info(struct seq_file *m,
 700                                  struct intel_engine_cs *engine)
 701 {
 702         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 703         struct rb_node *rb;
 704
 705         seq_printf(m, "Current sequence (%s): %x\n",
 706                    engine->name, intel_engine_get_seqno(engine));
 707
 708         spin_lock(&b->lock);
 709         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 710                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 711
 712                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 713                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 714         }
 715         spin_unlock(&b->lock);
 716 }
 717
 718 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 719 {
 720         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 721         struct intel_engine_cs *engine;
 722
 723         for_each_engine(engine, dev_priv)
 724                 i915_ring_seqno_info(m, engine);
 725
 726         return 0;
 727 }
 728
 729
 730 static int i915_interrupt_info(struct seq_file *m, void *data)
 731 {
 732         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 733         struct intel_engine_cs *engine;
 734         int i, pipe;
 735
 736         intel_runtime_pm_get(dev_priv);
 737
 738         if (IS_CHERRYVIEW(dev_priv)) {
 739                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 740                            I915_READ(GEN8_MASTER_IRQ));
 741
 742                 seq_printf(m, "Display IER:\t%08x\n",
 743                            I915_READ(VLV_IER));
 744                 seq_printf(m, "Display IIR:\t%08x\n",
 745                            I915_READ(VLV_IIR));
 746                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 747                            I915_READ(VLV_IIR_RW));
 748                 seq_printf(m, "Display IMR:\t%08x\n",
 749                            I915_READ(VLV_IMR));
 750                 for_each_pipe(dev_priv, pipe)
 751                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 752                                    pipe_name(pipe),
 753                                    I915_READ(PIPESTAT(pipe)));
 754
 755                 seq_printf(m, "Port hotplug:\t%08x\n",
 756                            I915_READ(PORT_HOTPLUG_EN));
 757                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 758                            I915_READ(VLV_DPFLIPSTAT));
 759                 seq_printf(m, "DPINVGTT:\t%08x\n",
 760                            I915_READ(DPINVGTT));
 761
 762                 for (i = 0; i < 4; i++) {
 763                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 764                                    i, I915_READ(GEN8_GT_IMR(i)));
 765                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IIR(i)));
 767                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IER(i)));
 769                 }
 770
 771                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 772                            I915_READ(GEN8_PCU_IMR));
 773                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 774                            I915_READ(GEN8_PCU_IIR));
 775                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 776                            I915_READ(GEN8_PCU_IER));
 777         } else if (INTEL_GEN(dev_priv) >= 8) {
 778                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 779                            I915_READ(GEN8_MASTER_IRQ));
 780
 781                 for (i = 0; i < 4; i++) {
 782                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 783                                    i, I915_READ(GEN8_GT_IMR(i)));
 784                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 785                                    i, I915_READ(GEN8_GT_IIR(i)));
 786                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 787                                    i, I915_READ(GEN8_GT_IER(i)));
 788                 }
 789
 790                 for_each_pipe(dev_priv, pipe) {
 791                         enum intel_display_power_domain power_domain;
 792
 793                         power_domain = POWER_DOMAIN_PIPE(pipe);
 794                         if (!intel_display_power_get_if_enabled(dev_priv,
 795                                                                 power_domain)) {
 796                                 seq_printf(m, "Pipe %c power disabled\n",
 797                                            pipe_name(pipe));
 798                                 continue;
 799                         }
 800                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 801                                    pipe_name(pipe),
 802                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 803                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 804                                    pipe_name(pipe),
 805                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 806                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 807                                    pipe_name(pipe),
 808                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 809
 810                         intel_display_power_put(dev_priv, power_domain);
 811                 }
 812
 813                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 814                            I915_READ(GEN8_DE_PORT_IMR));
 815                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 816                            I915_READ(GEN8_DE_PORT_IIR));
 817                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 818                            I915_READ(GEN8_DE_PORT_IER));
 819
 820                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 821                            I915_READ(GEN8_DE_MISC_IMR));
 822                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 823                            I915_READ(GEN8_DE_MISC_IIR));
 824                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 825                            I915_READ(GEN8_DE_MISC_IER));
 826
 827                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 828                            I915_READ(GEN8_PCU_IMR));
 829                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 830                            I915_READ(GEN8_PCU_IIR));
 831                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 832                            I915_READ(GEN8_PCU_IER));
 833         } else if (IS_VALLEYVIEW(dev_priv)) {
 834                 seq_printf(m, "Display IER:\t%08x\n",
 835                            I915_READ(VLV_IER));
 836                 seq_printf(m, "Display IIR:\t%08x\n",
 837                            I915_READ(VLV_IIR));
 838                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 839                            I915_READ(VLV_IIR_RW));
 840                 seq_printf(m, "Display IMR:\t%08x\n",
 841                            I915_READ(VLV_IMR));
 842                 for_each_pipe(dev_priv, pipe)
 843                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 844                                    pipe_name(pipe),
 845                                    I915_READ(PIPESTAT(pipe)));
 846
 847                 seq_printf(m, "Master IER:\t%08x\n",
 848                            I915_READ(VLV_MASTER_IER));
 849
 850                 seq_printf(m, "Render IER:\t%08x\n",
 851                            I915_READ(GTIER));
 852                 seq_printf(m, "Render IIR:\t%08x\n",
 853                            I915_READ(GTIIR));
 854                 seq_printf(m, "Render IMR:\t%08x\n",
 855                            I915_READ(GTIMR));
 856
 857                 seq_printf(m, "PM IER:\t\t%08x\n",
 858                            I915_READ(GEN6_PMIER));
 859                 seq_printf(m, "PM IIR:\t\t%08x\n",
 860                            I915_READ(GEN6_PMIIR));
 861                 seq_printf(m, "PM IMR:\t\t%08x\n",
 862                            I915_READ(GEN6_PMIMR));
 863
 864                 seq_printf(m, "Port hotplug:\t%08x\n",
 865                            I915_READ(PORT_HOTPLUG_EN));
 866                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 867                            I915_READ(VLV_DPFLIPSTAT));
 868                 seq_printf(m, "DPINVGTT:\t%08x\n",
 869                            I915_READ(DPINVGTT));
 870
 871         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 872                 seq_printf(m, "Interrupt enable:    %08x\n",
 873                            I915_READ(IER));
 874                 seq_printf(m, "Interrupt identity:  %08x\n",
 875                            I915_READ(IIR));
 876                 seq_printf(m, "Interrupt mask:      %08x\n",
 877                            I915_READ(IMR));
 878                 for_each_pipe(dev_priv, pipe)
 879                         seq_printf(m, "Pipe %c stat:         %08x\n",
 880                                    pipe_name(pipe),
 881                                    I915_READ(PIPESTAT(pipe)));
 882         } else {
 883                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 884                            I915_READ(DEIER));
 885                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 886                            I915_READ(DEIIR));
 887                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 888                            I915_READ(DEIMR));
 889                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 890                            I915_READ(SDEIER));
 891                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 892                            I915_READ(SDEIIR));
 893                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 894                            I915_READ(SDEIMR));
 895                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 896                            I915_READ(GTIER));
 897                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 898                            I915_READ(GTIIR));
 899                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 900                            I915_READ(GTIMR));
 901         }
 902         for_each_engine(engine, dev_priv) {
 903                 if (INTEL_GEN(dev_priv) >= 6) {
 904                         seq_printf(m,
 905                                    "Graphics Interrupt mask (%s):       %08x\n",
 906                                    engine->name, I915_READ_IMR(engine));
 907                 }
 908                 i915_ring_seqno_info(m, engine);
 909         }
 910         intel_runtime_pm_put(dev_priv);
 911
 912         return 0;
 913 }
 914
 915 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 916 {
 917         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 918         struct drm_device *dev = &dev_priv->drm;
 919         int i, ret;
 920
 921         ret = mutex_lock_interruptible(&dev->struct_mutex);
 922         if (ret)
 923                 return ret;
 924
 925         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 926         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 927                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 928
 929                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 930                            i, dev_priv->fence_regs[i].pin_count);
 931                 if (!vma)
 932                         seq_puts(m, "unused");
 933                 else
 934                         describe_obj(m, vma->obj);
 935                 seq_putc(m, '\n');
 936         }
 937
 938         mutex_unlock(&dev->struct_mutex);
 939         return 0;
 940 }
 941
 942 static int i915_hws_info(struct seq_file *m, void *data)
 943 {
 944         struct drm_info_node *node = m->private;
 945         struct drm_i915_private *dev_priv = node_to_i915(node);
 946         struct intel_engine_cs *engine;
 947         const u32 *hws;
 948         int i;
 949
 950         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 951         hws = engine->status_page.page_addr;
 952         if (hws == NULL)
 953                 return 0;
 954
 955         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 956                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 957                            i * 4,
 958                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 959         }
 960         return 0;
 961 }
 962
 963 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 964
 965 static ssize_t
 966 i915_error_state_write(struct file *filp,
 967                        const char __user *ubuf,
 968                        size_t cnt,
 969                        loff_t *ppos)
 970 {
 971         struct i915_error_state_file_priv *error_priv = filp->private_data;
 972
 973         DRM_DEBUG_DRIVER("Resetting error state\n");
 974         i915_destroy_error_state(error_priv->dev);
 975
 976         return cnt;
 977 }
 978
 979 static int i915_error_state_open(struct inode *inode, struct file *file)
 980 {
 981         struct drm_i915_private *dev_priv = inode->i_private;
 982         struct i915_error_state_file_priv *error_priv;
 983
 984         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 985         if (!error_priv)
 986                 return -ENOMEM;
 987
 988         error_priv->dev = &dev_priv->drm;
 989
 990         i915_error_state_get(&dev_priv->drm, error_priv);
 991
 992         file->private_data = error_priv;
 993
 994         return 0;
 995 }
 996
 997 static int i915_error_state_release(struct inode *inode, struct file *file)
 998 {
 999         struct i915_error_state_file_priv *error_priv = file->private_data;
1000
1001         i915_error_state_put(error_priv);
1002         kfree(error_priv);
1003
1004         return 0;
1005 }
1006
1007 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1008                                      size_t count, loff_t *pos)
1009 {
1010         struct i915_error_state_file_priv *error_priv = file->private_data;
1011         struct drm_i915_error_state_buf error_str;
1012         loff_t tmp_pos = 0;
1013         ssize_t ret_count = 0;
1014         int ret;
1015
1016         ret = i915_error_state_buf_init(&error_str,
1017                                         to_i915(error_priv->dev), count, *pos);
1018         if (ret)
1019                 return ret;
1020
1021         ret = i915_error_state_to_str(&error_str, error_priv);
1022         if (ret)
1023                 goto out;
1024
1025         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1026                                             error_str.buf,
1027                                             error_str.bytes);
1028
1029         if (ret_count < 0)
1030                 ret = ret_count;
1031         else
1032                 *pos = error_str.start + ret_count;
1033 out:
1034         i915_error_state_buf_release(&error_str);
1035         return ret ?: ret_count;
1036 }
1037
1038 static const struct file_operations i915_error_state_fops = {
1039         .owner = THIS_MODULE,
1040         .open = i915_error_state_open,
1041         .read = i915_error_state_read,
1042         .write = i915_error_state_write,
1043         .llseek = default_llseek,
1044         .release = i915_error_state_release,
1045 };
1046
1047 #endif
1048
1049 static int
1050 i915_next_seqno_get(void *data, u64 *val)
1051 {
1052         struct drm_i915_private *dev_priv = data;
1053         int ret;
1054
1055         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1056         if (ret)
1057                 return ret;
1058
1059         *val = dev_priv->next_seqno;
1060         mutex_unlock(&dev_priv->drm.struct_mutex);
1061
1062         return 0;
1063 }
1064
1065 static int
1066 i915_next_seqno_set(void *data, u64 val)
1067 {
1068         struct drm_i915_private *dev_priv = data;
1069         struct drm_device *dev = &dev_priv->drm;
1070         int ret;
1071
1072         ret = mutex_lock_interruptible(&dev->struct_mutex);
1073         if (ret)
1074                 return ret;
1075
1076         ret = i915_gem_set_seqno(dev, val);
1077         mutex_unlock(&dev->struct_mutex);
1078
1079         return ret;
1080 }
1081
1082 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1083                         i915_next_seqno_get, i915_next_seqno_set,
1084                         "0x%llx\n");
1085
1086 static int i915_frequency_info(struct seq_file *m, void *unused)
1087 {
1088         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1089         struct drm_device *dev = &dev_priv->drm;
1090         int ret = 0;
1091
1092         intel_runtime_pm_get(dev_priv);
1093
1094         if (IS_GEN5(dev_priv)) {
1095                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1096                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1097
1098                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1099                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1100                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1101                            MEMSTAT_VID_SHIFT);
1102                 seq_printf(m, "Current P-state: %d\n",
1103                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1104         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1105                 u32 freq_sts;
1106
1107                 mutex_lock(&dev_priv->rps.hw_lock);
1108                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1109                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1110                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1111
1112                 seq_printf(m, "actual GPU freq: %d MHz\n",
1113                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1114
1115                 seq_printf(m, "current GPU freq: %d MHz\n",
1116                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1117
1118                 seq_printf(m, "max GPU freq: %d MHz\n",
1119                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1120
1121                 seq_printf(m, "min GPU freq: %d MHz\n",
1122                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1123
1124                 seq_printf(m, "idle GPU freq: %d MHz\n",
1125                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1126
1127                 seq_printf(m,
1128                            "efficient (RPe) frequency: %d MHz\n",
1129                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1130                 mutex_unlock(&dev_priv->rps.hw_lock);
1131         } else if (INTEL_GEN(dev_priv) >= 6) {
1132                 u32 rp_state_limits;
1133                 u32 gt_perf_status;
1134                 u32 rp_state_cap;
1135                 u32 rpmodectl, rpinclimit, rpdeclimit;
1136                 u32 rpstat, cagf, reqf;
1137                 u32 rpupei, rpcurup, rpprevup;
1138                 u32 rpdownei, rpcurdown, rpprevdown;
1139                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1140                 int max_freq;
1141
1142                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1143                 if (IS_BROXTON(dev_priv)) {
1144                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1145                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1146                 } else {
1147                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1148                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1149                 }
1150
1151                 /* RPSTAT1 is in the GT power well */
1152                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1153                 if (ret)
1154                         goto out;
1155
1156                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1157
1158                 reqf = I915_READ(GEN6_RPNSWREQ);
1159                 if (IS_GEN9(dev_priv))
1160                         reqf >>= 23;
1161                 else {
1162                         reqf &= ~GEN6_TURBO_DISABLE;
1163                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1164                                 reqf >>= 24;
1165                         else
1166                                 reqf >>= 25;
1167                 }
1168                 reqf = intel_gpu_freq(dev_priv, reqf);
1169
1170                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1171                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1172                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1173
1174                 rpstat = I915_READ(GEN6_RPSTAT1);
1175                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1176                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1177                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1178                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1179                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1180                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1181                 if (IS_GEN9(dev_priv))
1182                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1183                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1184                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1185                 else
1186                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1187                 cagf = intel_gpu_freq(dev_priv, cagf);
1188
1189                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1190                 mutex_unlock(&dev->struct_mutex);
1191
1192                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1193                         pm_ier = I915_READ(GEN6_PMIER);
1194                         pm_imr = I915_READ(GEN6_PMIMR);
1195                         pm_isr = I915_READ(GEN6_PMISR);
1196                         pm_iir = I915_READ(GEN6_PMIIR);
1197                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1198                 } else {
1199                         pm_ier = I915_READ(GEN8_GT_IER(2));
1200                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1201                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1202                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1203                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1204                 }
1205                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1206                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1207                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1208                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1209                 seq_printf(m, "Render p-state ratio: %d\n",
1210                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1211                 seq_printf(m, "Render p-state VID: %d\n",
1212                            gt_perf_status & 0xff);
1213                 seq_printf(m, "Render p-state limit: %d\n",
1214                            rp_state_limits & 0xff);
1215                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1216                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1217                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1218                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1219                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1220                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1221                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1222                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1223                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1224                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1225                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1226                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1227                 seq_printf(m, "Up threshold: %d%%\n",
1228                            dev_priv->rps.up_threshold);
1229
1230                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1231                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1232                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1233                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1234                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1235                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1236                 seq_printf(m, "Down threshold: %d%%\n",
1237                            dev_priv->rps.down_threshold);
1238
1239                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1240                             rp_state_cap >> 16) & 0xff;
1241                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1242                              GEN9_FREQ_SCALER : 1);
1243                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1244                            intel_gpu_freq(dev_priv, max_freq));
1245
1246                 max_freq = (rp_state_cap & 0xff00) >> 8;
1247                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1248                              GEN9_FREQ_SCALER : 1);
1249                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1250                            intel_gpu_freq(dev_priv, max_freq));
1251
1252                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1253                             rp_state_cap >> 0) & 0xff;
1254                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1255                              GEN9_FREQ_SCALER : 1);
1256                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1257                            intel_gpu_freq(dev_priv, max_freq));
1258                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1260
1261                 seq_printf(m, "Current freq: %d MHz\n",
1262                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1263                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1264                 seq_printf(m, "Idle freq: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1266                 seq_printf(m, "Min freq: %d MHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1268                 seq_printf(m, "Boost freq: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1270                 seq_printf(m, "Max freq: %d MHz\n",
1271                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1272                 seq_printf(m,
1273                            "efficient (RPe) frequency: %d MHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1275         } else {
1276                 seq_puts(m, "no P-state info available\n");
1277         }
1278
1279         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1280         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1281         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1282
1283 out:
1284         intel_runtime_pm_put(dev_priv);
1285         return ret;
1286 }
1287
1288 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1289                                struct seq_file *m,
1290                                struct intel_instdone *instdone)
1291 {
1292         int slice;
1293         int subslice;
1294
1295         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1296                    instdone->instdone);
1297
1298         if (INTEL_GEN(dev_priv) <= 3)
1299                 return;
1300
1301         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1302                    instdone->slice_common);
1303
1304         if (INTEL_GEN(dev_priv) <= 6)
1305                 return;
1306
1307         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1308                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1309                            slice, subslice, instdone->sampler[slice][subslice]);
1310
1311         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1312                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1313                            slice, subslice, instdone->row[slice][subslice]);
1314 }
1315
1316 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1317 {
1318         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1319         struct intel_engine_cs *engine;
1320         u64 acthd[I915_NUM_ENGINES];
1321         u32 seqno[I915_NUM_ENGINES];
1322         struct intel_instdone instdone;
1323         enum intel_engine_id id;
1324
1325         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1326                 seq_printf(m, "Wedged\n");
1327         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1328                 seq_printf(m, "Reset in progress\n");
1329         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1330                 seq_printf(m, "Waiter holding struct mutex\n");
1331         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1332                 seq_printf(m, "struct_mutex blocked for reset\n");
1333
1334         if (!i915.enable_hangcheck) {
1335                 seq_printf(m, "Hangcheck disabled\n");
1336                 return 0;
1337         }
1338
1339         intel_runtime_pm_get(dev_priv);
1340
1341         for_each_engine_id(engine, dev_priv, id) {
1342                 acthd[id] = intel_engine_get_active_head(engine);
1343                 seqno[id] = intel_engine_get_seqno(engine);
1344         }
1345
1346         intel_engine_get_instdone(&dev_priv->engine[RCS], &instdone);
1347
1348         intel_runtime_pm_put(dev_priv);
1349
1350         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1351                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1352                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1353                                             jiffies));
1354         } else
1355                 seq_printf(m, "Hangcheck inactive\n");
1356
1357         for_each_engine_id(engine, dev_priv, id) {
1358                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1359                 struct rb_node *rb;
1360
1361                 seq_printf(m, "%s:\n", engine->name);
1362                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1363                            engine->hangcheck.seqno,
1364                            seqno[id],
1365                            engine->last_submitted_seqno);
1366                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1367                            yesno(intel_engine_has_waiter(engine)),
1368                            yesno(test_bit(engine->id,
1369                                           &dev_priv->gpu_error.missed_irq_rings)));
1370                 spin_lock(&b->lock);
1371                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1372                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1373
1374                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1375                                    w->tsk->comm, w->tsk->pid, w->seqno);
1376                 }
1377                 spin_unlock(&b->lock);
1378
1379                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1380                            (long long)engine->hangcheck.acthd,
1381                            (long long)acthd[id]);
1382                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1383                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1384
1385                 if (engine->id == RCS) {
1386                         seq_puts(m, "\tinstdone read =\n");
1387
1388                         i915_instdone_info(dev_priv, m, &instdone);
1389
1390                         seq_puts(m, "\tinstdone accu =\n");
1391
1392                         i915_instdone_info(dev_priv, m,
1393                                            &engine->hangcheck.instdone);
1394                 }
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ironlake_drpc_info(struct seq_file *m)
1401 {
1402         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1403         struct drm_device *dev = &dev_priv->drm;
1404         u32 rgvmodectl, rstdbyctl;
1405         u16 crstandvid;
1406         int ret;
1407
1408         ret = mutex_lock_interruptible(&dev->struct_mutex);
1409         if (ret)
1410                 return ret;
1411         intel_runtime_pm_get(dev_priv);
1412
1413         rgvmodectl = I915_READ(MEMMODECTL);
1414         rstdbyctl = I915_READ(RSTDBYCTL);
1415         crstandvid = I915_READ16(CRSTANDVID);
1416
1417         intel_runtime_pm_put(dev_priv);
1418         mutex_unlock(&dev->struct_mutex);
1419
1420         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1421         seq_printf(m, "Boost freq: %d\n",
1422                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1423                    MEMMODE_BOOST_FREQ_SHIFT);
1424         seq_printf(m, "HW control enabled: %s\n",
1425                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1426         seq_printf(m, "SW control enabled: %s\n",
1427                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1428         seq_printf(m, "Gated voltage change: %s\n",
1429                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1430         seq_printf(m, "Starting frequency: P%d\n",
1431                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1432         seq_printf(m, "Max P-state: P%d\n",
1433                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1434         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1435         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1436         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1437         seq_printf(m, "Render standby enabled: %s\n",
1438                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1439         seq_puts(m, "Current RS state: ");
1440         switch (rstdbyctl & RSX_STATUS_MASK) {
1441         case RSX_STATUS_ON:
1442                 seq_puts(m, "on\n");
1443                 break;
1444         case RSX_STATUS_RC1:
1445                 seq_puts(m, "RC1\n");
1446                 break;
1447         case RSX_STATUS_RC1E:
1448                 seq_puts(m, "RC1E\n");
1449                 break;
1450         case RSX_STATUS_RS1:
1451                 seq_puts(m, "RS1\n");
1452                 break;
1453         case RSX_STATUS_RS2:
1454                 seq_puts(m, "RS2 (RC6)\n");
1455                 break;
1456         case RSX_STATUS_RS3:
1457                 seq_puts(m, "RC3 (RC6+)\n");
1458                 break;
1459         default:
1460                 seq_puts(m, "unknown\n");
1461                 break;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int i915_forcewake_domains(struct seq_file *m, void *data)
1468 {
1469         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1470         struct intel_uncore_forcewake_domain *fw_domain;
1471
1472         spin_lock_irq(&dev_priv->uncore.lock);
1473         for_each_fw_domain(fw_domain, dev_priv) {
1474                 seq_printf(m, "%s.wake_count = %u\n",
1475                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1476                            fw_domain->wake_count);
1477         }
1478         spin_unlock_irq(&dev_priv->uncore.lock);
1479
1480         return 0;
1481 }
1482
1483 static int vlv_drpc_info(struct seq_file *m)
1484 {
1485         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1486         u32 rpmodectl1, rcctl1, pw_status;
1487
1488         intel_runtime_pm_get(dev_priv);
1489
1490         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1491         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1492         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1493
1494         intel_runtime_pm_put(dev_priv);
1495
1496         seq_printf(m, "Video Turbo Mode: %s\n",
1497                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1498         seq_printf(m, "Turbo enabled: %s\n",
1499                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500         seq_printf(m, "HW control enabled: %s\n",
1501                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1502         seq_printf(m, "SW control enabled: %s\n",
1503                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1504                           GEN6_RP_MEDIA_SW_MODE));
1505         seq_printf(m, "RC6 Enabled: %s\n",
1506                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1507                                         GEN6_RC_CTL_EI_MODE(1))));
1508         seq_printf(m, "Render Power Well: %s\n",
1509                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1510         seq_printf(m, "Media Power Well: %s\n",
1511                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1512
1513         seq_printf(m, "Render RC6 residency since boot: %u\n",
1514                    I915_READ(VLV_GT_RENDER_RC6));
1515         seq_printf(m, "Media RC6 residency since boot: %u\n",
1516                    I915_READ(VLV_GT_MEDIA_RC6));
1517
1518         return i915_forcewake_domains(m, NULL);
1519 }
1520
1521 static int gen6_drpc_info(struct seq_file *m)
1522 {
1523         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1524         struct drm_device *dev = &dev_priv->drm;
1525         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1526         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1527         unsigned forcewake_count;
1528         int count = 0, ret;
1529
1530         ret = mutex_lock_interruptible(&dev->struct_mutex);
1531         if (ret)
1532                 return ret;
1533         intel_runtime_pm_get(dev_priv);
1534
1535         spin_lock_irq(&dev_priv->uncore.lock);
1536         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1537         spin_unlock_irq(&dev_priv->uncore.lock);
1538
1539         if (forcewake_count) {
1540                 seq_puts(m, "RC information inaccurate because somebody "
1541                             "holds a forcewake reference \n");
1542         } else {
1543                 /* NB: we cannot use forcewake, else we read the wrong values */
1544                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1545                         udelay(10);
1546                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1547         }
1548
1549         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1550         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1551
1552         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1553         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1554         if (INTEL_GEN(dev_priv) >= 9) {
1555                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1556                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1557         }
1558         mutex_unlock(&dev->struct_mutex);
1559         mutex_lock(&dev_priv->rps.hw_lock);
1560         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1561         mutex_unlock(&dev_priv->rps.hw_lock);
1562
1563         intel_runtime_pm_put(dev_priv);
1564
1565         seq_printf(m, "Video Turbo Mode: %s\n",
1566                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1567         seq_printf(m, "HW control enabled: %s\n",
1568                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1569         seq_printf(m, "SW control enabled: %s\n",
1570                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1571                           GEN6_RP_MEDIA_SW_MODE));
1572         seq_printf(m, "RC1e Enabled: %s\n",
1573                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1574         seq_printf(m, "RC6 Enabled: %s\n",
1575                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1576         if (INTEL_GEN(dev_priv) >= 9) {
1577                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1578                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1579                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1580                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1581         }
1582         seq_printf(m, "Deep RC6 Enabled: %s\n",
1583                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1584         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1585                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1586         seq_puts(m, "Current RC state: ");
1587         switch (gt_core_status & GEN6_RCn_MASK) {
1588         case GEN6_RC0:
1589                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1590                         seq_puts(m, "Core Power Down\n");
1591                 else
1592                         seq_puts(m, "on\n");
1593                 break;
1594         case GEN6_RC3:
1595                 seq_puts(m, "RC3\n");
1596                 break;
1597         case GEN6_RC6:
1598                 seq_puts(m, "RC6\n");
1599                 break;
1600         case GEN6_RC7:
1601                 seq_puts(m, "RC7\n");
1602                 break;
1603         default:
1604                 seq_puts(m, "Unknown\n");
1605                 break;
1606         }
1607
1608         seq_printf(m, "Core Power Down: %s\n",
1609                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1610         if (INTEL_GEN(dev_priv) >= 9) {
1611                 seq_printf(m, "Render Power Well: %s\n",
1612                         (gen9_powergate_status &
1613                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1614                 seq_printf(m, "Media Power Well: %s\n",
1615                         (gen9_powergate_status &
1616                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1617         }
1618
1619         /* Not exactly sure what this is */
1620         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1621                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1622         seq_printf(m, "RC6 residency since boot: %u\n",
1623                    I915_READ(GEN6_GT_GFX_RC6));
1624         seq_printf(m, "RC6+ residency since boot: %u\n",
1625                    I915_READ(GEN6_GT_GFX_RC6p));
1626         seq_printf(m, "RC6++ residency since boot: %u\n",
1627                    I915_READ(GEN6_GT_GFX_RC6pp));
1628
1629         seq_printf(m, "RC6   voltage: %dmV\n",
1630                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1631         seq_printf(m, "RC6+  voltage: %dmV\n",
1632                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1633         seq_printf(m, "RC6++ voltage: %dmV\n",
1634                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1635         return i915_forcewake_domains(m, NULL);
1636 }
1637
1638 static int i915_drpc_info(struct seq_file *m, void *unused)
1639 {
1640         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1641
1642         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1643                 return vlv_drpc_info(m);
1644         else if (INTEL_GEN(dev_priv) >= 6)
1645                 return gen6_drpc_info(m);
1646         else
1647                 return ironlake_drpc_info(m);
1648 }
1649
1650 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1651 {
1652         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1653
1654         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1655                    dev_priv->fb_tracking.busy_bits);
1656
1657         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1658                    dev_priv->fb_tracking.flip_bits);
1659
1660         return 0;
1661 }
1662
1663 static int i915_fbc_status(struct seq_file *m, void *unused)
1664 {
1665         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1666
1667         if (!HAS_FBC(dev_priv)) {
1668                 seq_puts(m, "FBC unsupported on this chipset\n");
1669                 return 0;
1670         }
1671
1672         intel_runtime_pm_get(dev_priv);
1673         mutex_lock(&dev_priv->fbc.lock);
1674
1675         if (intel_fbc_is_active(dev_priv))
1676                 seq_puts(m, "FBC enabled\n");
1677         else
1678                 seq_printf(m, "FBC disabled: %s\n",
1679                            dev_priv->fbc.no_fbc_reason);
1680
1681         if (intel_fbc_is_active(dev_priv) &&
1682             INTEL_GEN(dev_priv) >= 7)
1683                 seq_printf(m, "Compressing: %s\n",
1684                            yesno(I915_READ(FBC_STATUS2) &
1685                                  FBC_COMPRESSION_MASK));
1686
1687         mutex_unlock(&dev_priv->fbc.lock);
1688         intel_runtime_pm_put(dev_priv);
1689
1690         return 0;
1691 }
1692
1693 static int i915_fbc_fc_get(void *data, u64 *val)
1694 {
1695         struct drm_i915_private *dev_priv = data;
1696
1697         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1698                 return -ENODEV;
1699
1700         *val = dev_priv->fbc.false_color;
1701
1702         return 0;
1703 }
1704
1705 static int i915_fbc_fc_set(void *data, u64 val)
1706 {
1707         struct drm_i915_private *dev_priv = data;
1708         u32 reg;
1709
1710         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1711                 return -ENODEV;
1712
1713         mutex_lock(&dev_priv->fbc.lock);
1714
1715         reg = I915_READ(ILK_DPFC_CONTROL);
1716         dev_priv->fbc.false_color = val;
1717
1718         I915_WRITE(ILK_DPFC_CONTROL, val ?
1719                    (reg | FBC_CTL_FALSE_COLOR) :
1720                    (reg & ~FBC_CTL_FALSE_COLOR));
1721
1722         mutex_unlock(&dev_priv->fbc.lock);
1723         return 0;
1724 }
1725
1726 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1727                         i915_fbc_fc_get, i915_fbc_fc_set,
1728                         "%llu\n");
1729
1730 static int i915_ips_status(struct seq_file *m, void *unused)
1731 {
1732         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1733
1734         if (!HAS_IPS(dev_priv)) {
1735                 seq_puts(m, "not supported\n");
1736                 return 0;
1737         }
1738
1739         intel_runtime_pm_get(dev_priv);
1740
1741         seq_printf(m, "Enabled by kernel parameter: %s\n",
1742                    yesno(i915.enable_ips));
1743
1744         if (INTEL_GEN(dev_priv) >= 8) {
1745                 seq_puts(m, "Currently: unknown\n");
1746         } else {
1747                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1748                         seq_puts(m, "Currently: enabled\n");
1749                 else
1750                         seq_puts(m, "Currently: disabled\n");
1751         }
1752
1753         intel_runtime_pm_put(dev_priv);
1754
1755         return 0;
1756 }
1757
1758 static int i915_sr_status(struct seq_file *m, void *unused)
1759 {
1760         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1761         bool sr_enabled = false;
1762
1763         intel_runtime_pm_get(dev_priv);
1764
1765         if (HAS_PCH_SPLIT(dev_priv))
1766                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1767         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1768                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1769                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1770         else if (IS_I915GM(dev_priv))
1771                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1772         else if (IS_PINEVIEW(dev_priv))
1773                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1774         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1775                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1776
1777         intel_runtime_pm_put(dev_priv);
1778
1779         seq_printf(m, "self-refresh: %s\n",
1780                    sr_enabled ? "enabled" : "disabled");
1781
1782         return 0;
1783 }
1784
1785 static int i915_emon_status(struct seq_file *m, void *unused)
1786 {
1787         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1788         struct drm_device *dev = &dev_priv->drm;
1789         unsigned long temp, chipset, gfx;
1790         int ret;
1791
1792         if (!IS_GEN5(dev_priv))
1793                 return -ENODEV;
1794
1795         ret = mutex_lock_interruptible(&dev->struct_mutex);
1796         if (ret)
1797                 return ret;
1798
1799         temp = i915_mch_val(dev_priv);
1800         chipset = i915_chipset_val(dev_priv);
1801         gfx = i915_gfx_val(dev_priv);
1802         mutex_unlock(&dev->struct_mutex);
1803
1804         seq_printf(m, "GMCH temp: %ld\n", temp);
1805         seq_printf(m, "Chipset power: %ld\n", chipset);
1806         seq_printf(m, "GFX power: %ld\n", gfx);
1807         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1808
1809         return 0;
1810 }
1811
1812 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1813 {
1814         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1815         int ret = 0;
1816         int gpu_freq, ia_freq;
1817         unsigned int max_gpu_freq, min_gpu_freq;
1818
1819         if (!HAS_LLC(dev_priv)) {
1820                 seq_puts(m, "unsupported on this chipset\n");
1821                 return 0;
1822         }
1823
1824         intel_runtime_pm_get(dev_priv);
1825
1826         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1827         if (ret)
1828                 goto out;
1829
1830         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1831                 /* Convert GT frequency to 50 HZ units */
1832                 min_gpu_freq =
1833                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1834                 max_gpu_freq =
1835                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1836         } else {
1837                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1838                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1839         }
1840
1841         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1842
1843         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1844                 ia_freq = gpu_freq;
1845                 sandybridge_pcode_read(dev_priv,
1846                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1847                                        &ia_freq);
1848                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1849                            intel_gpu_freq(dev_priv, (gpu_freq *
1850                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1851                                  GEN9_FREQ_SCALER : 1))),
1852                            ((ia_freq >> 0) & 0xff) * 100,
1853                            ((ia_freq >> 8) & 0xff) * 100);
1854         }
1855
1856         mutex_unlock(&dev_priv->rps.hw_lock);
1857
1858 out:
1859         intel_runtime_pm_put(dev_priv);
1860         return ret;
1861 }
1862
1863 static int i915_opregion(struct seq_file *m, void *unused)
1864 {
1865         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1866         struct drm_device *dev = &dev_priv->drm;
1867         struct intel_opregion *opregion = &dev_priv->opregion;
1868         int ret;
1869
1870         ret = mutex_lock_interruptible(&dev->struct_mutex);
1871         if (ret)
1872                 goto out;
1873
1874         if (opregion->header)
1875                 seq_write(m, opregion->header, OPREGION_SIZE);
1876
1877         mutex_unlock(&dev->struct_mutex);
1878
1879 out:
1880         return 0;
1881 }
1882
1883 static int i915_vbt(struct seq_file *m, void *unused)
1884 {
1885         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1886
1887         if (opregion->vbt)
1888                 seq_write(m, opregion->vbt, opregion->vbt_size);
1889
1890         return 0;
1891 }
1892
1893 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894 {
1895         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1896         struct drm_device *dev = &dev_priv->drm;
1897         struct intel_framebuffer *fbdev_fb = NULL;
1898         struct drm_framebuffer *drm_fb;
1899         int ret;
1900
1901         ret = mutex_lock_interruptible(&dev->struct_mutex);
1902         if (ret)
1903                 return ret;
1904
1905 #ifdef CONFIG_DRM_FBDEV_EMULATION
1906         if (dev_priv->fbdev) {
1907                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1908
1909                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910                            fbdev_fb->base.width,
1911                            fbdev_fb->base.height,
1912                            fbdev_fb->base.depth,
1913                            fbdev_fb->base.bits_per_pixel,
1914                            fbdev_fb->base.modifier[0],
1915                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1916                 describe_obj(m, fbdev_fb->obj);
1917                 seq_putc(m, '\n');
1918         }
1919 #endif
1920
1921         mutex_lock(&dev->mode_config.fb_lock);
1922         drm_for_each_fb(drm_fb, dev) {
1923                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1924                 if (fb == fbdev_fb)
1925                         continue;
1926
1927                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1928                            fb->base.width,
1929                            fb->base.height,
1930                            fb->base.depth,
1931                            fb->base.bits_per_pixel,
1932                            fb->base.modifier[0],
1933                            drm_framebuffer_read_refcount(&fb->base));
1934                 describe_obj(m, fb->obj);
1935                 seq_putc(m, '\n');
1936         }
1937         mutex_unlock(&dev->mode_config.fb_lock);
1938         mutex_unlock(&dev->struct_mutex);
1939
1940         return 0;
1941 }
1942
1943 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1944 {
1945         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1946                    ring->space, ring->head, ring->tail,
1947                    ring->last_retired_head);
1948 }
1949
1950 static int i915_context_status(struct seq_file *m, void *unused)
1951 {
1952         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1953         struct drm_device *dev = &dev_priv->drm;
1954         struct intel_engine_cs *engine;
1955         struct i915_gem_context *ctx;
1956         int ret;
1957
1958         ret = mutex_lock_interruptible(&dev->struct_mutex);
1959         if (ret)
1960                 return ret;
1961
1962         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1963                 seq_printf(m, "HW context %u ", ctx->hw_id);
1964                 if (ctx->pid) {
1965                         struct task_struct *task;
1966
1967                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1968                         if (task) {
1969                                 seq_printf(m, "(%s [%d]) ",
1970                                            task->comm, task->pid);
1971                                 put_task_struct(task);
1972                         }
1973                 } else if (IS_ERR(ctx->file_priv)) {
1974                         seq_puts(m, "(deleted) ");
1975                 } else {
1976                         seq_puts(m, "(kernel) ");
1977                 }
1978
1979                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1980                 seq_putc(m, '\n');
1981
1982                 for_each_engine(engine, dev_priv) {
1983                         struct intel_context *ce = &ctx->engine[engine->id];
1984
1985                         seq_printf(m, "%s: ", engine->name);
1986                         seq_putc(m, ce->initialised ? 'I' : 'i');
1987                         if (ce->state)
1988                                 describe_obj(m, ce->state->obj);
1989                         if (ce->ring)
1990                                 describe_ctx_ring(m, ce->ring);
1991                         seq_putc(m, '\n');
1992                 }
1993
1994                 seq_putc(m, '\n');
1995         }
1996
1997         mutex_unlock(&dev->struct_mutex);
1998
1999         return 0;
2000 }
2001
2002 static void i915_dump_lrc_obj(struct seq_file *m,
2003                               struct i915_gem_context *ctx,
2004                               struct intel_engine_cs *engine)
2005 {
2006         struct i915_vma *vma = ctx->engine[engine->id].state;
2007         struct page *page;
2008         int j;
2009
2010         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2011
2012         if (!vma) {
2013                 seq_puts(m, "\tFake context\n");
2014                 return;
2015         }
2016
2017         if (vma->flags & I915_VMA_GLOBAL_BIND)
2018                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2019                            i915_ggtt_offset(vma));
2020
2021         if (i915_gem_object_get_pages(vma->obj)) {
2022                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2023                 return;
2024         }
2025
2026         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2027         if (page) {
2028                 u32 *reg_state = kmap_atomic(page);
2029
2030                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2031                         seq_printf(m,
2032                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2033                                    j * 4,
2034                                    reg_state[j], reg_state[j + 1],
2035                                    reg_state[j + 2], reg_state[j + 3]);
2036                 }
2037                 kunmap_atomic(reg_state);
2038         }
2039
2040         seq_putc(m, '\n');
2041 }
2042
2043 static int i915_dump_lrc(struct seq_file *m, void *unused)
2044 {
2045         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2046         struct drm_device *dev = &dev_priv->drm;
2047         struct intel_engine_cs *engine;
2048         struct i915_gem_context *ctx;
2049         int ret;
2050
2051         if (!i915.enable_execlists) {
2052                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2053                 return 0;
2054         }
2055
2056         ret = mutex_lock_interruptible(&dev->struct_mutex);
2057         if (ret)
2058                 return ret;
2059
2060         list_for_each_entry(ctx, &dev_priv->context_list, link)
2061                 for_each_engine(engine, dev_priv)
2062                         i915_dump_lrc_obj(m, ctx, engine);
2063
2064         mutex_unlock(&dev->struct_mutex);
2065
2066         return 0;
2067 }
2068
2069 static const char *swizzle_string(unsigned swizzle)
2070 {
2071         switch (swizzle) {
2072         case I915_BIT_6_SWIZZLE_NONE:
2073                 return "none";
2074         case I915_BIT_6_SWIZZLE_9:
2075                 return "bit9";
2076         case I915_BIT_6_SWIZZLE_9_10:
2077                 return "bit9/bit10";
2078         case I915_BIT_6_SWIZZLE_9_11:
2079                 return "bit9/bit11";
2080         case I915_BIT_6_SWIZZLE_9_10_11:
2081                 return "bit9/bit10/bit11";
2082         case I915_BIT_6_SWIZZLE_9_17:
2083                 return "bit9/bit17";
2084         case I915_BIT_6_SWIZZLE_9_10_17:
2085                 return "bit9/bit10/bit17";
2086         case I915_BIT_6_SWIZZLE_UNKNOWN:
2087                 return "unknown";
2088         }
2089
2090         return "bug";
2091 }
2092
2093 static int i915_swizzle_info(struct seq_file *m, void *data)
2094 {
2095         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2096         struct drm_device *dev = &dev_priv->drm;
2097         int ret;
2098
2099         ret = mutex_lock_interruptible(&dev->struct_mutex);
2100         if (ret)
2101                 return ret;
2102         intel_runtime_pm_get(dev_priv);
2103
2104         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2105                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2106         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2107                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2108
2109         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2110                 seq_printf(m, "DDC = 0x%08x\n",
2111                            I915_READ(DCC));
2112                 seq_printf(m, "DDC2 = 0x%08x\n",
2113                            I915_READ(DCC2));
2114                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2115                            I915_READ16(C0DRB3));
2116                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2117                            I915_READ16(C1DRB3));
2118         } else if (INTEL_GEN(dev_priv) >= 6) {
2119                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2120                            I915_READ(MAD_DIMM_C0));
2121                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2122                            I915_READ(MAD_DIMM_C1));
2123                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2124                            I915_READ(MAD_DIMM_C2));
2125                 seq_printf(m, "TILECTL = 0x%08x\n",
2126                            I915_READ(TILECTL));
2127                 if (INTEL_GEN(dev_priv) >= 8)
2128                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2129                                    I915_READ(GAMTARBMODE));
2130                 else
2131                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2132                                    I915_READ(ARB_MODE));
2133                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2134                            I915_READ(DISP_ARB_CTL));
2135         }
2136
2137         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2138                 seq_puts(m, "L-shaped memory detected\n");
2139
2140         intel_runtime_pm_put(dev_priv);
2141         mutex_unlock(&dev->struct_mutex);
2142
2143         return 0;
2144 }
2145
2146 static int per_file_ctx(int id, void *ptr, void *data)
2147 {
2148         struct i915_gem_context *ctx = ptr;
2149         struct seq_file *m = data;
2150         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2151
2152         if (!ppgtt) {
2153                 seq_printf(m, "  no ppgtt for context %d\n",
2154                            ctx->user_handle);
2155                 return 0;
2156         }
2157
2158         if (i915_gem_context_is_default(ctx))
2159                 seq_puts(m, "  default context:\n");
2160         else
2161                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2162         ppgtt->debug_dump(ppgtt, m);
2163
2164         return 0;
2165 }
2166
2167 static void gen8_ppgtt_info(struct seq_file *m,
2168                             struct drm_i915_private *dev_priv)
2169 {
2170         struct intel_engine_cs *engine;
2171         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2172         int i;
2173
2174         if (!ppgtt)
2175                 return;
2176
2177         for_each_engine(engine, dev_priv) {
2178                 seq_printf(m, "%s\n", engine->name);
2179                 for (i = 0; i < 4; i++) {
2180                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2181                         pdp <<= 32;
2182                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2183                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2184                 }
2185         }
2186 }
2187
2188 static void gen6_ppgtt_info(struct seq_file *m,
2189                             struct drm_i915_private *dev_priv)
2190 {
2191         struct intel_engine_cs *engine;
2192
2193         if (IS_GEN6(dev_priv))
2194                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2195
2196         for_each_engine(engine, dev_priv) {
2197                 seq_printf(m, "%s\n", engine->name);
2198                 if (IS_GEN7(dev_priv))
2199                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2200                                    I915_READ(RING_MODE_GEN7(engine)));
2201                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2202                            I915_READ(RING_PP_DIR_BASE(engine)));
2203                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2204                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2205                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2206                            I915_READ(RING_PP_DIR_DCLV(engine)));
2207         }
2208         if (dev_priv->mm.aliasing_ppgtt) {
2209                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2210
2211                 seq_puts(m, "aliasing PPGTT:\n");
2212                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2213
2214                 ppgtt->debug_dump(ppgtt, m);
2215         }
2216
2217         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2218 }
2219
2220 static int i915_ppgtt_info(struct seq_file *m, void *data)
2221 {
2222         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2223         struct drm_device *dev = &dev_priv->drm;
2224         struct drm_file *file;
2225         int ret;
2226
2227         mutex_lock(&dev->filelist_mutex);
2228         ret = mutex_lock_interruptible(&dev->struct_mutex);
2229         if (ret)
2230                 goto out_unlock;
2231
2232         intel_runtime_pm_get(dev_priv);
2233
2234         if (INTEL_GEN(dev_priv) >= 8)
2235                 gen8_ppgtt_info(m, dev_priv);
2236         else if (INTEL_GEN(dev_priv) >= 6)
2237                 gen6_ppgtt_info(m, dev_priv);
2238
2239         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2240                 struct drm_i915_file_private *file_priv = file->driver_priv;
2241                 struct task_struct *task;
2242
2243                 task = get_pid_task(file->pid, PIDTYPE_PID);
2244                 if (!task) {
2245                         ret = -ESRCH;
2246                         goto out_rpm;
2247                 }
2248                 seq_printf(m, "\nproc: %s\n", task->comm);
2249                 put_task_struct(task);
2250                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2251                              (void *)(unsigned long)m);
2252         }
2253
2254 out_rpm:
2255         intel_runtime_pm_put(dev_priv);
2256         mutex_unlock(&dev->struct_mutex);
2257 out_unlock:
2258         mutex_unlock(&dev->filelist_mutex);
2259         return ret;
2260 }
2261
2262 static int count_irq_waiters(struct drm_i915_private *i915)
2263 {
2264         struct intel_engine_cs *engine;
2265         int count = 0;
2266
2267         for_each_engine(engine, i915)
2268                 count += intel_engine_has_waiter(engine);
2269
2270         return count;
2271 }
2272
2273 static const char *rps_power_to_str(unsigned int power)
2274 {
2275         static const char * const strings[] = {
2276                 [LOW_POWER] = "low power",
2277                 [BETWEEN] = "mixed",
2278                 [HIGH_POWER] = "high power",
2279         };
2280
2281         if (power >= ARRAY_SIZE(strings) || !strings[power])
2282                 return "unknown";
2283
2284         return strings[power];
2285 }
2286
2287 static int i915_rps_boost_info(struct seq_file *m, void *data)
2288 {
2289         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2290         struct drm_device *dev = &dev_priv->drm;
2291         struct drm_file *file;
2292
2293         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2294         seq_printf(m, "GPU busy? %s [%x]\n",
2295                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2296         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2297         seq_printf(m, "Frequency requested %d\n",
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2299         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2300                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2301                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2302                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2303                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2304         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2305                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2306                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2307                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2308
2309         mutex_lock(&dev->filelist_mutex);
2310         spin_lock(&dev_priv->rps.client_lock);
2311         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2312                 struct drm_i915_file_private *file_priv = file->driver_priv;
2313                 struct task_struct *task;
2314
2315                 rcu_read_lock();
2316                 task = pid_task(file->pid, PIDTYPE_PID);
2317                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2318                            task ? task->comm : "<unknown>",
2319                            task ? task->pid : -1,
2320                            file_priv->rps.boosts,
2321                            list_empty(&file_priv->rps.link) ? "" : ", active");
2322                 rcu_read_unlock();
2323         }
2324         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2325         spin_unlock(&dev_priv->rps.client_lock);
2326         mutex_unlock(&dev->filelist_mutex);
2327
2328         if (INTEL_GEN(dev_priv) >= 6 &&
2329             dev_priv->rps.enabled &&
2330             dev_priv->gt.active_engines) {
2331                 u32 rpup, rpupei;
2332                 u32 rpdown, rpdownei;
2333
2334                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2335                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2336                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2337                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2338                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2339                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2340
2341                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2342                            rps_power_to_str(dev_priv->rps.power));
2343                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2344                            100 * rpup / rpupei,
2345                            dev_priv->rps.up_threshold);
2346                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2347                            100 * rpdown / rpdownei,
2348                            dev_priv->rps.down_threshold);
2349         } else {
2350                 seq_puts(m, "\nRPS Autotuning inactive\n");
2351         }
2352
2353         return 0;
2354 }
2355
2356 static int i915_llc(struct seq_file *m, void *data)
2357 {
2358         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2359         const bool edram = INTEL_GEN(dev_priv) > 8;
2360
2361         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2362         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2363                    intel_uncore_edram_size(dev_priv)/1024/1024);
2364
2365         return 0;
2366 }
2367
2368 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2369 {
2370         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2371         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2372         u32 tmp, i;
2373
2374         if (!HAS_GUC_UCODE(dev_priv))
2375                 return 0;
2376
2377         seq_printf(m, "GuC firmware status:\n");
2378         seq_printf(m, "\tpath: %s\n",
2379                 guc_fw->guc_fw_path);
2380         seq_printf(m, "\tfetch: %s\n",
2381                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2382         seq_printf(m, "\tload: %s\n",
2383                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2384         seq_printf(m, "\tversion wanted: %d.%d\n",
2385                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2386         seq_printf(m, "\tversion found: %d.%d\n",
2387                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2388         seq_printf(m, "\theader: offset is %d; size = %d\n",
2389                 guc_fw->header_offset, guc_fw->header_size);
2390         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2391                 guc_fw->ucode_offset, guc_fw->ucode_size);
2392         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2393                 guc_fw->rsa_offset, guc_fw->rsa_size);
2394
2395         tmp = I915_READ(GUC_STATUS);
2396
2397         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2398         seq_printf(m, "\tBootrom status = 0x%x\n",
2399                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2400         seq_printf(m, "\tuKernel status = 0x%x\n",
2401                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2402         seq_printf(m, "\tMIA Core status = 0x%x\n",
2403                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2404         seq_puts(m, "\nScratch registers:\n");
2405         for (i = 0; i < 16; i++)
2406                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2407
2408         return 0;
2409 }
2410
2411 static void i915_guc_client_info(struct seq_file *m,
2412                                  struct drm_i915_private *dev_priv,
2413                                  struct i915_guc_client *client)
2414 {
2415         struct intel_engine_cs *engine;
2416         enum intel_engine_id id;
2417         uint64_t tot = 0;
2418
2419         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2420                 client->priority, client->ctx_index, client->proc_desc_offset);
2421         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2422                 client->doorbell_id, client->doorbell_offset, client->cookie);
2423         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2424                 client->wq_size, client->wq_offset, client->wq_tail);
2425
2426         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2427         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2428         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2429
2430         for_each_engine_id(engine, dev_priv, id) {
2431                 u64 submissions = client->submissions[id];
2432                 tot += submissions;
2433                 seq_printf(m, "\tSubmissions: %llu %s\n",
2434                                 submissions, engine->name);
2435         }
2436         seq_printf(m, "\tTotal: %llu\n", tot);
2437 }
2438
2439 static int i915_guc_info(struct seq_file *m, void *data)
2440 {
2441         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2442         struct drm_device *dev = &dev_priv->drm;
2443         struct intel_guc guc;
2444         struct i915_guc_client client = {};
2445         struct intel_engine_cs *engine;
2446         enum intel_engine_id id;
2447         u64 total = 0;
2448
2449         if (!HAS_GUC_SCHED(dev_priv))
2450                 return 0;
2451
2452         if (mutex_lock_interruptible(&dev->struct_mutex))
2453                 return 0;
2454
2455         /* Take a local copy of the GuC data, so we can dump it at leisure */
2456         guc = dev_priv->guc;
2457         if (guc.execbuf_client)
2458                 client = *guc.execbuf_client;
2459
2460         mutex_unlock(&dev->struct_mutex);
2461
2462         seq_printf(m, "Doorbell map:\n");
2463         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2464         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2465
2466         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2467         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2468         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2469         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2470         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2471
2472         seq_printf(m, "\nGuC submissions:\n");
2473         for_each_engine_id(engine, dev_priv, id) {
2474                 u64 submissions = guc.submissions[id];
2475                 total += submissions;
2476                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2477                         engine->name, submissions, guc.last_seqno[id]);
2478         }
2479         seq_printf(m, "\t%s: %llu\n", "Total", total);
2480
2481         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2482         i915_guc_client_info(m, dev_priv, &client);
2483
2484         /* Add more as required ... */
2485
2486         return 0;
2487 }
2488
2489 static int i915_guc_log_dump(struct seq_file *m, void *data)
2490 {
2491         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2492         struct drm_i915_gem_object *obj;
2493         int i = 0, pg;
2494
2495         if (!dev_priv->guc.log_vma)
2496                 return 0;
2497
2498         obj = dev_priv->guc.log_vma->obj;
2499         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2500                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2501
2502                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2503                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2504                                    *(log + i), *(log + i + 1),
2505                                    *(log + i + 2), *(log + i + 3));
2506
2507                 kunmap_atomic(log);
2508         }
2509
2510         seq_putc(m, '\n');
2511
2512         return 0;
2513 }
2514
2515 static int i915_edp_psr_status(struct seq_file *m, void *data)
2516 {
2517         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2518         u32 psrperf = 0;
2519         u32 stat[3];
2520         enum pipe pipe;
2521         bool enabled = false;
2522
2523         if (!HAS_PSR(dev_priv)) {
2524                 seq_puts(m, "PSR not supported\n");
2525                 return 0;
2526         }
2527
2528         intel_runtime_pm_get(dev_priv);
2529
2530         mutex_lock(&dev_priv->psr.lock);
2531         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2532         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2533         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2534         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2535         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2536                    dev_priv->psr.busy_frontbuffer_bits);
2537         seq_printf(m, "Re-enable work scheduled: %s\n",
2538                    yesno(work_busy(&dev_priv->psr.work.work)));
2539
2540         if (HAS_DDI(dev_priv))
2541                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2542         else {
2543                 for_each_pipe(dev_priv, pipe) {
2544                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2545                                 VLV_EDP_PSR_CURR_STATE_MASK;
2546                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2547                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2548                                 enabled = true;
2549                 }
2550         }
2551
2552         seq_printf(m, "Main link in standby mode: %s\n",
2553                    yesno(dev_priv->psr.link_standby));
2554
2555         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2556
2557         if (!HAS_DDI(dev_priv))
2558                 for_each_pipe(dev_priv, pipe) {
2559                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2560                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2561                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2562                 }
2563         seq_puts(m, "\n");
2564
2565         /*
2566          * VLV/CHV PSR has no kind of performance counter
2567          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2568          */
2569         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2570                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2571                         EDP_PSR_PERF_CNT_MASK;
2572
2573                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2574         }
2575         mutex_unlock(&dev_priv->psr.lock);
2576
2577         intel_runtime_pm_put(dev_priv);
2578         return 0;
2579 }
2580
2581 static int i915_sink_crc(struct seq_file *m, void *data)
2582 {
2583         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2584         struct drm_device *dev = &dev_priv->drm;
2585         struct intel_connector *connector;
2586         struct intel_dp *intel_dp = NULL;
2587         int ret;
2588         u8 crc[6];
2589
2590         drm_modeset_lock_all(dev);
2591         for_each_intel_connector(dev, connector) {
2592                 struct drm_crtc *crtc;
2593
2594                 if (!connector->base.state->best_encoder)
2595                         continue;
2596
2597                 crtc = connector->base.state->crtc;
2598                 if (!crtc->state->active)
2599                         continue;
2600
2601                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2602                         continue;
2603
2604                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2605
2606                 ret = intel_dp_sink_crc(intel_dp, crc);
2607                 if (ret)
2608                         goto out;
2609
2610                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2611                            crc[0], crc[1], crc[2],
2612                            crc[3], crc[4], crc[5]);
2613                 goto out;
2614         }
2615         ret = -ENODEV;
2616 out:
2617         drm_modeset_unlock_all(dev);
2618         return ret;
2619 }
2620
2621 static int i915_energy_uJ(struct seq_file *m, void *data)
2622 {
2623         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2624         u64 power;
2625         u32 units;
2626
2627         if (INTEL_GEN(dev_priv) < 6)
2628                 return -ENODEV;
2629
2630         intel_runtime_pm_get(dev_priv);
2631
2632         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2633         power = (power & 0x1f00) >> 8;
2634         units = 1000000 / (1 << power); /* convert to uJ */
2635         power = I915_READ(MCH_SECP_NRG_STTS);
2636         power *= units;
2637
2638         intel_runtime_pm_put(dev_priv);
2639
2640         seq_printf(m, "%llu", (long long unsigned)power);
2641
2642         return 0;
2643 }
2644
2645 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2646 {
2647         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2648         struct pci_dev *pdev = dev_priv->drm.pdev;
2649
2650         if (!HAS_RUNTIME_PM(dev_priv))
2651                 seq_puts(m, "Runtime power management not supported\n");
2652
2653         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2654         seq_printf(m, "IRQs disabled: %s\n",
2655                    yesno(!intel_irqs_enabled(dev_priv)));
2656 #ifdef CONFIG_PM
2657         seq_printf(m, "Usage count: %d\n",
2658                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2659 #else
2660         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2661 #endif
2662         seq_printf(m, "PCI device power state: %s [%d]\n",
2663                    pci_power_name(pdev->current_state),
2664                    pdev->current_state);
2665
2666         return 0;
2667 }
2668
2669 static int i915_power_domain_info(struct seq_file *m, void *unused)
2670 {
2671         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2672         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2673         int i;
2674
2675         mutex_lock(&power_domains->lock);
2676
2677         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2678         for (i = 0; i < power_domains->power_well_count; i++) {
2679                 struct i915_power_well *power_well;
2680                 enum intel_display_power_domain power_domain;
2681
2682                 power_well = &power_domains->power_wells[i];
2683                 seq_printf(m, "%-25s %d\n", power_well->name,
2684                            power_well->count);
2685
2686                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2687                      power_domain++) {
2688                         if (!(BIT(power_domain) & power_well->domains))
2689                                 continue;
2690
2691                         seq_printf(m, "  %-23s %d\n",
2692                                  intel_display_power_domain_str(power_domain),
2693                                  power_domains->domain_use_count[power_domain]);
2694                 }
2695         }
2696
2697         mutex_unlock(&power_domains->lock);
2698
2699         return 0;
2700 }
2701
2702 static int i915_dmc_info(struct seq_file *m, void *unused)
2703 {
2704         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2705         struct intel_csr *csr;
2706
2707         if (!HAS_CSR(dev_priv)) {
2708                 seq_puts(m, "not supported\n");
2709                 return 0;
2710         }
2711
2712         csr = &dev_priv->csr;
2713
2714         intel_runtime_pm_get(dev_priv);
2715
2716         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2717         seq_printf(m, "path: %s\n", csr->fw_path);
2718
2719         if (!csr->dmc_payload)
2720                 goto out;
2721
2722         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2723                    CSR_VERSION_MINOR(csr->version));
2724
2725         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2726                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2727                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2728                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2729                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2730         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2731                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2732                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2733         }
2734
2735 out:
2736         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2737         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2738         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2739
2740         intel_runtime_pm_put(dev_priv);
2741
2742         return 0;
2743 }
2744
2745 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2746                                  struct drm_display_mode *mode)
2747 {
2748         int i;
2749
2750         for (i = 0; i < tabs; i++)
2751                 seq_putc(m, '\t');
2752
2753         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2754                    mode->base.id, mode->name,
2755                    mode->vrefresh, mode->clock,
2756                    mode->hdisplay, mode->hsync_start,
2757                    mode->hsync_end, mode->htotal,
2758                    mode->vdisplay, mode->vsync_start,
2759                    mode->vsync_end, mode->vtotal,
2760                    mode->type, mode->flags);
2761 }
2762
2763 static void intel_encoder_info(struct seq_file *m,
2764                                struct intel_crtc *intel_crtc,
2765                                struct intel_encoder *intel_encoder)
2766 {
2767         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2768         struct drm_device *dev = &dev_priv->drm;
2769         struct drm_crtc *crtc = &intel_crtc->base;
2770         struct intel_connector *intel_connector;
2771         struct drm_encoder *encoder;
2772
2773         encoder = &intel_encoder->base;
2774         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2775                    encoder->base.id, encoder->name);
2776         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2777                 struct drm_connector *connector = &intel_connector->base;
2778                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2779                            connector->base.id,
2780                            connector->name,
2781                            drm_get_connector_status_name(connector->status));
2782                 if (connector->status == connector_status_connected) {
2783                         struct drm_display_mode *mode = &crtc->mode;
2784                         seq_printf(m, ", mode:\n");
2785                         intel_seq_print_mode(m, 2, mode);
2786                 } else {
2787                         seq_putc(m, '\n');
2788                 }
2789         }
2790 }
2791
2792 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2793 {
2794         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2795         struct drm_device *dev = &dev_priv->drm;
2796         struct drm_crtc *crtc = &intel_crtc->base;
2797         struct intel_encoder *intel_encoder;
2798         struct drm_plane_state *plane_state = crtc->primary->state;
2799         struct drm_framebuffer *fb = plane_state->fb;
2800
2801         if (fb)
2802                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2803                            fb->base.id, plane_state->src_x >> 16,
2804                            plane_state->src_y >> 16, fb->width, fb->height);
2805         else
2806                 seq_puts(m, "\tprimary plane disabled\n");
2807         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2808                 intel_encoder_info(m, intel_crtc, intel_encoder);
2809 }
2810
2811 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2812 {
2813         struct drm_display_mode *mode = panel->fixed_mode;
2814
2815         seq_printf(m, "\tfixed mode:\n");
2816         intel_seq_print_mode(m, 2, mode);
2817 }
2818
2819 static void intel_dp_info(struct seq_file *m,
2820                           struct intel_connector *intel_connector)
2821 {
2822         struct intel_encoder *intel_encoder = intel_connector->encoder;
2823         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2824
2825         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2826         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2827         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2828                 intel_panel_info(m, &intel_connector->panel);
2829
2830         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2831                                 &intel_dp->aux);
2832 }
2833
2834 static void intel_hdmi_info(struct seq_file *m,
2835                             struct intel_connector *intel_connector)
2836 {
2837         struct intel_encoder *intel_encoder = intel_connector->encoder;
2838         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2839
2840         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2841 }
2842
2843 static void intel_lvds_info(struct seq_file *m,
2844                             struct intel_connector *intel_connector)
2845 {
2846         intel_panel_info(m, &intel_connector->panel);
2847 }
2848
2849 static void intel_connector_info(struct seq_file *m,
2850                                  struct drm_connector *connector)
2851 {
2852         struct intel_connector *intel_connector = to_intel_connector(connector);
2853         struct intel_encoder *intel_encoder = intel_connector->encoder;
2854         struct drm_display_mode *mode;
2855
2856         seq_printf(m, "connector %d: type %s, status: %s\n",
2857                    connector->base.id, connector->name,
2858                    drm_get_connector_status_name(connector->status));
2859         if (connector->status == connector_status_connected) {
2860                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2861                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2862                            connector->display_info.width_mm,
2863                            connector->display_info.height_mm);
2864                 seq_printf(m, "\tsubpixel order: %s\n",
2865                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2866                 seq_printf(m, "\tCEA rev: %d\n",
2867                            connector->display_info.cea_rev);
2868         }
2869
2870         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2871                 return;
2872
2873         switch (connector->connector_type) {
2874         case DRM_MODE_CONNECTOR_DisplayPort:
2875         case DRM_MODE_CONNECTOR_eDP:
2876                 intel_dp_info(m, intel_connector);
2877                 break;
2878         case DRM_MODE_CONNECTOR_LVDS:
2879                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2880                         intel_lvds_info(m, intel_connector);
2881                 break;
2882         case DRM_MODE_CONNECTOR_HDMIA:
2883                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2884                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2885                         intel_hdmi_info(m, intel_connector);
2886                 break;
2887         default:
2888                 break;
2889         }
2890
2891         seq_printf(m, "\tmodes:\n");
2892         list_for_each_entry(mode, &connector->modes, head)
2893                 intel_seq_print_mode(m, 2, mode);
2894 }
2895
2896 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2897 {
2898         u32 state;
2899
2900         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2901                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2902         else
2903                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2904
2905         return state;
2906 }
2907
2908 static bool cursor_position(struct drm_i915_private *dev_priv,
2909                             int pipe, int *x, int *y)
2910 {
2911         u32 pos;
2912
2913         pos = I915_READ(CURPOS(pipe));
2914
2915         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2916         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2917                 *x = -*x;
2918
2919         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2920         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2921                 *y = -*y;
2922
2923         return cursor_active(dev_priv, pipe);
2924 }
2925
2926 static const char *plane_type(enum drm_plane_type type)
2927 {
2928         switch (type) {
2929         case DRM_PLANE_TYPE_OVERLAY:
2930                 return "OVL";
2931         case DRM_PLANE_TYPE_PRIMARY:
2932                 return "PRI";
2933         case DRM_PLANE_TYPE_CURSOR:
2934                 return "CUR";
2935         /*
2936          * Deliberately omitting default: to generate compiler warnings
2937          * when a new drm_plane_type gets added.
2938          */
2939         }
2940
2941         return "unknown";
2942 }
2943
2944 static const char *plane_rotation(unsigned int rotation)
2945 {
2946         static char buf[48];
2947         /*
2948          * According to doc only one DRM_ROTATE_ is allowed but this
2949          * will print them all to visualize if the values are misused
2950          */
2951         snprintf(buf, sizeof(buf),
2952                  "%s%s%s%s%s%s(0x%08x)",
2953                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2954                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2955                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2956                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2957                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2958                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2959                  rotation);
2960
2961         return buf;
2962 }
2963
2964 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2965 {
2966         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2967         struct drm_device *dev = &dev_priv->drm;
2968         struct intel_plane *intel_plane;
2969
2970         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2971                 struct drm_plane_state *state;
2972                 struct drm_plane *plane = &intel_plane->base;
2973                 char *format_name;
2974
2975                 if (!plane->state) {
2976                         seq_puts(m, "plane->state is NULL!\n");
2977                         continue;
2978                 }
2979
2980                 state = plane->state;
2981
2982                 if (state->fb) {
2983                         format_name = drm_get_format_name(state->fb->pixel_format);
2984                 } else {
2985                         format_name = kstrdup("N/A", GFP_KERNEL);
2986                 }
2987
2988                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2989                            plane->base.id,
2990                            plane_type(intel_plane->base.type),
2991                            state->crtc_x, state->crtc_y,
2992                            state->crtc_w, state->crtc_h,
2993                            (state->src_x >> 16),
2994                            ((state->src_x & 0xffff) * 15625) >> 10,
2995                            (state->src_y >> 16),
2996                            ((state->src_y & 0xffff) * 15625) >> 10,
2997                            (state->src_w >> 16),
2998                            ((state->src_w & 0xffff) * 15625) >> 10,
2999                            (state->src_h >> 16),
3000                            ((state->src_h & 0xffff) * 15625) >> 10,
3001                            format_name,
3002                            plane_rotation(state->rotation));
3003
3004                 kfree(format_name);
3005         }
3006 }
3007
3008 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3009 {
3010         struct intel_crtc_state *pipe_config;
3011         int num_scalers = intel_crtc->num_scalers;
3012         int i;
3013
3014         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3015
3016         /* Not all platformas have a scaler */
3017         if (num_scalers) {
3018                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3019                            num_scalers,
3020                            pipe_config->scaler_state.scaler_users,
3021                            pipe_config->scaler_state.scaler_id);
3022
3023                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3024                         struct intel_scaler *sc =
3025                                         &pipe_config->scaler_state.scalers[i];
3026
3027                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3028                                    i, yesno(sc->in_use), sc->mode);
3029                 }
3030                 seq_puts(m, "\n");
3031         } else {
3032                 seq_puts(m, "\tNo scalers available on this platform\n");
3033         }
3034 }
3035
3036 static int i915_display_info(struct seq_file *m, void *unused)
3037 {
3038         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3039         struct drm_device *dev = &dev_priv->drm;
3040         struct intel_crtc *crtc;
3041         struct drm_connector *connector;
3042
3043         intel_runtime_pm_get(dev_priv);
3044         drm_modeset_lock_all(dev);
3045         seq_printf(m, "CRTC info\n");
3046         seq_printf(m, "---------\n");
3047         for_each_intel_crtc(dev, crtc) {
3048                 bool active;
3049                 struct intel_crtc_state *pipe_config;
3050                 int x, y;
3051
3052                 pipe_config = to_intel_crtc_state(crtc->base.state);
3053
3054                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3055                            crtc->base.base.id, pipe_name(crtc->pipe),
3056                            yesno(pipe_config->base.active),
3057                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3058                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3059
3060                 if (pipe_config->base.active) {
3061                         intel_crtc_info(m, crtc);
3062
3063                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3064                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3065                                    yesno(crtc->cursor_base),
3066                                    x, y, crtc->base.cursor->state->crtc_w,
3067                                    crtc->base.cursor->state->crtc_h,
3068                                    crtc->cursor_addr, yesno(active));
3069                         intel_scaler_info(m, crtc);
3070                         intel_plane_info(m, crtc);
3071                 }
3072
3073                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3074                            yesno(!crtc->cpu_fifo_underrun_disabled),
3075                            yesno(!crtc->pch_fifo_underrun_disabled));
3076         }
3077
3078         seq_printf(m, "\n");
3079         seq_printf(m, "Connector info\n");
3080         seq_printf(m, "--------------\n");
3081         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3082                 intel_connector_info(m, connector);
3083         }
3084         drm_modeset_unlock_all(dev);
3085         intel_runtime_pm_put(dev_priv);
3086
3087         return 0;
3088 }
3089
3090 static int i915_engine_info(struct seq_file *m, void *unused)
3091 {
3092         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3093         struct intel_engine_cs *engine;
3094
3095         for_each_engine(engine, dev_priv) {
3096                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3097                 struct drm_i915_gem_request *rq;
3098                 struct rb_node *rb;
3099                 u64 addr;
3100
3101                 seq_printf(m, "%s\n", engine->name);
3102                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3103                            intel_engine_get_seqno(engine),
3104                            engine->last_submitted_seqno,
3105                            engine->hangcheck.seqno,
3106                            engine->hangcheck.score);
3107
3108                 rcu_read_lock();
3109
3110                 seq_printf(m, "\tRequests:\n");
3111
3112                 rq = list_first_entry(&engine->request_list,
3113                                 struct drm_i915_gem_request, link);
3114                 if (&rq->link != &engine->request_list)
3115                         print_request(m, rq, "\t\tfirst  ");
3116
3117                 rq = list_last_entry(&engine->request_list,
3118                                 struct drm_i915_gem_request, link);
3119                 if (&rq->link != &engine->request_list)
3120                         print_request(m, rq, "\t\tlast   ");
3121
3122                 rq = i915_gem_find_active_request(engine);
3123                 if (rq) {
3124                         print_request(m, rq, "\t\tactive ");
3125                         seq_printf(m,
3126                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3127                                    rq->head, rq->postfix, rq->tail,
3128                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3129                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3130                 }
3131
3132                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3133                            I915_READ(RING_START(engine->mmio_base)),
3134                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3135                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3136                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3137                            rq ? rq->ring->head : 0);
3138                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3139                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3140                            rq ? rq->ring->tail : 0);
3141                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3142                            I915_READ(RING_CTL(engine->mmio_base)),
3143                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3144
3145                 rcu_read_unlock();
3146
3147                 addr = intel_engine_get_active_head(engine);
3148                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3149                            upper_32_bits(addr), lower_32_bits(addr));
3150                 addr = intel_engine_get_last_batch_head(engine);
3151                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3152                            upper_32_bits(addr), lower_32_bits(addr));
3153
3154                 if (i915.enable_execlists) {
3155                         u32 ptr, read, write;
3156
3157                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3158                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3159                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3160
3161                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3162                         read = GEN8_CSB_READ_PTR(ptr);
3163                         write = GEN8_CSB_WRITE_PTR(ptr);
3164                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3165                                    read, write);
3166                         if (read >= GEN8_CSB_ENTRIES)
3167                                 read = 0;
3168                         if (write >= GEN8_CSB_ENTRIES)
3169                                 write = 0;
3170                         if (read > write)
3171                                 write += GEN8_CSB_ENTRIES;
3172                         while (read < write) {
3173                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3174
3175                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3176                                            idx,
3177                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3178                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3179                         }
3180
3181                         rcu_read_lock();
3182                         rq = READ_ONCE(engine->execlist_port[0].request);
3183                         if (rq)
3184                                 print_request(m, rq, "\t\tELSP[0] ");
3185                         else
3186                                 seq_printf(m, "\t\tELSP[0] idle\n");
3187                         rq = READ_ONCE(engine->execlist_port[1].request);
3188                         if (rq)
3189                                 print_request(m, rq, "\t\tELSP[1] ");
3190                         else
3191                                 seq_printf(m, "\t\tELSP[1] idle\n");
3192                         rcu_read_unlock();
3193                 } else if (INTEL_GEN(dev_priv) > 6) {
3194                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3195                                    I915_READ(RING_PP_DIR_BASE(engine)));
3196                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3197                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3198                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3199                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3200                 }
3201
3202                 spin_lock(&b->lock);
3203                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3204                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3205
3206                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3207                                    w->tsk->comm, w->tsk->pid, w->seqno);
3208                 }
3209                 spin_unlock(&b->lock);
3210
3211                 seq_puts(m, "\n");
3212         }
3213
3214         return 0;
3215 }
3216
3217 static int i915_semaphore_status(struct seq_file *m, void *unused)
3218 {
3219         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3220         struct drm_device *dev = &dev_priv->drm;
3221         struct intel_engine_cs *engine;
3222         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3223         enum intel_engine_id id;
3224         int j, ret;
3225
3226         if (!i915.semaphores) {
3227                 seq_puts(m, "Semaphores are disabled\n");
3228                 return 0;
3229         }
3230
3231         ret = mutex_lock_interruptible(&dev->struct_mutex);
3232         if (ret)
3233                 return ret;
3234         intel_runtime_pm_get(dev_priv);
3235
3236         if (IS_BROADWELL(dev_priv)) {
3237                 struct page *page;
3238                 uint64_t *seqno;
3239
3240                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3241
3242                 seqno = (uint64_t *)kmap_atomic(page);
3243                 for_each_engine_id(engine, dev_priv, id) {
3244                         uint64_t offset;
3245
3246                         seq_printf(m, "%s\n", engine->name);
3247
3248                         seq_puts(m, "  Last signal:");
3249                         for (j = 0; j < num_rings; j++) {
3250                                 offset = id * I915_NUM_ENGINES + j;
3251                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3252                                            seqno[offset], offset * 8);
3253                         }
3254                         seq_putc(m, '\n');
3255
3256                         seq_puts(m, "  Last wait:  ");
3257                         for (j = 0; j < num_rings; j++) {
3258                                 offset = id + (j * I915_NUM_ENGINES);
3259                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3260                                            seqno[offset], offset * 8);
3261                         }
3262                         seq_putc(m, '\n');
3263
3264                 }
3265                 kunmap_atomic(seqno);
3266         } else {
3267                 seq_puts(m, "  Last signal:");
3268                 for_each_engine(engine, dev_priv)
3269                         for (j = 0; j < num_rings; j++)
3270                                 seq_printf(m, "0x%08x\n",
3271                                            I915_READ(engine->semaphore.mbox.signal[j]));
3272                 seq_putc(m, '\n');
3273         }
3274
3275         seq_puts(m, "\nSync seqno:\n");
3276         for_each_engine(engine, dev_priv) {
3277                 for (j = 0; j < num_rings; j++)
3278                         seq_printf(m, "  0x%08x ",
3279                                    engine->semaphore.sync_seqno[j]);
3280                 seq_putc(m, '\n');
3281         }
3282         seq_putc(m, '\n');
3283
3284         intel_runtime_pm_put(dev_priv);
3285         mutex_unlock(&dev->struct_mutex);
3286         return 0;
3287 }
3288
3289 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3290 {
3291         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3292         struct drm_device *dev = &dev_priv->drm;
3293         int i;
3294
3295         drm_modeset_lock_all(dev);
3296         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3298
3299                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3300                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3301                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3302                 seq_printf(m, " tracked hardware state:\n");
3303                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3304                 seq_printf(m, " dpll_md: 0x%08x\n",
3305                            pll->config.hw_state.dpll_md);
3306                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3307                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3308                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3309         }
3310         drm_modeset_unlock_all(dev);
3311
3312         return 0;
3313 }
3314
3315 static int i915_wa_registers(struct seq_file *m, void *unused)
3316 {
3317         int i;
3318         int ret;
3319         struct intel_engine_cs *engine;
3320         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3321         struct drm_device *dev = &dev_priv->drm;
3322         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3323         enum intel_engine_id id;
3324
3325         ret = mutex_lock_interruptible(&dev->struct_mutex);
3326         if (ret)
3327                 return ret;
3328
3329         intel_runtime_pm_get(dev_priv);
3330
3331         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3332         for_each_engine_id(engine, dev_priv, id)
3333                 seq_printf(m, "HW whitelist count for %s: %d\n",
3334                            engine->name, workarounds->hw_whitelist_count[id]);
3335         for (i = 0; i < workarounds->count; ++i) {
3336                 i915_reg_t addr;
3337                 u32 mask, value, read;
3338                 bool ok;
3339
3340                 addr = workarounds->reg[i].addr;
3341                 mask = workarounds->reg[i].mask;
3342                 value = workarounds->reg[i].value;
3343                 read = I915_READ(addr);
3344                 ok = (value & mask) == (read & mask);
3345                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3346                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3347         }
3348
3349         intel_runtime_pm_put(dev_priv);
3350         mutex_unlock(&dev->struct_mutex);
3351
3352         return 0;
3353 }
3354
3355 static int i915_ddb_info(struct seq_file *m, void *unused)
3356 {
3357         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3358         struct drm_device *dev = &dev_priv->drm;
3359         struct skl_ddb_allocation *ddb;
3360         struct skl_ddb_entry *entry;
3361         enum pipe pipe;
3362         int plane;
3363
3364         if (INTEL_GEN(dev_priv) < 9)
3365                 return 0;
3366
3367         drm_modeset_lock_all(dev);
3368
3369         ddb = &dev_priv->wm.skl_hw.ddb;
3370
3371         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3372
3373         for_each_pipe(dev_priv, pipe) {
3374                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3375
3376                 for_each_plane(dev_priv, pipe, plane) {
3377                         entry = &ddb->plane[pipe][plane];
3378                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3379                                    entry->start, entry->end,
3380                                    skl_ddb_entry_size(entry));
3381                 }
3382
3383                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3384                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3385                            entry->end, skl_ddb_entry_size(entry));
3386         }
3387
3388         drm_modeset_unlock_all(dev);
3389
3390         return 0;
3391 }
3392
3393 static void drrs_status_per_crtc(struct seq_file *m,
3394                                  struct drm_device *dev,
3395                                  struct intel_crtc *intel_crtc)
3396 {
3397         struct drm_i915_private *dev_priv = to_i915(dev);
3398         struct i915_drrs *drrs = &dev_priv->drrs;
3399         int vrefresh = 0;
3400         struct drm_connector *connector;
3401
3402         drm_for_each_connector(connector, dev) {
3403                 if (connector->state->crtc != &intel_crtc->base)
3404                         continue;
3405
3406                 seq_printf(m, "%s:\n", connector->name);
3407         }
3408
3409         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3410                 seq_puts(m, "\tVBT: DRRS_type: Static");
3411         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3412                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3413         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3414                 seq_puts(m, "\tVBT: DRRS_type: None");
3415         else
3416                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3417
3418         seq_puts(m, "\n\n");
3419
3420         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3421                 struct intel_panel *panel;
3422
3423                 mutex_lock(&drrs->mutex);
3424                 /* DRRS Supported */
3425                 seq_puts(m, "\tDRRS Supported: Yes\n");
3426
3427                 /* disable_drrs() will make drrs->dp NULL */
3428                 if (!drrs->dp) {
3429                         seq_puts(m, "Idleness DRRS: Disabled");
3430                         mutex_unlock(&drrs->mutex);
3431                         return;
3432                 }
3433
3434                 panel = &drrs->dp->attached_connector->panel;
3435                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3436                                         drrs->busy_frontbuffer_bits);
3437
3438                 seq_puts(m, "\n\t\t");
3439                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3440                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3441                         vrefresh = panel->fixed_mode->vrefresh;
3442                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3443                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3444                         vrefresh = panel->downclock_mode->vrefresh;
3445                 } else {
3446                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3447                                                 drrs->refresh_rate_type);
3448                         mutex_unlock(&drrs->mutex);
3449                         return;
3450                 }
3451                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3452
3453                 seq_puts(m, "\n\t\t");
3454                 mutex_unlock(&drrs->mutex);
3455         } else {
3456                 /* DRRS not supported. Print the VBT parameter*/
3457                 seq_puts(m, "\tDRRS Supported : No");
3458         }
3459         seq_puts(m, "\n");
3460 }
3461
3462 static int i915_drrs_status(struct seq_file *m, void *unused)
3463 {
3464         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3465         struct drm_device *dev = &dev_priv->drm;
3466         struct intel_crtc *intel_crtc;
3467         int active_crtc_cnt = 0;
3468
3469         drm_modeset_lock_all(dev);
3470         for_each_intel_crtc(dev, intel_crtc) {
3471                 if (intel_crtc->base.state->active) {
3472                         active_crtc_cnt++;
3473                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3474
3475                         drrs_status_per_crtc(m, dev, intel_crtc);
3476                 }
3477         }
3478         drm_modeset_unlock_all(dev);
3479
3480         if (!active_crtc_cnt)
3481                 seq_puts(m, "No active crtc found\n");
3482
3483         return 0;
3484 }
3485
3486 struct pipe_crc_info {
3487         const char *name;
3488         struct drm_i915_private *dev_priv;
3489         enum pipe pipe;
3490 };
3491
3492 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3493 {
3494         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3495         struct drm_device *dev = &dev_priv->drm;
3496         struct intel_encoder *intel_encoder;
3497         struct intel_digital_port *intel_dig_port;
3498         struct drm_connector *connector;
3499
3500         drm_modeset_lock_all(dev);
3501         drm_for_each_connector(connector, dev) {
3502                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3503                         continue;
3504
3505                 intel_encoder = intel_attached_encoder(connector);
3506                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3507                         continue;
3508
3509                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3510                 if (!intel_dig_port->dp.can_mst)
3511                         continue;
3512
3513                 seq_printf(m, "MST Source Port %c\n",
3514                            port_name(intel_dig_port->port));
3515                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3516         }
3517         drm_modeset_unlock_all(dev);
3518         return 0;
3519 }
3520
3521 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3522 {
3523         struct pipe_crc_info *info = inode->i_private;
3524         struct drm_i915_private *dev_priv = info->dev_priv;
3525         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3526
3527         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3528                 return -ENODEV;
3529
3530         spin_lock_irq(&pipe_crc->lock);
3531
3532         if (pipe_crc->opened) {
3533                 spin_unlock_irq(&pipe_crc->lock);
3534                 return -EBUSY; /* already open */
3535         }
3536
3537         pipe_crc->opened = true;
3538         filep->private_data = inode->i_private;
3539
3540         spin_unlock_irq(&pipe_crc->lock);
3541
3542         return 0;
3543 }
3544
3545 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3546 {
3547         struct pipe_crc_info *info = inode->i_private;
3548         struct drm_i915_private *dev_priv = info->dev_priv;
3549         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3550
3551         spin_lock_irq(&pipe_crc->lock);
3552         pipe_crc->opened = false;
3553         spin_unlock_irq(&pipe_crc->lock);
3554
3555         return 0;
3556 }
3557
3558 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3559 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3560 /* account for \'0' */
3561 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3562
3563 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3564 {
3565         assert_spin_locked(&pipe_crc->lock);
3566         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3567                         INTEL_PIPE_CRC_ENTRIES_NR);
3568 }
3569
3570 static ssize_t
3571 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3572                    loff_t *pos)
3573 {
3574         struct pipe_crc_info *info = filep->private_data;
3575         struct drm_i915_private *dev_priv = info->dev_priv;
3576         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3577         char buf[PIPE_CRC_BUFFER_LEN];
3578         int n_entries;
3579         ssize_t bytes_read;
3580
3581         /*
3582          * Don't allow user space to provide buffers not big enough to hold
3583          * a line of data.
3584          */
3585         if (count < PIPE_CRC_LINE_LEN)
3586                 return -EINVAL;
3587
3588         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3589                 return 0;
3590
3591         /* nothing to read */
3592         spin_lock_irq(&pipe_crc->lock);
3593         while (pipe_crc_data_count(pipe_crc) == 0) {
3594                 int ret;
3595
3596                 if (filep->f_flags & O_NONBLOCK) {
3597                         spin_unlock_irq(&pipe_crc->lock);
3598                         return -EAGAIN;
3599                 }
3600
3601                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3602                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3603                 if (ret) {
3604                         spin_unlock_irq(&pipe_crc->lock);
3605                         return ret;
3606                 }
3607         }
3608
3609         /* We now have one or more entries to read */
3610         n_entries = count / PIPE_CRC_LINE_LEN;
3611
3612         bytes_read = 0;
3613         while (n_entries > 0) {
3614                 struct intel_pipe_crc_entry *entry =
3615                         &pipe_crc->entries[pipe_crc->tail];
3616
3617                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3618                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3619                         break;
3620
3621                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3622                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3623
3624                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3625                                        "%8u %8x %8x %8x %8x %8x\n",
3626                                        entry->frame, entry->crc[0],
3627                                        entry->crc[1], entry->crc[2],
3628                                        entry->crc[3], entry->crc[4]);
3629
3630                 spin_unlock_irq(&pipe_crc->lock);
3631
3632                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3633                         return -EFAULT;
3634
3635                 user_buf += PIPE_CRC_LINE_LEN;
3636                 n_entries--;
3637
3638                 spin_lock_irq(&pipe_crc->lock);
3639         }
3640
3641         spin_unlock_irq(&pipe_crc->lock);
3642
3643         return bytes_read;
3644 }
3645
3646 static const struct file_operations i915_pipe_crc_fops = {
3647         .owner = THIS_MODULE,
3648         .open = i915_pipe_crc_open,
3649         .read = i915_pipe_crc_read,
3650         .release = i915_pipe_crc_release,
3651 };
3652
3653 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3654         {
3655                 .name = "i915_pipe_A_crc",
3656                 .pipe = PIPE_A,
3657         },
3658         {
3659                 .name = "i915_pipe_B_crc",
3660                 .pipe = PIPE_B,
3661         },
3662         {
3663                 .name = "i915_pipe_C_crc",
3664                 .pipe = PIPE_C,
3665         },
3666 };
3667
3668 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3669                                 enum pipe pipe)
3670 {
3671         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3672         struct dentry *ent;
3673         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3674
3675         info->dev_priv = dev_priv;
3676         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3677                                   &i915_pipe_crc_fops);
3678         if (!ent)
3679                 return -ENOMEM;
3680
3681         return drm_add_fake_info_node(minor, ent, info);
3682 }
3683
3684 static const char * const pipe_crc_sources[] = {
3685         "none",
3686         "plane1",
3687         "plane2",
3688         "pf",
3689         "pipe",
3690         "TV",
3691         "DP-B",
3692         "DP-C",
3693         "DP-D",
3694         "auto",
3695 };
3696
3697 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3698 {
3699         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3700         return pipe_crc_sources[source];
3701 }
3702
3703 static int display_crc_ctl_show(struct seq_file *m, void *data)
3704 {
3705         struct drm_i915_private *dev_priv = m->private;
3706         int i;
3707
3708         for (i = 0; i < I915_MAX_PIPES; i++)
3709                 seq_printf(m, "%c %s\n", pipe_name(i),
3710                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3711
3712         return 0;
3713 }
3714
3715 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3716 {
3717         return single_open(file, display_crc_ctl_show, inode->i_private);
3718 }
3719
3720 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3721                                  uint32_t *val)
3722 {
3723         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3724                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3725
3726         switch (*source) {
3727         case INTEL_PIPE_CRC_SOURCE_PIPE:
3728                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3729                 break;
3730         case INTEL_PIPE_CRC_SOURCE_NONE:
3731                 *val = 0;
3732                 break;
3733         default:
3734                 return -EINVAL;
3735         }
3736
3737         return 0;
3738 }
3739
3740 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3741                                      enum pipe pipe,
3742                                      enum intel_pipe_crc_source *source)
3743 {
3744         struct drm_device *dev = &dev_priv->drm;
3745         struct intel_encoder *encoder;
3746         struct intel_crtc *crtc;
3747         struct intel_digital_port *dig_port;
3748         int ret = 0;
3749
3750         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3751
3752         drm_modeset_lock_all(dev);
3753         for_each_intel_encoder(dev, encoder) {
3754                 if (!encoder->base.crtc)
3755                         continue;
3756
3757                 crtc = to_intel_crtc(encoder->base.crtc);
3758
3759                 if (crtc->pipe != pipe)
3760                         continue;
3761
3762                 switch (encoder->type) {
3763                 case INTEL_OUTPUT_TVOUT:
3764                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3765                         break;
3766                 case INTEL_OUTPUT_DP:
3767                 case INTEL_OUTPUT_EDP:
3768                         dig_port = enc_to_dig_port(&encoder->base);
3769                         switch (dig_port->port) {
3770                         case PORT_B:
3771                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3772                                 break;
3773                         case PORT_C:
3774                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3775                                 break;
3776                         case PORT_D:
3777                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3778                                 break;
3779                         default:
3780                                 WARN(1, "nonexisting DP port %c\n",
3781                                      port_name(dig_port->port));
3782                                 break;
3783                         }
3784                         break;
3785                 default:
3786                         break;
3787                 }
3788         }
3789         drm_modeset_unlock_all(dev);
3790
3791         return ret;
3792 }
3793
3794 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3795                                 enum pipe pipe,
3796                                 enum intel_pipe_crc_source *source,
3797                                 uint32_t *val)
3798 {
3799         bool need_stable_symbols = false;
3800
3801         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3802                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3803                 if (ret)
3804                         return ret;
3805         }
3806
3807         switch (*source) {
3808         case INTEL_PIPE_CRC_SOURCE_PIPE:
3809                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3810                 break;
3811         case INTEL_PIPE_CRC_SOURCE_DP_B:
3812                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3813                 need_stable_symbols = true;
3814                 break;
3815         case INTEL_PIPE_CRC_SOURCE_DP_C:
3816                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3817                 need_stable_symbols = true;
3818                 break;
3819         case INTEL_PIPE_CRC_SOURCE_DP_D:
3820                 if (!IS_CHERRYVIEW(dev_priv))
3821                         return -EINVAL;
3822                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3823                 need_stable_symbols = true;
3824                 break;
3825         case INTEL_PIPE_CRC_SOURCE_NONE:
3826                 *val = 0;
3827                 break;
3828         default:
3829                 return -EINVAL;
3830         }
3831
3832         /*
3833          * When the pipe CRC tap point is after the transcoders we need
3834          * to tweak symbol-level features to produce a deterministic series of
3835          * symbols for a given frame. We need to reset those features only once
3836          * a frame (instead of every nth symbol):
3837          *   - DC-balance: used to ensure a better clock recovery from the data
3838          *     link (SDVO)
3839          *   - DisplayPort scrambling: used for EMI reduction
3840          */
3841         if (need_stable_symbols) {
3842                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3843
3844                 tmp |= DC_BALANCE_RESET_VLV;
3845                 switch (pipe) {
3846                 case PIPE_A:
3847                         tmp |= PIPE_A_SCRAMBLE_RESET;
3848                         break;
3849                 case PIPE_B:
3850                         tmp |= PIPE_B_SCRAMBLE_RESET;
3851                         break;
3852                 case PIPE_C:
3853                         tmp |= PIPE_C_SCRAMBLE_RESET;
3854                         break;
3855                 default:
3856                         return -EINVAL;
3857                 }
3858                 I915_WRITE(PORT_DFT2_G4X, tmp);
3859         }
3860
3861         return 0;
3862 }
3863
3864 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3865                                  enum pipe pipe,
3866                                  enum intel_pipe_crc_source *source,
3867                                  uint32_t *val)
3868 {
3869         bool need_stable_symbols = false;
3870
3871         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3872                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3873                 if (ret)
3874                         return ret;
3875         }
3876
3877         switch (*source) {
3878         case INTEL_PIPE_CRC_SOURCE_PIPE:
3879                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3880                 break;
3881         case INTEL_PIPE_CRC_SOURCE_TV:
3882                 if (!SUPPORTS_TV(dev_priv))
3883                         return -EINVAL;
3884                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3885                 break;
3886         case INTEL_PIPE_CRC_SOURCE_DP_B:
3887                 if (!IS_G4X(dev_priv))
3888                         return -EINVAL;
3889                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3890                 need_stable_symbols = true;
3891                 break;
3892         case INTEL_PIPE_CRC_SOURCE_DP_C:
3893                 if (!IS_G4X(dev_priv))
3894                         return -EINVAL;
3895                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3896                 need_stable_symbols = true;
3897                 break;
3898         case INTEL_PIPE_CRC_SOURCE_DP_D:
3899                 if (!IS_G4X(dev_priv))
3900                         return -EINVAL;
3901                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3902                 need_stable_symbols = true;
3903                 break;
3904         case INTEL_PIPE_CRC_SOURCE_NONE:
3905                 *val = 0;
3906                 break;
3907         default:
3908                 return -EINVAL;
3909         }
3910
3911         /*
3912          * When the pipe CRC tap point is after the transcoders we need
3913          * to tweak symbol-level features to produce a deterministic series of
3914          * symbols for a given frame. We need to reset those features only once
3915          * a frame (instead of every nth symbol):
3916          *   - DC-balance: used to ensure a better clock recovery from the data
3917          *     link (SDVO)
3918          *   - DisplayPort scrambling: used for EMI reduction
3919          */
3920         if (need_stable_symbols) {
3921                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3922
3923                 WARN_ON(!IS_G4X(dev_priv));
3924
3925                 I915_WRITE(PORT_DFT_I9XX,
3926                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3927
3928                 if (pipe == PIPE_A)
3929                         tmp |= PIPE_A_SCRAMBLE_RESET;
3930                 else
3931                         tmp |= PIPE_B_SCRAMBLE_RESET;
3932
3933                 I915_WRITE(PORT_DFT2_G4X, tmp);
3934         }
3935
3936         return 0;
3937 }
3938
3939 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3940                                          enum pipe pipe)
3941 {
3942         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3943
3944         switch (pipe) {
3945         case PIPE_A:
3946                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3947                 break;
3948         case PIPE_B:
3949                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3950                 break;
3951         case PIPE_C:
3952                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3953                 break;
3954         default:
3955                 return;
3956         }
3957         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3958                 tmp &= ~DC_BALANCE_RESET_VLV;
3959         I915_WRITE(PORT_DFT2_G4X, tmp);
3960
3961 }
3962
3963 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3964                                          enum pipe pipe)
3965 {
3966         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3967
3968         if (pipe == PIPE_A)
3969                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3970         else
3971                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3972         I915_WRITE(PORT_DFT2_G4X, tmp);
3973
3974         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3975                 I915_WRITE(PORT_DFT_I9XX,
3976                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3977         }
3978 }
3979
3980 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3981                                 uint32_t *val)
3982 {
3983         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3984                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3985
3986         switch (*source) {
3987         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3988                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3989                 break;
3990         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3991                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3992                 break;
3993         case INTEL_PIPE_CRC_SOURCE_PIPE:
3994                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3995                 break;
3996         case INTEL_PIPE_CRC_SOURCE_NONE:
3997                 *val = 0;
3998                 break;
3999         default:
4000                 return -EINVAL;
4001         }
4002
4003         return 0;
4004 }
4005
4006 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4007                                         bool enable)
4008 {
4009         struct drm_device *dev = &dev_priv->drm;
4010         struct intel_crtc *crtc =
4011                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4012         struct intel_crtc_state *pipe_config;
4013         struct drm_atomic_state *state;
4014         int ret = 0;
4015
4016         drm_modeset_lock_all(dev);
4017         state = drm_atomic_state_alloc(dev);
4018         if (!state) {
4019                 ret = -ENOMEM;
4020                 goto out;
4021         }
4022
4023         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4024         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4025         if (IS_ERR(pipe_config)) {
4026                 ret = PTR_ERR(pipe_config);
4027                 goto out;
4028         }
4029
4030         pipe_config->pch_pfit.force_thru = enable;
4031         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4032             pipe_config->pch_pfit.enabled != enable)
4033                 pipe_config->base.connectors_changed = true;
4034
4035         ret = drm_atomic_commit(state);
4036 out:
4037         drm_modeset_unlock_all(dev);
4038         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4039         if (ret)
4040                 drm_atomic_state_free(state);
4041 }
4042
4043 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4044                                 enum pipe pipe,
4045                                 enum intel_pipe_crc_source *source,
4046                                 uint32_t *val)
4047 {
4048         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4049                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4050
4051         switch (*source) {
4052         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4053                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4054                 break;
4055         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4056                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4057                 break;
4058         case INTEL_PIPE_CRC_SOURCE_PF:
4059                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4060                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4061
4062                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4063                 break;
4064         case INTEL_PIPE_CRC_SOURCE_NONE:
4065                 *val = 0;
4066                 break;
4067         default:
4068                 return -EINVAL;
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4075                                enum pipe pipe,
4076                                enum intel_pipe_crc_source source)
4077 {
4078         struct drm_device *dev = &dev_priv->drm;
4079         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4080         struct intel_crtc *crtc =
4081                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4082         enum intel_display_power_domain power_domain;
4083         u32 val = 0; /* shut up gcc */
4084         int ret;
4085
4086         if (pipe_crc->source == source)
4087                 return 0;
4088
4089         /* forbid changing the source without going back to 'none' */
4090         if (pipe_crc->source && source)
4091                 return -EINVAL;
4092
4093         power_domain = POWER_DOMAIN_PIPE(pipe);
4094         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4095                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4096                 return -EIO;
4097         }
4098
4099         if (IS_GEN2(dev_priv))
4100                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4101         else if (INTEL_GEN(dev_priv) < 5)
4102                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4103         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4104                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4105         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4106                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4107         else
4108                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4109
4110         if (ret != 0)
4111                 goto out;
4112
4113         /* none -> real source transition */
4114         if (source) {
4115                 struct intel_pipe_crc_entry *entries;
4116
4117                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4118                                  pipe_name(pipe), pipe_crc_source_name(source));
4119
4120                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4121                                   sizeof(pipe_crc->entries[0]),
4122                                   GFP_KERNEL);
4123                 if (!entries) {
4124                         ret = -ENOMEM;
4125                         goto out;
4126                 }
4127
4128                 /*
4129                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4130                  * enabled and disabled dynamically based on package C states,
4131                  * user space can't make reliable use of the CRCs, so let's just
4132                  * completely disable it.
4133                  */
4134                 hsw_disable_ips(crtc);
4135
4136                 spin_lock_irq(&pipe_crc->lock);
4137                 kfree(pipe_crc->entries);
4138                 pipe_crc->entries = entries;
4139                 pipe_crc->head = 0;
4140                 pipe_crc->tail = 0;
4141                 spin_unlock_irq(&pipe_crc->lock);
4142         }
4143
4144         pipe_crc->source = source;
4145
4146         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4147         POSTING_READ(PIPE_CRC_CTL(pipe));
4148
4149         /* real source -> none transition */
4150         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4151                 struct intel_pipe_crc_entry *entries;
4152                 struct intel_crtc *crtc =
4153                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4154
4155                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4156                                  pipe_name(pipe));
4157
4158                 drm_modeset_lock(&crtc->base.mutex, NULL);
4159                 if (crtc->base.state->active)
4160                         intel_wait_for_vblank(dev, pipe);
4161                 drm_modeset_unlock(&crtc->base.mutex);
4162
4163                 spin_lock_irq(&pipe_crc->lock);
4164                 entries = pipe_crc->entries;
4165                 pipe_crc->entries = NULL;
4166                 pipe_crc->head = 0;
4167                 pipe_crc->tail = 0;
4168                 spin_unlock_irq(&pipe_crc->lock);
4169
4170                 kfree(entries);
4171
4172                 if (IS_G4X(dev_priv))
4173                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4174                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4175                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4176                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4177                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4178
4179                 hsw_enable_ips(crtc);
4180         }
4181
4182         ret = 0;
4183
4184 out:
4185         intel_display_power_put(dev_priv, power_domain);
4186
4187         return ret;
4188 }
4189
4190 /*
4191  * Parse pipe CRC command strings:
4192  *   command: wsp* object wsp+ name wsp+ source wsp*
4193  *   object: 'pipe'
4194  *   name: (A | B | C)
4195  *   source: (none | plane1 | plane2 | pf)
4196  *   wsp: (#0x20 | #0x9 | #0xA)+
4197  *
4198  * eg.:
4199  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4200  *  "pipe A none"    ->  Stop CRC
4201  */
4202 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4203 {
4204         int n_words = 0;
4205
4206         while (*buf) {
4207                 char *end;
4208
4209                 /* skip leading white space */
4210                 buf = skip_spaces(buf);
4211                 if (!*buf)
4212                         break;  /* end of buffer */
4213
4214                 /* find end of word */
4215                 for (end = buf; *end && !isspace(*end); end++)
4216                         ;
4217
4218                 if (n_words == max_words) {
4219                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4220                                          max_words);
4221                         return -EINVAL; /* ran out of words[] before bytes */
4222                 }
4223
4224                 if (*end)
4225                         *end++ = '\0';
4226                 words[n_words++] = buf;
4227                 buf = end;
4228         }
4229
4230         return n_words;
4231 }
4232
4233 enum intel_pipe_crc_object {
4234         PIPE_CRC_OBJECT_PIPE,
4235 };
4236
4237 static const char * const pipe_crc_objects[] = {
4238         "pipe",
4239 };
4240
4241 static int
4242 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4243 {
4244         int i;
4245
4246         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4247                 if (!strcmp(buf, pipe_crc_objects[i])) {
4248                         *o = i;
4249                         return 0;
4250                     }
4251
4252         return -EINVAL;
4253 }
4254
4255 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4256 {
4257         const char name = buf[0];
4258
4259         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4260                 return -EINVAL;
4261
4262         *pipe = name - 'A';
4263
4264         return 0;
4265 }
4266
4267 static int
4268 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4269 {
4270         int i;
4271
4272         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4273                 if (!strcmp(buf, pipe_crc_sources[i])) {
4274                         *s = i;
4275                         return 0;
4276                     }
4277
4278         return -EINVAL;
4279 }
4280
4281 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4282                                  char *buf, size_t len)
4283 {
4284 #define N_WORDS 3
4285         int n_words;
4286         char *words[N_WORDS];
4287         enum pipe pipe;
4288         enum intel_pipe_crc_object object;
4289         enum intel_pipe_crc_source source;
4290
4291         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4292         if (n_words != N_WORDS) {
4293                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4294                                  N_WORDS);
4295                 return -EINVAL;
4296         }
4297
4298         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4299                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4300                 return -EINVAL;
4301         }
4302
4303         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4304                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4305                 return -EINVAL;
4306         }
4307
4308         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4309                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4310                 return -EINVAL;
4311         }
4312
4313         return pipe_crc_set_source(dev_priv, pipe, source);
4314 }
4315
4316 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4317                                      size_t len, loff_t *offp)
4318 {
4319         struct seq_file *m = file->private_data;
4320         struct drm_i915_private *dev_priv = m->private;
4321         char *tmpbuf;
4322         int ret;
4323
4324         if (len == 0)
4325                 return 0;
4326
4327         if (len > PAGE_SIZE - 1) {
4328                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4329                                  PAGE_SIZE);
4330                 return -E2BIG;
4331         }
4332
4333         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4334         if (!tmpbuf)
4335                 return -ENOMEM;
4336
4337         if (copy_from_user(tmpbuf, ubuf, len)) {
4338                 ret = -EFAULT;
4339                 goto out;
4340         }
4341         tmpbuf[len] = '\0';
4342
4343         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4344
4345 out:
4346         kfree(tmpbuf);
4347         if (ret < 0)
4348                 return ret;
4349
4350         *offp += len;
4351         return len;
4352 }
4353
4354 static const struct file_operations i915_display_crc_ctl_fops = {
4355         .owner = THIS_MODULE,
4356         .open = display_crc_ctl_open,
4357         .read = seq_read,
4358         .llseek = seq_lseek,
4359         .release = single_release,
4360         .write = display_crc_ctl_write
4361 };
4362
4363 static ssize_t i915_displayport_test_active_write(struct file *file,
4364                                                   const char __user *ubuf,
4365                                                   size_t len, loff_t *offp)
4366 {
4367         char *input_buffer;
4368         int status = 0;
4369         struct drm_device *dev;
4370         struct drm_connector *connector;
4371         struct list_head *connector_list;
4372         struct intel_dp *intel_dp;
4373         int val = 0;
4374
4375         dev = ((struct seq_file *)file->private_data)->private;
4376
4377         connector_list = &dev->mode_config.connector_list;
4378
4379         if (len == 0)
4380                 return 0;
4381
4382         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4383         if (!input_buffer)
4384                 return -ENOMEM;
4385
4386         if (copy_from_user(input_buffer, ubuf, len)) {
4387                 status = -EFAULT;
4388                 goto out;
4389         }
4390
4391         input_buffer[len] = '\0';
4392         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4393
4394         list_for_each_entry(connector, connector_list, head) {
4395                 if (connector->connector_type !=
4396                     DRM_MODE_CONNECTOR_DisplayPort)
4397                         continue;
4398
4399                 if (connector->status == connector_status_connected &&
4400                     connector->encoder != NULL) {
4401                         intel_dp = enc_to_intel_dp(connector->encoder);
4402                         status = kstrtoint(input_buffer, 10, &val);
4403                         if (status < 0)
4404                                 goto out;
4405                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4406                         /* To prevent erroneous activation of the compliance
4407                          * testing code, only accept an actual value of 1 here
4408                          */
4409                         if (val == 1)
4410                                 intel_dp->compliance_test_active = 1;
4411                         else
4412                                 intel_dp->compliance_test_active = 0;
4413                 }
4414         }
4415 out:
4416         kfree(input_buffer);
4417         if (status < 0)
4418                 return status;
4419
4420         *offp += len;
4421         return len;
4422 }
4423
4424 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4425 {
4426         struct drm_device *dev = m->private;
4427         struct drm_connector *connector;
4428         struct list_head *connector_list = &dev->mode_config.connector_list;
4429         struct intel_dp *intel_dp;
4430
4431         list_for_each_entry(connector, connector_list, head) {
4432                 if (connector->connector_type !=
4433                     DRM_MODE_CONNECTOR_DisplayPort)
4434                         continue;
4435
4436                 if (connector->status == connector_status_connected &&
4437                     connector->encoder != NULL) {
4438                         intel_dp = enc_to_intel_dp(connector->encoder);
4439                         if (intel_dp->compliance_test_active)
4440                                 seq_puts(m, "1");
4441                         else
4442                                 seq_puts(m, "0");
4443                 } else
4444                         seq_puts(m, "0");
4445         }
4446
4447         return 0;
4448 }
4449
4450 static int i915_displayport_test_active_open(struct inode *inode,
4451                                              struct file *file)
4452 {
4453         struct drm_i915_private *dev_priv = inode->i_private;
4454
4455         return single_open(file, i915_displayport_test_active_show,
4456                            &dev_priv->drm);
4457 }
4458
4459 static const struct file_operations i915_displayport_test_active_fops = {
4460         .owner = THIS_MODULE,
4461         .open = i915_displayport_test_active_open,
4462         .read = seq_read,
4463         .llseek = seq_lseek,
4464         .release = single_release,
4465         .write = i915_displayport_test_active_write
4466 };
4467
4468 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4469 {
4470         struct drm_device *dev = m->private;
4471         struct drm_connector *connector;
4472         struct list_head *connector_list = &dev->mode_config.connector_list;
4473         struct intel_dp *intel_dp;
4474
4475         list_for_each_entry(connector, connector_list, head) {
4476                 if (connector->connector_type !=
4477                     DRM_MODE_CONNECTOR_DisplayPort)
4478                         continue;
4479
4480                 if (connector->status == connector_status_connected &&
4481                     connector->encoder != NULL) {
4482                         intel_dp = enc_to_intel_dp(connector->encoder);
4483                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4484                 } else
4485                         seq_puts(m, "0");
4486         }
4487
4488         return 0;
4489 }
4490 static int i915_displayport_test_data_open(struct inode *inode,
4491                                            struct file *file)
4492 {
4493         struct drm_i915_private *dev_priv = inode->i_private;
4494
4495         return single_open(file, i915_displayport_test_data_show,
4496                            &dev_priv->drm);
4497 }
4498
4499 static const struct file_operations i915_displayport_test_data_fops = {
4500         .owner = THIS_MODULE,
4501         .open = i915_displayport_test_data_open,
4502         .read = seq_read,
4503         .llseek = seq_lseek,
4504         .release = single_release
4505 };
4506
4507 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4508 {
4509         struct drm_device *dev = m->private;
4510         struct drm_connector *connector;
4511         struct list_head *connector_list = &dev->mode_config.connector_list;
4512         struct intel_dp *intel_dp;
4513
4514         list_for_each_entry(connector, connector_list, head) {
4515                 if (connector->connector_type !=
4516                     DRM_MODE_CONNECTOR_DisplayPort)
4517                         continue;
4518
4519                 if (connector->status == connector_status_connected &&
4520                     connector->encoder != NULL) {
4521                         intel_dp = enc_to_intel_dp(connector->encoder);
4522                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4523                 } else
4524                         seq_puts(m, "0");
4525         }
4526
4527         return 0;
4528 }
4529
4530 static int i915_displayport_test_type_open(struct inode *inode,
4531                                        struct file *file)
4532 {
4533         struct drm_i915_private *dev_priv = inode->i_private;
4534
4535         return single_open(file, i915_displayport_test_type_show,
4536                            &dev_priv->drm);
4537 }
4538
4539 static const struct file_operations i915_displayport_test_type_fops = {
4540         .owner = THIS_MODULE,
4541         .open = i915_displayport_test_type_open,
4542         .read = seq_read,
4543         .llseek = seq_lseek,
4544         .release = single_release
4545 };
4546
4547 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4548 {
4549         struct drm_i915_private *dev_priv = m->private;
4550         struct drm_device *dev = &dev_priv->drm;
4551         int level;
4552         int num_levels;
4553
4554         if (IS_CHERRYVIEW(dev_priv))
4555                 num_levels = 3;
4556         else if (IS_VALLEYVIEW(dev_priv))
4557                 num_levels = 1;
4558         else
4559                 num_levels = ilk_wm_max_level(dev) + 1;
4560
4561         drm_modeset_lock_all(dev);
4562
4563         for (level = 0; level < num_levels; level++) {
4564                 unsigned int latency = wm[level];
4565
4566                 /*
4567                  * - WM1+ latency values in 0.5us units
4568                  * - latencies are in us on gen9/vlv/chv
4569                  */
4570                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4571                     IS_CHERRYVIEW(dev_priv))
4572                         latency *= 10;
4573                 else if (level > 0)
4574                         latency *= 5;
4575
4576                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4577                            level, wm[level], latency / 10, latency % 10);
4578         }
4579
4580         drm_modeset_unlock_all(dev);
4581 }
4582
4583 static int pri_wm_latency_show(struct seq_file *m, void *data)
4584 {
4585         struct drm_i915_private *dev_priv = m->private;
4586         const uint16_t *latencies;
4587
4588         if (INTEL_GEN(dev_priv) >= 9)
4589                 latencies = dev_priv->wm.skl_latency;
4590         else
4591                 latencies = dev_priv->wm.pri_latency;
4592
4593         wm_latency_show(m, latencies);
4594
4595         return 0;
4596 }
4597
4598 static int spr_wm_latency_show(struct seq_file *m, void *data)
4599 {
4600         struct drm_i915_private *dev_priv = m->private;
4601         const uint16_t *latencies;
4602
4603         if (INTEL_GEN(dev_priv) >= 9)
4604                 latencies = dev_priv->wm.skl_latency;
4605         else
4606                 latencies = dev_priv->wm.spr_latency;
4607
4608         wm_latency_show(m, latencies);
4609
4610         return 0;
4611 }
4612
4613 static int cur_wm_latency_show(struct seq_file *m, void *data)
4614 {
4615         struct drm_i915_private *dev_priv = m->private;
4616         const uint16_t *latencies;
4617
4618         if (INTEL_GEN(dev_priv) >= 9)
4619                 latencies = dev_priv->wm.skl_latency;
4620         else
4621                 latencies = dev_priv->wm.cur_latency;
4622
4623         wm_latency_show(m, latencies);
4624
4625         return 0;
4626 }
4627
4628 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4629 {
4630         struct drm_i915_private *dev_priv = inode->i_private;
4631
4632         if (INTEL_GEN(dev_priv) < 5)
4633                 return -ENODEV;
4634
4635         return single_open(file, pri_wm_latency_show, dev_priv);
4636 }
4637
4638 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4639 {
4640         struct drm_i915_private *dev_priv = inode->i_private;
4641
4642         if (HAS_GMCH_DISPLAY(dev_priv))
4643                 return -ENODEV;
4644
4645         return single_open(file, spr_wm_latency_show, dev_priv);
4646 }
4647
4648 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4649 {
4650         struct drm_i915_private *dev_priv = inode->i_private;
4651
4652         if (HAS_GMCH_DISPLAY(dev_priv))
4653                 return -ENODEV;
4654
4655         return single_open(file, cur_wm_latency_show, dev_priv);
4656 }
4657
4658 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4659                                 size_t len, loff_t *offp, uint16_t wm[8])
4660 {
4661         struct seq_file *m = file->private_data;
4662         struct drm_i915_private *dev_priv = m->private;
4663         struct drm_device *dev = &dev_priv->drm;
4664         uint16_t new[8] = { 0 };
4665         int num_levels;
4666         int level;
4667         int ret;
4668         char tmp[32];
4669
4670         if (IS_CHERRYVIEW(dev_priv))
4671                 num_levels = 3;
4672         else if (IS_VALLEYVIEW(dev_priv))
4673                 num_levels = 1;
4674         else
4675                 num_levels = ilk_wm_max_level(dev) + 1;
4676
4677         if (len >= sizeof(tmp))
4678                 return -EINVAL;
4679
4680         if (copy_from_user(tmp, ubuf, len))
4681                 return -EFAULT;
4682
4683         tmp[len] = '\0';
4684
4685         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4686                      &new[0], &new[1], &new[2], &new[3],
4687                      &new[4], &new[5], &new[6], &new[7]);
4688         if (ret != num_levels)
4689                 return -EINVAL;
4690
4691         drm_modeset_lock_all(dev);
4692
4693         for (level = 0; level < num_levels; level++)
4694                 wm[level] = new[level];
4695
4696         drm_modeset_unlock_all(dev);
4697
4698         return len;
4699 }
4700
4701
4702 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4703                                     size_t len, loff_t *offp)
4704 {
4705         struct seq_file *m = file->private_data;
4706         struct drm_i915_private *dev_priv = m->private;
4707         uint16_t *latencies;
4708
4709         if (INTEL_GEN(dev_priv) >= 9)
4710                 latencies = dev_priv->wm.skl_latency;
4711         else
4712                 latencies = dev_priv->wm.pri_latency;
4713
4714         return wm_latency_write(file, ubuf, len, offp, latencies);
4715 }
4716
4717 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4718                                     size_t len, loff_t *offp)
4719 {
4720         struct seq_file *m = file->private_data;
4721         struct drm_i915_private *dev_priv = m->private;
4722         uint16_t *latencies;
4723
4724         if (INTEL_GEN(dev_priv) >= 9)
4725                 latencies = dev_priv->wm.skl_latency;
4726         else
4727                 latencies = dev_priv->wm.spr_latency;
4728
4729         return wm_latency_write(file, ubuf, len, offp, latencies);
4730 }
4731
4732 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4733                                     size_t len, loff_t *offp)
4734 {
4735         struct seq_file *m = file->private_data;
4736         struct drm_i915_private *dev_priv = m->private;
4737         uint16_t *latencies;
4738
4739         if (INTEL_GEN(dev_priv) >= 9)
4740                 latencies = dev_priv->wm.skl_latency;
4741         else
4742                 latencies = dev_priv->wm.cur_latency;
4743
4744         return wm_latency_write(file, ubuf, len, offp, latencies);
4745 }
4746
4747 static const struct file_operations i915_pri_wm_latency_fops = {
4748         .owner = THIS_MODULE,
4749         .open = pri_wm_latency_open,
4750         .read = seq_read,
4751         .llseek = seq_lseek,
4752         .release = single_release,
4753         .write = pri_wm_latency_write
4754 };
4755
4756 static const struct file_operations i915_spr_wm_latency_fops = {
4757         .owner = THIS_MODULE,
4758         .open = spr_wm_latency_open,
4759         .read = seq_read,
4760         .llseek = seq_lseek,
4761         .release = single_release,
4762         .write = spr_wm_latency_write
4763 };
4764
4765 static const struct file_operations i915_cur_wm_latency_fops = {
4766         .owner = THIS_MODULE,
4767         .open = cur_wm_latency_open,
4768         .read = seq_read,
4769         .llseek = seq_lseek,
4770         .release = single_release,
4771         .write = cur_wm_latency_write
4772 };
4773
4774 static int
4775 i915_wedged_get(void *data, u64 *val)
4776 {
4777         struct drm_i915_private *dev_priv = data;
4778
4779         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4780
4781         return 0;
4782 }
4783
4784 static int
4785 i915_wedged_set(void *data, u64 val)
4786 {
4787         struct drm_i915_private *dev_priv = data;
4788
4789         /*
4790          * There is no safeguard against this debugfs entry colliding
4791          * with the hangcheck calling same i915_handle_error() in
4792          * parallel, causing an explosion. For now we assume that the
4793          * test harness is responsible enough not to inject gpu hangs
4794          * while it is writing to 'i915_wedged'
4795          */
4796
4797         if (i915_reset_in_progress(&dev_priv->gpu_error))
4798                 return -EAGAIN;
4799
4800         intel_runtime_pm_get(dev_priv);
4801
4802         i915_handle_error(dev_priv, val,
4803                           "Manually setting wedged to %llu", val);
4804
4805         intel_runtime_pm_put(dev_priv);
4806
4807         return 0;
4808 }
4809
4810 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4811                         i915_wedged_get, i915_wedged_set,
4812                         "%llu\n");
4813
4814 static int
4815 i915_ring_missed_irq_get(void *data, u64 *val)
4816 {
4817         struct drm_i915_private *dev_priv = data;
4818
4819         *val = dev_priv->gpu_error.missed_irq_rings;
4820         return 0;
4821 }
4822
4823 static int
4824 i915_ring_missed_irq_set(void *data, u64 val)
4825 {
4826         struct drm_i915_private *dev_priv = data;
4827         struct drm_device *dev = &dev_priv->drm;
4828         int ret;
4829
4830         /* Lock against concurrent debugfs callers */
4831         ret = mutex_lock_interruptible(&dev->struct_mutex);
4832         if (ret)
4833                 return ret;
4834         dev_priv->gpu_error.missed_irq_rings = val;
4835         mutex_unlock(&dev->struct_mutex);
4836
4837         return 0;
4838 }
4839
4840 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4841                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4842                         "0x%08llx\n");
4843
4844 static int
4845 i915_ring_test_irq_get(void *data, u64 *val)
4846 {
4847         struct drm_i915_private *dev_priv = data;
4848
4849         *val = dev_priv->gpu_error.test_irq_rings;
4850
4851         return 0;
4852 }
4853
4854 static int
4855 i915_ring_test_irq_set(void *data, u64 val)
4856 {
4857         struct drm_i915_private *dev_priv = data;
4858
4859         val &= INTEL_INFO(dev_priv)->ring_mask;
4860         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4861         dev_priv->gpu_error.test_irq_rings = val;
4862
4863         return 0;
4864 }
4865
4866 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4867                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4868                         "0x%08llx\n");
4869
4870 #define DROP_UNBOUND 0x1
4871 #define DROP_BOUND 0x2
4872 #define DROP_RETIRE 0x4
4873 #define DROP_ACTIVE 0x8
4874 #define DROP_ALL (DROP_UNBOUND | \
4875                   DROP_BOUND | \
4876                   DROP_RETIRE | \
4877                   DROP_ACTIVE)
4878 static int
4879 i915_drop_caches_get(void *data, u64 *val)
4880 {
4881         *val = DROP_ALL;
4882
4883         return 0;
4884 }
4885
4886 static int
4887 i915_drop_caches_set(void *data, u64 val)
4888 {
4889         struct drm_i915_private *dev_priv = data;
4890         struct drm_device *dev = &dev_priv->drm;
4891         int ret;
4892
4893         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4894
4895         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4896          * on ioctls on -EAGAIN. */
4897         ret = mutex_lock_interruptible(&dev->struct_mutex);
4898         if (ret)
4899                 return ret;
4900
4901         if (val & DROP_ACTIVE) {
4902                 ret = i915_gem_wait_for_idle(dev_priv,
4903                                              I915_WAIT_INTERRUPTIBLE |
4904                                              I915_WAIT_LOCKED);
4905                 if (ret)
4906                         goto unlock;
4907         }
4908
4909         if (val & (DROP_RETIRE | DROP_ACTIVE))
4910                 i915_gem_retire_requests(dev_priv);
4911
4912         if (val & DROP_BOUND)
4913                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4914
4915         if (val & DROP_UNBOUND)
4916                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4917
4918 unlock:
4919         mutex_unlock(&dev->struct_mutex);
4920
4921         return ret;
4922 }
4923
4924 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4925                         i915_drop_caches_get, i915_drop_caches_set,
4926                         "0x%08llx\n");
4927
4928 static int
4929 i915_max_freq_get(void *data, u64 *val)
4930 {
4931         struct drm_i915_private *dev_priv = data;
4932
4933         if (INTEL_GEN(dev_priv) < 6)
4934                 return -ENODEV;
4935
4936         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4937         return 0;
4938 }
4939
4940 static int
4941 i915_max_freq_set(void *data, u64 val)
4942 {
4943         struct drm_i915_private *dev_priv = data;
4944         u32 hw_max, hw_min;
4945         int ret;
4946
4947         if (INTEL_GEN(dev_priv) < 6)
4948                 return -ENODEV;
4949
4950         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4951
4952         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4953         if (ret)
4954                 return ret;
4955
4956         /*
4957          * Turbo will still be enabled, but won't go above the set value.
4958          */
4959         val = intel_freq_opcode(dev_priv, val);
4960
4961         hw_max = dev_priv->rps.max_freq;
4962         hw_min = dev_priv->rps.min_freq;
4963
4964         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4965                 mutex_unlock(&dev_priv->rps.hw_lock);
4966                 return -EINVAL;
4967         }
4968
4969         dev_priv->rps.max_freq_softlimit = val;
4970
4971         intel_set_rps(dev_priv, val);
4972
4973         mutex_unlock(&dev_priv->rps.hw_lock);
4974
4975         return 0;
4976 }
4977
4978 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4979                         i915_max_freq_get, i915_max_freq_set,
4980                         "%llu\n");
4981
4982 static int
4983 i915_min_freq_get(void *data, u64 *val)
4984 {
4985         struct drm_i915_private *dev_priv = data;
4986
4987         if (INTEL_GEN(dev_priv) < 6)
4988                 return -ENODEV;
4989
4990         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4991         return 0;
4992 }
4993
4994 static int
4995 i915_min_freq_set(void *data, u64 val)
4996 {
4997         struct drm_i915_private *dev_priv = data;
4998         u32 hw_max, hw_min;
4999         int ret;
5000
5001         if (INTEL_GEN(dev_priv) < 6)
5002                 return -ENODEV;
5003
5004         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5005
5006         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5007         if (ret)
5008                 return ret;
5009
5010         /*
5011          * Turbo will still be enabled, but won't go below the set value.
5012          */
5013         val = intel_freq_opcode(dev_priv, val);
5014
5015         hw_max = dev_priv->rps.max_freq;
5016         hw_min = dev_priv->rps.min_freq;
5017
5018         if (val < hw_min ||
5019             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5020                 mutex_unlock(&dev_priv->rps.hw_lock);
5021                 return -EINVAL;
5022         }
5023
5024         dev_priv->rps.min_freq_softlimit = val;
5025
5026         intel_set_rps(dev_priv, val);
5027
5028         mutex_unlock(&dev_priv->rps.hw_lock);
5029
5030         return 0;
5031 }
5032
5033 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5034                         i915_min_freq_get, i915_min_freq_set,
5035                         "%llu\n");
5036
5037 static int
5038 i915_cache_sharing_get(void *data, u64 *val)
5039 {
5040         struct drm_i915_private *dev_priv = data;
5041         struct drm_device *dev = &dev_priv->drm;
5042         u32 snpcr;
5043         int ret;
5044
5045         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5046                 return -ENODEV;
5047
5048         ret = mutex_lock_interruptible(&dev->struct_mutex);
5049         if (ret)
5050                 return ret;
5051         intel_runtime_pm_get(dev_priv);
5052
5053         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5054
5055         intel_runtime_pm_put(dev_priv);
5056         mutex_unlock(&dev->struct_mutex);
5057
5058         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5059
5060         return 0;
5061 }
5062
5063 static int
5064 i915_cache_sharing_set(void *data, u64 val)
5065 {
5066         struct drm_i915_private *dev_priv = data;
5067         u32 snpcr;
5068
5069         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5070                 return -ENODEV;
5071
5072         if (val > 3)
5073                 return -EINVAL;
5074
5075         intel_runtime_pm_get(dev_priv);
5076         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5077
5078         /* Update the cache sharing policy here as well */
5079         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5080         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5081         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5082         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5083
5084         intel_runtime_pm_put(dev_priv);
5085         return 0;
5086 }
5087
5088 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5089                         i915_cache_sharing_get, i915_cache_sharing_set,
5090                         "%llu\n");
5091
5092 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5093                                           struct sseu_dev_info *sseu)
5094 {
5095         int ss_max = 2;
5096         int ss;
5097         u32 sig1[ss_max], sig2[ss_max];
5098
5099         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5100         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5101         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5102         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5103
5104         for (ss = 0; ss < ss_max; ss++) {
5105                 unsigned int eu_cnt;
5106
5107                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5108                         /* skip disabled subslice */
5109                         continue;
5110
5111                 sseu->slice_mask = BIT(0);
5112                 sseu->subslice_mask |= BIT(ss);
5113                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5114                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5115                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5116                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5117                 sseu->eu_total += eu_cnt;
5118                 sseu->eu_per_subslice = max_t(unsigned int,
5119                                               sseu->eu_per_subslice, eu_cnt);
5120         }
5121 }
5122
5123 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5124                                     struct sseu_dev_info *sseu)
5125 {
5126         int s_max = 3, ss_max = 4;
5127         int s, ss;
5128         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5129
5130         /* BXT has a single slice and at most 3 subslices. */
5131         if (IS_BROXTON(dev_priv)) {
5132                 s_max = 1;
5133                 ss_max = 3;
5134         }
5135
5136         for (s = 0; s < s_max; s++) {
5137                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5138                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5139                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5140         }
5141
5142         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5143                      GEN9_PGCTL_SSA_EU19_ACK |
5144                      GEN9_PGCTL_SSA_EU210_ACK |
5145                      GEN9_PGCTL_SSA_EU311_ACK;
5146         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5147                      GEN9_PGCTL_SSB_EU19_ACK |
5148                      GEN9_PGCTL_SSB_EU210_ACK |
5149                      GEN9_PGCTL_SSB_EU311_ACK;
5150
5151         for (s = 0; s < s_max; s++) {
5152                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5153                         /* skip disabled slice */
5154                         continue;
5155
5156                 sseu->slice_mask |= BIT(s);
5157
5158                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5159                         sseu->subslice_mask =
5160                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5161
5162                 for (ss = 0; ss < ss_max; ss++) {
5163                         unsigned int eu_cnt;
5164
5165                         if (IS_BROXTON(dev_priv)) {
5166                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5167                                         /* skip disabled subslice */
5168                                         continue;
5169
5170                                 sseu->subslice_mask |= BIT(ss);
5171                         }
5172
5173                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5174                                                eu_mask[ss%2]);
5175                         sseu->eu_total += eu_cnt;
5176                         sseu->eu_per_subslice = max_t(unsigned int,
5177                                                       sseu->eu_per_subslice,
5178                                                       eu_cnt);
5179                 }
5180         }
5181 }
5182
5183 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5184                                          struct sseu_dev_info *sseu)
5185 {
5186         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5187         int s;
5188
5189         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5190
5191         if (sseu->slice_mask) {
5192                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5193                 sseu->eu_per_subslice =
5194                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5195                 sseu->eu_total = sseu->eu_per_subslice *
5196                                  sseu_subslice_total(sseu);
5197
5198                 /* subtract fused off EU(s) from enabled slice(s) */
5199                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5200                         u8 subslice_7eu =
5201                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5202
5203                         sseu->eu_total -= hweight8(subslice_7eu);
5204                 }
5205         }
5206 }
5207
5208 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5209                                  const struct sseu_dev_info *sseu)
5210 {
5211         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5212         const char *type = is_available_info ? "Available" : "Enabled";
5213
5214         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5215                    sseu->slice_mask);
5216         seq_printf(m, "  %s Slice Total: %u\n", type,
5217                    hweight8(sseu->slice_mask));
5218         seq_printf(m, "  %s Subslice Total: %u\n", type,
5219                    sseu_subslice_total(sseu));
5220         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5221                    sseu->subslice_mask);
5222         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5223                    hweight8(sseu->subslice_mask));
5224         seq_printf(m, "  %s EU Total: %u\n", type,
5225                    sseu->eu_total);
5226         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5227                    sseu->eu_per_subslice);
5228
5229         if (!is_available_info)
5230                 return;
5231
5232         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5233         if (HAS_POOLED_EU(dev_priv))
5234                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5235
5236         seq_printf(m, "  Has Slice Power Gating: %s\n",
5237                    yesno(sseu->has_slice_pg));
5238         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5239                    yesno(sseu->has_subslice_pg));
5240         seq_printf(m, "  Has EU Power Gating: %s\n",
5241                    yesno(sseu->has_eu_pg));
5242 }
5243
5244 static int i915_sseu_status(struct seq_file *m, void *unused)
5245 {
5246         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5247         struct sseu_dev_info sseu;
5248
5249         if (INTEL_GEN(dev_priv) < 8)
5250                 return -ENODEV;
5251
5252         seq_puts(m, "SSEU Device Info\n");
5253         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5254
5255         seq_puts(m, "SSEU Device Status\n");
5256         memset(&sseu, 0, sizeof(sseu));
5257
5258         intel_runtime_pm_get(dev_priv);
5259
5260         if (IS_CHERRYVIEW(dev_priv)) {
5261                 cherryview_sseu_device_status(dev_priv, &sseu);
5262         } else if (IS_BROADWELL(dev_priv)) {
5263                 broadwell_sseu_device_status(dev_priv, &sseu);
5264         } else if (INTEL_GEN(dev_priv) >= 9) {
5265                 gen9_sseu_device_status(dev_priv, &sseu);
5266         }
5267
5268         intel_runtime_pm_put(dev_priv);
5269
5270         i915_print_sseu_info(m, false, &sseu);
5271
5272         return 0;
5273 }
5274
5275 static int i915_forcewake_open(struct inode *inode, struct file *file)
5276 {
5277         struct drm_i915_private *dev_priv = inode->i_private;
5278
5279         if (INTEL_GEN(dev_priv) < 6)
5280                 return 0;
5281
5282         intel_runtime_pm_get(dev_priv);
5283         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5284
5285         return 0;
5286 }
5287
5288 static int i915_forcewake_release(struct inode *inode, struct file *file)
5289 {
5290         struct drm_i915_private *dev_priv = inode->i_private;
5291
5292         if (INTEL_GEN(dev_priv) < 6)
5293                 return 0;
5294
5295         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5296         intel_runtime_pm_put(dev_priv);
5297
5298         return 0;
5299 }
5300
5301 static const struct file_operations i915_forcewake_fops = {
5302         .owner = THIS_MODULE,
5303         .open = i915_forcewake_open,
5304         .release = i915_forcewake_release,
5305 };
5306
5307 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5308 {
5309         struct dentry *ent;
5310
5311         ent = debugfs_create_file("i915_forcewake_user",
5312                                   S_IRUSR,
5313                                   root, to_i915(minor->dev),
5314                                   &i915_forcewake_fops);
5315         if (!ent)
5316                 return -ENOMEM;
5317
5318         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5319 }
5320
5321 static int i915_debugfs_create(struct dentry *root,
5322                                struct drm_minor *minor,
5323                                const char *name,
5324                                const struct file_operations *fops)
5325 {
5326         struct dentry *ent;
5327
5328         ent = debugfs_create_file(name,
5329                                   S_IRUGO | S_IWUSR,
5330                                   root, to_i915(minor->dev),
5331                                   fops);
5332         if (!ent)
5333                 return -ENOMEM;
5334
5335         return drm_add_fake_info_node(minor, ent, fops);
5336 }
5337
5338 static const struct drm_info_list i915_debugfs_list[] = {
5339         {"i915_capabilities", i915_capabilities, 0},
5340         {"i915_gem_objects", i915_gem_object_info, 0},
5341         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5342         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5343         {"i915_gem_stolen", i915_gem_stolen_list_info },
5344         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5345         {"i915_gem_request", i915_gem_request_info, 0},
5346         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5347         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5348         {"i915_gem_interrupt", i915_interrupt_info, 0},
5349         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5350         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5351         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5352         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5353         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5354         {"i915_guc_info", i915_guc_info, 0},
5355         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5356         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5357         {"i915_frequency_info", i915_frequency_info, 0},
5358         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5359         {"i915_drpc_info", i915_drpc_info, 0},
5360         {"i915_emon_status", i915_emon_status, 0},
5361         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5362         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5363         {"i915_fbc_status", i915_fbc_status, 0},
5364         {"i915_ips_status", i915_ips_status, 0},
5365         {"i915_sr_status", i915_sr_status, 0},
5366         {"i915_opregion", i915_opregion, 0},
5367         {"i915_vbt", i915_vbt, 0},
5368         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5369         {"i915_context_status", i915_context_status, 0},
5370         {"i915_dump_lrc", i915_dump_lrc, 0},
5371         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5372         {"i915_swizzle_info", i915_swizzle_info, 0},
5373         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5374         {"i915_llc", i915_llc, 0},
5375         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5376         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5377         {"i915_energy_uJ", i915_energy_uJ, 0},
5378         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5379         {"i915_power_domain_info", i915_power_domain_info, 0},
5380         {"i915_dmc_info", i915_dmc_info, 0},
5381         {"i915_display_info", i915_display_info, 0},
5382         {"i915_engine_info", i915_engine_info, 0},
5383         {"i915_semaphore_status", i915_semaphore_status, 0},
5384         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5385         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5386         {"i915_wa_registers", i915_wa_registers, 0},
5387         {"i915_ddb_info", i915_ddb_info, 0},
5388         {"i915_sseu_status", i915_sseu_status, 0},
5389         {"i915_drrs_status", i915_drrs_status, 0},
5390         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5391 };
5392 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5393
5394 static const struct i915_debugfs_files {
5395         const char *name;
5396         const struct file_operations *fops;
5397 } i915_debugfs_files[] = {
5398         {"i915_wedged", &i915_wedged_fops},
5399         {"i915_max_freq", &i915_max_freq_fops},
5400         {"i915_min_freq", &i915_min_freq_fops},
5401         {"i915_cache_sharing", &i915_cache_sharing_fops},
5402         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5403         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5404         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5405 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5406         {"i915_error_state", &i915_error_state_fops},
5407 #endif
5408         {"i915_next_seqno", &i915_next_seqno_fops},
5409         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5410         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5411         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5412         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5413         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5414         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5415         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5416         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5417 };
5418
5419 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5420 {
5421         enum pipe pipe;
5422
5423         for_each_pipe(dev_priv, pipe) {
5424                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5425
5426                 pipe_crc->opened = false;
5427                 spin_lock_init(&pipe_crc->lock);
5428                 init_waitqueue_head(&pipe_crc->wq);
5429         }
5430 }
5431
5432 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5433 {
5434         struct drm_minor *minor = dev_priv->drm.primary;
5435         int ret, i;
5436
5437         ret = i915_forcewake_create(minor->debugfs_root, minor);
5438         if (ret)
5439                 return ret;
5440
5441         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5442                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5443                 if (ret)
5444                         return ret;
5445         }
5446
5447         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5448                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5449                                           i915_debugfs_files[i].name,
5450                                           i915_debugfs_files[i].fops);
5451                 if (ret)
5452                         return ret;
5453         }
5454
5455         return drm_debugfs_create_files(i915_debugfs_list,
5456                                         I915_DEBUGFS_ENTRIES,
5457                                         minor->debugfs_root, minor);
5458 }
5459
5460 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5461 {
5462         struct drm_minor *minor = dev_priv->drm.primary;
5463         int i;
5464
5465         drm_debugfs_remove_files(i915_debugfs_list,
5466                                  I915_DEBUGFS_ENTRIES, minor);
5467
5468         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5469                                  1, minor);
5470
5471         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5472                 struct drm_info_list *info_list =
5473                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5474
5475                 drm_debugfs_remove_files(info_list, 1, minor);
5476         }
5477
5478         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5479                 struct drm_info_list *info_list =
5480                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5481
5482                 drm_debugfs_remove_files(info_list, 1, minor);
5483         }
5484 }
5485
5486 struct dpcd_block {
5487         /* DPCD dump start address. */
5488         unsigned int offset;
5489         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5490         unsigned int end;
5491         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5492         size_t size;
5493         /* Only valid for eDP. */
5494         bool edp;
5495 };
5496
5497 static const struct dpcd_block i915_dpcd_debug[] = {
5498         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5499         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5500         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5501         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5502         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5503         { .offset = DP_SET_POWER },
5504         { .offset = DP_EDP_DPCD_REV },
5505         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5506         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5507         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5508 };
5509
5510 static int i915_dpcd_show(struct seq_file *m, void *data)
5511 {
5512         struct drm_connector *connector = m->private;
5513         struct intel_dp *intel_dp =
5514                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5515         uint8_t buf[16];
5516         ssize_t err;
5517         int i;
5518
5519         if (connector->status != connector_status_connected)
5520                 return -ENODEV;
5521
5522         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5523                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5524                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5525
5526                 if (b->edp &&
5527                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5528                         continue;
5529
5530                 /* low tech for now */
5531                 if (WARN_ON(size > sizeof(buf)))
5532                         continue;
5533
5534                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5535                 if (err <= 0) {
5536                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5537                                   size, b->offset, err);
5538                         continue;
5539                 }
5540
5541                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5542         }
5543
5544         return 0;
5545 }
5546
5547 static int i915_dpcd_open(struct inode *inode, struct file *file)
5548 {
5549         return single_open(file, i915_dpcd_show, inode->i_private);
5550 }
5551
5552 static const struct file_operations i915_dpcd_fops = {
5553         .owner = THIS_MODULE,
5554         .open = i915_dpcd_open,
5555         .read = seq_read,
5556         .llseek = seq_lseek,
5557         .release = single_release,
5558 };
5559
5560 static int i915_panel_show(struct seq_file *m, void *data)
5561 {
5562         struct drm_connector *connector = m->private;
5563         struct intel_dp *intel_dp =
5564                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5565
5566         if (connector->status != connector_status_connected)
5567                 return -ENODEV;
5568
5569         seq_printf(m, "Panel power up delay: %d\n",
5570                    intel_dp->panel_power_up_delay);
5571         seq_printf(m, "Panel power down delay: %d\n",
5572                    intel_dp->panel_power_down_delay);
5573         seq_printf(m, "Backlight on delay: %d\n",
5574                    intel_dp->backlight_on_delay);
5575         seq_printf(m, "Backlight off delay: %d\n",
5576                    intel_dp->backlight_off_delay);
5577
5578         return 0;
5579 }
5580
5581 static int i915_panel_open(struct inode *inode, struct file *file)
5582 {
5583         return single_open(file, i915_panel_show, inode->i_private);
5584 }
5585
5586 static const struct file_operations i915_panel_fops = {
5587         .owner = THIS_MODULE,
5588         .open = i915_panel_open,
5589         .read = seq_read,
5590         .llseek = seq_lseek,
5591         .release = single_release,
5592 };
5593
5594 /**
5595  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5596  * @connector: pointer to a registered drm_connector
5597  *
5598  * Cleanup will be done by drm_connector_unregister() through a call to
5599  * drm_debugfs_connector_remove().
5600  *
5601  * Returns 0 on success, negative error codes on error.
5602  */
5603 int i915_debugfs_connector_add(struct drm_connector *connector)
5604 {
5605         struct dentry *root = connector->debugfs_entry;
5606
5607         /* The connector must have been registered beforehands. */
5608         if (!root)
5609                 return -ENODEV;
5610
5611         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5612             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5613                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5614                                     connector, &i915_dpcd_fops);
5615
5616         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5617                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5618                                     connector, &i915_panel_fops);
5619
5620         return 0;
5621 }