drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return obj->fault_mappable ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139         enum intel_engine_id id;
 140
 141         lockdep_assert_held(&obj->base.dev->struct_mutex);
 142
 143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    get_active_flag(obj),
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    get_pin_mapped_flag(obj),
 150                    obj->base.size / 1024,
 151                    obj->base.read_domains,
 152                    obj->base.write_domain);
 153         for_each_engine_id(engine, dev_priv, id)
 154                 seq_printf(m, "%x ",
 155                            i915_gem_active_get_seqno(&obj->last_read[id],
 156                                                      &obj->base.dev->struct_mutex));
 157         seq_printf(m, "] %x %s%s%s",
 158                    i915_gem_active_get_seqno(&obj->last_write,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(dev_priv, obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 173                 if (!drm_mm_node_allocated(&vma->node))
 174                         continue;
 175
 176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 178                            vma->node.start, vma->node.size);
 179                 if (i915_vma_is_ggtt(vma))
 180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 181                 if (vma->fence)
 182                         seq_printf(m, " , fence: %d%s",
 183                                    vma->fence->id,
 184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 185                 seq_puts(m, ")");
 186         }
 187         if (obj->stolen)
 188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 189
 190         engine = i915_gem_active_get_engine(&obj->last_write,
 191                                             &dev_priv->drm.struct_mutex);
 192         if (engine)
 193                 seq_printf(m, " (%s)", engine->name);
 194
 195         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 196         if (frontbuffer_bits)
 197                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 198 }
 199
 200 static int obj_rank_by_stolen(void *priv,
 201                               struct list_head *A, struct list_head *B)
 202 {
 203         struct drm_i915_gem_object *a =
 204                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 205         struct drm_i915_gem_object *b =
 206                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 207
 208         if (a->stolen->start < b->stolen->start)
 209                 return -1;
 210         if (a->stolen->start > b->stolen->start)
 211                 return 1;
 212         return 0;
 213 }
 214
 215 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 216 {
 217         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 218         struct drm_device *dev = &dev_priv->drm;
 219         struct drm_i915_gem_object *obj;
 220         u64 total_obj_size, total_gtt_size;
 221         LIST_HEAD(stolen);
 222         int count, ret;
 223
 224         ret = mutex_lock_interruptible(&dev->struct_mutex);
 225         if (ret)
 226                 return ret;
 227
 228         total_obj_size = total_gtt_size = count = 0;
 229         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 230                 if (obj->stolen == NULL)
 231                         continue;
 232
 233                 list_add(&obj->obj_exec_link, &stolen);
 234
 235                 total_obj_size += obj->base.size;
 236                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 237                 count++;
 238         }
 239         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 240                 if (obj->stolen == NULL)
 241                         continue;
 242
 243                 list_add(&obj->obj_exec_link, &stolen);
 244
 245                 total_obj_size += obj->base.size;
 246                 count++;
 247         }
 248         list_sort(NULL, &stolen, obj_rank_by_stolen);
 249         seq_puts(m, "Stolen:\n");
 250         while (!list_empty(&stolen)) {
 251                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 252                 seq_puts(m, "   ");
 253                 describe_obj(m, obj);
 254                 seq_putc(m, '\n');
 255                 list_del_init(&obj->obj_exec_link);
 256         }
 257         mutex_unlock(&dev->struct_mutex);
 258
 259         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 260                    count, total_obj_size, total_gtt_size);
 261         return 0;
 262 }
 263
 264 struct file_stats {
 265         struct drm_i915_file_private *file_priv;
 266         unsigned long count;
 267         u64 total, unbound;
 268         u64 global, shared;
 269         u64 active, inactive;
 270 };
 271
 272 static int per_file_stats(int id, void *ptr, void *data)
 273 {
 274         struct drm_i915_gem_object *obj = ptr;
 275         struct file_stats *stats = data;
 276         struct i915_vma *vma;
 277
 278         stats->count++;
 279         stats->total += obj->base.size;
 280         if (!obj->bind_count)
 281                 stats->unbound += obj->base.size;
 282         if (obj->base.name || obj->base.dma_buf)
 283                 stats->shared += obj->base.size;
 284
 285         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 286                 if (!drm_mm_node_allocated(&vma->node))
 287                         continue;
 288
 289                 if (i915_vma_is_ggtt(vma)) {
 290                         stats->global += vma->node.size;
 291                 } else {
 292                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 293
 294                         if (ppgtt->base.file != stats->file_priv)
 295                                 continue;
 296                 }
 297
 298                 if (i915_vma_is_active(vma))
 299                         stats->active += vma->node.size;
 300                 else
 301                         stats->inactive += vma->node.size;
 302         }
 303
 304         return 0;
 305 }
 306
 307 #define print_file_stats(m, name, stats) do { \
 308         if (stats.count) \
 309                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 310                            name, \
 311                            stats.count, \
 312                            stats.total, \
 313                            stats.active, \
 314                            stats.inactive, \
 315                            stats.global, \
 316                            stats.shared, \
 317                            stats.unbound); \
 318 } while (0)
 319
 320 static void print_batch_pool_stats(struct seq_file *m,
 321                                    struct drm_i915_private *dev_priv)
 322 {
 323         struct drm_i915_gem_object *obj;
 324         struct file_stats stats;
 325         struct intel_engine_cs *engine;
 326         int j;
 327
 328         memset(&stats, 0, sizeof(stats));
 329
 330         for_each_engine(engine, dev_priv) {
 331                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 332                         list_for_each_entry(obj,
 333                                             &engine->batch_pool.cache_list[j],
 334                                             batch_pool_link)
 335                                 per_file_stats(0, obj, &stats);
 336                 }
 337         }
 338
 339         print_file_stats(m, "[k]batch pool", stats);
 340 }
 341
 342 static int per_file_ctx_stats(int id, void *ptr, void *data)
 343 {
 344         struct i915_gem_context *ctx = ptr;
 345         int n;
 346
 347         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 348                 if (ctx->engine[n].state)
 349                         per_file_stats(0, ctx->engine[n].state->obj, data);
 350                 if (ctx->engine[n].ring)
 351                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void print_context_stats(struct seq_file *m,
 358                                 struct drm_i915_private *dev_priv)
 359 {
 360         struct drm_device *dev = &dev_priv->drm;
 361         struct file_stats stats;
 362         struct drm_file *file;
 363
 364         memset(&stats, 0, sizeof(stats));
 365
 366         mutex_lock(&dev->struct_mutex);
 367         if (dev_priv->kernel_context)
 368                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 369
 370         list_for_each_entry(file, &dev->filelist, lhead) {
 371                 struct drm_i915_file_private *fpriv = file->driver_priv;
 372                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 373         }
 374         mutex_unlock(&dev->struct_mutex);
 375
 376         print_file_stats(m, "[k]contexts", stats);
 377 }
 378
 379 static int i915_gem_object_info(struct seq_file *m, void *data)
 380 {
 381         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 382         struct drm_device *dev = &dev_priv->drm;
 383         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 384         u32 count, mapped_count, purgeable_count, dpy_count;
 385         u64 size, mapped_size, purgeable_size, dpy_size;
 386         struct drm_i915_gem_object *obj;
 387         struct drm_file *file;
 388         int ret;
 389
 390         ret = mutex_lock_interruptible(&dev->struct_mutex);
 391         if (ret)
 392                 return ret;
 393
 394         seq_printf(m, "%u objects, %zu bytes\n",
 395                    dev_priv->mm.object_count,
 396                    dev_priv->mm.object_memory);
 397
 398         size = count = 0;
 399         mapped_size = mapped_count = 0;
 400         purgeable_size = purgeable_count = 0;
 401         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 402                 size += obj->base.size;
 403                 ++count;
 404
 405                 if (obj->madv == I915_MADV_DONTNEED) {
 406                         purgeable_size += obj->base.size;
 407                         ++purgeable_count;
 408                 }
 409
 410                 if (obj->mapping) {
 411                         mapped_count++;
 412                         mapped_size += obj->base.size;
 413                 }
 414         }
 415         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 416
 417         size = count = dpy_size = dpy_count = 0;
 418         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 419                 size += obj->base.size;
 420                 ++count;
 421
 422                 if (obj->pin_display) {
 423                         dpy_size += obj->base.size;
 424                         ++dpy_count;
 425                 }
 426
 427                 if (obj->madv == I915_MADV_DONTNEED) {
 428                         purgeable_size += obj->base.size;
 429                         ++purgeable_count;
 430                 }
 431
 432                 if (obj->mapping) {
 433                         mapped_count++;
 434                         mapped_size += obj->base.size;
 435                 }
 436         }
 437         seq_printf(m, "%u bound objects, %llu bytes\n",
 438                    count, size);
 439         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 440                    purgeable_count, purgeable_size);
 441         seq_printf(m, "%u mapped objects, %llu bytes\n",
 442                    mapped_count, mapped_size);
 443         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 444                    dpy_count, dpy_size);
 445
 446         seq_printf(m, "%llu [%llu] gtt total\n",
 447                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 448
 449         seq_putc(m, '\n');
 450         print_batch_pool_stats(m, dev_priv);
 451         mutex_unlock(&dev->struct_mutex);
 452
 453         mutex_lock(&dev->filelist_mutex);
 454         print_context_stats(m, dev_priv);
 455         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 456                 struct file_stats stats;
 457                 struct drm_i915_file_private *file_priv = file->driver_priv;
 458                 struct drm_i915_gem_request *request;
 459                 struct task_struct *task;
 460
 461                 memset(&stats, 0, sizeof(stats));
 462                 stats.file_priv = file->driver_priv;
 463                 spin_lock(&file->table_lock);
 464                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 465                 spin_unlock(&file->table_lock);
 466                 /*
 467                  * Although we have a valid reference on file->pid, that does
 468                  * not guarantee that the task_struct who called get_pid() is
 469                  * still alive (e.g. get_pid(current) => fork() => exit()).
 470                  * Therefore, we need to protect this ->comm access using RCU.
 471                  */
 472                 mutex_lock(&dev->struct_mutex);
 473                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 474                                                    struct drm_i915_gem_request,
 475                                                    client_list);
 476                 rcu_read_lock();
 477                 task = pid_task(request && request->ctx->pid ?
 478                                 request->ctx->pid : file->pid,
 479                                 PIDTYPE_PID);
 480                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 481                 rcu_read_unlock();
 482                 mutex_unlock(&dev->struct_mutex);
 483         }
 484         mutex_unlock(&dev->filelist_mutex);
 485
 486         return 0;
 487 }
 488
 489 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 490 {
 491         struct drm_info_node *node = m->private;
 492         struct drm_i915_private *dev_priv = node_to_i915(node);
 493         struct drm_device *dev = &dev_priv->drm;
 494         bool show_pin_display_only = !!node->info_ent->data;
 495         struct drm_i915_gem_object *obj;
 496         u64 total_obj_size, total_gtt_size;
 497         int count, ret;
 498
 499         ret = mutex_lock_interruptible(&dev->struct_mutex);
 500         if (ret)
 501                 return ret;
 502
 503         total_obj_size = total_gtt_size = count = 0;
 504         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 505                 if (show_pin_display_only && !obj->pin_display)
 506                         continue;
 507
 508                 seq_puts(m, "   ");
 509                 describe_obj(m, obj);
 510                 seq_putc(m, '\n');
 511                 total_obj_size += obj->base.size;
 512                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 513                 count++;
 514         }
 515
 516         mutex_unlock(&dev->struct_mutex);
 517
 518         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 519                    count, total_obj_size, total_gtt_size);
 520
 521         return 0;
 522 }
 523
 524 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 525 {
 526         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 527         struct drm_device *dev = &dev_priv->drm;
 528         struct intel_crtc *crtc;
 529         int ret;
 530
 531         ret = mutex_lock_interruptible(&dev->struct_mutex);
 532         if (ret)
 533                 return ret;
 534
 535         for_each_intel_crtc(dev, crtc) {
 536                 const char pipe = pipe_name(crtc->pipe);
 537                 const char plane = plane_name(crtc->plane);
 538                 struct intel_flip_work *work;
 539
 540                 spin_lock_irq(&dev->event_lock);
 541                 work = crtc->flip_work;
 542                 if (work == NULL) {
 543                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 544                                    pipe, plane);
 545                 } else {
 546                         u32 pending;
 547                         u32 addr;
 548
 549                         pending = atomic_read(&work->pending);
 550                         if (pending) {
 551                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 552                                            pipe, plane);
 553                         } else {
 554                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 555                                            pipe, plane);
 556                         }
 557                         if (work->flip_queued_req) {
 558                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 559
 560                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 561                                            engine->name,
 562                                            i915_gem_request_get_seqno(work->flip_queued_req),
 563                                            dev_priv->next_seqno,
 564                                            intel_engine_get_seqno(engine),
 565                                            i915_gem_request_completed(work->flip_queued_req));
 566                         } else
 567                                 seq_printf(m, "Flip not associated with any ring\n");
 568                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 569                                    work->flip_queued_vblank,
 570                                    work->flip_ready_vblank,
 571                                    intel_crtc_get_vblank_counter(crtc));
 572                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 573
 574                         if (INTEL_GEN(dev_priv) >= 4)
 575                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 576                         else
 577                                 addr = I915_READ(DSPADDR(crtc->plane));
 578                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 579
 580                         if (work->pending_flip_obj) {
 581                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 582                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 583                         }
 584                 }
 585                 spin_unlock_irq(&dev->event_lock);
 586         }
 587
 588         mutex_unlock(&dev->struct_mutex);
 589
 590         return 0;
 591 }
 592
 593 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 594 {
 595         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 596         struct drm_device *dev = &dev_priv->drm;
 597         struct drm_i915_gem_object *obj;
 598         struct intel_engine_cs *engine;
 599         int total = 0;
 600         int ret, j;
 601
 602         ret = mutex_lock_interruptible(&dev->struct_mutex);
 603         if (ret)
 604                 return ret;
 605
 606         for_each_engine(engine, dev_priv) {
 607                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 608                         int count;
 609
 610                         count = 0;
 611                         list_for_each_entry(obj,
 612                                             &engine->batch_pool.cache_list[j],
 613                                             batch_pool_link)
 614                                 count++;
 615                         seq_printf(m, "%s cache[%d]: %d objects\n",
 616                                    engine->name, j, count);
 617
 618                         list_for_each_entry(obj,
 619                                             &engine->batch_pool.cache_list[j],
 620                                             batch_pool_link) {
 621                                 seq_puts(m, "   ");
 622                                 describe_obj(m, obj);
 623                                 seq_putc(m, '\n');
 624                         }
 625
 626                         total += count;
 627                 }
 628         }
 629
 630         seq_printf(m, "total: %d\n", total);
 631
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         return 0;
 635 }
 636
 637 static void print_request(struct seq_file *m,
 638                           struct drm_i915_gem_request *rq,
 639                           const char *prefix)
 640 {
 641         struct pid *pid = rq->ctx->pid;
 642         struct task_struct *task;
 643
 644         rcu_read_lock();
 645         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 646         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 647                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 648                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 649                    task ? task->comm : "<unknown>",
 650                    task ? task->pid : -1);
 651         rcu_read_unlock();
 652 }
 653
 654 static int i915_gem_request_info(struct seq_file *m, void *data)
 655 {
 656         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 657         struct drm_device *dev = &dev_priv->drm;
 658         struct intel_engine_cs *engine;
 659         struct drm_i915_gem_request *req;
 660         int ret, any;
 661
 662         ret = mutex_lock_interruptible(&dev->struct_mutex);
 663         if (ret)
 664                 return ret;
 665
 666         any = 0;
 667         for_each_engine(engine, dev_priv) {
 668                 int count;
 669
 670                 count = 0;
 671                 list_for_each_entry(req, &engine->request_list, link)
 672                         count++;
 673                 if (count == 0)
 674                         continue;
 675
 676                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 677                 list_for_each_entry(req, &engine->request_list, link)
 678                         print_request(m, req, "    ");
 679
 680                 any++;
 681         }
 682         mutex_unlock(&dev->struct_mutex);
 683
 684         if (any == 0)
 685                 seq_puts(m, "No requests\n");
 686
 687         return 0;
 688 }
 689
 690 static void i915_ring_seqno_info(struct seq_file *m,
 691                                  struct intel_engine_cs *engine)
 692 {
 693         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 694         struct rb_node *rb;
 695
 696         seq_printf(m, "Current sequence (%s): %x\n",
 697                    engine->name, intel_engine_get_seqno(engine));
 698
 699         spin_lock(&b->lock);
 700         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 701                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 702
 703                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 704                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 705         }
 706         spin_unlock(&b->lock);
 707 }
 708
 709 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 710 {
 711         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 712         struct intel_engine_cs *engine;
 713
 714         for_each_engine(engine, dev_priv)
 715                 i915_ring_seqno_info(m, engine);
 716
 717         return 0;
 718 }
 719
 720
 721 static int i915_interrupt_info(struct seq_file *m, void *data)
 722 {
 723         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 724         struct intel_engine_cs *engine;
 725         int i, pipe;
 726
 727         intel_runtime_pm_get(dev_priv);
 728
 729         if (IS_CHERRYVIEW(dev_priv)) {
 730                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 731                            I915_READ(GEN8_MASTER_IRQ));
 732
 733                 seq_printf(m, "Display IER:\t%08x\n",
 734                            I915_READ(VLV_IER));
 735                 seq_printf(m, "Display IIR:\t%08x\n",
 736                            I915_READ(VLV_IIR));
 737                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 738                            I915_READ(VLV_IIR_RW));
 739                 seq_printf(m, "Display IMR:\t%08x\n",
 740                            I915_READ(VLV_IMR));
 741                 for_each_pipe(dev_priv, pipe)
 742                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 743                                    pipe_name(pipe),
 744                                    I915_READ(PIPESTAT(pipe)));
 745
 746                 seq_printf(m, "Port hotplug:\t%08x\n",
 747                            I915_READ(PORT_HOTPLUG_EN));
 748                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 749                            I915_READ(VLV_DPFLIPSTAT));
 750                 seq_printf(m, "DPINVGTT:\t%08x\n",
 751                            I915_READ(DPINVGTT));
 752
 753                 for (i = 0; i < 4; i++) {
 754                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 755                                    i, I915_READ(GEN8_GT_IMR(i)));
 756                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 757                                    i, I915_READ(GEN8_GT_IIR(i)));
 758                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 759                                    i, I915_READ(GEN8_GT_IER(i)));
 760                 }
 761
 762                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 763                            I915_READ(GEN8_PCU_IMR));
 764                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 765                            I915_READ(GEN8_PCU_IIR));
 766                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 767                            I915_READ(GEN8_PCU_IER));
 768         } else if (INTEL_GEN(dev_priv) >= 8) {
 769                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 770                            I915_READ(GEN8_MASTER_IRQ));
 771
 772                 for (i = 0; i < 4; i++) {
 773                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 774                                    i, I915_READ(GEN8_GT_IMR(i)));
 775                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 776                                    i, I915_READ(GEN8_GT_IIR(i)));
 777                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 778                                    i, I915_READ(GEN8_GT_IER(i)));
 779                 }
 780
 781                 for_each_pipe(dev_priv, pipe) {
 782                         enum intel_display_power_domain power_domain;
 783
 784                         power_domain = POWER_DOMAIN_PIPE(pipe);
 785                         if (!intel_display_power_get_if_enabled(dev_priv,
 786                                                                 power_domain)) {
 787                                 seq_printf(m, "Pipe %c power disabled\n",
 788                                            pipe_name(pipe));
 789                                 continue;
 790                         }
 791                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 792                                    pipe_name(pipe),
 793                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 794                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 795                                    pipe_name(pipe),
 796                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 797                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 798                                    pipe_name(pipe),
 799                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 800
 801                         intel_display_power_put(dev_priv, power_domain);
 802                 }
 803
 804                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_DE_PORT_IMR));
 806                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_DE_PORT_IIR));
 808                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_DE_PORT_IER));
 810
 811                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 812                            I915_READ(GEN8_DE_MISC_IMR));
 813                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 814                            I915_READ(GEN8_DE_MISC_IIR));
 815                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 816                            I915_READ(GEN8_DE_MISC_IER));
 817
 818                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 819                            I915_READ(GEN8_PCU_IMR));
 820                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 821                            I915_READ(GEN8_PCU_IIR));
 822                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 823                            I915_READ(GEN8_PCU_IER));
 824         } else if (IS_VALLEYVIEW(dev_priv)) {
 825                 seq_printf(m, "Display IER:\t%08x\n",
 826                            I915_READ(VLV_IER));
 827                 seq_printf(m, "Display IIR:\t%08x\n",
 828                            I915_READ(VLV_IIR));
 829                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 830                            I915_READ(VLV_IIR_RW));
 831                 seq_printf(m, "Display IMR:\t%08x\n",
 832                            I915_READ(VLV_IMR));
 833                 for_each_pipe(dev_priv, pipe)
 834                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 835                                    pipe_name(pipe),
 836                                    I915_READ(PIPESTAT(pipe)));
 837
 838                 seq_printf(m, "Master IER:\t%08x\n",
 839                            I915_READ(VLV_MASTER_IER));
 840
 841                 seq_printf(m, "Render IER:\t%08x\n",
 842                            I915_READ(GTIER));
 843                 seq_printf(m, "Render IIR:\t%08x\n",
 844                            I915_READ(GTIIR));
 845                 seq_printf(m, "Render IMR:\t%08x\n",
 846                            I915_READ(GTIMR));
 847
 848                 seq_printf(m, "PM IER:\t\t%08x\n",
 849                            I915_READ(GEN6_PMIER));
 850                 seq_printf(m, "PM IIR:\t\t%08x\n",
 851                            I915_READ(GEN6_PMIIR));
 852                 seq_printf(m, "PM IMR:\t\t%08x\n",
 853                            I915_READ(GEN6_PMIMR));
 854
 855                 seq_printf(m, "Port hotplug:\t%08x\n",
 856                            I915_READ(PORT_HOTPLUG_EN));
 857                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 858                            I915_READ(VLV_DPFLIPSTAT));
 859                 seq_printf(m, "DPINVGTT:\t%08x\n",
 860                            I915_READ(DPINVGTT));
 861
 862         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 863                 seq_printf(m, "Interrupt enable:    %08x\n",
 864                            I915_READ(IER));
 865                 seq_printf(m, "Interrupt identity:  %08x\n",
 866                            I915_READ(IIR));
 867                 seq_printf(m, "Interrupt mask:      %08x\n",
 868                            I915_READ(IMR));
 869                 for_each_pipe(dev_priv, pipe)
 870                         seq_printf(m, "Pipe %c stat:         %08x\n",
 871                                    pipe_name(pipe),
 872                                    I915_READ(PIPESTAT(pipe)));
 873         } else {
 874                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 875                            I915_READ(DEIER));
 876                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 877                            I915_READ(DEIIR));
 878                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 879                            I915_READ(DEIMR));
 880                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 881                            I915_READ(SDEIER));
 882                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 883                            I915_READ(SDEIIR));
 884                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 885                            I915_READ(SDEIMR));
 886                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 887                            I915_READ(GTIER));
 888                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 889                            I915_READ(GTIIR));
 890                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 891                            I915_READ(GTIMR));
 892         }
 893         for_each_engine(engine, dev_priv) {
 894                 if (INTEL_GEN(dev_priv) >= 6) {
 895                         seq_printf(m,
 896                                    "Graphics Interrupt mask (%s):       %08x\n",
 897                                    engine->name, I915_READ_IMR(engine));
 898                 }
 899                 i915_ring_seqno_info(m, engine);
 900         }
 901         intel_runtime_pm_put(dev_priv);
 902
 903         return 0;
 904 }
 905
 906 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 907 {
 908         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 909         struct drm_device *dev = &dev_priv->drm;
 910         int i, ret;
 911
 912         ret = mutex_lock_interruptible(&dev->struct_mutex);
 913         if (ret)
 914                 return ret;
 915
 916         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 917         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 918                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 919
 920                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 921                            i, dev_priv->fence_regs[i].pin_count);
 922                 if (!vma)
 923                         seq_puts(m, "unused");
 924                 else
 925                         describe_obj(m, vma->obj);
 926                 seq_putc(m, '\n');
 927         }
 928
 929         mutex_unlock(&dev->struct_mutex);
 930         return 0;
 931 }
 932
 933 static int i915_hws_info(struct seq_file *m, void *data)
 934 {
 935         struct drm_info_node *node = m->private;
 936         struct drm_i915_private *dev_priv = node_to_i915(node);
 937         struct intel_engine_cs *engine;
 938         const u32 *hws;
 939         int i;
 940
 941         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 942         hws = engine->status_page.page_addr;
 943         if (hws == NULL)
 944                 return 0;
 945
 946         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 947                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 948                            i * 4,
 949                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 950         }
 951         return 0;
 952 }
 953
 954 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 955
 956 static ssize_t
 957 i915_error_state_write(struct file *filp,
 958                        const char __user *ubuf,
 959                        size_t cnt,
 960                        loff_t *ppos)
 961 {
 962         struct i915_error_state_file_priv *error_priv = filp->private_data;
 963
 964         DRM_DEBUG_DRIVER("Resetting error state\n");
 965         i915_destroy_error_state(error_priv->dev);
 966
 967         return cnt;
 968 }
 969
 970 static int i915_error_state_open(struct inode *inode, struct file *file)
 971 {
 972         struct drm_i915_private *dev_priv = inode->i_private;
 973         struct i915_error_state_file_priv *error_priv;
 974
 975         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 976         if (!error_priv)
 977                 return -ENOMEM;
 978
 979         error_priv->dev = &dev_priv->drm;
 980
 981         i915_error_state_get(&dev_priv->drm, error_priv);
 982
 983         file->private_data = error_priv;
 984
 985         return 0;
 986 }
 987
 988 static int i915_error_state_release(struct inode *inode, struct file *file)
 989 {
 990         struct i915_error_state_file_priv *error_priv = file->private_data;
 991
 992         i915_error_state_put(error_priv);
 993         kfree(error_priv);
 994
 995         return 0;
 996 }
 997
 998 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 999                                      size_t count, loff_t *pos)
1000 {
1001         struct i915_error_state_file_priv *error_priv = file->private_data;
1002         struct drm_i915_error_state_buf error_str;
1003         loff_t tmp_pos = 0;
1004         ssize_t ret_count = 0;
1005         int ret;
1006
1007         ret = i915_error_state_buf_init(&error_str,
1008                                         to_i915(error_priv->dev), count, *pos);
1009         if (ret)
1010                 return ret;
1011
1012         ret = i915_error_state_to_str(&error_str, error_priv);
1013         if (ret)
1014                 goto out;
1015
1016         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1017                                             error_str.buf,
1018                                             error_str.bytes);
1019
1020         if (ret_count < 0)
1021                 ret = ret_count;
1022         else
1023                 *pos = error_str.start + ret_count;
1024 out:
1025         i915_error_state_buf_release(&error_str);
1026         return ret ?: ret_count;
1027 }
1028
1029 static const struct file_operations i915_error_state_fops = {
1030         .owner = THIS_MODULE,
1031         .open = i915_error_state_open,
1032         .read = i915_error_state_read,
1033         .write = i915_error_state_write,
1034         .llseek = default_llseek,
1035         .release = i915_error_state_release,
1036 };
1037
1038 #endif
1039
1040 static int
1041 i915_next_seqno_get(void *data, u64 *val)
1042 {
1043         struct drm_i915_private *dev_priv = data;
1044         int ret;
1045
1046         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1047         if (ret)
1048                 return ret;
1049
1050         *val = dev_priv->next_seqno;
1051         mutex_unlock(&dev_priv->drm.struct_mutex);
1052
1053         return 0;
1054 }
1055
1056 static int
1057 i915_next_seqno_set(void *data, u64 val)
1058 {
1059         struct drm_i915_private *dev_priv = data;
1060         struct drm_device *dev = &dev_priv->drm;
1061         int ret;
1062
1063         ret = mutex_lock_interruptible(&dev->struct_mutex);
1064         if (ret)
1065                 return ret;
1066
1067         ret = i915_gem_set_seqno(dev, val);
1068         mutex_unlock(&dev->struct_mutex);
1069
1070         return ret;
1071 }
1072
1073 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1074                         i915_next_seqno_get, i915_next_seqno_set,
1075                         "0x%llx\n");
1076
1077 static int i915_frequency_info(struct seq_file *m, void *unused)
1078 {
1079         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1080         struct drm_device *dev = &dev_priv->drm;
1081         int ret = 0;
1082
1083         intel_runtime_pm_get(dev_priv);
1084
1085         if (IS_GEN5(dev_priv)) {
1086                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1087                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1088
1089                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1090                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1091                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1092                            MEMSTAT_VID_SHIFT);
1093                 seq_printf(m, "Current P-state: %d\n",
1094                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1095         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1096                 u32 freq_sts;
1097
1098                 mutex_lock(&dev_priv->rps.hw_lock);
1099                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1100                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1101                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1102
1103                 seq_printf(m, "actual GPU freq: %d MHz\n",
1104                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1105
1106                 seq_printf(m, "current GPU freq: %d MHz\n",
1107                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1108
1109                 seq_printf(m, "max GPU freq: %d MHz\n",
1110                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1111
1112                 seq_printf(m, "min GPU freq: %d MHz\n",
1113                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1114
1115                 seq_printf(m, "idle GPU freq: %d MHz\n",
1116                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1117
1118                 seq_printf(m,
1119                            "efficient (RPe) frequency: %d MHz\n",
1120                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1121                 mutex_unlock(&dev_priv->rps.hw_lock);
1122         } else if (INTEL_GEN(dev_priv) >= 6) {
1123                 u32 rp_state_limits;
1124                 u32 gt_perf_status;
1125                 u32 rp_state_cap;
1126                 u32 rpmodectl, rpinclimit, rpdeclimit;
1127                 u32 rpstat, cagf, reqf;
1128                 u32 rpupei, rpcurup, rpprevup;
1129                 u32 rpdownei, rpcurdown, rpprevdown;
1130                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1131                 int max_freq;
1132
1133                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1134                 if (IS_BROXTON(dev_priv)) {
1135                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1136                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1137                 } else {
1138                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1139                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1140                 }
1141
1142                 /* RPSTAT1 is in the GT power well */
1143                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1144                 if (ret)
1145                         goto out;
1146
1147                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1148
1149                 reqf = I915_READ(GEN6_RPNSWREQ);
1150                 if (IS_GEN9(dev_priv))
1151                         reqf >>= 23;
1152                 else {
1153                         reqf &= ~GEN6_TURBO_DISABLE;
1154                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1155                                 reqf >>= 24;
1156                         else
1157                                 reqf >>= 25;
1158                 }
1159                 reqf = intel_gpu_freq(dev_priv, reqf);
1160
1161                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1162                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1163                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1164
1165                 rpstat = I915_READ(GEN6_RPSTAT1);
1166                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1167                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1168                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1169                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1170                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1171                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1172                 if (IS_GEN9(dev_priv))
1173                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1174                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1175                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1176                 else
1177                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1178                 cagf = intel_gpu_freq(dev_priv, cagf);
1179
1180                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1181                 mutex_unlock(&dev->struct_mutex);
1182
1183                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1184                         pm_ier = I915_READ(GEN6_PMIER);
1185                         pm_imr = I915_READ(GEN6_PMIMR);
1186                         pm_isr = I915_READ(GEN6_PMISR);
1187                         pm_iir = I915_READ(GEN6_PMIIR);
1188                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1189                 } else {
1190                         pm_ier = I915_READ(GEN8_GT_IER(2));
1191                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1192                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1193                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1194                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1195                 }
1196                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1197                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1198                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1199                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1200                 seq_printf(m, "Render p-state ratio: %d\n",
1201                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1202                 seq_printf(m, "Render p-state VID: %d\n",
1203                            gt_perf_status & 0xff);
1204                 seq_printf(m, "Render p-state limit: %d\n",
1205                            rp_state_limits & 0xff);
1206                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1207                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1208                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1209                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1210                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1211                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1212                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1213                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1214                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1215                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1216                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1217                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1218                 seq_printf(m, "Up threshold: %d%%\n",
1219                            dev_priv->rps.up_threshold);
1220
1221                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1222                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1223                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1224                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1225                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1226                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1227                 seq_printf(m, "Down threshold: %d%%\n",
1228                            dev_priv->rps.down_threshold);
1229
1230                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1231                             rp_state_cap >> 16) & 0xff;
1232                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1233                              GEN9_FREQ_SCALER : 1);
1234                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1235                            intel_gpu_freq(dev_priv, max_freq));
1236
1237                 max_freq = (rp_state_cap & 0xff00) >> 8;
1238                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1239                              GEN9_FREQ_SCALER : 1);
1240                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1241                            intel_gpu_freq(dev_priv, max_freq));
1242
1243                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1244                             rp_state_cap >> 0) & 0xff;
1245                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1246                              GEN9_FREQ_SCALER : 1);
1247                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1248                            intel_gpu_freq(dev_priv, max_freq));
1249                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1250                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1251
1252                 seq_printf(m, "Current freq: %d MHz\n",
1253                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1254                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1255                 seq_printf(m, "Idle freq: %d MHz\n",
1256                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1257                 seq_printf(m, "Min freq: %d MHz\n",
1258                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1259                 seq_printf(m, "Boost freq: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1261                 seq_printf(m, "Max freq: %d MHz\n",
1262                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1263                 seq_printf(m,
1264                            "efficient (RPe) frequency: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1266         } else {
1267                 seq_puts(m, "no P-state info available\n");
1268         }
1269
1270         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1271         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1272         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1273
1274 out:
1275         intel_runtime_pm_put(dev_priv);
1276         return ret;
1277 }
1278
1279 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1280                                struct seq_file *m,
1281                                struct intel_instdone *instdone)
1282 {
1283         int slice;
1284         int subslice;
1285
1286         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1287                    instdone->instdone);
1288
1289         if (INTEL_GEN(dev_priv) <= 3)
1290                 return;
1291
1292         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1293                    instdone->slice_common);
1294
1295         if (INTEL_GEN(dev_priv) <= 6)
1296                 return;
1297
1298         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1299                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1300                            slice, subslice, instdone->sampler[slice][subslice]);
1301
1302         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1303                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1304                            slice, subslice, instdone->row[slice][subslice]);
1305 }
1306
1307 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1308 {
1309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1310         struct intel_engine_cs *engine;
1311         u64 acthd[I915_NUM_ENGINES];
1312         u32 seqno[I915_NUM_ENGINES];
1313         struct intel_instdone instdone;
1314         enum intel_engine_id id;
1315
1316         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1317                 seq_printf(m, "Wedged\n");
1318         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1319                 seq_printf(m, "Reset in progress\n");
1320         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1321                 seq_printf(m, "Waiter holding struct mutex\n");
1322         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1323                 seq_printf(m, "struct_mutex blocked for reset\n");
1324
1325         if (!i915.enable_hangcheck) {
1326                 seq_printf(m, "Hangcheck disabled\n");
1327                 return 0;
1328         }
1329
1330         intel_runtime_pm_get(dev_priv);
1331
1332         for_each_engine_id(engine, dev_priv, id) {
1333                 acthd[id] = intel_engine_get_active_head(engine);
1334                 seqno[id] = intel_engine_get_seqno(engine);
1335         }
1336
1337         intel_engine_get_instdone(&dev_priv->engine[RCS], &instdone);
1338
1339         intel_runtime_pm_put(dev_priv);
1340
1341         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1342                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1343                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1344                                             jiffies));
1345         } else
1346                 seq_printf(m, "Hangcheck inactive\n");
1347
1348         for_each_engine_id(engine, dev_priv, id) {
1349                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1350                 struct rb_node *rb;
1351
1352                 seq_printf(m, "%s:\n", engine->name);
1353                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1354                            engine->hangcheck.seqno,
1355                            seqno[id],
1356                            engine->last_submitted_seqno);
1357                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1358                            yesno(intel_engine_has_waiter(engine)),
1359                            yesno(test_bit(engine->id,
1360                                           &dev_priv->gpu_error.missed_irq_rings)));
1361                 spin_lock(&b->lock);
1362                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1363                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1364
1365                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1366                                    w->tsk->comm, w->tsk->pid, w->seqno);
1367                 }
1368                 spin_unlock(&b->lock);
1369
1370                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1371                            (long long)engine->hangcheck.acthd,
1372                            (long long)acthd[id]);
1373                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1374                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1375
1376                 if (engine->id == RCS) {
1377                         seq_puts(m, "\tinstdone read =\n");
1378
1379                         i915_instdone_info(dev_priv, m, &instdone);
1380
1381                         seq_puts(m, "\tinstdone accu =\n");
1382
1383                         i915_instdone_info(dev_priv, m,
1384                                            &engine->hangcheck.instdone);
1385                 }
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int ironlake_drpc_info(struct seq_file *m)
1392 {
1393         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1394         struct drm_device *dev = &dev_priv->drm;
1395         u32 rgvmodectl, rstdbyctl;
1396         u16 crstandvid;
1397         int ret;
1398
1399         ret = mutex_lock_interruptible(&dev->struct_mutex);
1400         if (ret)
1401                 return ret;
1402         intel_runtime_pm_get(dev_priv);
1403
1404         rgvmodectl = I915_READ(MEMMODECTL);
1405         rstdbyctl = I915_READ(RSTDBYCTL);
1406         crstandvid = I915_READ16(CRSTANDVID);
1407
1408         intel_runtime_pm_put(dev_priv);
1409         mutex_unlock(&dev->struct_mutex);
1410
1411         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1412         seq_printf(m, "Boost freq: %d\n",
1413                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1414                    MEMMODE_BOOST_FREQ_SHIFT);
1415         seq_printf(m, "HW control enabled: %s\n",
1416                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1417         seq_printf(m, "SW control enabled: %s\n",
1418                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1419         seq_printf(m, "Gated voltage change: %s\n",
1420                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1421         seq_printf(m, "Starting frequency: P%d\n",
1422                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1423         seq_printf(m, "Max P-state: P%d\n",
1424                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1425         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1426         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1427         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1428         seq_printf(m, "Render standby enabled: %s\n",
1429                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1430         seq_puts(m, "Current RS state: ");
1431         switch (rstdbyctl & RSX_STATUS_MASK) {
1432         case RSX_STATUS_ON:
1433                 seq_puts(m, "on\n");
1434                 break;
1435         case RSX_STATUS_RC1:
1436                 seq_puts(m, "RC1\n");
1437                 break;
1438         case RSX_STATUS_RC1E:
1439                 seq_puts(m, "RC1E\n");
1440                 break;
1441         case RSX_STATUS_RS1:
1442                 seq_puts(m, "RS1\n");
1443                 break;
1444         case RSX_STATUS_RS2:
1445                 seq_puts(m, "RS2 (RC6)\n");
1446                 break;
1447         case RSX_STATUS_RS3:
1448                 seq_puts(m, "RC3 (RC6+)\n");
1449                 break;
1450         default:
1451                 seq_puts(m, "unknown\n");
1452                 break;
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int i915_forcewake_domains(struct seq_file *m, void *data)
1459 {
1460         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1461         struct intel_uncore_forcewake_domain *fw_domain;
1462
1463         spin_lock_irq(&dev_priv->uncore.lock);
1464         for_each_fw_domain(fw_domain, dev_priv) {
1465                 seq_printf(m, "%s.wake_count = %u\n",
1466                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1467                            fw_domain->wake_count);
1468         }
1469         spin_unlock_irq(&dev_priv->uncore.lock);
1470
1471         return 0;
1472 }
1473
1474 static int vlv_drpc_info(struct seq_file *m)
1475 {
1476         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1477         u32 rpmodectl1, rcctl1, pw_status;
1478
1479         intel_runtime_pm_get(dev_priv);
1480
1481         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1482         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1483         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1484
1485         intel_runtime_pm_put(dev_priv);
1486
1487         seq_printf(m, "Video Turbo Mode: %s\n",
1488                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1489         seq_printf(m, "Turbo enabled: %s\n",
1490                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1491         seq_printf(m, "HW control enabled: %s\n",
1492                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1493         seq_printf(m, "SW control enabled: %s\n",
1494                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1495                           GEN6_RP_MEDIA_SW_MODE));
1496         seq_printf(m, "RC6 Enabled: %s\n",
1497                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1498                                         GEN6_RC_CTL_EI_MODE(1))));
1499         seq_printf(m, "Render Power Well: %s\n",
1500                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1501         seq_printf(m, "Media Power Well: %s\n",
1502                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1503
1504         seq_printf(m, "Render RC6 residency since boot: %u\n",
1505                    I915_READ(VLV_GT_RENDER_RC6));
1506         seq_printf(m, "Media RC6 residency since boot: %u\n",
1507                    I915_READ(VLV_GT_MEDIA_RC6));
1508
1509         return i915_forcewake_domains(m, NULL);
1510 }
1511
1512 static int gen6_drpc_info(struct seq_file *m)
1513 {
1514         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1515         struct drm_device *dev = &dev_priv->drm;
1516         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1517         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1518         unsigned forcewake_count;
1519         int count = 0, ret;
1520
1521         ret = mutex_lock_interruptible(&dev->struct_mutex);
1522         if (ret)
1523                 return ret;
1524         intel_runtime_pm_get(dev_priv);
1525
1526         spin_lock_irq(&dev_priv->uncore.lock);
1527         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1528         spin_unlock_irq(&dev_priv->uncore.lock);
1529
1530         if (forcewake_count) {
1531                 seq_puts(m, "RC information inaccurate because somebody "
1532                             "holds a forcewake reference \n");
1533         } else {
1534                 /* NB: we cannot use forcewake, else we read the wrong values */
1535                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1536                         udelay(10);
1537                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1538         }
1539
1540         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1541         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1542
1543         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1544         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1545         if (INTEL_GEN(dev_priv) >= 9) {
1546                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1547                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1548         }
1549         mutex_unlock(&dev->struct_mutex);
1550         mutex_lock(&dev_priv->rps.hw_lock);
1551         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1552         mutex_unlock(&dev_priv->rps.hw_lock);
1553
1554         intel_runtime_pm_put(dev_priv);
1555
1556         seq_printf(m, "Video Turbo Mode: %s\n",
1557                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1558         seq_printf(m, "HW control enabled: %s\n",
1559                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1560         seq_printf(m, "SW control enabled: %s\n",
1561                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1562                           GEN6_RP_MEDIA_SW_MODE));
1563         seq_printf(m, "RC1e Enabled: %s\n",
1564                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1565         seq_printf(m, "RC6 Enabled: %s\n",
1566                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1567         if (INTEL_GEN(dev_priv) >= 9) {
1568                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1569                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1570                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1571                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1572         }
1573         seq_printf(m, "Deep RC6 Enabled: %s\n",
1574                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1575         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1576                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1577         seq_puts(m, "Current RC state: ");
1578         switch (gt_core_status & GEN6_RCn_MASK) {
1579         case GEN6_RC0:
1580                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1581                         seq_puts(m, "Core Power Down\n");
1582                 else
1583                         seq_puts(m, "on\n");
1584                 break;
1585         case GEN6_RC3:
1586                 seq_puts(m, "RC3\n");
1587                 break;
1588         case GEN6_RC6:
1589                 seq_puts(m, "RC6\n");
1590                 break;
1591         case GEN6_RC7:
1592                 seq_puts(m, "RC7\n");
1593                 break;
1594         default:
1595                 seq_puts(m, "Unknown\n");
1596                 break;
1597         }
1598
1599         seq_printf(m, "Core Power Down: %s\n",
1600                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1601         if (INTEL_GEN(dev_priv) >= 9) {
1602                 seq_printf(m, "Render Power Well: %s\n",
1603                         (gen9_powergate_status &
1604                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1605                 seq_printf(m, "Media Power Well: %s\n",
1606                         (gen9_powergate_status &
1607                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1608         }
1609
1610         /* Not exactly sure what this is */
1611         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1612                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1613         seq_printf(m, "RC6 residency since boot: %u\n",
1614                    I915_READ(GEN6_GT_GFX_RC6));
1615         seq_printf(m, "RC6+ residency since boot: %u\n",
1616                    I915_READ(GEN6_GT_GFX_RC6p));
1617         seq_printf(m, "RC6++ residency since boot: %u\n",
1618                    I915_READ(GEN6_GT_GFX_RC6pp));
1619
1620         seq_printf(m, "RC6   voltage: %dmV\n",
1621                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1622         seq_printf(m, "RC6+  voltage: %dmV\n",
1623                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1624         seq_printf(m, "RC6++ voltage: %dmV\n",
1625                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1626         return i915_forcewake_domains(m, NULL);
1627 }
1628
1629 static int i915_drpc_info(struct seq_file *m, void *unused)
1630 {
1631         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1632
1633         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1634                 return vlv_drpc_info(m);
1635         else if (INTEL_GEN(dev_priv) >= 6)
1636                 return gen6_drpc_info(m);
1637         else
1638                 return ironlake_drpc_info(m);
1639 }
1640
1641 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1642 {
1643         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1644
1645         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1646                    dev_priv->fb_tracking.busy_bits);
1647
1648         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1649                    dev_priv->fb_tracking.flip_bits);
1650
1651         return 0;
1652 }
1653
1654 static int i915_fbc_status(struct seq_file *m, void *unused)
1655 {
1656         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1657
1658         if (!HAS_FBC(dev_priv)) {
1659                 seq_puts(m, "FBC unsupported on this chipset\n");
1660                 return 0;
1661         }
1662
1663         intel_runtime_pm_get(dev_priv);
1664         mutex_lock(&dev_priv->fbc.lock);
1665
1666         if (intel_fbc_is_active(dev_priv))
1667                 seq_puts(m, "FBC enabled\n");
1668         else
1669                 seq_printf(m, "FBC disabled: %s\n",
1670                            dev_priv->fbc.no_fbc_reason);
1671
1672         if (intel_fbc_is_active(dev_priv) &&
1673             INTEL_GEN(dev_priv) >= 7)
1674                 seq_printf(m, "Compressing: %s\n",
1675                            yesno(I915_READ(FBC_STATUS2) &
1676                                  FBC_COMPRESSION_MASK));
1677
1678         mutex_unlock(&dev_priv->fbc.lock);
1679         intel_runtime_pm_put(dev_priv);
1680
1681         return 0;
1682 }
1683
1684 static int i915_fbc_fc_get(void *data, u64 *val)
1685 {
1686         struct drm_i915_private *dev_priv = data;
1687
1688         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1689                 return -ENODEV;
1690
1691         *val = dev_priv->fbc.false_color;
1692
1693         return 0;
1694 }
1695
1696 static int i915_fbc_fc_set(void *data, u64 val)
1697 {
1698         struct drm_i915_private *dev_priv = data;
1699         u32 reg;
1700
1701         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1702                 return -ENODEV;
1703
1704         mutex_lock(&dev_priv->fbc.lock);
1705
1706         reg = I915_READ(ILK_DPFC_CONTROL);
1707         dev_priv->fbc.false_color = val;
1708
1709         I915_WRITE(ILK_DPFC_CONTROL, val ?
1710                    (reg | FBC_CTL_FALSE_COLOR) :
1711                    (reg & ~FBC_CTL_FALSE_COLOR));
1712
1713         mutex_unlock(&dev_priv->fbc.lock);
1714         return 0;
1715 }
1716
1717 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1718                         i915_fbc_fc_get, i915_fbc_fc_set,
1719                         "%llu\n");
1720
1721 static int i915_ips_status(struct seq_file *m, void *unused)
1722 {
1723         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1724
1725         if (!HAS_IPS(dev_priv)) {
1726                 seq_puts(m, "not supported\n");
1727                 return 0;
1728         }
1729
1730         intel_runtime_pm_get(dev_priv);
1731
1732         seq_printf(m, "Enabled by kernel parameter: %s\n",
1733                    yesno(i915.enable_ips));
1734
1735         if (INTEL_GEN(dev_priv) >= 8) {
1736                 seq_puts(m, "Currently: unknown\n");
1737         } else {
1738                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1739                         seq_puts(m, "Currently: enabled\n");
1740                 else
1741                         seq_puts(m, "Currently: disabled\n");
1742         }
1743
1744         intel_runtime_pm_put(dev_priv);
1745
1746         return 0;
1747 }
1748
1749 static int i915_sr_status(struct seq_file *m, void *unused)
1750 {
1751         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1752         bool sr_enabled = false;
1753
1754         intel_runtime_pm_get(dev_priv);
1755
1756         if (HAS_PCH_SPLIT(dev_priv))
1757                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1759                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1760                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761         else if (IS_I915GM(dev_priv))
1762                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763         else if (IS_PINEVIEW(dev_priv))
1764                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1766                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767
1768         intel_runtime_pm_put(dev_priv);
1769
1770         seq_printf(m, "self-refresh: %s\n",
1771                    sr_enabled ? "enabled" : "disabled");
1772
1773         return 0;
1774 }
1775
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1777 {
1778         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1779         struct drm_device *dev = &dev_priv->drm;
1780         unsigned long temp, chipset, gfx;
1781         int ret;
1782
1783         if (!IS_GEN5(dev_priv))
1784                 return -ENODEV;
1785
1786         ret = mutex_lock_interruptible(&dev->struct_mutex);
1787         if (ret)
1788                 return ret;
1789
1790         temp = i915_mch_val(dev_priv);
1791         chipset = i915_chipset_val(dev_priv);
1792         gfx = i915_gfx_val(dev_priv);
1793         mutex_unlock(&dev->struct_mutex);
1794
1795         seq_printf(m, "GMCH temp: %ld\n", temp);
1796         seq_printf(m, "Chipset power: %ld\n", chipset);
1797         seq_printf(m, "GFX power: %ld\n", gfx);
1798         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1799
1800         return 0;
1801 }
1802
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1804 {
1805         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1806         int ret = 0;
1807         int gpu_freq, ia_freq;
1808         unsigned int max_gpu_freq, min_gpu_freq;
1809
1810         if (!HAS_LLC(dev_priv)) {
1811                 seq_puts(m, "unsupported on this chipset\n");
1812                 return 0;
1813         }
1814
1815         intel_runtime_pm_get(dev_priv);
1816
1817         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1818         if (ret)
1819                 goto out;
1820
1821         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1822                 /* Convert GT frequency to 50 HZ units */
1823                 min_gpu_freq =
1824                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1825                 max_gpu_freq =
1826                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1827         } else {
1828                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1829                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1830         }
1831
1832         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1833
1834         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1835                 ia_freq = gpu_freq;
1836                 sandybridge_pcode_read(dev_priv,
1837                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1838                                        &ia_freq);
1839                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1840                            intel_gpu_freq(dev_priv, (gpu_freq *
1841                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1842                                  GEN9_FREQ_SCALER : 1))),
1843                            ((ia_freq >> 0) & 0xff) * 100,
1844                            ((ia_freq >> 8) & 0xff) * 100);
1845         }
1846
1847         mutex_unlock(&dev_priv->rps.hw_lock);
1848
1849 out:
1850         intel_runtime_pm_put(dev_priv);
1851         return ret;
1852 }
1853
1854 static int i915_opregion(struct seq_file *m, void *unused)
1855 {
1856         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1857         struct drm_device *dev = &dev_priv->drm;
1858         struct intel_opregion *opregion = &dev_priv->opregion;
1859         int ret;
1860
1861         ret = mutex_lock_interruptible(&dev->struct_mutex);
1862         if (ret)
1863                 goto out;
1864
1865         if (opregion->header)
1866                 seq_write(m, opregion->header, OPREGION_SIZE);
1867
1868         mutex_unlock(&dev->struct_mutex);
1869
1870 out:
1871         return 0;
1872 }
1873
1874 static int i915_vbt(struct seq_file *m, void *unused)
1875 {
1876         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1877
1878         if (opregion->vbt)
1879                 seq_write(m, opregion->vbt, opregion->vbt_size);
1880
1881         return 0;
1882 }
1883
1884 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1885 {
1886         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1887         struct drm_device *dev = &dev_priv->drm;
1888         struct intel_framebuffer *fbdev_fb = NULL;
1889         struct drm_framebuffer *drm_fb;
1890         int ret;
1891
1892         ret = mutex_lock_interruptible(&dev->struct_mutex);
1893         if (ret)
1894                 return ret;
1895
1896 #ifdef CONFIG_DRM_FBDEV_EMULATION
1897         if (dev_priv->fbdev) {
1898                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1899
1900                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1901                            fbdev_fb->base.width,
1902                            fbdev_fb->base.height,
1903                            fbdev_fb->base.depth,
1904                            fbdev_fb->base.bits_per_pixel,
1905                            fbdev_fb->base.modifier[0],
1906                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1907                 describe_obj(m, fbdev_fb->obj);
1908                 seq_putc(m, '\n');
1909         }
1910 #endif
1911
1912         mutex_lock(&dev->mode_config.fb_lock);
1913         drm_for_each_fb(drm_fb, dev) {
1914                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1915                 if (fb == fbdev_fb)
1916                         continue;
1917
1918                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1919                            fb->base.width,
1920                            fb->base.height,
1921                            fb->base.depth,
1922                            fb->base.bits_per_pixel,
1923                            fb->base.modifier[0],
1924                            drm_framebuffer_read_refcount(&fb->base));
1925                 describe_obj(m, fb->obj);
1926                 seq_putc(m, '\n');
1927         }
1928         mutex_unlock(&dev->mode_config.fb_lock);
1929         mutex_unlock(&dev->struct_mutex);
1930
1931         return 0;
1932 }
1933
1934 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1935 {
1936         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1937                    ring->space, ring->head, ring->tail,
1938                    ring->last_retired_head);
1939 }
1940
1941 static int i915_context_status(struct seq_file *m, void *unused)
1942 {
1943         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1944         struct drm_device *dev = &dev_priv->drm;
1945         struct intel_engine_cs *engine;
1946         struct i915_gem_context *ctx;
1947         int ret;
1948
1949         ret = mutex_lock_interruptible(&dev->struct_mutex);
1950         if (ret)
1951                 return ret;
1952
1953         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1954                 seq_printf(m, "HW context %u ", ctx->hw_id);
1955                 if (ctx->pid) {
1956                         struct task_struct *task;
1957
1958                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1959                         if (task) {
1960                                 seq_printf(m, "(%s [%d]) ",
1961                                            task->comm, task->pid);
1962                                 put_task_struct(task);
1963                         }
1964                 } else if (IS_ERR(ctx->file_priv)) {
1965                         seq_puts(m, "(deleted) ");
1966                 } else {
1967                         seq_puts(m, "(kernel) ");
1968                 }
1969
1970                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1971                 seq_putc(m, '\n');
1972
1973                 for_each_engine(engine, dev_priv) {
1974                         struct intel_context *ce = &ctx->engine[engine->id];
1975
1976                         seq_printf(m, "%s: ", engine->name);
1977                         seq_putc(m, ce->initialised ? 'I' : 'i');
1978                         if (ce->state)
1979                                 describe_obj(m, ce->state->obj);
1980                         if (ce->ring)
1981                                 describe_ctx_ring(m, ce->ring);
1982                         seq_putc(m, '\n');
1983                 }
1984
1985                 seq_putc(m, '\n');
1986         }
1987
1988         mutex_unlock(&dev->struct_mutex);
1989
1990         return 0;
1991 }
1992
1993 static void i915_dump_lrc_obj(struct seq_file *m,
1994                               struct i915_gem_context *ctx,
1995                               struct intel_engine_cs *engine)
1996 {
1997         struct i915_vma *vma = ctx->engine[engine->id].state;
1998         struct page *page;
1999         int j;
2000
2001         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2002
2003         if (!vma) {
2004                 seq_puts(m, "\tFake context\n");
2005                 return;
2006         }
2007
2008         if (vma->flags & I915_VMA_GLOBAL_BIND)
2009                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2010                            i915_ggtt_offset(vma));
2011
2012         if (i915_gem_object_get_pages(vma->obj)) {
2013                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2014                 return;
2015         }
2016
2017         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2018         if (page) {
2019                 u32 *reg_state = kmap_atomic(page);
2020
2021                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2022                         seq_printf(m,
2023                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2024                                    j * 4,
2025                                    reg_state[j], reg_state[j + 1],
2026                                    reg_state[j + 2], reg_state[j + 3]);
2027                 }
2028                 kunmap_atomic(reg_state);
2029         }
2030
2031         seq_putc(m, '\n');
2032 }
2033
2034 static int i915_dump_lrc(struct seq_file *m, void *unused)
2035 {
2036         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2037         struct drm_device *dev = &dev_priv->drm;
2038         struct intel_engine_cs *engine;
2039         struct i915_gem_context *ctx;
2040         int ret;
2041
2042         if (!i915.enable_execlists) {
2043                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2044                 return 0;
2045         }
2046
2047         ret = mutex_lock_interruptible(&dev->struct_mutex);
2048         if (ret)
2049                 return ret;
2050
2051         list_for_each_entry(ctx, &dev_priv->context_list, link)
2052                 for_each_engine(engine, dev_priv)
2053                         i915_dump_lrc_obj(m, ctx, engine);
2054
2055         mutex_unlock(&dev->struct_mutex);
2056
2057         return 0;
2058 }
2059
2060 static const char *swizzle_string(unsigned swizzle)
2061 {
2062         switch (swizzle) {
2063         case I915_BIT_6_SWIZZLE_NONE:
2064                 return "none";
2065         case I915_BIT_6_SWIZZLE_9:
2066                 return "bit9";
2067         case I915_BIT_6_SWIZZLE_9_10:
2068                 return "bit9/bit10";
2069         case I915_BIT_6_SWIZZLE_9_11:
2070                 return "bit9/bit11";
2071         case I915_BIT_6_SWIZZLE_9_10_11:
2072                 return "bit9/bit10/bit11";
2073         case I915_BIT_6_SWIZZLE_9_17:
2074                 return "bit9/bit17";
2075         case I915_BIT_6_SWIZZLE_9_10_17:
2076                 return "bit9/bit10/bit17";
2077         case I915_BIT_6_SWIZZLE_UNKNOWN:
2078                 return "unknown";
2079         }
2080
2081         return "bug";
2082 }
2083
2084 static int i915_swizzle_info(struct seq_file *m, void *data)
2085 {
2086         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2087         struct drm_device *dev = &dev_priv->drm;
2088         int ret;
2089
2090         ret = mutex_lock_interruptible(&dev->struct_mutex);
2091         if (ret)
2092                 return ret;
2093         intel_runtime_pm_get(dev_priv);
2094
2095         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2096                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2097         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2098                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2099
2100         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2101                 seq_printf(m, "DDC = 0x%08x\n",
2102                            I915_READ(DCC));
2103                 seq_printf(m, "DDC2 = 0x%08x\n",
2104                            I915_READ(DCC2));
2105                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2106                            I915_READ16(C0DRB3));
2107                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2108                            I915_READ16(C1DRB3));
2109         } else if (INTEL_GEN(dev_priv) >= 6) {
2110                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2111                            I915_READ(MAD_DIMM_C0));
2112                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2113                            I915_READ(MAD_DIMM_C1));
2114                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2115                            I915_READ(MAD_DIMM_C2));
2116                 seq_printf(m, "TILECTL = 0x%08x\n",
2117                            I915_READ(TILECTL));
2118                 if (INTEL_GEN(dev_priv) >= 8)
2119                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2120                                    I915_READ(GAMTARBMODE));
2121                 else
2122                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2123                                    I915_READ(ARB_MODE));
2124                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2125                            I915_READ(DISP_ARB_CTL));
2126         }
2127
2128         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2129                 seq_puts(m, "L-shaped memory detected\n");
2130
2131         intel_runtime_pm_put(dev_priv);
2132         mutex_unlock(&dev->struct_mutex);
2133
2134         return 0;
2135 }
2136
2137 static int per_file_ctx(int id, void *ptr, void *data)
2138 {
2139         struct i915_gem_context *ctx = ptr;
2140         struct seq_file *m = data;
2141         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2142
2143         if (!ppgtt) {
2144                 seq_printf(m, "  no ppgtt for context %d\n",
2145                            ctx->user_handle);
2146                 return 0;
2147         }
2148
2149         if (i915_gem_context_is_default(ctx))
2150                 seq_puts(m, "  default context:\n");
2151         else
2152                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2153         ppgtt->debug_dump(ppgtt, m);
2154
2155         return 0;
2156 }
2157
2158 static void gen8_ppgtt_info(struct seq_file *m,
2159                             struct drm_i915_private *dev_priv)
2160 {
2161         struct intel_engine_cs *engine;
2162         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2163         int i;
2164
2165         if (!ppgtt)
2166                 return;
2167
2168         for_each_engine(engine, dev_priv) {
2169                 seq_printf(m, "%s\n", engine->name);
2170                 for (i = 0; i < 4; i++) {
2171                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2172                         pdp <<= 32;
2173                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2174                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2175                 }
2176         }
2177 }
2178
2179 static void gen6_ppgtt_info(struct seq_file *m,
2180                             struct drm_i915_private *dev_priv)
2181 {
2182         struct intel_engine_cs *engine;
2183
2184         if (IS_GEN6(dev_priv))
2185                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2186
2187         for_each_engine(engine, dev_priv) {
2188                 seq_printf(m, "%s\n", engine->name);
2189                 if (IS_GEN7(dev_priv))
2190                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2191                                    I915_READ(RING_MODE_GEN7(engine)));
2192                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2193                            I915_READ(RING_PP_DIR_BASE(engine)));
2194                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2195                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2196                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2197                            I915_READ(RING_PP_DIR_DCLV(engine)));
2198         }
2199         if (dev_priv->mm.aliasing_ppgtt) {
2200                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2201
2202                 seq_puts(m, "aliasing PPGTT:\n");
2203                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2204
2205                 ppgtt->debug_dump(ppgtt, m);
2206         }
2207
2208         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2209 }
2210
2211 static int i915_ppgtt_info(struct seq_file *m, void *data)
2212 {
2213         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2214         struct drm_device *dev = &dev_priv->drm;
2215         struct drm_file *file;
2216         int ret;
2217
2218         mutex_lock(&dev->filelist_mutex);
2219         ret = mutex_lock_interruptible(&dev->struct_mutex);
2220         if (ret)
2221                 goto out_unlock;
2222
2223         intel_runtime_pm_get(dev_priv);
2224
2225         if (INTEL_GEN(dev_priv) >= 8)
2226                 gen8_ppgtt_info(m, dev_priv);
2227         else if (INTEL_GEN(dev_priv) >= 6)
2228                 gen6_ppgtt_info(m, dev_priv);
2229
2230         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2231                 struct drm_i915_file_private *file_priv = file->driver_priv;
2232                 struct task_struct *task;
2233
2234                 task = get_pid_task(file->pid, PIDTYPE_PID);
2235                 if (!task) {
2236                         ret = -ESRCH;
2237                         goto out_rpm;
2238                 }
2239                 seq_printf(m, "\nproc: %s\n", task->comm);
2240                 put_task_struct(task);
2241                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2242                              (void *)(unsigned long)m);
2243         }
2244
2245 out_rpm:
2246         intel_runtime_pm_put(dev_priv);
2247         mutex_unlock(&dev->struct_mutex);
2248 out_unlock:
2249         mutex_unlock(&dev->filelist_mutex);
2250         return ret;
2251 }
2252
2253 static int count_irq_waiters(struct drm_i915_private *i915)
2254 {
2255         struct intel_engine_cs *engine;
2256         int count = 0;
2257
2258         for_each_engine(engine, i915)
2259                 count += intel_engine_has_waiter(engine);
2260
2261         return count;
2262 }
2263
2264 static const char *rps_power_to_str(unsigned int power)
2265 {
2266         static const char * const strings[] = {
2267                 [LOW_POWER] = "low power",
2268                 [BETWEEN] = "mixed",
2269                 [HIGH_POWER] = "high power",
2270         };
2271
2272         if (power >= ARRAY_SIZE(strings) || !strings[power])
2273                 return "unknown";
2274
2275         return strings[power];
2276 }
2277
2278 static int i915_rps_boost_info(struct seq_file *m, void *data)
2279 {
2280         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2281         struct drm_device *dev = &dev_priv->drm;
2282         struct drm_file *file;
2283
2284         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2285         seq_printf(m, "GPU busy? %s [%x]\n",
2286                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2287         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2288         seq_printf(m, "Frequency requested %d\n",
2289                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2290         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2291                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2292                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2293                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2295         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2296                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2297                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2299
2300         mutex_lock(&dev->filelist_mutex);
2301         spin_lock(&dev_priv->rps.client_lock);
2302         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2303                 struct drm_i915_file_private *file_priv = file->driver_priv;
2304                 struct task_struct *task;
2305
2306                 rcu_read_lock();
2307                 task = pid_task(file->pid, PIDTYPE_PID);
2308                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2309                            task ? task->comm : "<unknown>",
2310                            task ? task->pid : -1,
2311                            file_priv->rps.boosts,
2312                            list_empty(&file_priv->rps.link) ? "" : ", active");
2313                 rcu_read_unlock();
2314         }
2315         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2316         spin_unlock(&dev_priv->rps.client_lock);
2317         mutex_unlock(&dev->filelist_mutex);
2318
2319         if (INTEL_GEN(dev_priv) >= 6 &&
2320             dev_priv->rps.enabled &&
2321             dev_priv->gt.active_engines) {
2322                 u32 rpup, rpupei;
2323                 u32 rpdown, rpdownei;
2324
2325                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2326                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2327                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2328                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2329                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2330                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2331
2332                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2333                            rps_power_to_str(dev_priv->rps.power));
2334                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2335                            100 * rpup / rpupei,
2336                            dev_priv->rps.up_threshold);
2337                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2338                            100 * rpdown / rpdownei,
2339                            dev_priv->rps.down_threshold);
2340         } else {
2341                 seq_puts(m, "\nRPS Autotuning inactive\n");
2342         }
2343
2344         return 0;
2345 }
2346
2347 static int i915_llc(struct seq_file *m, void *data)
2348 {
2349         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2350         const bool edram = INTEL_GEN(dev_priv) > 8;
2351
2352         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2353         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2354                    intel_uncore_edram_size(dev_priv)/1024/1024);
2355
2356         return 0;
2357 }
2358
2359 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2360 {
2361         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2362         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2363         u32 tmp, i;
2364
2365         if (!HAS_GUC_UCODE(dev_priv))
2366                 return 0;
2367
2368         seq_printf(m, "GuC firmware status:\n");
2369         seq_printf(m, "\tpath: %s\n",
2370                 guc_fw->guc_fw_path);
2371         seq_printf(m, "\tfetch: %s\n",
2372                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2373         seq_printf(m, "\tload: %s\n",
2374                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2375         seq_printf(m, "\tversion wanted: %d.%d\n",
2376                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2377         seq_printf(m, "\tversion found: %d.%d\n",
2378                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2379         seq_printf(m, "\theader: offset is %d; size = %d\n",
2380                 guc_fw->header_offset, guc_fw->header_size);
2381         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2382                 guc_fw->ucode_offset, guc_fw->ucode_size);
2383         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2384                 guc_fw->rsa_offset, guc_fw->rsa_size);
2385
2386         tmp = I915_READ(GUC_STATUS);
2387
2388         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2389         seq_printf(m, "\tBootrom status = 0x%x\n",
2390                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2391         seq_printf(m, "\tuKernel status = 0x%x\n",
2392                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2393         seq_printf(m, "\tMIA Core status = 0x%x\n",
2394                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2395         seq_puts(m, "\nScratch registers:\n");
2396         for (i = 0; i < 16; i++)
2397                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2398
2399         return 0;
2400 }
2401
2402 static void i915_guc_client_info(struct seq_file *m,
2403                                  struct drm_i915_private *dev_priv,
2404                                  struct i915_guc_client *client)
2405 {
2406         struct intel_engine_cs *engine;
2407         enum intel_engine_id id;
2408         uint64_t tot = 0;
2409
2410         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2411                 client->priority, client->ctx_index, client->proc_desc_offset);
2412         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2413                 client->doorbell_id, client->doorbell_offset, client->cookie);
2414         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2415                 client->wq_size, client->wq_offset, client->wq_tail);
2416
2417         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2418         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2419         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2420
2421         for_each_engine_id(engine, dev_priv, id) {
2422                 u64 submissions = client->submissions[id];
2423                 tot += submissions;
2424                 seq_printf(m, "\tSubmissions: %llu %s\n",
2425                                 submissions, engine->name);
2426         }
2427         seq_printf(m, "\tTotal: %llu\n", tot);
2428 }
2429
2430 static int i915_guc_info(struct seq_file *m, void *data)
2431 {
2432         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2433         struct drm_device *dev = &dev_priv->drm;
2434         struct intel_guc guc;
2435         struct i915_guc_client client = {};
2436         struct intel_engine_cs *engine;
2437         enum intel_engine_id id;
2438         u64 total = 0;
2439
2440         if (!HAS_GUC_SCHED(dev_priv))
2441                 return 0;
2442
2443         if (mutex_lock_interruptible(&dev->struct_mutex))
2444                 return 0;
2445
2446         /* Take a local copy of the GuC data, so we can dump it at leisure */
2447         guc = dev_priv->guc;
2448         if (guc.execbuf_client)
2449                 client = *guc.execbuf_client;
2450
2451         mutex_unlock(&dev->struct_mutex);
2452
2453         seq_printf(m, "Doorbell map:\n");
2454         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2455         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2456
2457         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2458         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2459         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2460         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2461         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2462
2463         seq_printf(m, "\nGuC submissions:\n");
2464         for_each_engine_id(engine, dev_priv, id) {
2465                 u64 submissions = guc.submissions[id];
2466                 total += submissions;
2467                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2468                         engine->name, submissions, guc.last_seqno[id]);
2469         }
2470         seq_printf(m, "\t%s: %llu\n", "Total", total);
2471
2472         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2473         i915_guc_client_info(m, dev_priv, &client);
2474
2475         /* Add more as required ... */
2476
2477         return 0;
2478 }
2479
2480 static int i915_guc_log_dump(struct seq_file *m, void *data)
2481 {
2482         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2483         struct drm_i915_gem_object *obj;
2484         int i = 0, pg;
2485
2486         if (!dev_priv->guc.log_vma)
2487                 return 0;
2488
2489         obj = dev_priv->guc.log_vma->obj;
2490         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2491                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2492
2493                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2494                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2495                                    *(log + i), *(log + i + 1),
2496                                    *(log + i + 2), *(log + i + 3));
2497
2498                 kunmap_atomic(log);
2499         }
2500
2501         seq_putc(m, '\n');
2502
2503         return 0;
2504 }
2505
2506 static int i915_edp_psr_status(struct seq_file *m, void *data)
2507 {
2508         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2509         u32 psrperf = 0;
2510         u32 stat[3];
2511         enum pipe pipe;
2512         bool enabled = false;
2513
2514         if (!HAS_PSR(dev_priv)) {
2515                 seq_puts(m, "PSR not supported\n");
2516                 return 0;
2517         }
2518
2519         intel_runtime_pm_get(dev_priv);
2520
2521         mutex_lock(&dev_priv->psr.lock);
2522         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2523         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2524         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2525         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2526         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2527                    dev_priv->psr.busy_frontbuffer_bits);
2528         seq_printf(m, "Re-enable work scheduled: %s\n",
2529                    yesno(work_busy(&dev_priv->psr.work.work)));
2530
2531         if (HAS_DDI(dev_priv))
2532                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2533         else {
2534                 for_each_pipe(dev_priv, pipe) {
2535                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2536                                 VLV_EDP_PSR_CURR_STATE_MASK;
2537                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2538                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2539                                 enabled = true;
2540                 }
2541         }
2542
2543         seq_printf(m, "Main link in standby mode: %s\n",
2544                    yesno(dev_priv->psr.link_standby));
2545
2546         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2547
2548         if (!HAS_DDI(dev_priv))
2549                 for_each_pipe(dev_priv, pipe) {
2550                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2551                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2552                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2553                 }
2554         seq_puts(m, "\n");
2555
2556         /*
2557          * VLV/CHV PSR has no kind of performance counter
2558          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2559          */
2560         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2561                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2562                         EDP_PSR_PERF_CNT_MASK;
2563
2564                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2565         }
2566         mutex_unlock(&dev_priv->psr.lock);
2567
2568         intel_runtime_pm_put(dev_priv);
2569         return 0;
2570 }
2571
2572 static int i915_sink_crc(struct seq_file *m, void *data)
2573 {
2574         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2575         struct drm_device *dev = &dev_priv->drm;
2576         struct intel_connector *connector;
2577         struct intel_dp *intel_dp = NULL;
2578         int ret;
2579         u8 crc[6];
2580
2581         drm_modeset_lock_all(dev);
2582         for_each_intel_connector(dev, connector) {
2583                 struct drm_crtc *crtc;
2584
2585                 if (!connector->base.state->best_encoder)
2586                         continue;
2587
2588                 crtc = connector->base.state->crtc;
2589                 if (!crtc->state->active)
2590                         continue;
2591
2592                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2593                         continue;
2594
2595                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2596
2597                 ret = intel_dp_sink_crc(intel_dp, crc);
2598                 if (ret)
2599                         goto out;
2600
2601                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2602                            crc[0], crc[1], crc[2],
2603                            crc[3], crc[4], crc[5]);
2604                 goto out;
2605         }
2606         ret = -ENODEV;
2607 out:
2608         drm_modeset_unlock_all(dev);
2609         return ret;
2610 }
2611
2612 static int i915_energy_uJ(struct seq_file *m, void *data)
2613 {
2614         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2615         u64 power;
2616         u32 units;
2617
2618         if (INTEL_GEN(dev_priv) < 6)
2619                 return -ENODEV;
2620
2621         intel_runtime_pm_get(dev_priv);
2622
2623         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2624         power = (power & 0x1f00) >> 8;
2625         units = 1000000 / (1 << power); /* convert to uJ */
2626         power = I915_READ(MCH_SECP_NRG_STTS);
2627         power *= units;
2628
2629         intel_runtime_pm_put(dev_priv);
2630
2631         seq_printf(m, "%llu", (long long unsigned)power);
2632
2633         return 0;
2634 }
2635
2636 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2637 {
2638         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2639         struct pci_dev *pdev = dev_priv->drm.pdev;
2640
2641         if (!HAS_RUNTIME_PM(dev_priv))
2642                 seq_puts(m, "Runtime power management not supported\n");
2643
2644         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2645         seq_printf(m, "IRQs disabled: %s\n",
2646                    yesno(!intel_irqs_enabled(dev_priv)));
2647 #ifdef CONFIG_PM
2648         seq_printf(m, "Usage count: %d\n",
2649                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2650 #else
2651         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2652 #endif
2653         seq_printf(m, "PCI device power state: %s [%d]\n",
2654                    pci_power_name(pdev->current_state),
2655                    pdev->current_state);
2656
2657         return 0;
2658 }
2659
2660 static int i915_power_domain_info(struct seq_file *m, void *unused)
2661 {
2662         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2663         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2664         int i;
2665
2666         mutex_lock(&power_domains->lock);
2667
2668         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2669         for (i = 0; i < power_domains->power_well_count; i++) {
2670                 struct i915_power_well *power_well;
2671                 enum intel_display_power_domain power_domain;
2672
2673                 power_well = &power_domains->power_wells[i];
2674                 seq_printf(m, "%-25s %d\n", power_well->name,
2675                            power_well->count);
2676
2677                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2678                      power_domain++) {
2679                         if (!(BIT(power_domain) & power_well->domains))
2680                                 continue;
2681
2682                         seq_printf(m, "  %-23s %d\n",
2683                                  intel_display_power_domain_str(power_domain),
2684                                  power_domains->domain_use_count[power_domain]);
2685                 }
2686         }
2687
2688         mutex_unlock(&power_domains->lock);
2689
2690         return 0;
2691 }
2692
2693 static int i915_dmc_info(struct seq_file *m, void *unused)
2694 {
2695         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2696         struct intel_csr *csr;
2697
2698         if (!HAS_CSR(dev_priv)) {
2699                 seq_puts(m, "not supported\n");
2700                 return 0;
2701         }
2702
2703         csr = &dev_priv->csr;
2704
2705         intel_runtime_pm_get(dev_priv);
2706
2707         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2708         seq_printf(m, "path: %s\n", csr->fw_path);
2709
2710         if (!csr->dmc_payload)
2711                 goto out;
2712
2713         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2714                    CSR_VERSION_MINOR(csr->version));
2715
2716         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2717                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2718                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2719                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2720                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2721         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2722                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2723                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2724         }
2725
2726 out:
2727         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2728         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2729         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2730
2731         intel_runtime_pm_put(dev_priv);
2732
2733         return 0;
2734 }
2735
2736 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2737                                  struct drm_display_mode *mode)
2738 {
2739         int i;
2740
2741         for (i = 0; i < tabs; i++)
2742                 seq_putc(m, '\t');
2743
2744         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2745                    mode->base.id, mode->name,
2746                    mode->vrefresh, mode->clock,
2747                    mode->hdisplay, mode->hsync_start,
2748                    mode->hsync_end, mode->htotal,
2749                    mode->vdisplay, mode->vsync_start,
2750                    mode->vsync_end, mode->vtotal,
2751                    mode->type, mode->flags);
2752 }
2753
2754 static void intel_encoder_info(struct seq_file *m,
2755                                struct intel_crtc *intel_crtc,
2756                                struct intel_encoder *intel_encoder)
2757 {
2758         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2759         struct drm_device *dev = &dev_priv->drm;
2760         struct drm_crtc *crtc = &intel_crtc->base;
2761         struct intel_connector *intel_connector;
2762         struct drm_encoder *encoder;
2763
2764         encoder = &intel_encoder->base;
2765         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2766                    encoder->base.id, encoder->name);
2767         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2768                 struct drm_connector *connector = &intel_connector->base;
2769                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2770                            connector->base.id,
2771                            connector->name,
2772                            drm_get_connector_status_name(connector->status));
2773                 if (connector->status == connector_status_connected) {
2774                         struct drm_display_mode *mode = &crtc->mode;
2775                         seq_printf(m, ", mode:\n");
2776                         intel_seq_print_mode(m, 2, mode);
2777                 } else {
2778                         seq_putc(m, '\n');
2779                 }
2780         }
2781 }
2782
2783 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2784 {
2785         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2786         struct drm_device *dev = &dev_priv->drm;
2787         struct drm_crtc *crtc = &intel_crtc->base;
2788         struct intel_encoder *intel_encoder;
2789         struct drm_plane_state *plane_state = crtc->primary->state;
2790         struct drm_framebuffer *fb = plane_state->fb;
2791
2792         if (fb)
2793                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2794                            fb->base.id, plane_state->src_x >> 16,
2795                            plane_state->src_y >> 16, fb->width, fb->height);
2796         else
2797                 seq_puts(m, "\tprimary plane disabled\n");
2798         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2799                 intel_encoder_info(m, intel_crtc, intel_encoder);
2800 }
2801
2802 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2803 {
2804         struct drm_display_mode *mode = panel->fixed_mode;
2805
2806         seq_printf(m, "\tfixed mode:\n");
2807         intel_seq_print_mode(m, 2, mode);
2808 }
2809
2810 static void intel_dp_info(struct seq_file *m,
2811                           struct intel_connector *intel_connector)
2812 {
2813         struct intel_encoder *intel_encoder = intel_connector->encoder;
2814         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2815
2816         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2817         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2818         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2819                 intel_panel_info(m, &intel_connector->panel);
2820
2821         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2822                                 &intel_dp->aux);
2823 }
2824
2825 static void intel_hdmi_info(struct seq_file *m,
2826                             struct intel_connector *intel_connector)
2827 {
2828         struct intel_encoder *intel_encoder = intel_connector->encoder;
2829         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2830
2831         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2832 }
2833
2834 static void intel_lvds_info(struct seq_file *m,
2835                             struct intel_connector *intel_connector)
2836 {
2837         intel_panel_info(m, &intel_connector->panel);
2838 }
2839
2840 static void intel_connector_info(struct seq_file *m,
2841                                  struct drm_connector *connector)
2842 {
2843         struct intel_connector *intel_connector = to_intel_connector(connector);
2844         struct intel_encoder *intel_encoder = intel_connector->encoder;
2845         struct drm_display_mode *mode;
2846
2847         seq_printf(m, "connector %d: type %s, status: %s\n",
2848                    connector->base.id, connector->name,
2849                    drm_get_connector_status_name(connector->status));
2850         if (connector->status == connector_status_connected) {
2851                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2852                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2853                            connector->display_info.width_mm,
2854                            connector->display_info.height_mm);
2855                 seq_printf(m, "\tsubpixel order: %s\n",
2856                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2857                 seq_printf(m, "\tCEA rev: %d\n",
2858                            connector->display_info.cea_rev);
2859         }
2860
2861         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2862                 return;
2863
2864         switch (connector->connector_type) {
2865         case DRM_MODE_CONNECTOR_DisplayPort:
2866         case DRM_MODE_CONNECTOR_eDP:
2867                 intel_dp_info(m, intel_connector);
2868                 break;
2869         case DRM_MODE_CONNECTOR_LVDS:
2870                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2871                         intel_lvds_info(m, intel_connector);
2872                 break;
2873         case DRM_MODE_CONNECTOR_HDMIA:
2874                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2875                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2876                         intel_hdmi_info(m, intel_connector);
2877                 break;
2878         default:
2879                 break;
2880         }
2881
2882         seq_printf(m, "\tmodes:\n");
2883         list_for_each_entry(mode, &connector->modes, head)
2884                 intel_seq_print_mode(m, 2, mode);
2885 }
2886
2887 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2888 {
2889         u32 state;
2890
2891         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2892                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2893         else
2894                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2895
2896         return state;
2897 }
2898
2899 static bool cursor_position(struct drm_i915_private *dev_priv,
2900                             int pipe, int *x, int *y)
2901 {
2902         u32 pos;
2903
2904         pos = I915_READ(CURPOS(pipe));
2905
2906         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2907         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2908                 *x = -*x;
2909
2910         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2911         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2912                 *y = -*y;
2913
2914         return cursor_active(dev_priv, pipe);
2915 }
2916
2917 static const char *plane_type(enum drm_plane_type type)
2918 {
2919         switch (type) {
2920         case DRM_PLANE_TYPE_OVERLAY:
2921                 return "OVL";
2922         case DRM_PLANE_TYPE_PRIMARY:
2923                 return "PRI";
2924         case DRM_PLANE_TYPE_CURSOR:
2925                 return "CUR";
2926         /*
2927          * Deliberately omitting default: to generate compiler warnings
2928          * when a new drm_plane_type gets added.
2929          */
2930         }
2931
2932         return "unknown";
2933 }
2934
2935 static const char *plane_rotation(unsigned int rotation)
2936 {
2937         static char buf[48];
2938         /*
2939          * According to doc only one DRM_ROTATE_ is allowed but this
2940          * will print them all to visualize if the values are misused
2941          */
2942         snprintf(buf, sizeof(buf),
2943                  "%s%s%s%s%s%s(0x%08x)",
2944                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2945                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2946                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2947                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2948                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2949                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2950                  rotation);
2951
2952         return buf;
2953 }
2954
2955 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2956 {
2957         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2958         struct drm_device *dev = &dev_priv->drm;
2959         struct intel_plane *intel_plane;
2960
2961         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2962                 struct drm_plane_state *state;
2963                 struct drm_plane *plane = &intel_plane->base;
2964                 char *format_name;
2965
2966                 if (!plane->state) {
2967                         seq_puts(m, "plane->state is NULL!\n");
2968                         continue;
2969                 }
2970
2971                 state = plane->state;
2972
2973                 if (state->fb) {
2974                         format_name = drm_get_format_name(state->fb->pixel_format);
2975                 } else {
2976                         format_name = kstrdup("N/A", GFP_KERNEL);
2977                 }
2978
2979                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2980                            plane->base.id,
2981                            plane_type(intel_plane->base.type),
2982                            state->crtc_x, state->crtc_y,
2983                            state->crtc_w, state->crtc_h,
2984                            (state->src_x >> 16),
2985                            ((state->src_x & 0xffff) * 15625) >> 10,
2986                            (state->src_y >> 16),
2987                            ((state->src_y & 0xffff) * 15625) >> 10,
2988                            (state->src_w >> 16),
2989                            ((state->src_w & 0xffff) * 15625) >> 10,
2990                            (state->src_h >> 16),
2991                            ((state->src_h & 0xffff) * 15625) >> 10,
2992                            format_name,
2993                            plane_rotation(state->rotation));
2994
2995                 kfree(format_name);
2996         }
2997 }
2998
2999 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3000 {
3001         struct intel_crtc_state *pipe_config;
3002         int num_scalers = intel_crtc->num_scalers;
3003         int i;
3004
3005         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3006
3007         /* Not all platformas have a scaler */
3008         if (num_scalers) {
3009                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3010                            num_scalers,
3011                            pipe_config->scaler_state.scaler_users,
3012                            pipe_config->scaler_state.scaler_id);
3013
3014                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3015                         struct intel_scaler *sc =
3016                                         &pipe_config->scaler_state.scalers[i];
3017
3018                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3019                                    i, yesno(sc->in_use), sc->mode);
3020                 }
3021                 seq_puts(m, "\n");
3022         } else {
3023                 seq_puts(m, "\tNo scalers available on this platform\n");
3024         }
3025 }
3026
3027 static int i915_display_info(struct seq_file *m, void *unused)
3028 {
3029         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3030         struct drm_device *dev = &dev_priv->drm;
3031         struct intel_crtc *crtc;
3032         struct drm_connector *connector;
3033
3034         intel_runtime_pm_get(dev_priv);
3035         drm_modeset_lock_all(dev);
3036         seq_printf(m, "CRTC info\n");
3037         seq_printf(m, "---------\n");
3038         for_each_intel_crtc(dev, crtc) {
3039                 bool active;
3040                 struct intel_crtc_state *pipe_config;
3041                 int x, y;
3042
3043                 pipe_config = to_intel_crtc_state(crtc->base.state);
3044
3045                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3046                            crtc->base.base.id, pipe_name(crtc->pipe),
3047                            yesno(pipe_config->base.active),
3048                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3049                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3050
3051                 if (pipe_config->base.active) {
3052                         intel_crtc_info(m, crtc);
3053
3054                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3055                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3056                                    yesno(crtc->cursor_base),
3057                                    x, y, crtc->base.cursor->state->crtc_w,
3058                                    crtc->base.cursor->state->crtc_h,
3059                                    crtc->cursor_addr, yesno(active));
3060                         intel_scaler_info(m, crtc);
3061                         intel_plane_info(m, crtc);
3062                 }
3063
3064                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3065                            yesno(!crtc->cpu_fifo_underrun_disabled),
3066                            yesno(!crtc->pch_fifo_underrun_disabled));
3067         }
3068
3069         seq_printf(m, "\n");
3070         seq_printf(m, "Connector info\n");
3071         seq_printf(m, "--------------\n");
3072         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3073                 intel_connector_info(m, connector);
3074         }
3075         drm_modeset_unlock_all(dev);
3076         intel_runtime_pm_put(dev_priv);
3077
3078         return 0;
3079 }
3080
3081 static int i915_engine_info(struct seq_file *m, void *unused)
3082 {
3083         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3084         struct intel_engine_cs *engine;
3085
3086         for_each_engine(engine, dev_priv) {
3087                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3088                 struct drm_i915_gem_request *rq;
3089                 struct rb_node *rb;
3090                 u64 addr;
3091
3092                 seq_printf(m, "%s\n", engine->name);
3093                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3094                            intel_engine_get_seqno(engine),
3095                            engine->last_submitted_seqno,
3096                            engine->hangcheck.seqno,
3097                            engine->hangcheck.score);
3098
3099                 rcu_read_lock();
3100
3101                 seq_printf(m, "\tRequests:\n");
3102
3103                 rq = list_first_entry(&engine->request_list,
3104                                 struct drm_i915_gem_request, link);
3105                 if (&rq->link != &engine->request_list)
3106                         print_request(m, rq, "\t\tfirst  ");
3107
3108                 rq = list_last_entry(&engine->request_list,
3109                                 struct drm_i915_gem_request, link);
3110                 if (&rq->link != &engine->request_list)
3111                         print_request(m, rq, "\t\tlast   ");
3112
3113                 rq = i915_gem_find_active_request(engine);
3114                 if (rq) {
3115                         print_request(m, rq, "\t\tactive ");
3116                         seq_printf(m,
3117                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3118                                    rq->head, rq->postfix, rq->tail,
3119                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3120                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3121                 }
3122
3123                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3124                            I915_READ(RING_START(engine->mmio_base)),
3125                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3126                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3127                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3128                            rq ? rq->ring->head : 0);
3129                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3130                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3131                            rq ? rq->ring->tail : 0);
3132                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3133                            I915_READ(RING_CTL(engine->mmio_base)),
3134                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3135
3136                 rcu_read_unlock();
3137
3138                 addr = intel_engine_get_active_head(engine);
3139                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3140                            upper_32_bits(addr), lower_32_bits(addr));
3141                 addr = intel_engine_get_last_batch_head(engine);
3142                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3143                            upper_32_bits(addr), lower_32_bits(addr));
3144
3145                 if (i915.enable_execlists) {
3146                         u32 ptr, read, write;
3147
3148                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3149                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3150                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3151
3152                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3153                         read = GEN8_CSB_READ_PTR(ptr);
3154                         write = GEN8_CSB_WRITE_PTR(ptr);
3155                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3156                                    read, write);
3157                         if (read >= GEN8_CSB_ENTRIES)
3158                                 read = 0;
3159                         if (write >= GEN8_CSB_ENTRIES)
3160                                 write = 0;
3161                         if (read > write)
3162                                 write += GEN8_CSB_ENTRIES;
3163                         while (read < write) {
3164                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3165
3166                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3167                                            idx,
3168                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3169                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3170                         }
3171
3172                         rcu_read_lock();
3173                         rq = READ_ONCE(engine->execlist_port[0].request);
3174                         if (rq)
3175                                 print_request(m, rq, "\t\tELSP[0] ");
3176                         else
3177                                 seq_printf(m, "\t\tELSP[0] idle\n");
3178                         rq = READ_ONCE(engine->execlist_port[1].request);
3179                         if (rq)
3180                                 print_request(m, rq, "\t\tELSP[1] ");
3181                         else
3182                                 seq_printf(m, "\t\tELSP[1] idle\n");
3183                         rcu_read_unlock();
3184                 } else if (INTEL_GEN(dev_priv) > 6) {
3185                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3186                                    I915_READ(RING_PP_DIR_BASE(engine)));
3187                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3188                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3189                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3190                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3191                 }
3192
3193                 spin_lock(&b->lock);
3194                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3195                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3196
3197                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3198                                    w->tsk->comm, w->tsk->pid, w->seqno);
3199                 }
3200                 spin_unlock(&b->lock);
3201
3202                 seq_puts(m, "\n");
3203         }
3204
3205         return 0;
3206 }
3207
3208 static int i915_semaphore_status(struct seq_file *m, void *unused)
3209 {
3210         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3211         struct drm_device *dev = &dev_priv->drm;
3212         struct intel_engine_cs *engine;
3213         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3214         enum intel_engine_id id;
3215         int j, ret;
3216
3217         if (!i915.semaphores) {
3218                 seq_puts(m, "Semaphores are disabled\n");
3219                 return 0;
3220         }
3221
3222         ret = mutex_lock_interruptible(&dev->struct_mutex);
3223         if (ret)
3224                 return ret;
3225         intel_runtime_pm_get(dev_priv);
3226
3227         if (IS_BROADWELL(dev_priv)) {
3228                 struct page *page;
3229                 uint64_t *seqno;
3230
3231                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3232
3233                 seqno = (uint64_t *)kmap_atomic(page);
3234                 for_each_engine_id(engine, dev_priv, id) {
3235                         uint64_t offset;
3236
3237                         seq_printf(m, "%s\n", engine->name);
3238
3239                         seq_puts(m, "  Last signal:");
3240                         for (j = 0; j < num_rings; j++) {
3241                                 offset = id * I915_NUM_ENGINES + j;
3242                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3243                                            seqno[offset], offset * 8);
3244                         }
3245                         seq_putc(m, '\n');
3246
3247                         seq_puts(m, "  Last wait:  ");
3248                         for (j = 0; j < num_rings; j++) {
3249                                 offset = id + (j * I915_NUM_ENGINES);
3250                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3251                                            seqno[offset], offset * 8);
3252                         }
3253                         seq_putc(m, '\n');
3254
3255                 }
3256                 kunmap_atomic(seqno);
3257         } else {
3258                 seq_puts(m, "  Last signal:");
3259                 for_each_engine(engine, dev_priv)
3260                         for (j = 0; j < num_rings; j++)
3261                                 seq_printf(m, "0x%08x\n",
3262                                            I915_READ(engine->semaphore.mbox.signal[j]));
3263                 seq_putc(m, '\n');
3264         }
3265
3266         seq_puts(m, "\nSync seqno:\n");
3267         for_each_engine(engine, dev_priv) {
3268                 for (j = 0; j < num_rings; j++)
3269                         seq_printf(m, "  0x%08x ",
3270                                    engine->semaphore.sync_seqno[j]);
3271                 seq_putc(m, '\n');
3272         }
3273         seq_putc(m, '\n');
3274
3275         intel_runtime_pm_put(dev_priv);
3276         mutex_unlock(&dev->struct_mutex);
3277         return 0;
3278 }
3279
3280 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3281 {
3282         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3283         struct drm_device *dev = &dev_priv->drm;
3284         int i;
3285
3286         drm_modeset_lock_all(dev);
3287         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3288                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3289
3290                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3291                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3292                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3293                 seq_printf(m, " tracked hardware state:\n");
3294                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3295                 seq_printf(m, " dpll_md: 0x%08x\n",
3296                            pll->config.hw_state.dpll_md);
3297                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3298                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3299                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3300         }
3301         drm_modeset_unlock_all(dev);
3302
3303         return 0;
3304 }
3305
3306 static int i915_wa_registers(struct seq_file *m, void *unused)
3307 {
3308         int i;
3309         int ret;
3310         struct intel_engine_cs *engine;
3311         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3312         struct drm_device *dev = &dev_priv->drm;
3313         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3314         enum intel_engine_id id;
3315
3316         ret = mutex_lock_interruptible(&dev->struct_mutex);
3317         if (ret)
3318                 return ret;
3319
3320         intel_runtime_pm_get(dev_priv);
3321
3322         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3323         for_each_engine_id(engine, dev_priv, id)
3324                 seq_printf(m, "HW whitelist count for %s: %d\n",
3325                            engine->name, workarounds->hw_whitelist_count[id]);
3326         for (i = 0; i < workarounds->count; ++i) {
3327                 i915_reg_t addr;
3328                 u32 mask, value, read;
3329                 bool ok;
3330
3331                 addr = workarounds->reg[i].addr;
3332                 mask = workarounds->reg[i].mask;
3333                 value = workarounds->reg[i].value;
3334                 read = I915_READ(addr);
3335                 ok = (value & mask) == (read & mask);
3336                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3337                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3338         }
3339
3340         intel_runtime_pm_put(dev_priv);
3341         mutex_unlock(&dev->struct_mutex);
3342
3343         return 0;
3344 }
3345
3346 static int i915_ddb_info(struct seq_file *m, void *unused)
3347 {
3348         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3349         struct drm_device *dev = &dev_priv->drm;
3350         struct skl_ddb_allocation *ddb;
3351         struct skl_ddb_entry *entry;
3352         enum pipe pipe;
3353         int plane;
3354
3355         if (INTEL_GEN(dev_priv) < 9)
3356                 return 0;
3357
3358         drm_modeset_lock_all(dev);
3359
3360         ddb = &dev_priv->wm.skl_hw.ddb;
3361
3362         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3363
3364         for_each_pipe(dev_priv, pipe) {
3365                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3366
3367                 for_each_plane(dev_priv, pipe, plane) {
3368                         entry = &ddb->plane[pipe][plane];
3369                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3370                                    entry->start, entry->end,
3371                                    skl_ddb_entry_size(entry));
3372                 }
3373
3374                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3375                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3376                            entry->end, skl_ddb_entry_size(entry));
3377         }
3378
3379         drm_modeset_unlock_all(dev);
3380
3381         return 0;
3382 }
3383
3384 static void drrs_status_per_crtc(struct seq_file *m,
3385                                  struct drm_device *dev,
3386                                  struct intel_crtc *intel_crtc)
3387 {
3388         struct drm_i915_private *dev_priv = to_i915(dev);
3389         struct i915_drrs *drrs = &dev_priv->drrs;
3390         int vrefresh = 0;
3391         struct drm_connector *connector;
3392
3393         drm_for_each_connector(connector, dev) {
3394                 if (connector->state->crtc != &intel_crtc->base)
3395                         continue;
3396
3397                 seq_printf(m, "%s:\n", connector->name);
3398         }
3399
3400         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3401                 seq_puts(m, "\tVBT: DRRS_type: Static");
3402         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3403                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3404         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3405                 seq_puts(m, "\tVBT: DRRS_type: None");
3406         else
3407                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3408
3409         seq_puts(m, "\n\n");
3410
3411         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3412                 struct intel_panel *panel;
3413
3414                 mutex_lock(&drrs->mutex);
3415                 /* DRRS Supported */
3416                 seq_puts(m, "\tDRRS Supported: Yes\n");
3417
3418                 /* disable_drrs() will make drrs->dp NULL */
3419                 if (!drrs->dp) {
3420                         seq_puts(m, "Idleness DRRS: Disabled");
3421                         mutex_unlock(&drrs->mutex);
3422                         return;
3423                 }
3424
3425                 panel = &drrs->dp->attached_connector->panel;
3426                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3427                                         drrs->busy_frontbuffer_bits);
3428
3429                 seq_puts(m, "\n\t\t");
3430                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3431                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3432                         vrefresh = panel->fixed_mode->vrefresh;
3433                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3434                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3435                         vrefresh = panel->downclock_mode->vrefresh;
3436                 } else {
3437                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3438                                                 drrs->refresh_rate_type);
3439                         mutex_unlock(&drrs->mutex);
3440                         return;
3441                 }
3442                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3443
3444                 seq_puts(m, "\n\t\t");
3445                 mutex_unlock(&drrs->mutex);
3446         } else {
3447                 /* DRRS not supported. Print the VBT parameter*/
3448                 seq_puts(m, "\tDRRS Supported : No");
3449         }
3450         seq_puts(m, "\n");
3451 }
3452
3453 static int i915_drrs_status(struct seq_file *m, void *unused)
3454 {
3455         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3456         struct drm_device *dev = &dev_priv->drm;
3457         struct intel_crtc *intel_crtc;
3458         int active_crtc_cnt = 0;
3459
3460         drm_modeset_lock_all(dev);
3461         for_each_intel_crtc(dev, intel_crtc) {
3462                 if (intel_crtc->base.state->active) {
3463                         active_crtc_cnt++;
3464                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3465
3466                         drrs_status_per_crtc(m, dev, intel_crtc);
3467                 }
3468         }
3469         drm_modeset_unlock_all(dev);
3470
3471         if (!active_crtc_cnt)
3472                 seq_puts(m, "No active crtc found\n");
3473
3474         return 0;
3475 }
3476
3477 struct pipe_crc_info {
3478         const char *name;
3479         struct drm_i915_private *dev_priv;
3480         enum pipe pipe;
3481 };
3482
3483 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3484 {
3485         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3486         struct drm_device *dev = &dev_priv->drm;
3487         struct intel_encoder *intel_encoder;
3488         struct intel_digital_port *intel_dig_port;
3489         struct drm_connector *connector;
3490
3491         drm_modeset_lock_all(dev);
3492         drm_for_each_connector(connector, dev) {
3493                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3494                         continue;
3495
3496                 intel_encoder = intel_attached_encoder(connector);
3497                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3498                         continue;
3499
3500                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3501                 if (!intel_dig_port->dp.can_mst)
3502                         continue;
3503
3504                 seq_printf(m, "MST Source Port %c\n",
3505                            port_name(intel_dig_port->port));
3506                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3507         }
3508         drm_modeset_unlock_all(dev);
3509         return 0;
3510 }
3511
3512 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3513 {
3514         struct pipe_crc_info *info = inode->i_private;
3515         struct drm_i915_private *dev_priv = info->dev_priv;
3516         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3517
3518         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3519                 return -ENODEV;
3520
3521         spin_lock_irq(&pipe_crc->lock);
3522
3523         if (pipe_crc->opened) {
3524                 spin_unlock_irq(&pipe_crc->lock);
3525                 return -EBUSY; /* already open */
3526         }
3527
3528         pipe_crc->opened = true;
3529         filep->private_data = inode->i_private;
3530
3531         spin_unlock_irq(&pipe_crc->lock);
3532
3533         return 0;
3534 }
3535
3536 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3537 {
3538         struct pipe_crc_info *info = inode->i_private;
3539         struct drm_i915_private *dev_priv = info->dev_priv;
3540         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3541
3542         spin_lock_irq(&pipe_crc->lock);
3543         pipe_crc->opened = false;
3544         spin_unlock_irq(&pipe_crc->lock);
3545
3546         return 0;
3547 }
3548
3549 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3550 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3551 /* account for \'0' */
3552 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3553
3554 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3555 {
3556         assert_spin_locked(&pipe_crc->lock);
3557         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3558                         INTEL_PIPE_CRC_ENTRIES_NR);
3559 }
3560
3561 static ssize_t
3562 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3563                    loff_t *pos)
3564 {
3565         struct pipe_crc_info *info = filep->private_data;
3566         struct drm_i915_private *dev_priv = info->dev_priv;
3567         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3568         char buf[PIPE_CRC_BUFFER_LEN];
3569         int n_entries;
3570         ssize_t bytes_read;
3571
3572         /*
3573          * Don't allow user space to provide buffers not big enough to hold
3574          * a line of data.
3575          */
3576         if (count < PIPE_CRC_LINE_LEN)
3577                 return -EINVAL;
3578
3579         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3580                 return 0;
3581
3582         /* nothing to read */
3583         spin_lock_irq(&pipe_crc->lock);
3584         while (pipe_crc_data_count(pipe_crc) == 0) {
3585                 int ret;
3586
3587                 if (filep->f_flags & O_NONBLOCK) {
3588                         spin_unlock_irq(&pipe_crc->lock);
3589                         return -EAGAIN;
3590                 }
3591
3592                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3593                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3594                 if (ret) {
3595                         spin_unlock_irq(&pipe_crc->lock);
3596                         return ret;
3597                 }
3598         }
3599
3600         /* We now have one or more entries to read */
3601         n_entries = count / PIPE_CRC_LINE_LEN;
3602
3603         bytes_read = 0;
3604         while (n_entries > 0) {
3605                 struct intel_pipe_crc_entry *entry =
3606                         &pipe_crc->entries[pipe_crc->tail];
3607
3608                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3609                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3610                         break;
3611
3612                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3613                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3614
3615                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3616                                        "%8u %8x %8x %8x %8x %8x\n",
3617                                        entry->frame, entry->crc[0],
3618                                        entry->crc[1], entry->crc[2],
3619                                        entry->crc[3], entry->crc[4]);
3620
3621                 spin_unlock_irq(&pipe_crc->lock);
3622
3623                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3624                         return -EFAULT;
3625
3626                 user_buf += PIPE_CRC_LINE_LEN;
3627                 n_entries--;
3628
3629                 spin_lock_irq(&pipe_crc->lock);
3630         }
3631
3632         spin_unlock_irq(&pipe_crc->lock);
3633
3634         return bytes_read;
3635 }
3636
3637 static const struct file_operations i915_pipe_crc_fops = {
3638         .owner = THIS_MODULE,
3639         .open = i915_pipe_crc_open,
3640         .read = i915_pipe_crc_read,
3641         .release = i915_pipe_crc_release,
3642 };
3643
3644 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3645         {
3646                 .name = "i915_pipe_A_crc",
3647                 .pipe = PIPE_A,
3648         },
3649         {
3650                 .name = "i915_pipe_B_crc",
3651                 .pipe = PIPE_B,
3652         },
3653         {
3654                 .name = "i915_pipe_C_crc",
3655                 .pipe = PIPE_C,
3656         },
3657 };
3658
3659 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3660                                 enum pipe pipe)
3661 {
3662         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3663         struct dentry *ent;
3664         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3665
3666         info->dev_priv = dev_priv;
3667         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3668                                   &i915_pipe_crc_fops);
3669         if (!ent)
3670                 return -ENOMEM;
3671
3672         return drm_add_fake_info_node(minor, ent, info);
3673 }
3674
3675 static const char * const pipe_crc_sources[] = {
3676         "none",
3677         "plane1",
3678         "plane2",
3679         "pf",
3680         "pipe",
3681         "TV",
3682         "DP-B",
3683         "DP-C",
3684         "DP-D",
3685         "auto",
3686 };
3687
3688 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3689 {
3690         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3691         return pipe_crc_sources[source];
3692 }
3693
3694 static int display_crc_ctl_show(struct seq_file *m, void *data)
3695 {
3696         struct drm_i915_private *dev_priv = m->private;
3697         int i;
3698
3699         for (i = 0; i < I915_MAX_PIPES; i++)
3700                 seq_printf(m, "%c %s\n", pipe_name(i),
3701                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3702
3703         return 0;
3704 }
3705
3706 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3707 {
3708         return single_open(file, display_crc_ctl_show, inode->i_private);
3709 }
3710
3711 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3712                                  uint32_t *val)
3713 {
3714         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3715                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3716
3717         switch (*source) {
3718         case INTEL_PIPE_CRC_SOURCE_PIPE:
3719                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3720                 break;
3721         case INTEL_PIPE_CRC_SOURCE_NONE:
3722                 *val = 0;
3723                 break;
3724         default:
3725                 return -EINVAL;
3726         }
3727
3728         return 0;
3729 }
3730
3731 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3732                                      enum pipe pipe,
3733                                      enum intel_pipe_crc_source *source)
3734 {
3735         struct drm_device *dev = &dev_priv->drm;
3736         struct intel_encoder *encoder;
3737         struct intel_crtc *crtc;
3738         struct intel_digital_port *dig_port;
3739         int ret = 0;
3740
3741         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3742
3743         drm_modeset_lock_all(dev);
3744         for_each_intel_encoder(dev, encoder) {
3745                 if (!encoder->base.crtc)
3746                         continue;
3747
3748                 crtc = to_intel_crtc(encoder->base.crtc);
3749
3750                 if (crtc->pipe != pipe)
3751                         continue;
3752
3753                 switch (encoder->type) {
3754                 case INTEL_OUTPUT_TVOUT:
3755                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3756                         break;
3757                 case INTEL_OUTPUT_DP:
3758                 case INTEL_OUTPUT_EDP:
3759                         dig_port = enc_to_dig_port(&encoder->base);
3760                         switch (dig_port->port) {
3761                         case PORT_B:
3762                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3763                                 break;
3764                         case PORT_C:
3765                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3766                                 break;
3767                         case PORT_D:
3768                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3769                                 break;
3770                         default:
3771                                 WARN(1, "nonexisting DP port %c\n",
3772                                      port_name(dig_port->port));
3773                                 break;
3774                         }
3775                         break;
3776                 default:
3777                         break;
3778                 }
3779         }
3780         drm_modeset_unlock_all(dev);
3781
3782         return ret;
3783 }
3784
3785 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3786                                 enum pipe pipe,
3787                                 enum intel_pipe_crc_source *source,
3788                                 uint32_t *val)
3789 {
3790         bool need_stable_symbols = false;
3791
3792         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3793                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3794                 if (ret)
3795                         return ret;
3796         }
3797
3798         switch (*source) {
3799         case INTEL_PIPE_CRC_SOURCE_PIPE:
3800                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3801                 break;
3802         case INTEL_PIPE_CRC_SOURCE_DP_B:
3803                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3804                 need_stable_symbols = true;
3805                 break;
3806         case INTEL_PIPE_CRC_SOURCE_DP_C:
3807                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3808                 need_stable_symbols = true;
3809                 break;
3810         case INTEL_PIPE_CRC_SOURCE_DP_D:
3811                 if (!IS_CHERRYVIEW(dev_priv))
3812                         return -EINVAL;
3813                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3814                 need_stable_symbols = true;
3815                 break;
3816         case INTEL_PIPE_CRC_SOURCE_NONE:
3817                 *val = 0;
3818                 break;
3819         default:
3820                 return -EINVAL;
3821         }
3822
3823         /*
3824          * When the pipe CRC tap point is after the transcoders we need
3825          * to tweak symbol-level features to produce a deterministic series of
3826          * symbols for a given frame. We need to reset those features only once
3827          * a frame (instead of every nth symbol):
3828          *   - DC-balance: used to ensure a better clock recovery from the data
3829          *     link (SDVO)
3830          *   - DisplayPort scrambling: used for EMI reduction
3831          */
3832         if (need_stable_symbols) {
3833                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3834
3835                 tmp |= DC_BALANCE_RESET_VLV;
3836                 switch (pipe) {
3837                 case PIPE_A:
3838                         tmp |= PIPE_A_SCRAMBLE_RESET;
3839                         break;
3840                 case PIPE_B:
3841                         tmp |= PIPE_B_SCRAMBLE_RESET;
3842                         break;
3843                 case PIPE_C:
3844                         tmp |= PIPE_C_SCRAMBLE_RESET;
3845                         break;
3846                 default:
3847                         return -EINVAL;
3848                 }
3849                 I915_WRITE(PORT_DFT2_G4X, tmp);
3850         }
3851
3852         return 0;
3853 }
3854
3855 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3856                                  enum pipe pipe,
3857                                  enum intel_pipe_crc_source *source,
3858                                  uint32_t *val)
3859 {
3860         bool need_stable_symbols = false;
3861
3862         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3863                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3864                 if (ret)
3865                         return ret;
3866         }
3867
3868         switch (*source) {
3869         case INTEL_PIPE_CRC_SOURCE_PIPE:
3870                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3871                 break;
3872         case INTEL_PIPE_CRC_SOURCE_TV:
3873                 if (!SUPPORTS_TV(dev_priv))
3874                         return -EINVAL;
3875                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3876                 break;
3877         case INTEL_PIPE_CRC_SOURCE_DP_B:
3878                 if (!IS_G4X(dev_priv))
3879                         return -EINVAL;
3880                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3881                 need_stable_symbols = true;
3882                 break;
3883         case INTEL_PIPE_CRC_SOURCE_DP_C:
3884                 if (!IS_G4X(dev_priv))
3885                         return -EINVAL;
3886                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3887                 need_stable_symbols = true;
3888                 break;
3889         case INTEL_PIPE_CRC_SOURCE_DP_D:
3890                 if (!IS_G4X(dev_priv))
3891                         return -EINVAL;
3892                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3893                 need_stable_symbols = true;
3894                 break;
3895         case INTEL_PIPE_CRC_SOURCE_NONE:
3896                 *val = 0;
3897                 break;
3898         default:
3899                 return -EINVAL;
3900         }
3901
3902         /*
3903          * When the pipe CRC tap point is after the transcoders we need
3904          * to tweak symbol-level features to produce a deterministic series of
3905          * symbols for a given frame. We need to reset those features only once
3906          * a frame (instead of every nth symbol):
3907          *   - DC-balance: used to ensure a better clock recovery from the data
3908          *     link (SDVO)
3909          *   - DisplayPort scrambling: used for EMI reduction
3910          */
3911         if (need_stable_symbols) {
3912                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3913
3914                 WARN_ON(!IS_G4X(dev_priv));
3915
3916                 I915_WRITE(PORT_DFT_I9XX,
3917                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3918
3919                 if (pipe == PIPE_A)
3920                         tmp |= PIPE_A_SCRAMBLE_RESET;
3921                 else
3922                         tmp |= PIPE_B_SCRAMBLE_RESET;
3923
3924                 I915_WRITE(PORT_DFT2_G4X, tmp);
3925         }
3926
3927         return 0;
3928 }
3929
3930 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3931                                          enum pipe pipe)
3932 {
3933         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3934
3935         switch (pipe) {
3936         case PIPE_A:
3937                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3938                 break;
3939         case PIPE_B:
3940                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3941                 break;
3942         case PIPE_C:
3943                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3944                 break;
3945         default:
3946                 return;
3947         }
3948         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3949                 tmp &= ~DC_BALANCE_RESET_VLV;
3950         I915_WRITE(PORT_DFT2_G4X, tmp);
3951
3952 }
3953
3954 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3955                                          enum pipe pipe)
3956 {
3957         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3958
3959         if (pipe == PIPE_A)
3960                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3961         else
3962                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3963         I915_WRITE(PORT_DFT2_G4X, tmp);
3964
3965         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3966                 I915_WRITE(PORT_DFT_I9XX,
3967                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3968         }
3969 }
3970
3971 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3972                                 uint32_t *val)
3973 {
3974         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3975                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3976
3977         switch (*source) {
3978         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3979                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3980                 break;
3981         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3982                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3983                 break;
3984         case INTEL_PIPE_CRC_SOURCE_PIPE:
3985                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3986                 break;
3987         case INTEL_PIPE_CRC_SOURCE_NONE:
3988                 *val = 0;
3989                 break;
3990         default:
3991                 return -EINVAL;
3992         }
3993
3994         return 0;
3995 }
3996
3997 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
3998                                         bool enable)
3999 {
4000         struct drm_device *dev = &dev_priv->drm;
4001         struct intel_crtc *crtc =
4002                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4003         struct intel_crtc_state *pipe_config;
4004         struct drm_atomic_state *state;
4005         int ret = 0;
4006
4007         drm_modeset_lock_all(dev);
4008         state = drm_atomic_state_alloc(dev);
4009         if (!state) {
4010                 ret = -ENOMEM;
4011                 goto out;
4012         }
4013
4014         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4015         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4016         if (IS_ERR(pipe_config)) {
4017                 ret = PTR_ERR(pipe_config);
4018                 goto out;
4019         }
4020
4021         pipe_config->pch_pfit.force_thru = enable;
4022         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4023             pipe_config->pch_pfit.enabled != enable)
4024                 pipe_config->base.connectors_changed = true;
4025
4026         ret = drm_atomic_commit(state);
4027 out:
4028         drm_modeset_unlock_all(dev);
4029         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4030         if (ret)
4031                 drm_atomic_state_free(state);
4032 }
4033
4034 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4035                                 enum pipe pipe,
4036                                 enum intel_pipe_crc_source *source,
4037                                 uint32_t *val)
4038 {
4039         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4040                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4041
4042         switch (*source) {
4043         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4044                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4045                 break;
4046         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4047                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4048                 break;
4049         case INTEL_PIPE_CRC_SOURCE_PF:
4050                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4051                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4052
4053                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4054                 break;
4055         case INTEL_PIPE_CRC_SOURCE_NONE:
4056                 *val = 0;
4057                 break;
4058         default:
4059                 return -EINVAL;
4060         }
4061
4062         return 0;
4063 }
4064
4065 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4066                                enum pipe pipe,
4067                                enum intel_pipe_crc_source source)
4068 {
4069         struct drm_device *dev = &dev_priv->drm;
4070         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4071         struct intel_crtc *crtc =
4072                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4073         enum intel_display_power_domain power_domain;
4074         u32 val = 0; /* shut up gcc */
4075         int ret;
4076
4077         if (pipe_crc->source == source)
4078                 return 0;
4079
4080         /* forbid changing the source without going back to 'none' */
4081         if (pipe_crc->source && source)
4082                 return -EINVAL;
4083
4084         power_domain = POWER_DOMAIN_PIPE(pipe);
4085         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4086                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4087                 return -EIO;
4088         }
4089
4090         if (IS_GEN2(dev_priv))
4091                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4092         else if (INTEL_GEN(dev_priv) < 5)
4093                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4094         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4095                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4096         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4097                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4098         else
4099                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4100
4101         if (ret != 0)
4102                 goto out;
4103
4104         /* none -> real source transition */
4105         if (source) {
4106                 struct intel_pipe_crc_entry *entries;
4107
4108                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4109                                  pipe_name(pipe), pipe_crc_source_name(source));
4110
4111                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4112                                   sizeof(pipe_crc->entries[0]),
4113                                   GFP_KERNEL);
4114                 if (!entries) {
4115                         ret = -ENOMEM;
4116                         goto out;
4117                 }
4118
4119                 /*
4120                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4121                  * enabled and disabled dynamically based on package C states,
4122                  * user space can't make reliable use of the CRCs, so let's just
4123                  * completely disable it.
4124                  */
4125                 hsw_disable_ips(crtc);
4126
4127                 spin_lock_irq(&pipe_crc->lock);
4128                 kfree(pipe_crc->entries);
4129                 pipe_crc->entries = entries;
4130                 pipe_crc->head = 0;
4131                 pipe_crc->tail = 0;
4132                 spin_unlock_irq(&pipe_crc->lock);
4133         }
4134
4135         pipe_crc->source = source;
4136
4137         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4138         POSTING_READ(PIPE_CRC_CTL(pipe));
4139
4140         /* real source -> none transition */
4141         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4142                 struct intel_pipe_crc_entry *entries;
4143                 struct intel_crtc *crtc =
4144                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4145
4146                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4147                                  pipe_name(pipe));
4148
4149                 drm_modeset_lock(&crtc->base.mutex, NULL);
4150                 if (crtc->base.state->active)
4151                         intel_wait_for_vblank(dev, pipe);
4152                 drm_modeset_unlock(&crtc->base.mutex);
4153
4154                 spin_lock_irq(&pipe_crc->lock);
4155                 entries = pipe_crc->entries;
4156                 pipe_crc->entries = NULL;
4157                 pipe_crc->head = 0;
4158                 pipe_crc->tail = 0;
4159                 spin_unlock_irq(&pipe_crc->lock);
4160
4161                 kfree(entries);
4162
4163                 if (IS_G4X(dev_priv))
4164                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4165                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4166                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4167                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4168                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4169
4170                 hsw_enable_ips(crtc);
4171         }
4172
4173         ret = 0;
4174
4175 out:
4176         intel_display_power_put(dev_priv, power_domain);
4177
4178         return ret;
4179 }
4180
4181 /*
4182  * Parse pipe CRC command strings:
4183  *   command: wsp* object wsp+ name wsp+ source wsp*
4184  *   object: 'pipe'
4185  *   name: (A | B | C)
4186  *   source: (none | plane1 | plane2 | pf)
4187  *   wsp: (#0x20 | #0x9 | #0xA)+
4188  *
4189  * eg.:
4190  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4191  *  "pipe A none"    ->  Stop CRC
4192  */
4193 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4194 {
4195         int n_words = 0;
4196
4197         while (*buf) {
4198                 char *end;
4199
4200                 /* skip leading white space */
4201                 buf = skip_spaces(buf);
4202                 if (!*buf)
4203                         break;  /* end of buffer */
4204
4205                 /* find end of word */
4206                 for (end = buf; *end && !isspace(*end); end++)
4207                         ;
4208
4209                 if (n_words == max_words) {
4210                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4211                                          max_words);
4212                         return -EINVAL; /* ran out of words[] before bytes */
4213                 }
4214
4215                 if (*end)
4216                         *end++ = '\0';
4217                 words[n_words++] = buf;
4218                 buf = end;
4219         }
4220
4221         return n_words;
4222 }
4223
4224 enum intel_pipe_crc_object {
4225         PIPE_CRC_OBJECT_PIPE,
4226 };
4227
4228 static const char * const pipe_crc_objects[] = {
4229         "pipe",
4230 };
4231
4232 static int
4233 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4234 {
4235         int i;
4236
4237         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4238                 if (!strcmp(buf, pipe_crc_objects[i])) {
4239                         *o = i;
4240                         return 0;
4241                     }
4242
4243         return -EINVAL;
4244 }
4245
4246 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4247 {
4248         const char name = buf[0];
4249
4250         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4251                 return -EINVAL;
4252
4253         *pipe = name - 'A';
4254
4255         return 0;
4256 }
4257
4258 static int
4259 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4260 {
4261         int i;
4262
4263         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4264                 if (!strcmp(buf, pipe_crc_sources[i])) {
4265                         *s = i;
4266                         return 0;
4267                     }
4268
4269         return -EINVAL;
4270 }
4271
4272 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4273                                  char *buf, size_t len)
4274 {
4275 #define N_WORDS 3
4276         int n_words;
4277         char *words[N_WORDS];
4278         enum pipe pipe;
4279         enum intel_pipe_crc_object object;
4280         enum intel_pipe_crc_source source;
4281
4282         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4283         if (n_words != N_WORDS) {
4284                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4285                                  N_WORDS);
4286                 return -EINVAL;
4287         }
4288
4289         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4290                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4291                 return -EINVAL;
4292         }
4293
4294         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4295                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4296                 return -EINVAL;
4297         }
4298
4299         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4300                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4301                 return -EINVAL;
4302         }
4303
4304         return pipe_crc_set_source(dev_priv, pipe, source);
4305 }
4306
4307 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4308                                      size_t len, loff_t *offp)
4309 {
4310         struct seq_file *m = file->private_data;
4311         struct drm_i915_private *dev_priv = m->private;
4312         char *tmpbuf;
4313         int ret;
4314
4315         if (len == 0)
4316                 return 0;
4317
4318         if (len > PAGE_SIZE - 1) {
4319                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4320                                  PAGE_SIZE);
4321                 return -E2BIG;
4322         }
4323
4324         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4325         if (!tmpbuf)
4326                 return -ENOMEM;
4327
4328         if (copy_from_user(tmpbuf, ubuf, len)) {
4329                 ret = -EFAULT;
4330                 goto out;
4331         }
4332         tmpbuf[len] = '\0';
4333
4334         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4335
4336 out:
4337         kfree(tmpbuf);
4338         if (ret < 0)
4339                 return ret;
4340
4341         *offp += len;
4342         return len;
4343 }
4344
4345 static const struct file_operations i915_display_crc_ctl_fops = {
4346         .owner = THIS_MODULE,
4347         .open = display_crc_ctl_open,
4348         .read = seq_read,
4349         .llseek = seq_lseek,
4350         .release = single_release,
4351         .write = display_crc_ctl_write
4352 };
4353
4354 static ssize_t i915_displayport_test_active_write(struct file *file,
4355                                                   const char __user *ubuf,
4356                                                   size_t len, loff_t *offp)
4357 {
4358         char *input_buffer;
4359         int status = 0;
4360         struct drm_device *dev;
4361         struct drm_connector *connector;
4362         struct list_head *connector_list;
4363         struct intel_dp *intel_dp;
4364         int val = 0;
4365
4366         dev = ((struct seq_file *)file->private_data)->private;
4367
4368         connector_list = &dev->mode_config.connector_list;
4369
4370         if (len == 0)
4371                 return 0;
4372
4373         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4374         if (!input_buffer)
4375                 return -ENOMEM;
4376
4377         if (copy_from_user(input_buffer, ubuf, len)) {
4378                 status = -EFAULT;
4379                 goto out;
4380         }
4381
4382         input_buffer[len] = '\0';
4383         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4384
4385         list_for_each_entry(connector, connector_list, head) {
4386                 if (connector->connector_type !=
4387                     DRM_MODE_CONNECTOR_DisplayPort)
4388                         continue;
4389
4390                 if (connector->status == connector_status_connected &&
4391                     connector->encoder != NULL) {
4392                         intel_dp = enc_to_intel_dp(connector->encoder);
4393                         status = kstrtoint(input_buffer, 10, &val);
4394                         if (status < 0)
4395                                 goto out;
4396                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4397                         /* To prevent erroneous activation of the compliance
4398                          * testing code, only accept an actual value of 1 here
4399                          */
4400                         if (val == 1)
4401                                 intel_dp->compliance_test_active = 1;
4402                         else
4403                                 intel_dp->compliance_test_active = 0;
4404                 }
4405         }
4406 out:
4407         kfree(input_buffer);
4408         if (status < 0)
4409                 return status;
4410
4411         *offp += len;
4412         return len;
4413 }
4414
4415 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4416 {
4417         struct drm_device *dev = m->private;
4418         struct drm_connector *connector;
4419         struct list_head *connector_list = &dev->mode_config.connector_list;
4420         struct intel_dp *intel_dp;
4421
4422         list_for_each_entry(connector, connector_list, head) {
4423                 if (connector->connector_type !=
4424                     DRM_MODE_CONNECTOR_DisplayPort)
4425                         continue;
4426
4427                 if (connector->status == connector_status_connected &&
4428                     connector->encoder != NULL) {
4429                         intel_dp = enc_to_intel_dp(connector->encoder);
4430                         if (intel_dp->compliance_test_active)
4431                                 seq_puts(m, "1");
4432                         else
4433                                 seq_puts(m, "0");
4434                 } else
4435                         seq_puts(m, "0");
4436         }
4437
4438         return 0;
4439 }
4440
4441 static int i915_displayport_test_active_open(struct inode *inode,
4442                                              struct file *file)
4443 {
4444         struct drm_i915_private *dev_priv = inode->i_private;
4445
4446         return single_open(file, i915_displayport_test_active_show,
4447                            &dev_priv->drm);
4448 }
4449
4450 static const struct file_operations i915_displayport_test_active_fops = {
4451         .owner = THIS_MODULE,
4452         .open = i915_displayport_test_active_open,
4453         .read = seq_read,
4454         .llseek = seq_lseek,
4455         .release = single_release,
4456         .write = i915_displayport_test_active_write
4457 };
4458
4459 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4460 {
4461         struct drm_device *dev = m->private;
4462         struct drm_connector *connector;
4463         struct list_head *connector_list = &dev->mode_config.connector_list;
4464         struct intel_dp *intel_dp;
4465
4466         list_for_each_entry(connector, connector_list, head) {
4467                 if (connector->connector_type !=
4468                     DRM_MODE_CONNECTOR_DisplayPort)
4469                         continue;
4470
4471                 if (connector->status == connector_status_connected &&
4472                     connector->encoder != NULL) {
4473                         intel_dp = enc_to_intel_dp(connector->encoder);
4474                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4475                 } else
4476                         seq_puts(m, "0");
4477         }
4478
4479         return 0;
4480 }
4481 static int i915_displayport_test_data_open(struct inode *inode,
4482                                            struct file *file)
4483 {
4484         struct drm_i915_private *dev_priv = inode->i_private;
4485
4486         return single_open(file, i915_displayport_test_data_show,
4487                            &dev_priv->drm);
4488 }
4489
4490 static const struct file_operations i915_displayport_test_data_fops = {
4491         .owner = THIS_MODULE,
4492         .open = i915_displayport_test_data_open,
4493         .read = seq_read,
4494         .llseek = seq_lseek,
4495         .release = single_release
4496 };
4497
4498 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4499 {
4500         struct drm_device *dev = m->private;
4501         struct drm_connector *connector;
4502         struct list_head *connector_list = &dev->mode_config.connector_list;
4503         struct intel_dp *intel_dp;
4504
4505         list_for_each_entry(connector, connector_list, head) {
4506                 if (connector->connector_type !=
4507                     DRM_MODE_CONNECTOR_DisplayPort)
4508                         continue;
4509
4510                 if (connector->status == connector_status_connected &&
4511                     connector->encoder != NULL) {
4512                         intel_dp = enc_to_intel_dp(connector->encoder);
4513                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4514                 } else
4515                         seq_puts(m, "0");
4516         }
4517
4518         return 0;
4519 }
4520
4521 static int i915_displayport_test_type_open(struct inode *inode,
4522                                        struct file *file)
4523 {
4524         struct drm_i915_private *dev_priv = inode->i_private;
4525
4526         return single_open(file, i915_displayport_test_type_show,
4527                            &dev_priv->drm);
4528 }
4529
4530 static const struct file_operations i915_displayport_test_type_fops = {
4531         .owner = THIS_MODULE,
4532         .open = i915_displayport_test_type_open,
4533         .read = seq_read,
4534         .llseek = seq_lseek,
4535         .release = single_release
4536 };
4537
4538 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4539 {
4540         struct drm_i915_private *dev_priv = m->private;
4541         struct drm_device *dev = &dev_priv->drm;
4542         int level;
4543         int num_levels;
4544
4545         if (IS_CHERRYVIEW(dev_priv))
4546                 num_levels = 3;
4547         else if (IS_VALLEYVIEW(dev_priv))
4548                 num_levels = 1;
4549         else
4550                 num_levels = ilk_wm_max_level(dev) + 1;
4551
4552         drm_modeset_lock_all(dev);
4553
4554         for (level = 0; level < num_levels; level++) {
4555                 unsigned int latency = wm[level];
4556
4557                 /*
4558                  * - WM1+ latency values in 0.5us units
4559                  * - latencies are in us on gen9/vlv/chv
4560                  */
4561                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4562                     IS_CHERRYVIEW(dev_priv))
4563                         latency *= 10;
4564                 else if (level > 0)
4565                         latency *= 5;
4566
4567                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4568                            level, wm[level], latency / 10, latency % 10);
4569         }
4570
4571         drm_modeset_unlock_all(dev);
4572 }
4573
4574 static int pri_wm_latency_show(struct seq_file *m, void *data)
4575 {
4576         struct drm_i915_private *dev_priv = m->private;
4577         const uint16_t *latencies;
4578
4579         if (INTEL_GEN(dev_priv) >= 9)
4580                 latencies = dev_priv->wm.skl_latency;
4581         else
4582                 latencies = dev_priv->wm.pri_latency;
4583
4584         wm_latency_show(m, latencies);
4585
4586         return 0;
4587 }
4588
4589 static int spr_wm_latency_show(struct seq_file *m, void *data)
4590 {
4591         struct drm_i915_private *dev_priv = m->private;
4592         const uint16_t *latencies;
4593
4594         if (INTEL_GEN(dev_priv) >= 9)
4595                 latencies = dev_priv->wm.skl_latency;
4596         else
4597                 latencies = dev_priv->wm.spr_latency;
4598
4599         wm_latency_show(m, latencies);
4600
4601         return 0;
4602 }
4603
4604 static int cur_wm_latency_show(struct seq_file *m, void *data)
4605 {
4606         struct drm_i915_private *dev_priv = m->private;
4607         const uint16_t *latencies;
4608
4609         if (INTEL_GEN(dev_priv) >= 9)
4610                 latencies = dev_priv->wm.skl_latency;
4611         else
4612                 latencies = dev_priv->wm.cur_latency;
4613
4614         wm_latency_show(m, latencies);
4615
4616         return 0;
4617 }
4618
4619 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4620 {
4621         struct drm_i915_private *dev_priv = inode->i_private;
4622
4623         if (INTEL_GEN(dev_priv) < 5)
4624                 return -ENODEV;
4625
4626         return single_open(file, pri_wm_latency_show, dev_priv);
4627 }
4628
4629 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4630 {
4631         struct drm_i915_private *dev_priv = inode->i_private;
4632
4633         if (HAS_GMCH_DISPLAY(dev_priv))
4634                 return -ENODEV;
4635
4636         return single_open(file, spr_wm_latency_show, dev_priv);
4637 }
4638
4639 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4640 {
4641         struct drm_i915_private *dev_priv = inode->i_private;
4642
4643         if (HAS_GMCH_DISPLAY(dev_priv))
4644                 return -ENODEV;
4645
4646         return single_open(file, cur_wm_latency_show, dev_priv);
4647 }
4648
4649 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4650                                 size_t len, loff_t *offp, uint16_t wm[8])
4651 {
4652         struct seq_file *m = file->private_data;
4653         struct drm_i915_private *dev_priv = m->private;
4654         struct drm_device *dev = &dev_priv->drm;
4655         uint16_t new[8] = { 0 };
4656         int num_levels;
4657         int level;
4658         int ret;
4659         char tmp[32];
4660
4661         if (IS_CHERRYVIEW(dev_priv))
4662                 num_levels = 3;
4663         else if (IS_VALLEYVIEW(dev_priv))
4664                 num_levels = 1;
4665         else
4666                 num_levels = ilk_wm_max_level(dev) + 1;
4667
4668         if (len >= sizeof(tmp))
4669                 return -EINVAL;
4670
4671         if (copy_from_user(tmp, ubuf, len))
4672                 return -EFAULT;
4673
4674         tmp[len] = '\0';
4675
4676         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4677                      &new[0], &new[1], &new[2], &new[3],
4678                      &new[4], &new[5], &new[6], &new[7]);
4679         if (ret != num_levels)
4680                 return -EINVAL;
4681
4682         drm_modeset_lock_all(dev);
4683
4684         for (level = 0; level < num_levels; level++)
4685                 wm[level] = new[level];
4686
4687         drm_modeset_unlock_all(dev);
4688
4689         return len;
4690 }
4691
4692
4693 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4694                                     size_t len, loff_t *offp)
4695 {
4696         struct seq_file *m = file->private_data;
4697         struct drm_i915_private *dev_priv = m->private;
4698         uint16_t *latencies;
4699
4700         if (INTEL_GEN(dev_priv) >= 9)
4701                 latencies = dev_priv->wm.skl_latency;
4702         else
4703                 latencies = dev_priv->wm.pri_latency;
4704
4705         return wm_latency_write(file, ubuf, len, offp, latencies);
4706 }
4707
4708 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4709                                     size_t len, loff_t *offp)
4710 {
4711         struct seq_file *m = file->private_data;
4712         struct drm_i915_private *dev_priv = m->private;
4713         uint16_t *latencies;
4714
4715         if (INTEL_GEN(dev_priv) >= 9)
4716                 latencies = dev_priv->wm.skl_latency;
4717         else
4718                 latencies = dev_priv->wm.spr_latency;
4719
4720         return wm_latency_write(file, ubuf, len, offp, latencies);
4721 }
4722
4723 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4724                                     size_t len, loff_t *offp)
4725 {
4726         struct seq_file *m = file->private_data;
4727         struct drm_i915_private *dev_priv = m->private;
4728         uint16_t *latencies;
4729
4730         if (INTEL_GEN(dev_priv) >= 9)
4731                 latencies = dev_priv->wm.skl_latency;
4732         else
4733                 latencies = dev_priv->wm.cur_latency;
4734
4735         return wm_latency_write(file, ubuf, len, offp, latencies);
4736 }
4737
4738 static const struct file_operations i915_pri_wm_latency_fops = {
4739         .owner = THIS_MODULE,
4740         .open = pri_wm_latency_open,
4741         .read = seq_read,
4742         .llseek = seq_lseek,
4743         .release = single_release,
4744         .write = pri_wm_latency_write
4745 };
4746
4747 static const struct file_operations i915_spr_wm_latency_fops = {
4748         .owner = THIS_MODULE,
4749         .open = spr_wm_latency_open,
4750         .read = seq_read,
4751         .llseek = seq_lseek,
4752         .release = single_release,
4753         .write = spr_wm_latency_write
4754 };
4755
4756 static const struct file_operations i915_cur_wm_latency_fops = {
4757         .owner = THIS_MODULE,
4758         .open = cur_wm_latency_open,
4759         .read = seq_read,
4760         .llseek = seq_lseek,
4761         .release = single_release,
4762         .write = cur_wm_latency_write
4763 };
4764
4765 static int
4766 i915_wedged_get(void *data, u64 *val)
4767 {
4768         struct drm_i915_private *dev_priv = data;
4769
4770         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4771
4772         return 0;
4773 }
4774
4775 static int
4776 i915_wedged_set(void *data, u64 val)
4777 {
4778         struct drm_i915_private *dev_priv = data;
4779
4780         /*
4781          * There is no safeguard against this debugfs entry colliding
4782          * with the hangcheck calling same i915_handle_error() in
4783          * parallel, causing an explosion. For now we assume that the
4784          * test harness is responsible enough not to inject gpu hangs
4785          * while it is writing to 'i915_wedged'
4786          */
4787
4788         if (i915_reset_in_progress(&dev_priv->gpu_error))
4789                 return -EAGAIN;
4790
4791         intel_runtime_pm_get(dev_priv);
4792
4793         i915_handle_error(dev_priv, val,
4794                           "Manually setting wedged to %llu", val);
4795
4796         intel_runtime_pm_put(dev_priv);
4797
4798         return 0;
4799 }
4800
4801 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4802                         i915_wedged_get, i915_wedged_set,
4803                         "%llu\n");
4804
4805 static int
4806 i915_ring_missed_irq_get(void *data, u64 *val)
4807 {
4808         struct drm_i915_private *dev_priv = data;
4809
4810         *val = dev_priv->gpu_error.missed_irq_rings;
4811         return 0;
4812 }
4813
4814 static int
4815 i915_ring_missed_irq_set(void *data, u64 val)
4816 {
4817         struct drm_i915_private *dev_priv = data;
4818         struct drm_device *dev = &dev_priv->drm;
4819         int ret;
4820
4821         /* Lock against concurrent debugfs callers */
4822         ret = mutex_lock_interruptible(&dev->struct_mutex);
4823         if (ret)
4824                 return ret;
4825         dev_priv->gpu_error.missed_irq_rings = val;
4826         mutex_unlock(&dev->struct_mutex);
4827
4828         return 0;
4829 }
4830
4831 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4832                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4833                         "0x%08llx\n");
4834
4835 static int
4836 i915_ring_test_irq_get(void *data, u64 *val)
4837 {
4838         struct drm_i915_private *dev_priv = data;
4839
4840         *val = dev_priv->gpu_error.test_irq_rings;
4841
4842         return 0;
4843 }
4844
4845 static int
4846 i915_ring_test_irq_set(void *data, u64 val)
4847 {
4848         struct drm_i915_private *dev_priv = data;
4849
4850         val &= INTEL_INFO(dev_priv)->ring_mask;
4851         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4852         dev_priv->gpu_error.test_irq_rings = val;
4853
4854         return 0;
4855 }
4856
4857 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4858                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4859                         "0x%08llx\n");
4860
4861 #define DROP_UNBOUND 0x1
4862 #define DROP_BOUND 0x2
4863 #define DROP_RETIRE 0x4
4864 #define DROP_ACTIVE 0x8
4865 #define DROP_ALL (DROP_UNBOUND | \
4866                   DROP_BOUND | \
4867                   DROP_RETIRE | \
4868                   DROP_ACTIVE)
4869 static int
4870 i915_drop_caches_get(void *data, u64 *val)
4871 {
4872         *val = DROP_ALL;
4873
4874         return 0;
4875 }
4876
4877 static int
4878 i915_drop_caches_set(void *data, u64 val)
4879 {
4880         struct drm_i915_private *dev_priv = data;
4881         struct drm_device *dev = &dev_priv->drm;
4882         int ret;
4883
4884         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4885
4886         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4887          * on ioctls on -EAGAIN. */
4888         ret = mutex_lock_interruptible(&dev->struct_mutex);
4889         if (ret)
4890                 return ret;
4891
4892         if (val & DROP_ACTIVE) {
4893                 ret = i915_gem_wait_for_idle(dev_priv,
4894                                              I915_WAIT_INTERRUPTIBLE |
4895                                              I915_WAIT_LOCKED);
4896                 if (ret)
4897                         goto unlock;
4898         }
4899
4900         if (val & (DROP_RETIRE | DROP_ACTIVE))
4901                 i915_gem_retire_requests(dev_priv);
4902
4903         if (val & DROP_BOUND)
4904                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4905
4906         if (val & DROP_UNBOUND)
4907                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4908
4909 unlock:
4910         mutex_unlock(&dev->struct_mutex);
4911
4912         return ret;
4913 }
4914
4915 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4916                         i915_drop_caches_get, i915_drop_caches_set,
4917                         "0x%08llx\n");
4918
4919 static int
4920 i915_max_freq_get(void *data, u64 *val)
4921 {
4922         struct drm_i915_private *dev_priv = data;
4923
4924         if (INTEL_GEN(dev_priv) < 6)
4925                 return -ENODEV;
4926
4927         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4928         return 0;
4929 }
4930
4931 static int
4932 i915_max_freq_set(void *data, u64 val)
4933 {
4934         struct drm_i915_private *dev_priv = data;
4935         u32 hw_max, hw_min;
4936         int ret;
4937
4938         if (INTEL_GEN(dev_priv) < 6)
4939                 return -ENODEV;
4940
4941         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4942
4943         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4944         if (ret)
4945                 return ret;
4946
4947         /*
4948          * Turbo will still be enabled, but won't go above the set value.
4949          */
4950         val = intel_freq_opcode(dev_priv, val);
4951
4952         hw_max = dev_priv->rps.max_freq;
4953         hw_min = dev_priv->rps.min_freq;
4954
4955         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4956                 mutex_unlock(&dev_priv->rps.hw_lock);
4957                 return -EINVAL;
4958         }
4959
4960         dev_priv->rps.max_freq_softlimit = val;
4961
4962         intel_set_rps(dev_priv, val);
4963
4964         mutex_unlock(&dev_priv->rps.hw_lock);
4965
4966         return 0;
4967 }
4968
4969 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4970                         i915_max_freq_get, i915_max_freq_set,
4971                         "%llu\n");
4972
4973 static int
4974 i915_min_freq_get(void *data, u64 *val)
4975 {
4976         struct drm_i915_private *dev_priv = data;
4977
4978         if (INTEL_GEN(dev_priv) < 6)
4979                 return -ENODEV;
4980
4981         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4982         return 0;
4983 }
4984
4985 static int
4986 i915_min_freq_set(void *data, u64 val)
4987 {
4988         struct drm_i915_private *dev_priv = data;
4989         u32 hw_max, hw_min;
4990         int ret;
4991
4992         if (INTEL_GEN(dev_priv) < 6)
4993                 return -ENODEV;
4994
4995         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4996
4997         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4998         if (ret)
4999                 return ret;
5000
5001         /*
5002          * Turbo will still be enabled, but won't go below the set value.
5003          */
5004         val = intel_freq_opcode(dev_priv, val);
5005
5006         hw_max = dev_priv->rps.max_freq;
5007         hw_min = dev_priv->rps.min_freq;
5008
5009         if (val < hw_min ||
5010             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5011                 mutex_unlock(&dev_priv->rps.hw_lock);
5012                 return -EINVAL;
5013         }
5014
5015         dev_priv->rps.min_freq_softlimit = val;
5016
5017         intel_set_rps(dev_priv, val);
5018
5019         mutex_unlock(&dev_priv->rps.hw_lock);
5020
5021         return 0;
5022 }
5023
5024 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5025                         i915_min_freq_get, i915_min_freq_set,
5026                         "%llu\n");
5027
5028 static int
5029 i915_cache_sharing_get(void *data, u64 *val)
5030 {
5031         struct drm_i915_private *dev_priv = data;
5032         struct drm_device *dev = &dev_priv->drm;
5033         u32 snpcr;
5034         int ret;
5035
5036         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5037                 return -ENODEV;
5038
5039         ret = mutex_lock_interruptible(&dev->struct_mutex);
5040         if (ret)
5041                 return ret;
5042         intel_runtime_pm_get(dev_priv);
5043
5044         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5045
5046         intel_runtime_pm_put(dev_priv);
5047         mutex_unlock(&dev->struct_mutex);
5048
5049         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5050
5051         return 0;
5052 }
5053
5054 static int
5055 i915_cache_sharing_set(void *data, u64 val)
5056 {
5057         struct drm_i915_private *dev_priv = data;
5058         u32 snpcr;
5059
5060         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5061                 return -ENODEV;
5062
5063         if (val > 3)
5064                 return -EINVAL;
5065
5066         intel_runtime_pm_get(dev_priv);
5067         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5068
5069         /* Update the cache sharing policy here as well */
5070         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5071         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5072         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5073         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5074
5075         intel_runtime_pm_put(dev_priv);
5076         return 0;
5077 }
5078
5079 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5080                         i915_cache_sharing_get, i915_cache_sharing_set,
5081                         "%llu\n");
5082
5083 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5084                                           struct sseu_dev_info *sseu)
5085 {
5086         int ss_max = 2;
5087         int ss;
5088         u32 sig1[ss_max], sig2[ss_max];
5089
5090         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5091         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5092         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5093         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5094
5095         for (ss = 0; ss < ss_max; ss++) {
5096                 unsigned int eu_cnt;
5097
5098                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5099                         /* skip disabled subslice */
5100                         continue;
5101
5102                 sseu->slice_mask = BIT(0);
5103                 sseu->subslice_mask |= BIT(ss);
5104                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5105                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5106                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5107                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5108                 sseu->eu_total += eu_cnt;
5109                 sseu->eu_per_subslice = max_t(unsigned int,
5110                                               sseu->eu_per_subslice, eu_cnt);
5111         }
5112 }
5113
5114 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5115                                     struct sseu_dev_info *sseu)
5116 {
5117         int s_max = 3, ss_max = 4;
5118         int s, ss;
5119         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5120
5121         /* BXT has a single slice and at most 3 subslices. */
5122         if (IS_BROXTON(dev_priv)) {
5123                 s_max = 1;
5124                 ss_max = 3;
5125         }
5126
5127         for (s = 0; s < s_max; s++) {
5128                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5129                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5130                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5131         }
5132
5133         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5134                      GEN9_PGCTL_SSA_EU19_ACK |
5135                      GEN9_PGCTL_SSA_EU210_ACK |
5136                      GEN9_PGCTL_SSA_EU311_ACK;
5137         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5138                      GEN9_PGCTL_SSB_EU19_ACK |
5139                      GEN9_PGCTL_SSB_EU210_ACK |
5140                      GEN9_PGCTL_SSB_EU311_ACK;
5141
5142         for (s = 0; s < s_max; s++) {
5143                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5144                         /* skip disabled slice */
5145                         continue;
5146
5147                 sseu->slice_mask |= BIT(s);
5148
5149                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5150                         sseu->subslice_mask =
5151                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5152
5153                 for (ss = 0; ss < ss_max; ss++) {
5154                         unsigned int eu_cnt;
5155
5156                         if (IS_BROXTON(dev_priv)) {
5157                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5158                                         /* skip disabled subslice */
5159                                         continue;
5160
5161                                 sseu->subslice_mask |= BIT(ss);
5162                         }
5163
5164                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5165                                                eu_mask[ss%2]);
5166                         sseu->eu_total += eu_cnt;
5167                         sseu->eu_per_subslice = max_t(unsigned int,
5168                                                       sseu->eu_per_subslice,
5169                                                       eu_cnt);
5170                 }
5171         }
5172 }
5173
5174 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5175                                          struct sseu_dev_info *sseu)
5176 {
5177         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5178         int s;
5179
5180         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5181
5182         if (sseu->slice_mask) {
5183                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5184                 sseu->eu_per_subslice =
5185                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5186                 sseu->eu_total = sseu->eu_per_subslice *
5187                                  sseu_subslice_total(sseu);
5188
5189                 /* subtract fused off EU(s) from enabled slice(s) */
5190                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5191                         u8 subslice_7eu =
5192                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5193
5194                         sseu->eu_total -= hweight8(subslice_7eu);
5195                 }
5196         }
5197 }
5198
5199 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5200                                  const struct sseu_dev_info *sseu)
5201 {
5202         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5203         const char *type = is_available_info ? "Available" : "Enabled";
5204
5205         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5206                    sseu->slice_mask);
5207         seq_printf(m, "  %s Slice Total: %u\n", type,
5208                    hweight8(sseu->slice_mask));
5209         seq_printf(m, "  %s Subslice Total: %u\n", type,
5210                    sseu_subslice_total(sseu));
5211         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5212                    sseu->subslice_mask);
5213         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5214                    hweight8(sseu->subslice_mask));
5215         seq_printf(m, "  %s EU Total: %u\n", type,
5216                    sseu->eu_total);
5217         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5218                    sseu->eu_per_subslice);
5219
5220         if (!is_available_info)
5221                 return;
5222
5223         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5224         if (HAS_POOLED_EU(dev_priv))
5225                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5226
5227         seq_printf(m, "  Has Slice Power Gating: %s\n",
5228                    yesno(sseu->has_slice_pg));
5229         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5230                    yesno(sseu->has_subslice_pg));
5231         seq_printf(m, "  Has EU Power Gating: %s\n",
5232                    yesno(sseu->has_eu_pg));
5233 }
5234
5235 static int i915_sseu_status(struct seq_file *m, void *unused)
5236 {
5237         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5238         struct sseu_dev_info sseu;
5239
5240         if (INTEL_GEN(dev_priv) < 8)
5241                 return -ENODEV;
5242
5243         seq_puts(m, "SSEU Device Info\n");
5244         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5245
5246         seq_puts(m, "SSEU Device Status\n");
5247         memset(&sseu, 0, sizeof(sseu));
5248
5249         intel_runtime_pm_get(dev_priv);
5250
5251         if (IS_CHERRYVIEW(dev_priv)) {
5252                 cherryview_sseu_device_status(dev_priv, &sseu);
5253         } else if (IS_BROADWELL(dev_priv)) {
5254                 broadwell_sseu_device_status(dev_priv, &sseu);
5255         } else if (INTEL_GEN(dev_priv) >= 9) {
5256                 gen9_sseu_device_status(dev_priv, &sseu);
5257         }
5258
5259         intel_runtime_pm_put(dev_priv);
5260
5261         i915_print_sseu_info(m, false, &sseu);
5262
5263         return 0;
5264 }
5265
5266 static int i915_forcewake_open(struct inode *inode, struct file *file)
5267 {
5268         struct drm_i915_private *dev_priv = inode->i_private;
5269
5270         if (INTEL_GEN(dev_priv) < 6)
5271                 return 0;
5272
5273         intel_runtime_pm_get(dev_priv);
5274         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5275
5276         return 0;
5277 }
5278
5279 static int i915_forcewake_release(struct inode *inode, struct file *file)
5280 {
5281         struct drm_i915_private *dev_priv = inode->i_private;
5282
5283         if (INTEL_GEN(dev_priv) < 6)
5284                 return 0;
5285
5286         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5287         intel_runtime_pm_put(dev_priv);
5288
5289         return 0;
5290 }
5291
5292 static const struct file_operations i915_forcewake_fops = {
5293         .owner = THIS_MODULE,
5294         .open = i915_forcewake_open,
5295         .release = i915_forcewake_release,
5296 };
5297
5298 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5299 {
5300         struct dentry *ent;
5301
5302         ent = debugfs_create_file("i915_forcewake_user",
5303                                   S_IRUSR,
5304                                   root, to_i915(minor->dev),
5305                                   &i915_forcewake_fops);
5306         if (!ent)
5307                 return -ENOMEM;
5308
5309         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5310 }
5311
5312 static int i915_debugfs_create(struct dentry *root,
5313                                struct drm_minor *minor,
5314                                const char *name,
5315                                const struct file_operations *fops)
5316 {
5317         struct dentry *ent;
5318
5319         ent = debugfs_create_file(name,
5320                                   S_IRUGO | S_IWUSR,
5321                                   root, to_i915(minor->dev),
5322                                   fops);
5323         if (!ent)
5324                 return -ENOMEM;
5325
5326         return drm_add_fake_info_node(minor, ent, fops);
5327 }
5328
5329 static const struct drm_info_list i915_debugfs_list[] = {
5330         {"i915_capabilities", i915_capabilities, 0},
5331         {"i915_gem_objects", i915_gem_object_info, 0},
5332         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5333         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5334         {"i915_gem_stolen", i915_gem_stolen_list_info },
5335         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5336         {"i915_gem_request", i915_gem_request_info, 0},
5337         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5338         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5339         {"i915_gem_interrupt", i915_interrupt_info, 0},
5340         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5341         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5342         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5343         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5344         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5345         {"i915_guc_info", i915_guc_info, 0},
5346         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5347         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5348         {"i915_frequency_info", i915_frequency_info, 0},
5349         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5350         {"i915_drpc_info", i915_drpc_info, 0},
5351         {"i915_emon_status", i915_emon_status, 0},
5352         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5353         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5354         {"i915_fbc_status", i915_fbc_status, 0},
5355         {"i915_ips_status", i915_ips_status, 0},
5356         {"i915_sr_status", i915_sr_status, 0},
5357         {"i915_opregion", i915_opregion, 0},
5358         {"i915_vbt", i915_vbt, 0},
5359         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5360         {"i915_context_status", i915_context_status, 0},
5361         {"i915_dump_lrc", i915_dump_lrc, 0},
5362         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5363         {"i915_swizzle_info", i915_swizzle_info, 0},
5364         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5365         {"i915_llc", i915_llc, 0},
5366         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5367         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5368         {"i915_energy_uJ", i915_energy_uJ, 0},
5369         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5370         {"i915_power_domain_info", i915_power_domain_info, 0},
5371         {"i915_dmc_info", i915_dmc_info, 0},
5372         {"i915_display_info", i915_display_info, 0},
5373         {"i915_engine_info", i915_engine_info, 0},
5374         {"i915_semaphore_status", i915_semaphore_status, 0},
5375         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5376         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5377         {"i915_wa_registers", i915_wa_registers, 0},
5378         {"i915_ddb_info", i915_ddb_info, 0},
5379         {"i915_sseu_status", i915_sseu_status, 0},
5380         {"i915_drrs_status", i915_drrs_status, 0},
5381         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5382 };
5383 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5384
5385 static const struct i915_debugfs_files {
5386         const char *name;
5387         const struct file_operations *fops;
5388 } i915_debugfs_files[] = {
5389         {"i915_wedged", &i915_wedged_fops},
5390         {"i915_max_freq", &i915_max_freq_fops},
5391         {"i915_min_freq", &i915_min_freq_fops},
5392         {"i915_cache_sharing", &i915_cache_sharing_fops},
5393         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5394         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5395         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5396 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5397         {"i915_error_state", &i915_error_state_fops},
5398 #endif
5399         {"i915_next_seqno", &i915_next_seqno_fops},
5400         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5401         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5402         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5403         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5404         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5405         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5406         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5407         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5408 };
5409
5410 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5411 {
5412         enum pipe pipe;
5413
5414         for_each_pipe(dev_priv, pipe) {
5415                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5416
5417                 pipe_crc->opened = false;
5418                 spin_lock_init(&pipe_crc->lock);
5419                 init_waitqueue_head(&pipe_crc->wq);
5420         }
5421 }
5422
5423 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5424 {
5425         struct drm_minor *minor = dev_priv->drm.primary;
5426         int ret, i;
5427
5428         ret = i915_forcewake_create(minor->debugfs_root, minor);
5429         if (ret)
5430                 return ret;
5431
5432         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5433                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5434                 if (ret)
5435                         return ret;
5436         }
5437
5438         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5439                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5440                                           i915_debugfs_files[i].name,
5441                                           i915_debugfs_files[i].fops);
5442                 if (ret)
5443                         return ret;
5444         }
5445
5446         return drm_debugfs_create_files(i915_debugfs_list,
5447                                         I915_DEBUGFS_ENTRIES,
5448                                         minor->debugfs_root, minor);
5449 }
5450
5451 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5452 {
5453         struct drm_minor *minor = dev_priv->drm.primary;
5454         int i;
5455
5456         drm_debugfs_remove_files(i915_debugfs_list,
5457                                  I915_DEBUGFS_ENTRIES, minor);
5458
5459         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5460                                  1, minor);
5461
5462         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5463                 struct drm_info_list *info_list =
5464                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5465
5466                 drm_debugfs_remove_files(info_list, 1, minor);
5467         }
5468
5469         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5470                 struct drm_info_list *info_list =
5471                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5472
5473                 drm_debugfs_remove_files(info_list, 1, minor);
5474         }
5475 }
5476
5477 struct dpcd_block {
5478         /* DPCD dump start address. */
5479         unsigned int offset;
5480         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5481         unsigned int end;
5482         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5483         size_t size;
5484         /* Only valid for eDP. */
5485         bool edp;
5486 };
5487
5488 static const struct dpcd_block i915_dpcd_debug[] = {
5489         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5490         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5491         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5492         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5493         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5494         { .offset = DP_SET_POWER },
5495         { .offset = DP_EDP_DPCD_REV },
5496         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5497         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5498         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5499 };
5500
5501 static int i915_dpcd_show(struct seq_file *m, void *data)
5502 {
5503         struct drm_connector *connector = m->private;
5504         struct intel_dp *intel_dp =
5505                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5506         uint8_t buf[16];
5507         ssize_t err;
5508         int i;
5509
5510         if (connector->status != connector_status_connected)
5511                 return -ENODEV;
5512
5513         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5514                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5515                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5516
5517                 if (b->edp &&
5518                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5519                         continue;
5520
5521                 /* low tech for now */
5522                 if (WARN_ON(size > sizeof(buf)))
5523                         continue;
5524
5525                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5526                 if (err <= 0) {
5527                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5528                                   size, b->offset, err);
5529                         continue;
5530                 }
5531
5532                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5533         }
5534
5535         return 0;
5536 }
5537
5538 static int i915_dpcd_open(struct inode *inode, struct file *file)
5539 {
5540         return single_open(file, i915_dpcd_show, inode->i_private);
5541 }
5542
5543 static const struct file_operations i915_dpcd_fops = {
5544         .owner = THIS_MODULE,
5545         .open = i915_dpcd_open,
5546         .read = seq_read,
5547         .llseek = seq_lseek,
5548         .release = single_release,
5549 };
5550
5551 static int i915_panel_show(struct seq_file *m, void *data)
5552 {
5553         struct drm_connector *connector = m->private;
5554         struct intel_dp *intel_dp =
5555                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5556
5557         if (connector->status != connector_status_connected)
5558                 return -ENODEV;
5559
5560         seq_printf(m, "Panel power up delay: %d\n",
5561                    intel_dp->panel_power_up_delay);
5562         seq_printf(m, "Panel power down delay: %d\n",
5563                    intel_dp->panel_power_down_delay);
5564         seq_printf(m, "Backlight on delay: %d\n",
5565                    intel_dp->backlight_on_delay);
5566         seq_printf(m, "Backlight off delay: %d\n",
5567                    intel_dp->backlight_off_delay);
5568
5569         return 0;
5570 }
5571
5572 static int i915_panel_open(struct inode *inode, struct file *file)
5573 {
5574         return single_open(file, i915_panel_show, inode->i_private);
5575 }
5576
5577 static const struct file_operations i915_panel_fops = {
5578         .owner = THIS_MODULE,
5579         .open = i915_panel_open,
5580         .read = seq_read,
5581         .llseek = seq_lseek,
5582         .release = single_release,
5583 };
5584
5585 /**
5586  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5587  * @connector: pointer to a registered drm_connector
5588  *
5589  * Cleanup will be done by drm_connector_unregister() through a call to
5590  * drm_debugfs_connector_remove().
5591  *
5592  * Returns 0 on success, negative error codes on error.
5593  */
5594 int i915_debugfs_connector_add(struct drm_connector *connector)
5595 {
5596         struct dentry *root = connector->debugfs_entry;
5597
5598         /* The connector must have been registered beforehands. */
5599         if (!root)
5600                 return -ENODEV;
5601
5602         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5603             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5604                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5605                                     connector, &i915_dpcd_fops);
5606
5607         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5608                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5609                                     connector, &i915_panel_fops);
5610
5611         return 0;
5612 }