drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/debugfs.h>
  30 #include <linux/sort.h>
  31 #include "intel_drv.h"
  32
  33 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  34 {
  35         return to_i915(node->minor->dev);
  36 }
  37
  38 static __always_inline void seq_print_param(struct seq_file *m,
  39                                             const char *name,
  40                                             const char *type,
  41                                             const void *x)
  42 {
  43         if (!__builtin_strcmp(type, "bool"))
  44                 seq_printf(m, "i915.%s=%s\n", name, yesno(*(const bool *)x));
  45         else if (!__builtin_strcmp(type, "int"))
  46                 seq_printf(m, "i915.%s=%d\n", name, *(const int *)x);
  47         else if (!__builtin_strcmp(type, "unsigned int"))
  48                 seq_printf(m, "i915.%s=%u\n", name, *(const unsigned int *)x);
  49         else if (!__builtin_strcmp(type, "char *"))
  50                 seq_printf(m, "i915.%s=%s\n", name, *(const char **)x);
  51         else
  52                 BUILD_BUG();
  53 }
  54
  55 static int i915_capabilities(struct seq_file *m, void *data)
  56 {
  57         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  58         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  59
  60         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  61         seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  63
  64 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  65         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  66 #undef PRINT_FLAG
  67
  68         kernel_param_lock(THIS_MODULE);
  69 #define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, &i915.x);
  70         I915_PARAMS_FOR_EACH(PRINT_PARAM);
  71 #undef PRINT_PARAM
  72         kernel_param_unlock(THIS_MODULE);
  73
  74         return 0;
  75 }
  76
  77 static char get_active_flag(struct drm_i915_gem_object *obj)
  78 {
  79         return i915_gem_object_is_active(obj) ? '*' : ' ';
  80 }
  81
  82 static char get_pin_flag(struct drm_i915_gem_object *obj)
  83 {
  84         return obj->pin_display ? 'p' : ' ';
  85 }
  86
  87 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  88 {
  89         switch (i915_gem_object_get_tiling(obj)) {
  90         default:
  91         case I915_TILING_NONE: return ' ';
  92         case I915_TILING_X: return 'X';
  93         case I915_TILING_Y: return 'Y';
  94         }
  95 }
  96
  97 static char get_global_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 100 }
 101
 102 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 103 {
 104         return obj->mm.mapping ? 'M' : ' ';
 105 }
 106
 107 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 108 {
 109         u64 size = 0;
 110         struct i915_vma *vma;
 111
 112         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 113                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 114                         size += vma->node.size;
 115         }
 116
 117         return size;
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 124         struct intel_engine_cs *engine;
 125         struct i915_vma *vma;
 126         unsigned int frontbuffer_bits;
 127         int pin_count = 0;
 128
 129         lockdep_assert_held(&obj->base.dev->struct_mutex);
 130
 131         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 132                    &obj->base,
 133                    get_active_flag(obj),
 134                    get_pin_flag(obj),
 135                    get_tiling_flag(obj),
 136                    get_global_flag(obj),
 137                    get_pin_mapped_flag(obj),
 138                    obj->base.size / 1024,
 139                    obj->base.read_domains,
 140                    obj->base.write_domain,
 141                    i915_cache_level_str(dev_priv, obj->cache_level),
 142                    obj->mm.dirty ? " dirty" : "",
 143                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 144         if (obj->base.name)
 145                 seq_printf(m, " (name: %d)", obj->base.name);
 146         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 147                 if (i915_vma_is_pinned(vma))
 148                         pin_count++;
 149         }
 150         seq_printf(m, " (pinned x %d)", pin_count);
 151         if (obj->pin_display)
 152                 seq_printf(m, " (display)");
 153         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 154                 if (!drm_mm_node_allocated(&vma->node))
 155                         continue;
 156
 157                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 158                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 159                            vma->node.start, vma->node.size);
 160                 if (i915_vma_is_ggtt(vma)) {
 161                         switch (vma->ggtt_view.type) {
 162                         case I915_GGTT_VIEW_NORMAL:
 163                                 seq_puts(m, ", normal");
 164                                 break;
 165
 166                         case I915_GGTT_VIEW_PARTIAL:
 167                                 seq_printf(m, ", partial [%08llx+%x]",
 168                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 169                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 170                                 break;
 171
 172                         case I915_GGTT_VIEW_ROTATED:
 173                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 174                                            vma->ggtt_view.rotated.plane[0].width,
 175                                            vma->ggtt_view.rotated.plane[0].height,
 176                                            vma->ggtt_view.rotated.plane[0].stride,
 177                                            vma->ggtt_view.rotated.plane[0].offset,
 178                                            vma->ggtt_view.rotated.plane[1].width,
 179                                            vma->ggtt_view.rotated.plane[1].height,
 180                                            vma->ggtt_view.rotated.plane[1].stride,
 181                                            vma->ggtt_view.rotated.plane[1].offset);
 182                                 break;
 183
 184                         default:
 185                                 MISSING_CASE(vma->ggtt_view.type);
 186                                 break;
 187                         }
 188                 }
 189                 if (vma->fence)
 190                         seq_printf(m, " , fence: %d%s",
 191                                    vma->fence->id,
 192                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 193                 seq_puts(m, ")");
 194         }
 195         if (obj->stolen)
 196                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 197
 198         engine = i915_gem_object_last_write_engine(obj);
 199         if (engine)
 200                 seq_printf(m, " (%s)", engine->name);
 201
 202         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 203         if (frontbuffer_bits)
 204                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 205 }
 206
 207 static int obj_rank_by_stolen(const void *A, const void *B)
 208 {
 209         const struct drm_i915_gem_object *a =
 210                 *(const struct drm_i915_gem_object **)A;
 211         const struct drm_i915_gem_object *b =
 212                 *(const struct drm_i915_gem_object **)B;
 213
 214         if (a->stolen->start < b->stolen->start)
 215                 return -1;
 216         if (a->stolen->start > b->stolen->start)
 217                 return 1;
 218         return 0;
 219 }
 220
 221 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 222 {
 223         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 224         struct drm_device *dev = &dev_priv->drm;
 225         struct drm_i915_gem_object **objects;
 226         struct drm_i915_gem_object *obj;
 227         u64 total_obj_size, total_gtt_size;
 228         unsigned long total, count, n;
 229         int ret;
 230
 231         total = READ_ONCE(dev_priv->mm.object_count);
 232         objects = drm_malloc_ab(total, sizeof(*objects));
 233         if (!objects)
 234                 return -ENOMEM;
 235
 236         ret = mutex_lock_interruptible(&dev->struct_mutex);
 237         if (ret)
 238                 goto out;
 239
 240         total_obj_size = total_gtt_size = count = 0;
 241         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 242                 if (count == total)
 243                         break;
 244
 245                 if (obj->stolen == NULL)
 246                         continue;
 247
 248                 objects[count++] = obj;
 249                 total_obj_size += obj->base.size;
 250                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 251
 252         }
 253         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 254                 if (count == total)
 255                         break;
 256
 257                 if (obj->stolen == NULL)
 258                         continue;
 259
 260                 objects[count++] = obj;
 261                 total_obj_size += obj->base.size;
 262         }
 263
 264         sort(objects, count, sizeof(*objects), obj_rank_by_stolen, NULL);
 265
 266         seq_puts(m, "Stolen:\n");
 267         for (n = 0; n < count; n++) {
 268                 seq_puts(m, "   ");
 269                 describe_obj(m, objects[n]);
 270                 seq_putc(m, '\n');
 271         }
 272         seq_printf(m, "Total %lu objects, %llu bytes, %llu GTT size\n",
 273                    count, total_obj_size, total_gtt_size);
 274
 275         mutex_unlock(&dev->struct_mutex);
 276 out:
 277         drm_free_large(objects);
 278         return ret;
 279 }
 280
 281 struct file_stats {
 282         struct drm_i915_file_private *file_priv;
 283         unsigned long count;
 284         u64 total, unbound;
 285         u64 global, shared;
 286         u64 active, inactive;
 287 };
 288
 289 static int per_file_stats(int id, void *ptr, void *data)
 290 {
 291         struct drm_i915_gem_object *obj = ptr;
 292         struct file_stats *stats = data;
 293         struct i915_vma *vma;
 294
 295         lockdep_assert_held(&obj->base.dev->struct_mutex);
 296
 297         stats->count++;
 298         stats->total += obj->base.size;
 299         if (!obj->bind_count)
 300                 stats->unbound += obj->base.size;
 301         if (obj->base.name || obj->base.dma_buf)
 302                 stats->shared += obj->base.size;
 303
 304         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 305                 if (!drm_mm_node_allocated(&vma->node))
 306                         continue;
 307
 308                 if (i915_vma_is_ggtt(vma)) {
 309                         stats->global += vma->node.size;
 310                 } else {
 311                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 312
 313                         if (ppgtt->base.file != stats->file_priv)
 314                                 continue;
 315                 }
 316
 317                 if (i915_vma_is_active(vma))
 318                         stats->active += vma->node.size;
 319                 else
 320                         stats->inactive += vma->node.size;
 321         }
 322
 323         return 0;
 324 }
 325
 326 #define print_file_stats(m, name, stats) do { \
 327         if (stats.count) \
 328                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 329                            name, \
 330                            stats.count, \
 331                            stats.total, \
 332                            stats.active, \
 333                            stats.inactive, \
 334                            stats.global, \
 335                            stats.shared, \
 336                            stats.unbound); \
 337 } while (0)
 338
 339 static void print_batch_pool_stats(struct seq_file *m,
 340                                    struct drm_i915_private *dev_priv)
 341 {
 342         struct drm_i915_gem_object *obj;
 343         struct file_stats stats;
 344         struct intel_engine_cs *engine;
 345         enum intel_engine_id id;
 346         int j;
 347
 348         memset(&stats, 0, sizeof(stats));
 349
 350         for_each_engine(engine, dev_priv, id) {
 351                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 352                         list_for_each_entry(obj,
 353                                             &engine->batch_pool.cache_list[j],
 354                                             batch_pool_link)
 355                                 per_file_stats(0, obj, &stats);
 356                 }
 357         }
 358
 359         print_file_stats(m, "[k]batch pool", stats);
 360 }
 361
 362 static int per_file_ctx_stats(int id, void *ptr, void *data)
 363 {
 364         struct i915_gem_context *ctx = ptr;
 365         int n;
 366
 367         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 368                 if (ctx->engine[n].state)
 369                         per_file_stats(0, ctx->engine[n].state->obj, data);
 370                 if (ctx->engine[n].ring)
 371                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void print_context_stats(struct seq_file *m,
 378                                 struct drm_i915_private *dev_priv)
 379 {
 380         struct drm_device *dev = &dev_priv->drm;
 381         struct file_stats stats;
 382         struct drm_file *file;
 383
 384         memset(&stats, 0, sizeof(stats));
 385
 386         mutex_lock(&dev->struct_mutex);
 387         if (dev_priv->kernel_context)
 388                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 389
 390         list_for_each_entry(file, &dev->filelist, lhead) {
 391                 struct drm_i915_file_private *fpriv = file->driver_priv;
 392                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 393         }
 394         mutex_unlock(&dev->struct_mutex);
 395
 396         print_file_stats(m, "[k]contexts", stats);
 397 }
 398
 399 static int i915_gem_object_info(struct seq_file *m, void *data)
 400 {
 401         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 402         struct drm_device *dev = &dev_priv->drm;
 403         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 404         u32 count, mapped_count, purgeable_count, dpy_count;
 405         u64 size, mapped_size, purgeable_size, dpy_size;
 406         struct drm_i915_gem_object *obj;
 407         struct drm_file *file;
 408         int ret;
 409
 410         ret = mutex_lock_interruptible(&dev->struct_mutex);
 411         if (ret)
 412                 return ret;
 413
 414         seq_printf(m, "%u objects, %llu bytes\n",
 415                    dev_priv->mm.object_count,
 416                    dev_priv->mm.object_memory);
 417
 418         size = count = 0;
 419         mapped_size = mapped_count = 0;
 420         purgeable_size = purgeable_count = 0;
 421         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 422                 size += obj->base.size;
 423                 ++count;
 424
 425                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 426                         purgeable_size += obj->base.size;
 427                         ++purgeable_count;
 428                 }
 429
 430                 if (obj->mm.mapping) {
 431                         mapped_count++;
 432                         mapped_size += obj->base.size;
 433                 }
 434         }
 435         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 436
 437         size = count = dpy_size = dpy_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 439                 size += obj->base.size;
 440                 ++count;
 441
 442                 if (obj->pin_display) {
 443                         dpy_size += obj->base.size;
 444                         ++dpy_count;
 445                 }
 446
 447                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 448                         purgeable_size += obj->base.size;
 449                         ++purgeable_count;
 450                 }
 451
 452                 if (obj->mm.mapping) {
 453                         mapped_count++;
 454                         mapped_size += obj->base.size;
 455                 }
 456         }
 457         seq_printf(m, "%u bound objects, %llu bytes\n",
 458                    count, size);
 459         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 460                    purgeable_count, purgeable_size);
 461         seq_printf(m, "%u mapped objects, %llu bytes\n",
 462                    mapped_count, mapped_size);
 463         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 464                    dpy_count, dpy_size);
 465
 466         seq_printf(m, "%llu [%llu] gtt total\n",
 467                    ggtt->base.total, ggtt->mappable_end);
 468
 469         seq_putc(m, '\n');
 470         print_batch_pool_stats(m, dev_priv);
 471         mutex_unlock(&dev->struct_mutex);
 472
 473         mutex_lock(&dev->filelist_mutex);
 474         print_context_stats(m, dev_priv);
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct drm_i915_file_private *file_priv = file->driver_priv;
 478                 struct drm_i915_gem_request *request;
 479                 struct task_struct *task;
 480
 481                 mutex_lock(&dev->struct_mutex);
 482
 483                 memset(&stats, 0, sizeof(stats));
 484                 stats.file_priv = file->driver_priv;
 485                 spin_lock(&file->table_lock);
 486                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 487                 spin_unlock(&file->table_lock);
 488                 /*
 489                  * Although we have a valid reference on file->pid, that does
 490                  * not guarantee that the task_struct who called get_pid() is
 491                  * still alive (e.g. get_pid(current) => fork() => exit()).
 492                  * Therefore, we need to protect this ->comm access using RCU.
 493                  */
 494                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 495                                                    struct drm_i915_gem_request,
 496                                                    client_link);
 497                 rcu_read_lock();
 498                 task = pid_task(request && request->ctx->pid ?
 499                                 request->ctx->pid : file->pid,
 500                                 PIDTYPE_PID);
 501                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 502                 rcu_read_unlock();
 503
 504                 mutex_unlock(&dev->struct_mutex);
 505         }
 506         mutex_unlock(&dev->filelist_mutex);
 507
 508         return 0;
 509 }
 510
 511 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 512 {
 513         struct drm_info_node *node = m->private;
 514         struct drm_i915_private *dev_priv = node_to_i915(node);
 515         struct drm_device *dev = &dev_priv->drm;
 516         bool show_pin_display_only = !!node->info_ent->data;
 517         struct drm_i915_gem_object *obj;
 518         u64 total_obj_size, total_gtt_size;
 519         int count, ret;
 520
 521         ret = mutex_lock_interruptible(&dev->struct_mutex);
 522         if (ret)
 523                 return ret;
 524
 525         total_obj_size = total_gtt_size = count = 0;
 526         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 527                 if (show_pin_display_only && !obj->pin_display)
 528                         continue;
 529
 530                 seq_puts(m, "   ");
 531                 describe_obj(m, obj);
 532                 seq_putc(m, '\n');
 533                 total_obj_size += obj->base.size;
 534                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 535                 count++;
 536         }
 537
 538         mutex_unlock(&dev->struct_mutex);
 539
 540         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 541                    count, total_obj_size, total_gtt_size);
 542
 543         return 0;
 544 }
 545
 546 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 547 {
 548         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 549         struct drm_device *dev = &dev_priv->drm;
 550         struct intel_crtc *crtc;
 551         int ret;
 552
 553         ret = mutex_lock_interruptible(&dev->struct_mutex);
 554         if (ret)
 555                 return ret;
 556
 557         for_each_intel_crtc(dev, crtc) {
 558                 const char pipe = pipe_name(crtc->pipe);
 559                 const char plane = plane_name(crtc->plane);
 560                 struct intel_flip_work *work;
 561
 562                 spin_lock_irq(&dev->event_lock);
 563                 work = crtc->flip_work;
 564                 if (work == NULL) {
 565                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 566                                    pipe, plane);
 567                 } else {
 568                         u32 pending;
 569                         u32 addr;
 570
 571                         pending = atomic_read(&work->pending);
 572                         if (pending) {
 573                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 574                                            pipe, plane);
 575                         } else {
 576                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 577                                            pipe, plane);
 578                         }
 579                         if (work->flip_queued_req) {
 580                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 581
 582                                 seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n",
 583                                            engine->name,
 584                                            work->flip_queued_req->global_seqno,
 585                                            intel_engine_last_submit(engine),
 586                                            intel_engine_get_seqno(engine),
 587                                            i915_gem_request_completed(work->flip_queued_req));
 588                         } else
 589                                 seq_printf(m, "Flip not associated with any ring\n");
 590                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 591                                    work->flip_queued_vblank,
 592                                    work->flip_ready_vblank,
 593                                    intel_crtc_get_vblank_counter(crtc));
 594                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 595
 596                         if (INTEL_GEN(dev_priv) >= 4)
 597                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 598                         else
 599                                 addr = I915_READ(DSPADDR(crtc->plane));
 600                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 601
 602                         if (work->pending_flip_obj) {
 603                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 604                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 605                         }
 606                 }
 607                 spin_unlock_irq(&dev->event_lock);
 608         }
 609
 610         mutex_unlock(&dev->struct_mutex);
 611
 612         return 0;
 613 }
 614
 615 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 616 {
 617         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 618         struct drm_device *dev = &dev_priv->drm;
 619         struct drm_i915_gem_object *obj;
 620         struct intel_engine_cs *engine;
 621         enum intel_engine_id id;
 622         int total = 0;
 623         int ret, j;
 624
 625         ret = mutex_lock_interruptible(&dev->struct_mutex);
 626         if (ret)
 627                 return ret;
 628
 629         for_each_engine(engine, dev_priv, id) {
 630                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 631                         int count;
 632
 633                         count = 0;
 634                         list_for_each_entry(obj,
 635                                             &engine->batch_pool.cache_list[j],
 636                                             batch_pool_link)
 637                                 count++;
 638                         seq_printf(m, "%s cache[%d]: %d objects\n",
 639                                    engine->name, j, count);
 640
 641                         list_for_each_entry(obj,
 642                                             &engine->batch_pool.cache_list[j],
 643                                             batch_pool_link) {
 644                                 seq_puts(m, "   ");
 645                                 describe_obj(m, obj);
 646                                 seq_putc(m, '\n');
 647                         }
 648
 649                         total += count;
 650                 }
 651         }
 652
 653         seq_printf(m, "total: %d\n", total);
 654
 655         mutex_unlock(&dev->struct_mutex);
 656
 657         return 0;
 658 }
 659
 660 static void print_request(struct seq_file *m,
 661                           struct drm_i915_gem_request *rq,
 662                           const char *prefix)
 663 {
 664         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 665                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 666                    rq->priotree.priority,
 667                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 668                    rq->timeline->common->name);
 669 }
 670
 671 static int i915_gem_request_info(struct seq_file *m, void *data)
 672 {
 673         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 674         struct drm_device *dev = &dev_priv->drm;
 675         struct drm_i915_gem_request *req;
 676         struct intel_engine_cs *engine;
 677         enum intel_engine_id id;
 678         int ret, any;
 679
 680         ret = mutex_lock_interruptible(&dev->struct_mutex);
 681         if (ret)
 682                 return ret;
 683
 684         any = 0;
 685         for_each_engine(engine, dev_priv, id) {
 686                 int count;
 687
 688                 count = 0;
 689                 list_for_each_entry(req, &engine->timeline->requests, link)
 690                         count++;
 691                 if (count == 0)
 692                         continue;
 693
 694                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 695                 list_for_each_entry(req, &engine->timeline->requests, link)
 696                         print_request(m, req, "    ");
 697
 698                 any++;
 699         }
 700         mutex_unlock(&dev->struct_mutex);
 701
 702         if (any == 0)
 703                 seq_puts(m, "No requests\n");
 704
 705         return 0;
 706 }
 707
 708 static void i915_ring_seqno_info(struct seq_file *m,
 709                                  struct intel_engine_cs *engine)
 710 {
 711         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 712         struct rb_node *rb;
 713
 714         seq_printf(m, "Current sequence (%s): %x\n",
 715                    engine->name, intel_engine_get_seqno(engine));
 716
 717         spin_lock_irq(&b->rb_lock);
 718         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 719                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
 720
 721                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 722                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 723         }
 724         spin_unlock_irq(&b->rb_lock);
 725 }
 726
 727 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 728 {
 729         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 730         struct intel_engine_cs *engine;
 731         enum intel_engine_id id;
 732
 733         for_each_engine(engine, dev_priv, id)
 734                 i915_ring_seqno_info(m, engine);
 735
 736         return 0;
 737 }
 738
 739
 740 static int i915_interrupt_info(struct seq_file *m, void *data)
 741 {
 742         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 743         struct intel_engine_cs *engine;
 744         enum intel_engine_id id;
 745         int i, pipe;
 746
 747         intel_runtime_pm_get(dev_priv);
 748
 749         if (IS_CHERRYVIEW(dev_priv)) {
 750                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 751                            I915_READ(GEN8_MASTER_IRQ));
 752
 753                 seq_printf(m, "Display IER:\t%08x\n",
 754                            I915_READ(VLV_IER));
 755                 seq_printf(m, "Display IIR:\t%08x\n",
 756                            I915_READ(VLV_IIR));
 757                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 758                            I915_READ(VLV_IIR_RW));
 759                 seq_printf(m, "Display IMR:\t%08x\n",
 760                            I915_READ(VLV_IMR));
 761                 for_each_pipe(dev_priv, pipe) {
 762                         enum intel_display_power_domain power_domain;
 763
 764                         power_domain = POWER_DOMAIN_PIPE(pipe);
 765                         if (!intel_display_power_get_if_enabled(dev_priv,
 766                                                                 power_domain)) {
 767                                 seq_printf(m, "Pipe %c power disabled\n",
 768                                            pipe_name(pipe));
 769                                 continue;
 770                         }
 771
 772                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 773                                    pipe_name(pipe),
 774                                    I915_READ(PIPESTAT(pipe)));
 775
 776                         intel_display_power_put(dev_priv, power_domain);
 777                 }
 778
 779                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 780                 seq_printf(m, "Port hotplug:\t%08x\n",
 781                            I915_READ(PORT_HOTPLUG_EN));
 782                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 783                            I915_READ(VLV_DPFLIPSTAT));
 784                 seq_printf(m, "DPINVGTT:\t%08x\n",
 785                            I915_READ(DPINVGTT));
 786                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 787
 788                 for (i = 0; i < 4; i++) {
 789                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 790                                    i, I915_READ(GEN8_GT_IMR(i)));
 791                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 792                                    i, I915_READ(GEN8_GT_IIR(i)));
 793                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 794                                    i, I915_READ(GEN8_GT_IER(i)));
 795                 }
 796
 797                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_PCU_IMR));
 799                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_PCU_IIR));
 801                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_PCU_IER));
 803         } else if (INTEL_GEN(dev_priv) >= 8) {
 804                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 805                            I915_READ(GEN8_MASTER_IRQ));
 806
 807                 for (i = 0; i < 4; i++) {
 808                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 809                                    i, I915_READ(GEN8_GT_IMR(i)));
 810                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 811                                    i, I915_READ(GEN8_GT_IIR(i)));
 812                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 813                                    i, I915_READ(GEN8_GT_IER(i)));
 814                 }
 815
 816                 for_each_pipe(dev_priv, pipe) {
 817                         enum intel_display_power_domain power_domain;
 818
 819                         power_domain = POWER_DOMAIN_PIPE(pipe);
 820                         if (!intel_display_power_get_if_enabled(dev_priv,
 821                                                                 power_domain)) {
 822                                 seq_printf(m, "Pipe %c power disabled\n",
 823                                            pipe_name(pipe));
 824                                 continue;
 825                         }
 826                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 827                                    pipe_name(pipe),
 828                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 829                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 830                                    pipe_name(pipe),
 831                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 832                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 833                                    pipe_name(pipe),
 834                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 835
 836                         intel_display_power_put(dev_priv, power_domain);
 837                 }
 838
 839                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 840                            I915_READ(GEN8_DE_PORT_IMR));
 841                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 842                            I915_READ(GEN8_DE_PORT_IIR));
 843                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 844                            I915_READ(GEN8_DE_PORT_IER));
 845
 846                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 847                            I915_READ(GEN8_DE_MISC_IMR));
 848                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 849                            I915_READ(GEN8_DE_MISC_IIR));
 850                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 851                            I915_READ(GEN8_DE_MISC_IER));
 852
 853                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 854                            I915_READ(GEN8_PCU_IMR));
 855                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 856                            I915_READ(GEN8_PCU_IIR));
 857                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 858                            I915_READ(GEN8_PCU_IER));
 859         } else if (IS_VALLEYVIEW(dev_priv)) {
 860                 seq_printf(m, "Display IER:\t%08x\n",
 861                            I915_READ(VLV_IER));
 862                 seq_printf(m, "Display IIR:\t%08x\n",
 863                            I915_READ(VLV_IIR));
 864                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 865                            I915_READ(VLV_IIR_RW));
 866                 seq_printf(m, "Display IMR:\t%08x\n",
 867                            I915_READ(VLV_IMR));
 868                 for_each_pipe(dev_priv, pipe) {
 869                         enum intel_display_power_domain power_domain;
 870
 871                         power_domain = POWER_DOMAIN_PIPE(pipe);
 872                         if (!intel_display_power_get_if_enabled(dev_priv,
 873                                                                 power_domain)) {
 874                                 seq_printf(m, "Pipe %c power disabled\n",
 875                                            pipe_name(pipe));
 876                                 continue;
 877                         }
 878
 879                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 880                                    pipe_name(pipe),
 881                                    I915_READ(PIPESTAT(pipe)));
 882                         intel_display_power_put(dev_priv, power_domain);
 883                 }
 884
 885                 seq_printf(m, "Master IER:\t%08x\n",
 886                            I915_READ(VLV_MASTER_IER));
 887
 888                 seq_printf(m, "Render IER:\t%08x\n",
 889                            I915_READ(GTIER));
 890                 seq_printf(m, "Render IIR:\t%08x\n",
 891                            I915_READ(GTIIR));
 892                 seq_printf(m, "Render IMR:\t%08x\n",
 893                            I915_READ(GTIMR));
 894
 895                 seq_printf(m, "PM IER:\t\t%08x\n",
 896                            I915_READ(GEN6_PMIER));
 897                 seq_printf(m, "PM IIR:\t\t%08x\n",
 898                            I915_READ(GEN6_PMIIR));
 899                 seq_printf(m, "PM IMR:\t\t%08x\n",
 900                            I915_READ(GEN6_PMIMR));
 901
 902                 seq_printf(m, "Port hotplug:\t%08x\n",
 903                            I915_READ(PORT_HOTPLUG_EN));
 904                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 905                            I915_READ(VLV_DPFLIPSTAT));
 906                 seq_printf(m, "DPINVGTT:\t%08x\n",
 907                            I915_READ(DPINVGTT));
 908
 909         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 910                 seq_printf(m, "Interrupt enable:    %08x\n",
 911                            I915_READ(IER));
 912                 seq_printf(m, "Interrupt identity:  %08x\n",
 913                            I915_READ(IIR));
 914                 seq_printf(m, "Interrupt mask:      %08x\n",
 915                            I915_READ(IMR));
 916                 for_each_pipe(dev_priv, pipe)
 917                         seq_printf(m, "Pipe %c stat:         %08x\n",
 918                                    pipe_name(pipe),
 919                                    I915_READ(PIPESTAT(pipe)));
 920         } else {
 921                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 922                            I915_READ(DEIER));
 923                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 924                            I915_READ(DEIIR));
 925                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 926                            I915_READ(DEIMR));
 927                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 928                            I915_READ(SDEIER));
 929                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 930                            I915_READ(SDEIIR));
 931                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 932                            I915_READ(SDEIMR));
 933                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 934                            I915_READ(GTIER));
 935                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 936                            I915_READ(GTIIR));
 937                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 938                            I915_READ(GTIMR));
 939         }
 940         for_each_engine(engine, dev_priv, id) {
 941                 if (INTEL_GEN(dev_priv) >= 6) {
 942                         seq_printf(m,
 943                                    "Graphics Interrupt mask (%s):       %08x\n",
 944                                    engine->name, I915_READ_IMR(engine));
 945                 }
 946                 i915_ring_seqno_info(m, engine);
 947         }
 948         intel_runtime_pm_put(dev_priv);
 949
 950         return 0;
 951 }
 952
 953 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 954 {
 955         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 956         struct drm_device *dev = &dev_priv->drm;
 957         int i, ret;
 958
 959         ret = mutex_lock_interruptible(&dev->struct_mutex);
 960         if (ret)
 961                 return ret;
 962
 963         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 964         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 965                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 966
 967                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 968                            i, dev_priv->fence_regs[i].pin_count);
 969                 if (!vma)
 970                         seq_puts(m, "unused");
 971                 else
 972                         describe_obj(m, vma->obj);
 973                 seq_putc(m, '\n');
 974         }
 975
 976         mutex_unlock(&dev->struct_mutex);
 977         return 0;
 978 }
 979
 980 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 981 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 982                               size_t count, loff_t *pos)
 983 {
 984         struct i915_gpu_state *error = file->private_data;
 985         struct drm_i915_error_state_buf str;
 986         ssize_t ret;
 987         loff_t tmp;
 988
 989         if (!error)
 990                 return 0;
 991
 992         ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
 993         if (ret)
 994                 return ret;
 995
 996         ret = i915_error_state_to_str(&str, error);
 997         if (ret)
 998                 goto out;
 999
1000         tmp = 0;
1001         ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
1002         if (ret < 0)
1003                 goto out;
1004
1005         *pos = str.start + ret;
1006 out:
1007         i915_error_state_buf_release(&str);
1008         return ret;
1009 }
1010
1011 static int gpu_state_release(struct inode *inode, struct file *file)
1012 {
1013         i915_gpu_state_put(file->private_data);
1014         return 0;
1015 }
1016
1017 static int i915_gpu_info_open(struct inode *inode, struct file *file)
1018 {
1019         struct drm_i915_private *i915 = inode->i_private;
1020         struct i915_gpu_state *gpu;
1021
1022         intel_runtime_pm_get(i915);
1023         gpu = i915_capture_gpu_state(i915);
1024         intel_runtime_pm_put(i915);
1025         if (!gpu)
1026                 return -ENOMEM;
1027
1028         file->private_data = gpu;
1029         return 0;
1030 }
1031
1032 static const struct file_operations i915_gpu_info_fops = {
1033         .owner = THIS_MODULE,
1034         .open = i915_gpu_info_open,
1035         .read = gpu_state_read,
1036         .llseek = default_llseek,
1037         .release = gpu_state_release,
1038 };
1039
1040 static ssize_t
1041 i915_error_state_write(struct file *filp,
1042                        const char __user *ubuf,
1043                        size_t cnt,
1044                        loff_t *ppos)
1045 {
1046         struct i915_gpu_state *error = filp->private_data;
1047
1048         if (!error)
1049                 return 0;
1050
1051         DRM_DEBUG_DRIVER("Resetting error state\n");
1052         i915_reset_error_state(error->i915);
1053
1054         return cnt;
1055 }
1056
1057 static int i915_error_state_open(struct inode *inode, struct file *file)
1058 {
1059         file->private_data = i915_first_error_state(inode->i_private);
1060         return 0;
1061 }
1062
1063 static const struct file_operations i915_error_state_fops = {
1064         .owner = THIS_MODULE,
1065         .open = i915_error_state_open,
1066         .read = gpu_state_read,
1067         .write = i915_error_state_write,
1068         .llseek = default_llseek,
1069         .release = gpu_state_release,
1070 };
1071 #endif
1072
1073 static int
1074 i915_next_seqno_set(void *data, u64 val)
1075 {
1076         struct drm_i915_private *dev_priv = data;
1077         struct drm_device *dev = &dev_priv->drm;
1078         int ret;
1079
1080         ret = mutex_lock_interruptible(&dev->struct_mutex);
1081         if (ret)
1082                 return ret;
1083
1084         ret = i915_gem_set_global_seqno(dev, val);
1085         mutex_unlock(&dev->struct_mutex);
1086
1087         return ret;
1088 }
1089
1090 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1091                         NULL, i915_next_seqno_set,
1092                         "0x%llx\n");
1093
1094 static int i915_frequency_info(struct seq_file *m, void *unused)
1095 {
1096         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1097         int ret = 0;
1098
1099         intel_runtime_pm_get(dev_priv);
1100
1101         if (IS_GEN5(dev_priv)) {
1102                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1103                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1104
1105                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1106                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1107                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1108                            MEMSTAT_VID_SHIFT);
1109                 seq_printf(m, "Current P-state: %d\n",
1110                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1111         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1112                 u32 freq_sts;
1113
1114                 mutex_lock(&dev_priv->rps.hw_lock);
1115                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1116                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1117                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1118
1119                 seq_printf(m, "actual GPU freq: %d MHz\n",
1120                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1121
1122                 seq_printf(m, "current GPU freq: %d MHz\n",
1123                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1124
1125                 seq_printf(m, "max GPU freq: %d MHz\n",
1126                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1127
1128                 seq_printf(m, "min GPU freq: %d MHz\n",
1129                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1130
1131                 seq_printf(m, "idle GPU freq: %d MHz\n",
1132                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1133
1134                 seq_printf(m,
1135                            "efficient (RPe) frequency: %d MHz\n",
1136                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1137                 mutex_unlock(&dev_priv->rps.hw_lock);
1138         } else if (INTEL_GEN(dev_priv) >= 6) {
1139                 u32 rp_state_limits;
1140                 u32 gt_perf_status;
1141                 u32 rp_state_cap;
1142                 u32 rpmodectl, rpinclimit, rpdeclimit;
1143                 u32 rpstat, cagf, reqf;
1144                 u32 rpupei, rpcurup, rpprevup;
1145                 u32 rpdownei, rpcurdown, rpprevdown;
1146                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1147                 int max_freq;
1148
1149                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1150                 if (IS_GEN9_LP(dev_priv)) {
1151                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1152                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1153                 } else {
1154                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1155                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1156                 }
1157
1158                 /* RPSTAT1 is in the GT power well */
1159                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1160
1161                 reqf = I915_READ(GEN6_RPNSWREQ);
1162                 if (IS_GEN9(dev_priv))
1163                         reqf >>= 23;
1164                 else {
1165                         reqf &= ~GEN6_TURBO_DISABLE;
1166                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1167                                 reqf >>= 24;
1168                         else
1169                                 reqf >>= 25;
1170                 }
1171                 reqf = intel_gpu_freq(dev_priv, reqf);
1172
1173                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1174                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1175                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1176
1177                 rpstat = I915_READ(GEN6_RPSTAT1);
1178                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1179                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1180                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1181                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1182                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1183                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1184                 if (IS_GEN9(dev_priv))
1185                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1186                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1187                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1188                 else
1189                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1190                 cagf = intel_gpu_freq(dev_priv, cagf);
1191
1192                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1193
1194                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1195                         pm_ier = I915_READ(GEN6_PMIER);
1196                         pm_imr = I915_READ(GEN6_PMIMR);
1197                         pm_isr = I915_READ(GEN6_PMISR);
1198                         pm_iir = I915_READ(GEN6_PMIIR);
1199                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1200                 } else {
1201                         pm_ier = I915_READ(GEN8_GT_IER(2));
1202                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1203                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1204                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1205                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1206                 }
1207                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1208                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1209                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
1210                            dev_priv->rps.pm_intrmsk_mbz);
1211                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1212                 seq_printf(m, "Render p-state ratio: %d\n",
1213                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1214                 seq_printf(m, "Render p-state VID: %d\n",
1215                            gt_perf_status & 0xff);
1216                 seq_printf(m, "Render p-state limit: %d\n",
1217                            rp_state_limits & 0xff);
1218                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1219                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1220                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1221                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1222                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1223                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1224                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1225                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1226                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1227                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1228                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1229                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1230                 seq_printf(m, "Up threshold: %d%%\n",
1231                            dev_priv->rps.up_threshold);
1232
1233                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1234                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1235                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1236                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1237                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1238                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1239                 seq_printf(m, "Down threshold: %d%%\n",
1240                            dev_priv->rps.down_threshold);
1241
1242                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
1243                             rp_state_cap >> 16) & 0xff;
1244                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1245                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1246                            intel_gpu_freq(dev_priv, max_freq));
1247
1248                 max_freq = (rp_state_cap & 0xff00) >> 8;
1249                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1250                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1251                            intel_gpu_freq(dev_priv, max_freq));
1252
1253                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
1254                             rp_state_cap >> 0) & 0xff;
1255                 max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
1256                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1257                            intel_gpu_freq(dev_priv, max_freq));
1258                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1260
1261                 seq_printf(m, "Current freq: %d MHz\n",
1262                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1263                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1264                 seq_printf(m, "Idle freq: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1266                 seq_printf(m, "Min freq: %d MHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1268                 seq_printf(m, "Boost freq: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1270                 seq_printf(m, "Max freq: %d MHz\n",
1271                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1272                 seq_printf(m,
1273                            "efficient (RPe) frequency: %d MHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1275         } else {
1276                 seq_puts(m, "no P-state info available\n");
1277         }
1278
1279         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1280         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1281         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1282
1283         intel_runtime_pm_put(dev_priv);
1284         return ret;
1285 }
1286
1287 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1288                                struct seq_file *m,
1289                                struct intel_instdone *instdone)
1290 {
1291         int slice;
1292         int subslice;
1293
1294         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1295                    instdone->instdone);
1296
1297         if (INTEL_GEN(dev_priv) <= 3)
1298                 return;
1299
1300         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1301                    instdone->slice_common);
1302
1303         if (INTEL_GEN(dev_priv) <= 6)
1304                 return;
1305
1306         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1307                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1308                            slice, subslice, instdone->sampler[slice][subslice]);
1309
1310         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1311                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1312                            slice, subslice, instdone->row[slice][subslice]);
1313 }
1314
1315 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1316 {
1317         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1318         struct intel_engine_cs *engine;
1319         u64 acthd[I915_NUM_ENGINES];
1320         u32 seqno[I915_NUM_ENGINES];
1321         struct intel_instdone instdone;
1322         enum intel_engine_id id;
1323
1324         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1325                 seq_puts(m, "Wedged\n");
1326         if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
1327                 seq_puts(m, "Reset in progress: struct_mutex backoff\n");
1328         if (test_bit(I915_RESET_HANDOFF, &dev_priv->gpu_error.flags))
1329                 seq_puts(m, "Reset in progress: reset handoff to waiter\n");
1330         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1331                 seq_puts(m, "Waiter holding struct mutex\n");
1332         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1333                 seq_puts(m, "struct_mutex blocked for reset\n");
1334
1335         if (!i915.enable_hangcheck) {
1336                 seq_puts(m, "Hangcheck disabled\n");
1337                 return 0;
1338         }
1339
1340         intel_runtime_pm_get(dev_priv);
1341
1342         for_each_engine(engine, dev_priv, id) {
1343                 acthd[id] = intel_engine_get_active_head(engine);
1344                 seqno[id] = intel_engine_get_seqno(engine);
1345         }
1346
1347         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1348
1349         intel_runtime_pm_put(dev_priv);
1350
1351         if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
1352                 seq_printf(m, "Hangcheck active, timer fires in %dms\n",
1353                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1354                                             jiffies));
1355         else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
1356                 seq_puts(m, "Hangcheck active, work pending\n");
1357         else
1358                 seq_puts(m, "Hangcheck inactive\n");
1359
1360         seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
1361
1362         for_each_engine(engine, dev_priv, id) {
1363                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1364                 struct rb_node *rb;
1365
1366                 seq_printf(m, "%s:\n", engine->name);
1367                 seq_printf(m, "\tseqno = %x [current %x, last %x], inflight %d\n",
1368                            engine->hangcheck.seqno, seqno[id],
1369                            intel_engine_last_submit(engine),
1370                            engine->timeline->inflight_seqnos);
1371                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1372                            yesno(intel_engine_has_waiter(engine)),
1373                            yesno(test_bit(engine->id,
1374                                           &dev_priv->gpu_error.missed_irq_rings)),
1375                            yesno(engine->hangcheck.stalled));
1376
1377                 spin_lock_irq(&b->rb_lock);
1378                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1379                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1380
1381                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1382                                    w->tsk->comm, w->tsk->pid, w->seqno);
1383                 }
1384                 spin_unlock_irq(&b->rb_lock);
1385
1386                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1387                            (long long)engine->hangcheck.acthd,
1388                            (long long)acthd[id]);
1389                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1390                            hangcheck_action_to_str(engine->hangcheck.action),
1391                            engine->hangcheck.action,
1392                            jiffies_to_msecs(jiffies -
1393                                             engine->hangcheck.action_timestamp));
1394
1395                 if (engine->id == RCS) {
1396                         seq_puts(m, "\tinstdone read =\n");
1397
1398                         i915_instdone_info(dev_priv, m, &instdone);
1399
1400                         seq_puts(m, "\tinstdone accu =\n");
1401
1402                         i915_instdone_info(dev_priv, m,
1403                                            &engine->hangcheck.instdone);
1404                 }
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int ironlake_drpc_info(struct seq_file *m)
1411 {
1412         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1413         u32 rgvmodectl, rstdbyctl;
1414         u16 crstandvid;
1415
1416         rgvmodectl = I915_READ(MEMMODECTL);
1417         rstdbyctl = I915_READ(RSTDBYCTL);
1418         crstandvid = I915_READ16(CRSTANDVID);
1419
1420         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1421         seq_printf(m, "Boost freq: %d\n",
1422                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1423                    MEMMODE_BOOST_FREQ_SHIFT);
1424         seq_printf(m, "HW control enabled: %s\n",
1425                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1426         seq_printf(m, "SW control enabled: %s\n",
1427                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1428         seq_printf(m, "Gated voltage change: %s\n",
1429                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1430         seq_printf(m, "Starting frequency: P%d\n",
1431                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1432         seq_printf(m, "Max P-state: P%d\n",
1433                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1434         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1435         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1436         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1437         seq_printf(m, "Render standby enabled: %s\n",
1438                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1439         seq_puts(m, "Current RS state: ");
1440         switch (rstdbyctl & RSX_STATUS_MASK) {
1441         case RSX_STATUS_ON:
1442                 seq_puts(m, "on\n");
1443                 break;
1444         case RSX_STATUS_RC1:
1445                 seq_puts(m, "RC1\n");
1446                 break;
1447         case RSX_STATUS_RC1E:
1448                 seq_puts(m, "RC1E\n");
1449                 break;
1450         case RSX_STATUS_RS1:
1451                 seq_puts(m, "RS1\n");
1452                 break;
1453         case RSX_STATUS_RS2:
1454                 seq_puts(m, "RS2 (RC6)\n");
1455                 break;
1456         case RSX_STATUS_RS3:
1457                 seq_puts(m, "RC3 (RC6+)\n");
1458                 break;
1459         default:
1460                 seq_puts(m, "unknown\n");
1461                 break;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int i915_forcewake_domains(struct seq_file *m, void *data)
1468 {
1469         struct drm_i915_private *i915 = node_to_i915(m->private);
1470         struct intel_uncore_forcewake_domain *fw_domain;
1471         unsigned int tmp;
1472
1473         for_each_fw_domain(fw_domain, i915, tmp)
1474                 seq_printf(m, "%s.wake_count = %u\n",
1475                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1476                            READ_ONCE(fw_domain->wake_count));
1477
1478         return 0;
1479 }
1480
1481 static void print_rc6_res(struct seq_file *m,
1482                           const char *title,
1483                           const i915_reg_t reg)
1484 {
1485         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1486
1487         seq_printf(m, "%s %u (%llu us)\n",
1488                    title, I915_READ(reg),
1489                    intel_rc6_residency_us(dev_priv, reg));
1490 }
1491
1492 static int vlv_drpc_info(struct seq_file *m)
1493 {
1494         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1495         u32 rpmodectl1, rcctl1, pw_status;
1496
1497         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1498         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1499         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1500
1501         seq_printf(m, "Video Turbo Mode: %s\n",
1502                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1503         seq_printf(m, "Turbo enabled: %s\n",
1504                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1505         seq_printf(m, "HW control enabled: %s\n",
1506                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1507         seq_printf(m, "SW control enabled: %s\n",
1508                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1509                           GEN6_RP_MEDIA_SW_MODE));
1510         seq_printf(m, "RC6 Enabled: %s\n",
1511                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1512                                         GEN6_RC_CTL_EI_MODE(1))));
1513         seq_printf(m, "Render Power Well: %s\n",
1514                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1515         seq_printf(m, "Media Power Well: %s\n",
1516                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1517
1518         print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
1519         print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
1520
1521         return i915_forcewake_domains(m, NULL);
1522 }
1523
1524 static int gen6_drpc_info(struct seq_file *m)
1525 {
1526         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1527         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1528         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1529         unsigned forcewake_count;
1530         int count = 0;
1531
1532         forcewake_count = READ_ONCE(dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count);
1533         if (forcewake_count) {
1534                 seq_puts(m, "RC information inaccurate because somebody "
1535                             "holds a forcewake reference \n");
1536         } else {
1537                 /* NB: we cannot use forcewake, else we read the wrong values */
1538                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1539                         udelay(10);
1540                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1541         }
1542
1543         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1544         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1545
1546         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1547         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1548         if (INTEL_GEN(dev_priv) >= 9) {
1549                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1550                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1551         }
1552
1553         mutex_lock(&dev_priv->rps.hw_lock);
1554         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1555         mutex_unlock(&dev_priv->rps.hw_lock);
1556
1557         seq_printf(m, "Video Turbo Mode: %s\n",
1558                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1559         seq_printf(m, "HW control enabled: %s\n",
1560                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1561         seq_printf(m, "SW control enabled: %s\n",
1562                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1563                           GEN6_RP_MEDIA_SW_MODE));
1564         seq_printf(m, "RC1e Enabled: %s\n",
1565                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1566         seq_printf(m, "RC6 Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1568         if (INTEL_GEN(dev_priv) >= 9) {
1569                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1570                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1571                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1572                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1573         }
1574         seq_printf(m, "Deep RC6 Enabled: %s\n",
1575                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1576         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1577                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1578         seq_puts(m, "Current RC state: ");
1579         switch (gt_core_status & GEN6_RCn_MASK) {
1580         case GEN6_RC0:
1581                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1582                         seq_puts(m, "Core Power Down\n");
1583                 else
1584                         seq_puts(m, "on\n");
1585                 break;
1586         case GEN6_RC3:
1587                 seq_puts(m, "RC3\n");
1588                 break;
1589         case GEN6_RC6:
1590                 seq_puts(m, "RC6\n");
1591                 break;
1592         case GEN6_RC7:
1593                 seq_puts(m, "RC7\n");
1594                 break;
1595         default:
1596                 seq_puts(m, "Unknown\n");
1597                 break;
1598         }
1599
1600         seq_printf(m, "Core Power Down: %s\n",
1601                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1602         if (INTEL_GEN(dev_priv) >= 9) {
1603                 seq_printf(m, "Render Power Well: %s\n",
1604                         (gen9_powergate_status &
1605                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1606                 seq_printf(m, "Media Power Well: %s\n",
1607                         (gen9_powergate_status &
1608                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1609         }
1610
1611         /* Not exactly sure what this is */
1612         print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
1613                       GEN6_GT_GFX_RC6_LOCKED);
1614         print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
1615         print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
1616         print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
1617
1618         seq_printf(m, "RC6   voltage: %dmV\n",
1619                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1620         seq_printf(m, "RC6+  voltage: %dmV\n",
1621                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1622         seq_printf(m, "RC6++ voltage: %dmV\n",
1623                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1624         return i915_forcewake_domains(m, NULL);
1625 }
1626
1627 static int i915_drpc_info(struct seq_file *m, void *unused)
1628 {
1629         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1630         int err;
1631
1632         intel_runtime_pm_get(dev_priv);
1633
1634         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1635                 err = vlv_drpc_info(m);
1636         else if (INTEL_GEN(dev_priv) >= 6)
1637                 err = gen6_drpc_info(m);
1638         else
1639                 err = ironlake_drpc_info(m);
1640
1641         intel_runtime_pm_put(dev_priv);
1642
1643         return err;
1644 }
1645
1646 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1647 {
1648         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1649
1650         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1651                    dev_priv->fb_tracking.busy_bits);
1652
1653         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1654                    dev_priv->fb_tracking.flip_bits);
1655
1656         return 0;
1657 }
1658
1659 static int i915_fbc_status(struct seq_file *m, void *unused)
1660 {
1661         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1662
1663         if (!HAS_FBC(dev_priv)) {
1664                 seq_puts(m, "FBC unsupported on this chipset\n");
1665                 return 0;
1666         }
1667
1668         intel_runtime_pm_get(dev_priv);
1669         mutex_lock(&dev_priv->fbc.lock);
1670
1671         if (intel_fbc_is_active(dev_priv))
1672                 seq_puts(m, "FBC enabled\n");
1673         else
1674                 seq_printf(m, "FBC disabled: %s\n",
1675                            dev_priv->fbc.no_fbc_reason);
1676
1677         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1678                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1679                                 BDW_FBC_COMPRESSION_MASK :
1680                                 IVB_FBC_COMPRESSION_MASK;
1681                 seq_printf(m, "Compressing: %s\n",
1682                            yesno(I915_READ(FBC_STATUS2) & mask));
1683         }
1684
1685         mutex_unlock(&dev_priv->fbc.lock);
1686         intel_runtime_pm_put(dev_priv);
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_get(void *data, u64 *val)
1692 {
1693         struct drm_i915_private *dev_priv = data;
1694
1695         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1696                 return -ENODEV;
1697
1698         *val = dev_priv->fbc.false_color;
1699
1700         return 0;
1701 }
1702
1703 static int i915_fbc_fc_set(void *data, u64 val)
1704 {
1705         struct drm_i915_private *dev_priv = data;
1706         u32 reg;
1707
1708         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1709                 return -ENODEV;
1710
1711         mutex_lock(&dev_priv->fbc.lock);
1712
1713         reg = I915_READ(ILK_DPFC_CONTROL);
1714         dev_priv->fbc.false_color = val;
1715
1716         I915_WRITE(ILK_DPFC_CONTROL, val ?
1717                    (reg | FBC_CTL_FALSE_COLOR) :
1718                    (reg & ~FBC_CTL_FALSE_COLOR));
1719
1720         mutex_unlock(&dev_priv->fbc.lock);
1721         return 0;
1722 }
1723
1724 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1725                         i915_fbc_fc_get, i915_fbc_fc_set,
1726                         "%llu\n");
1727
1728 static int i915_ips_status(struct seq_file *m, void *unused)
1729 {
1730         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1731
1732         if (!HAS_IPS(dev_priv)) {
1733                 seq_puts(m, "not supported\n");
1734                 return 0;
1735         }
1736
1737         intel_runtime_pm_get(dev_priv);
1738
1739         seq_printf(m, "Enabled by kernel parameter: %s\n",
1740                    yesno(i915.enable_ips));
1741
1742         if (INTEL_GEN(dev_priv) >= 8) {
1743                 seq_puts(m, "Currently: unknown\n");
1744         } else {
1745                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1746                         seq_puts(m, "Currently: enabled\n");
1747                 else
1748                         seq_puts(m, "Currently: disabled\n");
1749         }
1750
1751         intel_runtime_pm_put(dev_priv);
1752
1753         return 0;
1754 }
1755
1756 static int i915_sr_status(struct seq_file *m, void *unused)
1757 {
1758         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1759         bool sr_enabled = false;
1760
1761         intel_runtime_pm_get(dev_priv);
1762         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1763
1764         if (INTEL_GEN(dev_priv) >= 9)
1765                 /* no global SR status; inspect per-plane WM */;
1766         else if (HAS_PCH_SPLIT(dev_priv))
1767                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1768         else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
1769                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1770                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1771         else if (IS_I915GM(dev_priv))
1772                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1773         else if (IS_PINEVIEW(dev_priv))
1774                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1775         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1776                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1777
1778         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1779         intel_runtime_pm_put(dev_priv);
1780
1781         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1782
1783         return 0;
1784 }
1785
1786 static int i915_emon_status(struct seq_file *m, void *unused)
1787 {
1788         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1789         struct drm_device *dev = &dev_priv->drm;
1790         unsigned long temp, chipset, gfx;
1791         int ret;
1792
1793         if (!IS_GEN5(dev_priv))
1794                 return -ENODEV;
1795
1796         ret = mutex_lock_interruptible(&dev->struct_mutex);
1797         if (ret)
1798                 return ret;
1799
1800         temp = i915_mch_val(dev_priv);
1801         chipset = i915_chipset_val(dev_priv);
1802         gfx = i915_gfx_val(dev_priv);
1803         mutex_unlock(&dev->struct_mutex);
1804
1805         seq_printf(m, "GMCH temp: %ld\n", temp);
1806         seq_printf(m, "Chipset power: %ld\n", chipset);
1807         seq_printf(m, "GFX power: %ld\n", gfx);
1808         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1809
1810         return 0;
1811 }
1812
1813 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1814 {
1815         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1816         int ret = 0;
1817         int gpu_freq, ia_freq;
1818         unsigned int max_gpu_freq, min_gpu_freq;
1819
1820         if (!HAS_LLC(dev_priv)) {
1821                 seq_puts(m, "unsupported on this chipset\n");
1822                 return 0;
1823         }
1824
1825         intel_runtime_pm_get(dev_priv);
1826
1827         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1828         if (ret)
1829                 goto out;
1830
1831         if (IS_GEN9_BC(dev_priv)) {
1832                 /* Convert GT frequency to 50 HZ units */
1833                 min_gpu_freq =
1834                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1835                 max_gpu_freq =
1836                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1837         } else {
1838                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1839                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1840         }
1841
1842         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1843
1844         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1845                 ia_freq = gpu_freq;
1846                 sandybridge_pcode_read(dev_priv,
1847                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1848                                        &ia_freq);
1849                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1850                            intel_gpu_freq(dev_priv, (gpu_freq *
1851                                                      (IS_GEN9_BC(dev_priv) ?
1852                                                       GEN9_FREQ_SCALER : 1))),
1853                            ((ia_freq >> 0) & 0xff) * 100,
1854                            ((ia_freq >> 8) & 0xff) * 100);
1855         }
1856
1857         mutex_unlock(&dev_priv->rps.hw_lock);
1858
1859 out:
1860         intel_runtime_pm_put(dev_priv);
1861         return ret;
1862 }
1863
1864 static int i915_opregion(struct seq_file *m, void *unused)
1865 {
1866         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1867         struct drm_device *dev = &dev_priv->drm;
1868         struct intel_opregion *opregion = &dev_priv->opregion;
1869         int ret;
1870
1871         ret = mutex_lock_interruptible(&dev->struct_mutex);
1872         if (ret)
1873                 goto out;
1874
1875         if (opregion->header)
1876                 seq_write(m, opregion->header, OPREGION_SIZE);
1877
1878         mutex_unlock(&dev->struct_mutex);
1879
1880 out:
1881         return 0;
1882 }
1883
1884 static int i915_vbt(struct seq_file *m, void *unused)
1885 {
1886         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1887
1888         if (opregion->vbt)
1889                 seq_write(m, opregion->vbt, opregion->vbt_size);
1890
1891         return 0;
1892 }
1893
1894 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1895 {
1896         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1897         struct drm_device *dev = &dev_priv->drm;
1898         struct intel_framebuffer *fbdev_fb = NULL;
1899         struct drm_framebuffer *drm_fb;
1900         int ret;
1901
1902         ret = mutex_lock_interruptible(&dev->struct_mutex);
1903         if (ret)
1904                 return ret;
1905
1906 #ifdef CONFIG_DRM_FBDEV_EMULATION
1907         if (dev_priv->fbdev) {
1908                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1909
1910                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1911                            fbdev_fb->base.width,
1912                            fbdev_fb->base.height,
1913                            fbdev_fb->base.format->depth,
1914                            fbdev_fb->base.format->cpp[0] * 8,
1915                            fbdev_fb->base.modifier,
1916                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1917                 describe_obj(m, fbdev_fb->obj);
1918                 seq_putc(m, '\n');
1919         }
1920 #endif
1921
1922         mutex_lock(&dev->mode_config.fb_lock);
1923         drm_for_each_fb(drm_fb, dev) {
1924                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1925                 if (fb == fbdev_fb)
1926                         continue;
1927
1928                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1929                            fb->base.width,
1930                            fb->base.height,
1931                            fb->base.format->depth,
1932                            fb->base.format->cpp[0] * 8,
1933                            fb->base.modifier,
1934                            drm_framebuffer_read_refcount(&fb->base));
1935                 describe_obj(m, fb->obj);
1936                 seq_putc(m, '\n');
1937         }
1938         mutex_unlock(&dev->mode_config.fb_lock);
1939         mutex_unlock(&dev->struct_mutex);
1940
1941         return 0;
1942 }
1943
1944 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1945 {
1946         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u)",
1947                    ring->space, ring->head, ring->tail);
1948 }
1949
1950 static int i915_context_status(struct seq_file *m, void *unused)
1951 {
1952         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1953         struct drm_device *dev = &dev_priv->drm;
1954         struct intel_engine_cs *engine;
1955         struct i915_gem_context *ctx;
1956         enum intel_engine_id id;
1957         int ret;
1958
1959         ret = mutex_lock_interruptible(&dev->struct_mutex);
1960         if (ret)
1961                 return ret;
1962
1963         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1964                 seq_printf(m, "HW context %u ", ctx->hw_id);
1965                 if (ctx->pid) {
1966                         struct task_struct *task;
1967
1968                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1969                         if (task) {
1970                                 seq_printf(m, "(%s [%d]) ",
1971                                            task->comm, task->pid);
1972                                 put_task_struct(task);
1973                         }
1974                 } else if (IS_ERR(ctx->file_priv)) {
1975                         seq_puts(m, "(deleted) ");
1976                 } else {
1977                         seq_puts(m, "(kernel) ");
1978                 }
1979
1980                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1981                 seq_putc(m, '\n');
1982
1983                 for_each_engine(engine, dev_priv, id) {
1984                         struct intel_context *ce = &ctx->engine[engine->id];
1985
1986                         seq_printf(m, "%s: ", engine->name);
1987                         seq_putc(m, ce->initialised ? 'I' : 'i');
1988                         if (ce->state)
1989                                 describe_obj(m, ce->state->obj);
1990                         if (ce->ring)
1991                                 describe_ctx_ring(m, ce->ring);
1992                         seq_putc(m, '\n');
1993                 }
1994
1995                 seq_putc(m, '\n');
1996         }
1997
1998         mutex_unlock(&dev->struct_mutex);
1999
2000         return 0;
2001 }
2002
2003 static void i915_dump_lrc_obj(struct seq_file *m,
2004                               struct i915_gem_context *ctx,
2005                               struct intel_engine_cs *engine)
2006 {
2007         struct i915_vma *vma = ctx->engine[engine->id].state;
2008         struct page *page;
2009         int j;
2010
2011         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2012
2013         if (!vma) {
2014                 seq_puts(m, "\tFake context\n");
2015                 return;
2016         }
2017
2018         if (vma->flags & I915_VMA_GLOBAL_BIND)
2019                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2020                            i915_ggtt_offset(vma));
2021
2022         if (i915_gem_object_pin_pages(vma->obj)) {
2023                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2024                 return;
2025         }
2026
2027         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2028         if (page) {
2029                 u32 *reg_state = kmap_atomic(page);
2030
2031                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2032                         seq_printf(m,
2033                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2034                                    j * 4,
2035                                    reg_state[j], reg_state[j + 1],
2036                                    reg_state[j + 2], reg_state[j + 3]);
2037                 }
2038                 kunmap_atomic(reg_state);
2039         }
2040
2041         i915_gem_object_unpin_pages(vma->obj);
2042         seq_putc(m, '\n');
2043 }
2044
2045 static int i915_dump_lrc(struct seq_file *m, void *unused)
2046 {
2047         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2048         struct drm_device *dev = &dev_priv->drm;
2049         struct intel_engine_cs *engine;
2050         struct i915_gem_context *ctx;
2051         enum intel_engine_id id;
2052         int ret;
2053
2054         if (!i915.enable_execlists) {
2055                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2056                 return 0;
2057         }
2058
2059         ret = mutex_lock_interruptible(&dev->struct_mutex);
2060         if (ret)
2061                 return ret;
2062
2063         list_for_each_entry(ctx, &dev_priv->context_list, link)
2064                 for_each_engine(engine, dev_priv, id)
2065                         i915_dump_lrc_obj(m, ctx, engine);
2066
2067         mutex_unlock(&dev->struct_mutex);
2068
2069         return 0;
2070 }
2071
2072 static const char *swizzle_string(unsigned swizzle)
2073 {
2074         switch (swizzle) {
2075         case I915_BIT_6_SWIZZLE_NONE:
2076                 return "none";
2077         case I915_BIT_6_SWIZZLE_9:
2078                 return "bit9";
2079         case I915_BIT_6_SWIZZLE_9_10:
2080                 return "bit9/bit10";
2081         case I915_BIT_6_SWIZZLE_9_11:
2082                 return "bit9/bit11";
2083         case I915_BIT_6_SWIZZLE_9_10_11:
2084                 return "bit9/bit10/bit11";
2085         case I915_BIT_6_SWIZZLE_9_17:
2086                 return "bit9/bit17";
2087         case I915_BIT_6_SWIZZLE_9_10_17:
2088                 return "bit9/bit10/bit17";
2089         case I915_BIT_6_SWIZZLE_UNKNOWN:
2090                 return "unknown";
2091         }
2092
2093         return "bug";
2094 }
2095
2096 static int i915_swizzle_info(struct seq_file *m, void *data)
2097 {
2098         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2099
2100         intel_runtime_pm_get(dev_priv);
2101
2102         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2103                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2104         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2105                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2106
2107         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2108                 seq_printf(m, "DDC = 0x%08x\n",
2109                            I915_READ(DCC));
2110                 seq_printf(m, "DDC2 = 0x%08x\n",
2111                            I915_READ(DCC2));
2112                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2113                            I915_READ16(C0DRB3));
2114                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2115                            I915_READ16(C1DRB3));
2116         } else if (INTEL_GEN(dev_priv) >= 6) {
2117                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2118                            I915_READ(MAD_DIMM_C0));
2119                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2120                            I915_READ(MAD_DIMM_C1));
2121                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2122                            I915_READ(MAD_DIMM_C2));
2123                 seq_printf(m, "TILECTL = 0x%08x\n",
2124                            I915_READ(TILECTL));
2125                 if (INTEL_GEN(dev_priv) >= 8)
2126                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2127                                    I915_READ(GAMTARBMODE));
2128                 else
2129                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2130                                    I915_READ(ARB_MODE));
2131                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2132                            I915_READ(DISP_ARB_CTL));
2133         }
2134
2135         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2136                 seq_puts(m, "L-shaped memory detected\n");
2137
2138         intel_runtime_pm_put(dev_priv);
2139
2140         return 0;
2141 }
2142
2143 static int per_file_ctx(int id, void *ptr, void *data)
2144 {
2145         struct i915_gem_context *ctx = ptr;
2146         struct seq_file *m = data;
2147         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2148
2149         if (!ppgtt) {
2150                 seq_printf(m, "  no ppgtt for context %d\n",
2151                            ctx->user_handle);
2152                 return 0;
2153         }
2154
2155         if (i915_gem_context_is_default(ctx))
2156                 seq_puts(m, "  default context:\n");
2157         else
2158                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2159         ppgtt->debug_dump(ppgtt, m);
2160
2161         return 0;
2162 }
2163
2164 static void gen8_ppgtt_info(struct seq_file *m,
2165                             struct drm_i915_private *dev_priv)
2166 {
2167         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2168         struct intel_engine_cs *engine;
2169         enum intel_engine_id id;
2170         int i;
2171
2172         if (!ppgtt)
2173                 return;
2174
2175         for_each_engine(engine, dev_priv, id) {
2176                 seq_printf(m, "%s\n", engine->name);
2177                 for (i = 0; i < 4; i++) {
2178                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2179                         pdp <<= 32;
2180                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2181                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2182                 }
2183         }
2184 }
2185
2186 static void gen6_ppgtt_info(struct seq_file *m,
2187                             struct drm_i915_private *dev_priv)
2188 {
2189         struct intel_engine_cs *engine;
2190         enum intel_engine_id id;
2191
2192         if (IS_GEN6(dev_priv))
2193                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2194
2195         for_each_engine(engine, dev_priv, id) {
2196                 seq_printf(m, "%s\n", engine->name);
2197                 if (IS_GEN7(dev_priv))
2198                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2199                                    I915_READ(RING_MODE_GEN7(engine)));
2200                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2201                            I915_READ(RING_PP_DIR_BASE(engine)));
2202                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2203                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2204                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2205                            I915_READ(RING_PP_DIR_DCLV(engine)));
2206         }
2207         if (dev_priv->mm.aliasing_ppgtt) {
2208                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2209
2210                 seq_puts(m, "aliasing PPGTT:\n");
2211                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2212
2213                 ppgtt->debug_dump(ppgtt, m);
2214         }
2215
2216         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2217 }
2218
2219 static int i915_ppgtt_info(struct seq_file *m, void *data)
2220 {
2221         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2222         struct drm_device *dev = &dev_priv->drm;
2223         struct drm_file *file;
2224         int ret;
2225
2226         mutex_lock(&dev->filelist_mutex);
2227         ret = mutex_lock_interruptible(&dev->struct_mutex);
2228         if (ret)
2229                 goto out_unlock;
2230
2231         intel_runtime_pm_get(dev_priv);
2232
2233         if (INTEL_GEN(dev_priv) >= 8)
2234                 gen8_ppgtt_info(m, dev_priv);
2235         else if (INTEL_GEN(dev_priv) >= 6)
2236                 gen6_ppgtt_info(m, dev_priv);
2237
2238         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2239                 struct drm_i915_file_private *file_priv = file->driver_priv;
2240                 struct task_struct *task;
2241
2242                 task = get_pid_task(file->pid, PIDTYPE_PID);
2243                 if (!task) {
2244                         ret = -ESRCH;
2245                         goto out_rpm;
2246                 }
2247                 seq_printf(m, "\nproc: %s\n", task->comm);
2248                 put_task_struct(task);
2249                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2250                              (void *)(unsigned long)m);
2251         }
2252
2253 out_rpm:
2254         intel_runtime_pm_put(dev_priv);
2255         mutex_unlock(&dev->struct_mutex);
2256 out_unlock:
2257         mutex_unlock(&dev->filelist_mutex);
2258         return ret;
2259 }
2260
2261 static int count_irq_waiters(struct drm_i915_private *i915)
2262 {
2263         struct intel_engine_cs *engine;
2264         enum intel_engine_id id;
2265         int count = 0;
2266
2267         for_each_engine(engine, i915, id)
2268                 count += intel_engine_has_waiter(engine);
2269
2270         return count;
2271 }
2272
2273 static const char *rps_power_to_str(unsigned int power)
2274 {
2275         static const char * const strings[] = {
2276                 [LOW_POWER] = "low power",
2277                 [BETWEEN] = "mixed",
2278                 [HIGH_POWER] = "high power",
2279         };
2280
2281         if (power >= ARRAY_SIZE(strings) || !strings[power])
2282                 return "unknown";
2283
2284         return strings[power];
2285 }
2286
2287 static int i915_rps_boost_info(struct seq_file *m, void *data)
2288 {
2289         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2290         struct drm_device *dev = &dev_priv->drm;
2291         struct drm_file *file;
2292
2293         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2294         seq_printf(m, "GPU busy? %s [%d requests]\n",
2295                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2296         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2297         seq_printf(m, "Frequency requested %d\n",
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2299         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2300                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2301                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2302                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2303                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2304         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2305                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2306                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2307                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2308
2309         mutex_lock(&dev->filelist_mutex);
2310         spin_lock(&dev_priv->rps.client_lock);
2311         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2312                 struct drm_i915_file_private *file_priv = file->driver_priv;
2313                 struct task_struct *task;
2314
2315                 rcu_read_lock();
2316                 task = pid_task(file->pid, PIDTYPE_PID);
2317                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2318                            task ? task->comm : "<unknown>",
2319                            task ? task->pid : -1,
2320                            file_priv->rps.boosts,
2321                            list_empty(&file_priv->rps.link) ? "" : ", active");
2322                 rcu_read_unlock();
2323         }
2324         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2325         spin_unlock(&dev_priv->rps.client_lock);
2326         mutex_unlock(&dev->filelist_mutex);
2327
2328         if (INTEL_GEN(dev_priv) >= 6 &&
2329             dev_priv->rps.enabled &&
2330             dev_priv->gt.active_requests) {
2331                 u32 rpup, rpupei;
2332                 u32 rpdown, rpdownei;
2333
2334                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2335                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2336                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2337                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2338                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2339                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2340
2341                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2342                            rps_power_to_str(dev_priv->rps.power));
2343                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2344                            rpup && rpupei ? 100 * rpup / rpupei : 0,
2345                            dev_priv->rps.up_threshold);
2346                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2347                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
2348                            dev_priv->rps.down_threshold);
2349         } else {
2350                 seq_puts(m, "\nRPS Autotuning inactive\n");
2351         }
2352
2353         return 0;
2354 }
2355
2356 static int i915_llc(struct seq_file *m, void *data)
2357 {
2358         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2359         const bool edram = INTEL_GEN(dev_priv) > 8;
2360
2361         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2362         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2363                    intel_uncore_edram_size(dev_priv)/1024/1024);
2364
2365         return 0;
2366 }
2367
2368 static int i915_huc_load_status_info(struct seq_file *m, void *data)
2369 {
2370         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2371         struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
2372
2373         if (!HAS_HUC_UCODE(dev_priv))
2374                 return 0;
2375
2376         seq_puts(m, "HuC firmware status:\n");
2377         seq_printf(m, "\tpath: %s\n", huc_fw->path);
2378         seq_printf(m, "\tfetch: %s\n",
2379                 intel_uc_fw_status_repr(huc_fw->fetch_status));
2380         seq_printf(m, "\tload: %s\n",
2381                 intel_uc_fw_status_repr(huc_fw->load_status));
2382         seq_printf(m, "\tversion wanted: %d.%d\n",
2383                 huc_fw->major_ver_wanted, huc_fw->minor_ver_wanted);
2384         seq_printf(m, "\tversion found: %d.%d\n",
2385                 huc_fw->major_ver_found, huc_fw->minor_ver_found);
2386         seq_printf(m, "\theader: offset is %d; size = %d\n",
2387                 huc_fw->header_offset, huc_fw->header_size);
2388         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2389                 huc_fw->ucode_offset, huc_fw->ucode_size);
2390         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2391                 huc_fw->rsa_offset, huc_fw->rsa_size);
2392
2393         intel_runtime_pm_get(dev_priv);
2394         seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
2395         intel_runtime_pm_put(dev_priv);
2396
2397         return 0;
2398 }
2399
2400 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2401 {
2402         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2403         struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
2404         u32 tmp, i;
2405
2406         if (!HAS_GUC_UCODE(dev_priv))
2407                 return 0;
2408
2409         seq_printf(m, "GuC firmware status:\n");
2410         seq_printf(m, "\tpath: %s\n",
2411                 guc_fw->path);
2412         seq_printf(m, "\tfetch: %s\n",
2413                 intel_uc_fw_status_repr(guc_fw->fetch_status));
2414         seq_printf(m, "\tload: %s\n",
2415                 intel_uc_fw_status_repr(guc_fw->load_status));
2416         seq_printf(m, "\tversion wanted: %d.%d\n",
2417                 guc_fw->major_ver_wanted, guc_fw->minor_ver_wanted);
2418         seq_printf(m, "\tversion found: %d.%d\n",
2419                 guc_fw->major_ver_found, guc_fw->minor_ver_found);
2420         seq_printf(m, "\theader: offset is %d; size = %d\n",
2421                 guc_fw->header_offset, guc_fw->header_size);
2422         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2423                 guc_fw->ucode_offset, guc_fw->ucode_size);
2424         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2425                 guc_fw->rsa_offset, guc_fw->rsa_size);
2426
2427         intel_runtime_pm_get(dev_priv);
2428
2429         tmp = I915_READ(GUC_STATUS);
2430
2431         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2432         seq_printf(m, "\tBootrom status = 0x%x\n",
2433                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2434         seq_printf(m, "\tuKernel status = 0x%x\n",
2435                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2436         seq_printf(m, "\tMIA Core status = 0x%x\n",
2437                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2438         seq_puts(m, "\nScratch registers:\n");
2439         for (i = 0; i < 16; i++)
2440                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2441
2442         intel_runtime_pm_put(dev_priv);
2443
2444         return 0;
2445 }
2446
2447 static void i915_guc_log_info(struct seq_file *m,
2448                               struct drm_i915_private *dev_priv)
2449 {
2450         struct intel_guc *guc = &dev_priv->guc;
2451
2452         seq_puts(m, "\nGuC logging stats:\n");
2453
2454         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2455                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2456                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2457
2458         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2459                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2460                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2461
2462         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2463                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2464                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2465
2466         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2467                    guc->log.flush_interrupt_count);
2468
2469         seq_printf(m, "\tCapture miss count: %u\n",
2470                    guc->log.capture_miss_count);
2471 }
2472
2473 static void i915_guc_client_info(struct seq_file *m,
2474                                  struct drm_i915_private *dev_priv,
2475                                  struct i915_guc_client *client)
2476 {
2477         struct intel_engine_cs *engine;
2478         enum intel_engine_id id;
2479         uint64_t tot = 0;
2480
2481         seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n",
2482                 client->priority, client->stage_id, client->proc_desc_offset);
2483         seq_printf(m, "\tDoorbell id %d, offset: 0x%lx, cookie 0x%x\n",
2484                 client->doorbell_id, client->doorbell_offset, client->doorbell_cookie);
2485         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2486                 client->wq_size, client->wq_offset, client->wq_tail);
2487
2488         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2489         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2490         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2491
2492         for_each_engine(engine, dev_priv, id) {
2493                 u64 submissions = client->submissions[id];
2494                 tot += submissions;
2495                 seq_printf(m, "\tSubmissions: %llu %s\n",
2496                                 submissions, engine->name);
2497         }
2498         seq_printf(m, "\tTotal: %llu\n", tot);
2499 }
2500
2501 static int i915_guc_info(struct seq_file *m, void *data)
2502 {
2503         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2504         const struct intel_guc *guc = &dev_priv->guc;
2505         struct intel_engine_cs *engine;
2506         enum intel_engine_id id;
2507         u64 total;
2508
2509         if (!guc->execbuf_client) {
2510                 seq_printf(m, "GuC submission %s\n",
2511                            HAS_GUC_SCHED(dev_priv) ?
2512                            "disabled" :
2513                            "not supported");
2514                 return 0;
2515         }
2516
2517         seq_printf(m, "Doorbell map:\n");
2518         seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
2519         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
2520
2521         seq_printf(m, "GuC total action count: %llu\n", guc->action_count);
2522         seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);
2523         seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);
2524         seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);
2525         seq_printf(m, "GuC last action error code: %d\n", guc->action_err);
2526
2527         total = 0;
2528         seq_printf(m, "\nGuC submissions:\n");
2529         for_each_engine(engine, dev_priv, id) {
2530                 u64 submissions = guc->submissions[id];
2531                 total += submissions;
2532                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2533                         engine->name, submissions, guc->last_seqno[id]);
2534         }
2535         seq_printf(m, "\t%s: %llu\n", "Total", total);
2536
2537         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
2538         i915_guc_client_info(m, dev_priv, guc->execbuf_client);
2539
2540         i915_guc_log_info(m, dev_priv);
2541
2542         /* Add more as required ... */
2543
2544         return 0;
2545 }
2546
2547 static int i915_guc_log_dump(struct seq_file *m, void *data)
2548 {
2549         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2550         struct drm_i915_gem_object *obj;
2551         int i = 0, pg;
2552
2553         if (!dev_priv->guc.log.vma)
2554                 return 0;
2555
2556         obj = dev_priv->guc.log.vma->obj;
2557         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2558                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2559
2560                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2561                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2562                                    *(log + i), *(log + i + 1),
2563                                    *(log + i + 2), *(log + i + 3));
2564
2565                 kunmap_atomic(log);
2566         }
2567
2568         seq_putc(m, '\n');
2569
2570         return 0;
2571 }
2572
2573 static int i915_guc_log_control_get(void *data, u64 *val)
2574 {
2575         struct drm_device *dev = data;
2576         struct drm_i915_private *dev_priv = to_i915(dev);
2577
2578         if (!dev_priv->guc.log.vma)
2579                 return -EINVAL;
2580
2581         *val = i915.guc_log_level;
2582
2583         return 0;
2584 }
2585
2586 static int i915_guc_log_control_set(void *data, u64 val)
2587 {
2588         struct drm_device *dev = data;
2589         struct drm_i915_private *dev_priv = to_i915(dev);
2590         int ret;
2591
2592         if (!dev_priv->guc.log.vma)
2593                 return -EINVAL;
2594
2595         ret = mutex_lock_interruptible(&dev->struct_mutex);
2596         if (ret)
2597                 return ret;
2598
2599         intel_runtime_pm_get(dev_priv);
2600         ret = i915_guc_log_control(dev_priv, val);
2601         intel_runtime_pm_put(dev_priv);
2602
2603         mutex_unlock(&dev->struct_mutex);
2604         return ret;
2605 }
2606
2607 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2608                         i915_guc_log_control_get, i915_guc_log_control_set,
2609                         "%lld\n");
2610
2611 static const char *psr2_live_status(u32 val)
2612 {
2613         static const char * const live_status[] = {
2614                 "IDLE",
2615                 "CAPTURE",
2616                 "CAPTURE_FS",
2617                 "SLEEP",
2618                 "BUFON_FW",
2619                 "ML_UP",
2620                 "SU_STANDBY",
2621                 "FAST_SLEEP",
2622                 "DEEP_SLEEP",
2623                 "BUF_ON",
2624                 "TG_ON"
2625         };
2626
2627         val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
2628         if (val < ARRAY_SIZE(live_status))
2629                 return live_status[val];
2630
2631         return "unknown";
2632 }
2633
2634 static int i915_edp_psr_status(struct seq_file *m, void *data)
2635 {
2636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2637         u32 psrperf = 0;
2638         u32 stat[3];
2639         enum pipe pipe;
2640         bool enabled = false;
2641
2642         if (!HAS_PSR(dev_priv)) {
2643                 seq_puts(m, "PSR not supported\n");
2644                 return 0;
2645         }
2646
2647         intel_runtime_pm_get(dev_priv);
2648
2649         mutex_lock(&dev_priv->psr.lock);
2650         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2651         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2652         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2653         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2654         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2655                    dev_priv->psr.busy_frontbuffer_bits);
2656         seq_printf(m, "Re-enable work scheduled: %s\n",
2657                    yesno(work_busy(&dev_priv->psr.work.work)));
2658
2659         if (HAS_DDI(dev_priv)) {
2660                 if (dev_priv->psr.psr2_support)
2661                         enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
2662                 else
2663                         enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2664         } else {
2665                 for_each_pipe(dev_priv, pipe) {
2666                         enum transcoder cpu_transcoder =
2667                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2668                         enum intel_display_power_domain power_domain;
2669
2670                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2671                         if (!intel_display_power_get_if_enabled(dev_priv,
2672                                                                 power_domain))
2673                                 continue;
2674
2675                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2676                                 VLV_EDP_PSR_CURR_STATE_MASK;
2677                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2678                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2679                                 enabled = true;
2680
2681                         intel_display_power_put(dev_priv, power_domain);
2682                 }
2683         }
2684
2685         seq_printf(m, "Main link in standby mode: %s\n",
2686                    yesno(dev_priv->psr.link_standby));
2687
2688         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2689
2690         if (!HAS_DDI(dev_priv))
2691                 for_each_pipe(dev_priv, pipe) {
2692                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2693                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2694                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2695                 }
2696         seq_puts(m, "\n");
2697
2698         /*
2699          * VLV/CHV PSR has no kind of performance counter
2700          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2701          */
2702         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2703                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2704                         EDP_PSR_PERF_CNT_MASK;
2705
2706                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2707         }
2708         if (dev_priv->psr.psr2_support) {
2709                 u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
2710
2711                 seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
2712                            psr2, psr2_live_status(psr2));
2713         }
2714         mutex_unlock(&dev_priv->psr.lock);
2715
2716         intel_runtime_pm_put(dev_priv);
2717         return 0;
2718 }
2719
2720 static int i915_sink_crc(struct seq_file *m, void *data)
2721 {
2722         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2723         struct drm_device *dev = &dev_priv->drm;
2724         struct intel_connector *connector;
2725         struct drm_connector_list_iter conn_iter;
2726         struct intel_dp *intel_dp = NULL;
2727         int ret;
2728         u8 crc[6];
2729
2730         drm_modeset_lock_all(dev);
2731         drm_connector_list_iter_begin(dev, &conn_iter);
2732         for_each_intel_connector_iter(connector, &conn_iter) {
2733                 struct drm_crtc *crtc;
2734
2735                 if (!connector->base.state->best_encoder)
2736                         continue;
2737
2738                 crtc = connector->base.state->crtc;
2739                 if (!crtc->state->active)
2740                         continue;
2741
2742                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2743                         continue;
2744
2745                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2746
2747                 ret = intel_dp_sink_crc(intel_dp, crc);
2748                 if (ret)
2749                         goto out;
2750
2751                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2752                            crc[0], crc[1], crc[2],
2753                            crc[3], crc[4], crc[5]);
2754                 goto out;
2755         }
2756         ret = -ENODEV;
2757 out:
2758         drm_connector_list_iter_end(&conn_iter);
2759         drm_modeset_unlock_all(dev);
2760         return ret;
2761 }
2762
2763 static int i915_energy_uJ(struct seq_file *m, void *data)
2764 {
2765         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2766         u64 power;
2767         u32 units;
2768
2769         if (INTEL_GEN(dev_priv) < 6)
2770                 return -ENODEV;
2771
2772         intel_runtime_pm_get(dev_priv);
2773
2774         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2775         power = (power & 0x1f00) >> 8;
2776         units = 1000000 / (1 << power); /* convert to uJ */
2777         power = I915_READ(MCH_SECP_NRG_STTS);
2778         power *= units;
2779
2780         intel_runtime_pm_put(dev_priv);
2781
2782         seq_printf(m, "%llu", (long long unsigned)power);
2783
2784         return 0;
2785 }
2786
2787 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2788 {
2789         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2790         struct pci_dev *pdev = dev_priv->drm.pdev;
2791
2792         if (!HAS_RUNTIME_PM(dev_priv))
2793                 seq_puts(m, "Runtime power management not supported\n");
2794
2795         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2796         seq_printf(m, "IRQs disabled: %s\n",
2797                    yesno(!intel_irqs_enabled(dev_priv)));
2798 #ifdef CONFIG_PM
2799         seq_printf(m, "Usage count: %d\n",
2800                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2801 #else
2802         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2803 #endif
2804         seq_printf(m, "PCI device power state: %s [%d]\n",
2805                    pci_power_name(pdev->current_state),
2806                    pdev->current_state);
2807
2808         return 0;
2809 }
2810
2811 static int i915_power_domain_info(struct seq_file *m, void *unused)
2812 {
2813         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2814         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2815         int i;
2816
2817         mutex_lock(&power_domains->lock);
2818
2819         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2820         for (i = 0; i < power_domains->power_well_count; i++) {
2821                 struct i915_power_well *power_well;
2822                 enum intel_display_power_domain power_domain;
2823
2824                 power_well = &power_domains->power_wells[i];
2825                 seq_printf(m, "%-25s %d\n", power_well->name,
2826                            power_well->count);
2827
2828                 for_each_power_domain(power_domain, power_well->domains)
2829                         seq_printf(m, "  %-23s %d\n",
2830                                  intel_display_power_domain_str(power_domain),
2831                                  power_domains->domain_use_count[power_domain]);
2832         }
2833
2834         mutex_unlock(&power_domains->lock);
2835
2836         return 0;
2837 }
2838
2839 static int i915_dmc_info(struct seq_file *m, void *unused)
2840 {
2841         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2842         struct intel_csr *csr;
2843
2844         if (!HAS_CSR(dev_priv)) {
2845                 seq_puts(m, "not supported\n");
2846                 return 0;
2847         }
2848
2849         csr = &dev_priv->csr;
2850
2851         intel_runtime_pm_get(dev_priv);
2852
2853         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2854         seq_printf(m, "path: %s\n", csr->fw_path);
2855
2856         if (!csr->dmc_payload)
2857                 goto out;
2858
2859         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2860                    CSR_VERSION_MINOR(csr->version));
2861
2862         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2863                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2864                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2865                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2866                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2867         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2868                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2869                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2870         }
2871
2872 out:
2873         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2874         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2875         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2876
2877         intel_runtime_pm_put(dev_priv);
2878
2879         return 0;
2880 }
2881
2882 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2883                                  struct drm_display_mode *mode)
2884 {
2885         int i;
2886
2887         for (i = 0; i < tabs; i++)
2888                 seq_putc(m, '\t');
2889
2890         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2891                    mode->base.id, mode->name,
2892                    mode->vrefresh, mode->clock,
2893                    mode->hdisplay, mode->hsync_start,
2894                    mode->hsync_end, mode->htotal,
2895                    mode->vdisplay, mode->vsync_start,
2896                    mode->vsync_end, mode->vtotal,
2897                    mode->type, mode->flags);
2898 }
2899
2900 static void intel_encoder_info(struct seq_file *m,
2901                                struct intel_crtc *intel_crtc,
2902                                struct intel_encoder *intel_encoder)
2903 {
2904         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2905         struct drm_device *dev = &dev_priv->drm;
2906         struct drm_crtc *crtc = &intel_crtc->base;
2907         struct intel_connector *intel_connector;
2908         struct drm_encoder *encoder;
2909
2910         encoder = &intel_encoder->base;
2911         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2912                    encoder->base.id, encoder->name);
2913         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2914                 struct drm_connector *connector = &intel_connector->base;
2915                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2916                            connector->base.id,
2917                            connector->name,
2918                            drm_get_connector_status_name(connector->status));
2919                 if (connector->status == connector_status_connected) {
2920                         struct drm_display_mode *mode = &crtc->mode;
2921                         seq_printf(m, ", mode:\n");
2922                         intel_seq_print_mode(m, 2, mode);
2923                 } else {
2924                         seq_putc(m, '\n');
2925                 }
2926         }
2927 }
2928
2929 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2930 {
2931         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2932         struct drm_device *dev = &dev_priv->drm;
2933         struct drm_crtc *crtc = &intel_crtc->base;
2934         struct intel_encoder *intel_encoder;
2935         struct drm_plane_state *plane_state = crtc->primary->state;
2936         struct drm_framebuffer *fb = plane_state->fb;
2937
2938         if (fb)
2939                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2940                            fb->base.id, plane_state->src_x >> 16,
2941                            plane_state->src_y >> 16, fb->width, fb->height);
2942         else
2943                 seq_puts(m, "\tprimary plane disabled\n");
2944         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2945                 intel_encoder_info(m, intel_crtc, intel_encoder);
2946 }
2947
2948 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2949 {
2950         struct drm_display_mode *mode = panel->fixed_mode;
2951
2952         seq_printf(m, "\tfixed mode:\n");
2953         intel_seq_print_mode(m, 2, mode);
2954 }
2955
2956 static void intel_dp_info(struct seq_file *m,
2957                           struct intel_connector *intel_connector)
2958 {
2959         struct intel_encoder *intel_encoder = intel_connector->encoder;
2960         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2961
2962         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2963         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2964         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2965                 intel_panel_info(m, &intel_connector->panel);
2966
2967         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2968                                 &intel_dp->aux);
2969 }
2970
2971 static void intel_dp_mst_info(struct seq_file *m,
2972                           struct intel_connector *intel_connector)
2973 {
2974         struct intel_encoder *intel_encoder = intel_connector->encoder;
2975         struct intel_dp_mst_encoder *intel_mst =
2976                 enc_to_mst(&intel_encoder->base);
2977         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2978         struct intel_dp *intel_dp = &intel_dig_port->dp;
2979         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2980                                         intel_connector->port);
2981
2982         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2983 }
2984
2985 static void intel_hdmi_info(struct seq_file *m,
2986                             struct intel_connector *intel_connector)
2987 {
2988         struct intel_encoder *intel_encoder = intel_connector->encoder;
2989         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2990
2991         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2992 }
2993
2994 static void intel_lvds_info(struct seq_file *m,
2995                             struct intel_connector *intel_connector)
2996 {
2997         intel_panel_info(m, &intel_connector->panel);
2998 }
2999
3000 static void intel_connector_info(struct seq_file *m,
3001                                  struct drm_connector *connector)
3002 {
3003         struct intel_connector *intel_connector = to_intel_connector(connector);
3004         struct intel_encoder *intel_encoder = intel_connector->encoder;
3005         struct drm_display_mode *mode;
3006
3007         seq_printf(m, "connector %d: type %s, status: %s\n",
3008                    connector->base.id, connector->name,
3009                    drm_get_connector_status_name(connector->status));
3010         if (connector->status == connector_status_connected) {
3011                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3012                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3013                            connector->display_info.width_mm,
3014                            connector->display_info.height_mm);
3015                 seq_printf(m, "\tsubpixel order: %s\n",
3016                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3017                 seq_printf(m, "\tCEA rev: %d\n",
3018                            connector->display_info.cea_rev);
3019         }
3020
3021         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3022                 return;
3023
3024         switch (connector->connector_type) {
3025         case DRM_MODE_CONNECTOR_DisplayPort:
3026         case DRM_MODE_CONNECTOR_eDP:
3027                 if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
3028                         intel_dp_mst_info(m, intel_connector);
3029                 else
3030                         intel_dp_info(m, intel_connector);
3031                 break;
3032         case DRM_MODE_CONNECTOR_LVDS:
3033                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3034                         intel_lvds_info(m, intel_connector);
3035                 break;
3036         case DRM_MODE_CONNECTOR_HDMIA:
3037                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3038                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3039                         intel_hdmi_info(m, intel_connector);
3040                 break;
3041         default:
3042                 break;
3043         }
3044
3045         seq_printf(m, "\tmodes:\n");
3046         list_for_each_entry(mode, &connector->modes, head)
3047                 intel_seq_print_mode(m, 2, mode);
3048 }
3049
3050 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
3051 {
3052         u32 state;
3053
3054         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
3055                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3056         else
3057                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3058
3059         return state;
3060 }
3061
3062 static bool cursor_position(struct drm_i915_private *dev_priv,
3063                             int pipe, int *x, int *y)
3064 {
3065         u32 pos;
3066
3067         pos = I915_READ(CURPOS(pipe));
3068
3069         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3070         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3071                 *x = -*x;
3072
3073         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3074         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3075                 *y = -*y;
3076
3077         return cursor_active(dev_priv, pipe);
3078 }
3079
3080 static const char *plane_type(enum drm_plane_type type)
3081 {
3082         switch (type) {
3083         case DRM_PLANE_TYPE_OVERLAY:
3084                 return "OVL";
3085         case DRM_PLANE_TYPE_PRIMARY:
3086                 return "PRI";
3087         case DRM_PLANE_TYPE_CURSOR:
3088                 return "CUR";
3089         /*
3090          * Deliberately omitting default: to generate compiler warnings
3091          * when a new drm_plane_type gets added.
3092          */
3093         }
3094
3095         return "unknown";
3096 }
3097
3098 static const char *plane_rotation(unsigned int rotation)
3099 {
3100         static char buf[48];
3101         /*
3102          * According to doc only one DRM_ROTATE_ is allowed but this
3103          * will print them all to visualize if the values are misused
3104          */
3105         snprintf(buf, sizeof(buf),
3106                  "%s%s%s%s%s%s(0x%08x)",
3107                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3108                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3109                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3110                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3111                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3112                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3113                  rotation);
3114
3115         return buf;
3116 }
3117
3118 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3119 {
3120         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3121         struct drm_device *dev = &dev_priv->drm;
3122         struct intel_plane *intel_plane;
3123
3124         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3125                 struct drm_plane_state *state;
3126                 struct drm_plane *plane = &intel_plane->base;
3127                 struct drm_format_name_buf format_name;
3128
3129                 if (!plane->state) {
3130                         seq_puts(m, "plane->state is NULL!\n");
3131                         continue;
3132                 }
3133
3134                 state = plane->state;
3135
3136                 if (state->fb) {
3137                         drm_get_format_name(state->fb->format->format,
3138                                             &format_name);
3139                 } else {
3140                         sprintf(format_name.str, "N/A");
3141                 }
3142
3143                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3144                            plane->base.id,
3145                            plane_type(intel_plane->base.type),
3146                            state->crtc_x, state->crtc_y,
3147                            state->crtc_w, state->crtc_h,
3148                            (state->src_x >> 16),
3149                            ((state->src_x & 0xffff) * 15625) >> 10,
3150                            (state->src_y >> 16),
3151                            ((state->src_y & 0xffff) * 15625) >> 10,
3152                            (state->src_w >> 16),
3153                            ((state->src_w & 0xffff) * 15625) >> 10,
3154                            (state->src_h >> 16),
3155                            ((state->src_h & 0xffff) * 15625) >> 10,
3156                            format_name.str,
3157                            plane_rotation(state->rotation));
3158         }
3159 }
3160
3161 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3162 {
3163         struct intel_crtc_state *pipe_config;
3164         int num_scalers = intel_crtc->num_scalers;
3165         int i;
3166
3167         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3168
3169         /* Not all platformas have a scaler */
3170         if (num_scalers) {
3171                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3172                            num_scalers,
3173                            pipe_config->scaler_state.scaler_users,
3174                            pipe_config->scaler_state.scaler_id);
3175
3176                 for (i = 0; i < num_scalers; i++) {
3177                         struct intel_scaler *sc =
3178                                         &pipe_config->scaler_state.scalers[i];
3179
3180                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3181                                    i, yesno(sc->in_use), sc->mode);
3182                 }
3183                 seq_puts(m, "\n");
3184         } else {
3185                 seq_puts(m, "\tNo scalers available on this platform\n");
3186         }
3187 }
3188
3189 static int i915_display_info(struct seq_file *m, void *unused)
3190 {
3191         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3192         struct drm_device *dev = &dev_priv->drm;
3193         struct intel_crtc *crtc;
3194         struct drm_connector *connector;
3195         struct drm_connector_list_iter conn_iter;
3196
3197         intel_runtime_pm_get(dev_priv);
3198         seq_printf(m, "CRTC info\n");
3199         seq_printf(m, "---------\n");
3200         for_each_intel_crtc(dev, crtc) {
3201                 bool active;
3202                 struct intel_crtc_state *pipe_config;
3203                 int x, y;
3204
3205                 drm_modeset_lock(&crtc->base.mutex, NULL);
3206                 pipe_config = to_intel_crtc_state(crtc->base.state);
3207
3208                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3209                            crtc->base.base.id, pipe_name(crtc->pipe),
3210                            yesno(pipe_config->base.active),
3211                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3212                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3213
3214                 if (pipe_config->base.active) {
3215                         intel_crtc_info(m, crtc);
3216
3217                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3218                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3219                                    yesno(crtc->cursor_base),
3220                                    x, y, crtc->base.cursor->state->crtc_w,
3221                                    crtc->base.cursor->state->crtc_h,
3222                                    crtc->cursor_addr, yesno(active));
3223                         intel_scaler_info(m, crtc);
3224                         intel_plane_info(m, crtc);
3225                 }
3226
3227                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3228                            yesno(!crtc->cpu_fifo_underrun_disabled),
3229                            yesno(!crtc->pch_fifo_underrun_disabled));
3230                 drm_modeset_unlock(&crtc->base.mutex);
3231         }
3232
3233         seq_printf(m, "\n");
3234         seq_printf(m, "Connector info\n");
3235         seq_printf(m, "--------------\n");
3236         mutex_lock(&dev->mode_config.mutex);
3237         drm_connector_list_iter_begin(dev, &conn_iter);
3238         drm_for_each_connector_iter(connector, &conn_iter)
3239                 intel_connector_info(m, connector);
3240         drm_connector_list_iter_end(&conn_iter);
3241         mutex_unlock(&dev->mode_config.mutex);
3242
3243         intel_runtime_pm_put(dev_priv);
3244
3245         return 0;
3246 }
3247
3248 static int i915_engine_info(struct seq_file *m, void *unused)
3249 {
3250         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3251         struct intel_engine_cs *engine;
3252         enum intel_engine_id id;
3253
3254         intel_runtime_pm_get(dev_priv);
3255
3256         seq_printf(m, "GT awake? %s\n",
3257                    yesno(dev_priv->gt.awake));
3258         seq_printf(m, "Global active requests: %d\n",
3259                    dev_priv->gt.active_requests);
3260
3261         for_each_engine(engine, dev_priv, id) {
3262                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3263                 struct drm_i915_gem_request *rq;
3264                 struct rb_node *rb;
3265                 u64 addr;
3266
3267                 seq_printf(m, "%s\n", engine->name);
3268                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], inflight %d\n",
3269                            intel_engine_get_seqno(engine),
3270                            intel_engine_last_submit(engine),
3271                            engine->hangcheck.seqno,
3272                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
3273                            engine->timeline->inflight_seqnos);
3274
3275                 rcu_read_lock();
3276
3277                 seq_printf(m, "\tRequests:\n");
3278
3279                 rq = list_first_entry(&engine->timeline->requests,
3280                                       struct drm_i915_gem_request, link);
3281                 if (&rq->link != &engine->timeline->requests)
3282                         print_request(m, rq, "\t\tfirst  ");
3283
3284                 rq = list_last_entry(&engine->timeline->requests,
3285                                      struct drm_i915_gem_request, link);
3286                 if (&rq->link != &engine->timeline->requests)
3287                         print_request(m, rq, "\t\tlast   ");
3288
3289                 rq = i915_gem_find_active_request(engine);
3290                 if (rq) {
3291                         print_request(m, rq, "\t\tactive ");
3292                         seq_printf(m,
3293                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3294                                    rq->head, rq->postfix, rq->tail,
3295                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3296                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3297                 }
3298
3299                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3300                            I915_READ(RING_START(engine->mmio_base)),
3301                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3302                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3303                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3304                            rq ? rq->ring->head : 0);
3305                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3306                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3307                            rq ? rq->ring->tail : 0);
3308                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3309                            I915_READ(RING_CTL(engine->mmio_base)),
3310                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3311
3312                 rcu_read_unlock();
3313
3314                 addr = intel_engine_get_active_head(engine);
3315                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3316                            upper_32_bits(addr), lower_32_bits(addr));
3317                 addr = intel_engine_get_last_batch_head(engine);
3318                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3319                            upper_32_bits(addr), lower_32_bits(addr));
3320
3321                 if (i915.enable_execlists) {
3322                         u32 ptr, read, write;
3323                         struct rb_node *rb;
3324
3325                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3326                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3327                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3328
3329                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3330                         read = GEN8_CSB_READ_PTR(ptr);
3331                         write = GEN8_CSB_WRITE_PTR(ptr);
3332                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3333                                    read, write);
3334                         if (read >= GEN8_CSB_ENTRIES)
3335                                 read = 0;
3336                         if (write >= GEN8_CSB_ENTRIES)
3337                                 write = 0;
3338                         if (read > write)
3339                                 write += GEN8_CSB_ENTRIES;
3340                         while (read < write) {
3341                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3342
3343                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3344                                            idx,
3345                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3346                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3347                         }
3348
3349                         rcu_read_lock();
3350                         rq = READ_ONCE(engine->execlist_port[0].request);
3351                         if (rq) {
3352                                 seq_printf(m, "\t\tELSP[0] count=%d, ",
3353                                            engine->execlist_port[0].count);
3354                                 print_request(m, rq, "rq: ");
3355                         } else {
3356                                 seq_printf(m, "\t\tELSP[0] idle\n");
3357                         }
3358                         rq = READ_ONCE(engine->execlist_port[1].request);
3359                         if (rq) {
3360                                 seq_printf(m, "\t\tELSP[1] count=%d, ",
3361                                            engine->execlist_port[1].count);
3362                                 print_request(m, rq, "rq: ");
3363                         } else {
3364                                 seq_printf(m, "\t\tELSP[1] idle\n");
3365                         }
3366                         rcu_read_unlock();
3367
3368                         spin_lock_irq(&engine->timeline->lock);
3369                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3370                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3371                                 print_request(m, rq, "\t\tQ ");
3372                         }
3373                         spin_unlock_irq(&engine->timeline->lock);
3374                 } else if (INTEL_GEN(dev_priv) > 6) {
3375                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3376                                    I915_READ(RING_PP_DIR_BASE(engine)));
3377                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3378                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3379                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3380                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3381                 }
3382
3383                 spin_lock_irq(&b->rb_lock);
3384                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3385                         struct intel_wait *w = rb_entry(rb, typeof(*w), node);
3386
3387                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3388                                    w->tsk->comm, w->tsk->pid, w->seqno);
3389                 }
3390                 spin_unlock_irq(&b->rb_lock);
3391
3392                 seq_puts(m, "\n");
3393         }
3394
3395         intel_runtime_pm_put(dev_priv);
3396
3397         return 0;
3398 }
3399
3400 static int i915_semaphore_status(struct seq_file *m, void *unused)
3401 {
3402         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3403         struct drm_device *dev = &dev_priv->drm;
3404         struct intel_engine_cs *engine;
3405         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3406         enum intel_engine_id id;
3407         int j, ret;
3408
3409         if (!i915.semaphores) {
3410                 seq_puts(m, "Semaphores are disabled\n");
3411                 return 0;
3412         }
3413
3414         ret = mutex_lock_interruptible(&dev->struct_mutex);
3415         if (ret)
3416                 return ret;
3417         intel_runtime_pm_get(dev_priv);
3418
3419         if (IS_BROADWELL(dev_priv)) {
3420                 struct page *page;
3421                 uint64_t *seqno;
3422
3423                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3424
3425                 seqno = (uint64_t *)kmap_atomic(page);
3426                 for_each_engine(engine, dev_priv, id) {
3427                         uint64_t offset;
3428
3429                         seq_printf(m, "%s\n", engine->name);
3430
3431                         seq_puts(m, "  Last signal:");
3432                         for (j = 0; j < num_rings; j++) {
3433                                 offset = id * I915_NUM_ENGINES + j;
3434                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3435                                            seqno[offset], offset * 8);
3436                         }
3437                         seq_putc(m, '\n');
3438
3439                         seq_puts(m, "  Last wait:  ");
3440                         for (j = 0; j < num_rings; j++) {
3441                                 offset = id + (j * I915_NUM_ENGINES);
3442                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3443                                            seqno[offset], offset * 8);
3444                         }
3445                         seq_putc(m, '\n');
3446
3447                 }
3448                 kunmap_atomic(seqno);
3449         } else {
3450                 seq_puts(m, "  Last signal:");
3451                 for_each_engine(engine, dev_priv, id)
3452                         for (j = 0; j < num_rings; j++)
3453                                 seq_printf(m, "0x%08x\n",
3454                                            I915_READ(engine->semaphore.mbox.signal[j]));
3455                 seq_putc(m, '\n');
3456         }
3457
3458         intel_runtime_pm_put(dev_priv);
3459         mutex_unlock(&dev->struct_mutex);
3460         return 0;
3461 }
3462
3463 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3464 {
3465         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3466         struct drm_device *dev = &dev_priv->drm;
3467         int i;
3468
3469         drm_modeset_lock_all(dev);
3470         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3471                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3472
3473                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3474                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3475                            pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
3476                 seq_printf(m, " tracked hardware state:\n");
3477                 seq_printf(m, " dpll:    0x%08x\n", pll->state.hw_state.dpll);
3478                 seq_printf(m, " dpll_md: 0x%08x\n",
3479                            pll->state.hw_state.dpll_md);
3480                 seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
3481                 seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
3482                 seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
3483         }
3484         drm_modeset_unlock_all(dev);
3485
3486         return 0;
3487 }
3488
3489 static int i915_wa_registers(struct seq_file *m, void *unused)
3490 {
3491         int i;
3492         int ret;
3493         struct intel_engine_cs *engine;
3494         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3495         struct drm_device *dev = &dev_priv->drm;
3496         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3497         enum intel_engine_id id;
3498
3499         ret = mutex_lock_interruptible(&dev->struct_mutex);
3500         if (ret)
3501                 return ret;
3502
3503         intel_runtime_pm_get(dev_priv);
3504
3505         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3506         for_each_engine(engine, dev_priv, id)
3507                 seq_printf(m, "HW whitelist count for %s: %d\n",
3508                            engine->name, workarounds->hw_whitelist_count[id]);
3509         for (i = 0; i < workarounds->count; ++i) {
3510                 i915_reg_t addr;
3511                 u32 mask, value, read;
3512                 bool ok;
3513
3514                 addr = workarounds->reg[i].addr;
3515                 mask = workarounds->reg[i].mask;
3516                 value = workarounds->reg[i].value;
3517                 read = I915_READ(addr);
3518                 ok = (value & mask) == (read & mask);
3519                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3520                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3521         }
3522
3523         intel_runtime_pm_put(dev_priv);
3524         mutex_unlock(&dev->struct_mutex);
3525
3526         return 0;
3527 }
3528
3529 static int i915_ddb_info(struct seq_file *m, void *unused)
3530 {
3531         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3532         struct drm_device *dev = &dev_priv->drm;
3533         struct skl_ddb_allocation *ddb;
3534         struct skl_ddb_entry *entry;
3535         enum pipe pipe;
3536         int plane;
3537
3538         if (INTEL_GEN(dev_priv) < 9)
3539                 return 0;
3540
3541         drm_modeset_lock_all(dev);
3542
3543         ddb = &dev_priv->wm.skl_hw.ddb;
3544
3545         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3546
3547         for_each_pipe(dev_priv, pipe) {
3548                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3549
3550                 for_each_universal_plane(dev_priv, pipe, plane) {
3551                         entry = &ddb->plane[pipe][plane];
3552                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3553                                    entry->start, entry->end,
3554                                    skl_ddb_entry_size(entry));
3555                 }
3556
3557                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3558                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3559                            entry->end, skl_ddb_entry_size(entry));
3560         }
3561
3562         drm_modeset_unlock_all(dev);
3563
3564         return 0;
3565 }
3566
3567 static void drrs_status_per_crtc(struct seq_file *m,
3568                                  struct drm_device *dev,
3569                                  struct intel_crtc *intel_crtc)
3570 {
3571         struct drm_i915_private *dev_priv = to_i915(dev);
3572         struct i915_drrs *drrs = &dev_priv->drrs;
3573         int vrefresh = 0;
3574         struct drm_connector *connector;
3575         struct drm_connector_list_iter conn_iter;
3576
3577         drm_connector_list_iter_begin(dev, &conn_iter);
3578         drm_for_each_connector_iter(connector, &conn_iter) {
3579                 if (connector->state->crtc != &intel_crtc->base)
3580                         continue;
3581
3582                 seq_printf(m, "%s:\n", connector->name);
3583         }
3584         drm_connector_list_iter_end(&conn_iter);
3585
3586         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3587                 seq_puts(m, "\tVBT: DRRS_type: Static");
3588         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3589                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3590         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3591                 seq_puts(m, "\tVBT: DRRS_type: None");
3592         else
3593                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3594
3595         seq_puts(m, "\n\n");
3596
3597         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3598                 struct intel_panel *panel;
3599
3600                 mutex_lock(&drrs->mutex);
3601                 /* DRRS Supported */
3602                 seq_puts(m, "\tDRRS Supported: Yes\n");
3603
3604                 /* disable_drrs() will make drrs->dp NULL */
3605                 if (!drrs->dp) {
3606                         seq_puts(m, "Idleness DRRS: Disabled");
3607                         mutex_unlock(&drrs->mutex);
3608                         return;
3609                 }
3610
3611                 panel = &drrs->dp->attached_connector->panel;
3612                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3613                                         drrs->busy_frontbuffer_bits);
3614
3615                 seq_puts(m, "\n\t\t");
3616                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3617                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3618                         vrefresh = panel->fixed_mode->vrefresh;
3619                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3620                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3621                         vrefresh = panel->downclock_mode->vrefresh;
3622                 } else {
3623                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3624                                                 drrs->refresh_rate_type);
3625                         mutex_unlock(&drrs->mutex);
3626                         return;
3627                 }
3628                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3629
3630                 seq_puts(m, "\n\t\t");
3631                 mutex_unlock(&drrs->mutex);
3632         } else {
3633                 /* DRRS not supported. Print the VBT parameter*/
3634                 seq_puts(m, "\tDRRS Supported : No");
3635         }
3636         seq_puts(m, "\n");
3637 }
3638
3639 static int i915_drrs_status(struct seq_file *m, void *unused)
3640 {
3641         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3642         struct drm_device *dev = &dev_priv->drm;
3643         struct intel_crtc *intel_crtc;
3644         int active_crtc_cnt = 0;
3645
3646         drm_modeset_lock_all(dev);
3647         for_each_intel_crtc(dev, intel_crtc) {
3648                 if (intel_crtc->base.state->active) {
3649                         active_crtc_cnt++;
3650                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3651
3652                         drrs_status_per_crtc(m, dev, intel_crtc);
3653                 }
3654         }
3655         drm_modeset_unlock_all(dev);
3656
3657         if (!active_crtc_cnt)
3658                 seq_puts(m, "No active crtc found\n");
3659
3660         return 0;
3661 }
3662
3663 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3664 {
3665         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3666         struct drm_device *dev = &dev_priv->drm;
3667         struct intel_encoder *intel_encoder;
3668         struct intel_digital_port *intel_dig_port;
3669         struct drm_connector *connector;
3670         struct drm_connector_list_iter conn_iter;
3671
3672         drm_connector_list_iter_begin(dev, &conn_iter);
3673         drm_for_each_connector_iter(connector, &conn_iter) {
3674                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3675                         continue;
3676
3677                 intel_encoder = intel_attached_encoder(connector);
3678                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3679                         continue;
3680
3681                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3682                 if (!intel_dig_port->dp.can_mst)
3683                         continue;
3684
3685                 seq_printf(m, "MST Source Port %c\n",
3686                            port_name(intel_dig_port->port));
3687                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3688         }
3689         drm_connector_list_iter_end(&conn_iter);
3690
3691         return 0;
3692 }
3693
3694 static ssize_t i915_displayport_test_active_write(struct file *file,
3695                                                   const char __user *ubuf,
3696                                                   size_t len, loff_t *offp)
3697 {
3698         char *input_buffer;
3699         int status = 0;
3700         struct drm_device *dev;
3701         struct drm_connector *connector;
3702         struct drm_connector_list_iter conn_iter;
3703         struct intel_dp *intel_dp;
3704         int val = 0;
3705
3706         dev = ((struct seq_file *)file->private_data)->private;
3707
3708         if (len == 0)
3709                 return 0;
3710
3711         input_buffer = kmalloc(len + 1, GFP_KERNEL);
3712         if (!input_buffer)
3713                 return -ENOMEM;
3714
3715         if (copy_from_user(input_buffer, ubuf, len)) {
3716                 status = -EFAULT;
3717                 goto out;
3718         }
3719
3720         input_buffer[len] = '\0';
3721         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
3722
3723         drm_connector_list_iter_begin(dev, &conn_iter);
3724         drm_for_each_connector_iter(connector, &conn_iter) {
3725                 if (connector->connector_type !=
3726                     DRM_MODE_CONNECTOR_DisplayPort)
3727                         continue;
3728
3729                 if (connector->status == connector_status_connected &&
3730                     connector->encoder != NULL) {
3731                         intel_dp = enc_to_intel_dp(connector->encoder);
3732                         status = kstrtoint(input_buffer, 10, &val);
3733                         if (status < 0)
3734                                 break;
3735                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
3736                         /* To prevent erroneous activation of the compliance
3737                          * testing code, only accept an actual value of 1 here
3738                          */
3739                         if (val == 1)
3740                                 intel_dp->compliance.test_active = 1;
3741                         else
3742                                 intel_dp->compliance.test_active = 0;
3743                 }
3744         }
3745         drm_connector_list_iter_end(&conn_iter);
3746 out:
3747         kfree(input_buffer);
3748         if (status < 0)
3749                 return status;
3750
3751         *offp += len;
3752         return len;
3753 }
3754
3755 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
3756 {
3757         struct drm_device *dev = m->private;
3758         struct drm_connector *connector;
3759         struct drm_connector_list_iter conn_iter;
3760         struct intel_dp *intel_dp;
3761
3762         drm_connector_list_iter_begin(dev, &conn_iter);
3763         drm_for_each_connector_iter(connector, &conn_iter) {
3764                 if (connector->connector_type !=
3765                     DRM_MODE_CONNECTOR_DisplayPort)
3766                         continue;
3767
3768                 if (connector->status == connector_status_connected &&
3769                     connector->encoder != NULL) {
3770                         intel_dp = enc_to_intel_dp(connector->encoder);
3771                         if (intel_dp->compliance.test_active)
3772                                 seq_puts(m, "1");
3773                         else
3774                                 seq_puts(m, "0");
3775                 } else
3776                         seq_puts(m, "0");
3777         }
3778         drm_connector_list_iter_end(&conn_iter);
3779
3780         return 0;
3781 }
3782
3783 static int i915_displayport_test_active_open(struct inode *inode,
3784                                              struct file *file)
3785 {
3786         struct drm_i915_private *dev_priv = inode->i_private;
3787
3788         return single_open(file, i915_displayport_test_active_show,
3789                            &dev_priv->drm);
3790 }
3791
3792 static const struct file_operations i915_displayport_test_active_fops = {
3793         .owner = THIS_MODULE,
3794         .open = i915_displayport_test_active_open,
3795         .read = seq_read,
3796         .llseek = seq_lseek,
3797         .release = single_release,
3798         .write = i915_displayport_test_active_write
3799 };
3800
3801 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
3802 {
3803         struct drm_device *dev = m->private;
3804         struct drm_connector *connector;
3805         struct drm_connector_list_iter conn_iter;
3806         struct intel_dp *intel_dp;
3807
3808         drm_connector_list_iter_begin(dev, &conn_iter);
3809         drm_for_each_connector_iter(connector, &conn_iter) {
3810                 if (connector->connector_type !=
3811                     DRM_MODE_CONNECTOR_DisplayPort)
3812                         continue;
3813
3814                 if (connector->status == connector_status_connected &&
3815                     connector->encoder != NULL) {
3816                         intel_dp = enc_to_intel_dp(connector->encoder);
3817                         if (intel_dp->compliance.test_type ==
3818                             DP_TEST_LINK_EDID_READ)
3819                                 seq_printf(m, "%lx",
3820                                            intel_dp->compliance.test_data.edid);
3821                         else if (intel_dp->compliance.test_type ==
3822                                  DP_TEST_LINK_VIDEO_PATTERN) {
3823                                 seq_printf(m, "hdisplay: %d\n",
3824                                            intel_dp->compliance.test_data.hdisplay);
3825                                 seq_printf(m, "vdisplay: %d\n",
3826                                            intel_dp->compliance.test_data.vdisplay);
3827                                 seq_printf(m, "bpc: %u\n",
3828                                            intel_dp->compliance.test_data.bpc);
3829                         }
3830                 } else
3831                         seq_puts(m, "0");
3832         }
3833         drm_connector_list_iter_end(&conn_iter);
3834
3835         return 0;
3836 }
3837 static int i915_displayport_test_data_open(struct inode *inode,
3838                                            struct file *file)
3839 {
3840         struct drm_i915_private *dev_priv = inode->i_private;
3841
3842         return single_open(file, i915_displayport_test_data_show,
3843                            &dev_priv->drm);
3844 }
3845
3846 static const struct file_operations i915_displayport_test_data_fops = {
3847         .owner = THIS_MODULE,
3848         .open = i915_displayport_test_data_open,
3849         .read = seq_read,
3850         .llseek = seq_lseek,
3851         .release = single_release
3852 };
3853
3854 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
3855 {
3856         struct drm_device *dev = m->private;
3857         struct drm_connector *connector;
3858         struct drm_connector_list_iter conn_iter;
3859         struct intel_dp *intel_dp;
3860
3861         drm_connector_list_iter_begin(dev, &conn_iter);
3862         drm_for_each_connector_iter(connector, &conn_iter) {
3863                 if (connector->connector_type !=
3864                     DRM_MODE_CONNECTOR_DisplayPort)
3865                         continue;
3866
3867                 if (connector->status == connector_status_connected &&
3868                     connector->encoder != NULL) {
3869                         intel_dp = enc_to_intel_dp(connector->encoder);
3870                         seq_printf(m, "%02lx", intel_dp->compliance.test_type);
3871                 } else
3872                         seq_puts(m, "0");
3873         }
3874         drm_connector_list_iter_end(&conn_iter);
3875
3876         return 0;
3877 }
3878
3879 static int i915_displayport_test_type_open(struct inode *inode,
3880                                        struct file *file)
3881 {
3882         struct drm_i915_private *dev_priv = inode->i_private;
3883
3884         return single_open(file, i915_displayport_test_type_show,
3885                            &dev_priv->drm);
3886 }
3887
3888 static const struct file_operations i915_displayport_test_type_fops = {
3889         .owner = THIS_MODULE,
3890         .open = i915_displayport_test_type_open,
3891         .read = seq_read,
3892         .llseek = seq_lseek,
3893         .release = single_release
3894 };
3895
3896 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3897 {
3898         struct drm_i915_private *dev_priv = m->private;
3899         struct drm_device *dev = &dev_priv->drm;
3900         int level;
3901         int num_levels;
3902
3903         if (IS_CHERRYVIEW(dev_priv))
3904                 num_levels = 3;
3905         else if (IS_VALLEYVIEW(dev_priv))
3906                 num_levels = 1;
3907         else
3908                 num_levels = ilk_wm_max_level(dev_priv) + 1;
3909
3910         drm_modeset_lock_all(dev);
3911
3912         for (level = 0; level < num_levels; level++) {
3913                 unsigned int latency = wm[level];
3914
3915                 /*
3916                  * - WM1+ latency values in 0.5us units
3917                  * - latencies are in us on gen9/vlv/chv
3918                  */
3919                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
3920                     IS_CHERRYVIEW(dev_priv))
3921                         latency *= 10;
3922                 else if (level > 0)
3923                         latency *= 5;
3924
3925                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3926                            level, wm[level], latency / 10, latency % 10);
3927         }
3928
3929         drm_modeset_unlock_all(dev);
3930 }
3931
3932 static int pri_wm_latency_show(struct seq_file *m, void *data)
3933 {
3934         struct drm_i915_private *dev_priv = m->private;
3935         const uint16_t *latencies;
3936
3937         if (INTEL_GEN(dev_priv) >= 9)
3938                 latencies = dev_priv->wm.skl_latency;
3939         else
3940                 latencies = dev_priv->wm.pri_latency;
3941
3942         wm_latency_show(m, latencies);
3943
3944         return 0;
3945 }
3946
3947 static int spr_wm_latency_show(struct seq_file *m, void *data)
3948 {
3949         struct drm_i915_private *dev_priv = m->private;
3950         const uint16_t *latencies;
3951
3952         if (INTEL_GEN(dev_priv) >= 9)
3953                 latencies = dev_priv->wm.skl_latency;
3954         else
3955                 latencies = dev_priv->wm.spr_latency;
3956
3957         wm_latency_show(m, latencies);
3958
3959         return 0;
3960 }
3961
3962 static int cur_wm_latency_show(struct seq_file *m, void *data)
3963 {
3964         struct drm_i915_private *dev_priv = m->private;
3965         const uint16_t *latencies;
3966
3967         if (INTEL_GEN(dev_priv) >= 9)
3968                 latencies = dev_priv->wm.skl_latency;
3969         else
3970                 latencies = dev_priv->wm.cur_latency;
3971
3972         wm_latency_show(m, latencies);
3973
3974         return 0;
3975 }
3976
3977 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3978 {
3979         struct drm_i915_private *dev_priv = inode->i_private;
3980
3981         if (INTEL_GEN(dev_priv) < 5)
3982                 return -ENODEV;
3983
3984         return single_open(file, pri_wm_latency_show, dev_priv);
3985 }
3986
3987 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3988 {
3989         struct drm_i915_private *dev_priv = inode->i_private;
3990
3991         if (HAS_GMCH_DISPLAY(dev_priv))
3992                 return -ENODEV;
3993
3994         return single_open(file, spr_wm_latency_show, dev_priv);
3995 }
3996
3997 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3998 {
3999         struct drm_i915_private *dev_priv = inode->i_private;
4000
4001         if (HAS_GMCH_DISPLAY(dev_priv))
4002                 return -ENODEV;
4003
4004         return single_open(file, cur_wm_latency_show, dev_priv);
4005 }
4006
4007 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4008                                 size_t len, loff_t *offp, uint16_t wm[8])
4009 {
4010         struct seq_file *m = file->private_data;
4011         struct drm_i915_private *dev_priv = m->private;
4012         struct drm_device *dev = &dev_priv->drm;
4013         uint16_t new[8] = { 0 };
4014         int num_levels;
4015         int level;
4016         int ret;
4017         char tmp[32];
4018
4019         if (IS_CHERRYVIEW(dev_priv))
4020                 num_levels = 3;
4021         else if (IS_VALLEYVIEW(dev_priv))
4022                 num_levels = 1;
4023         else
4024                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4025
4026         if (len >= sizeof(tmp))
4027                 return -EINVAL;
4028
4029         if (copy_from_user(tmp, ubuf, len))
4030                 return -EFAULT;
4031
4032         tmp[len] = '\0';
4033
4034         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4035                      &new[0], &new[1], &new[2], &new[3],
4036                      &new[4], &new[5], &new[6], &new[7]);
4037         if (ret != num_levels)
4038                 return -EINVAL;
4039
4040         drm_modeset_lock_all(dev);
4041
4042         for (level = 0; level < num_levels; level++)
4043                 wm[level] = new[level];
4044
4045         drm_modeset_unlock_all(dev);
4046
4047         return len;
4048 }
4049
4050
4051 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4052                                     size_t len, loff_t *offp)
4053 {
4054         struct seq_file *m = file->private_data;
4055         struct drm_i915_private *dev_priv = m->private;
4056         uint16_t *latencies;
4057
4058         if (INTEL_GEN(dev_priv) >= 9)
4059                 latencies = dev_priv->wm.skl_latency;
4060         else
4061                 latencies = dev_priv->wm.pri_latency;
4062
4063         return wm_latency_write(file, ubuf, len, offp, latencies);
4064 }
4065
4066 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4067                                     size_t len, loff_t *offp)
4068 {
4069         struct seq_file *m = file->private_data;
4070         struct drm_i915_private *dev_priv = m->private;
4071         uint16_t *latencies;
4072
4073         if (INTEL_GEN(dev_priv) >= 9)
4074                 latencies = dev_priv->wm.skl_latency;
4075         else
4076                 latencies = dev_priv->wm.spr_latency;
4077
4078         return wm_latency_write(file, ubuf, len, offp, latencies);
4079 }
4080
4081 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4082                                     size_t len, loff_t *offp)
4083 {
4084         struct seq_file *m = file->private_data;
4085         struct drm_i915_private *dev_priv = m->private;
4086         uint16_t *latencies;
4087
4088         if (INTEL_GEN(dev_priv) >= 9)
4089                 latencies = dev_priv->wm.skl_latency;
4090         else
4091                 latencies = dev_priv->wm.cur_latency;
4092
4093         return wm_latency_write(file, ubuf, len, offp, latencies);
4094 }
4095
4096 static const struct file_operations i915_pri_wm_latency_fops = {
4097         .owner = THIS_MODULE,
4098         .open = pri_wm_latency_open,
4099         .read = seq_read,
4100         .llseek = seq_lseek,
4101         .release = single_release,
4102         .write = pri_wm_latency_write
4103 };
4104
4105 static const struct file_operations i915_spr_wm_latency_fops = {
4106         .owner = THIS_MODULE,
4107         .open = spr_wm_latency_open,
4108         .read = seq_read,
4109         .llseek = seq_lseek,
4110         .release = single_release,
4111         .write = spr_wm_latency_write
4112 };
4113
4114 static const struct file_operations i915_cur_wm_latency_fops = {
4115         .owner = THIS_MODULE,
4116         .open = cur_wm_latency_open,
4117         .read = seq_read,
4118         .llseek = seq_lseek,
4119         .release = single_release,
4120         .write = cur_wm_latency_write
4121 };
4122
4123 static int
4124 i915_wedged_get(void *data, u64 *val)
4125 {
4126         struct drm_i915_private *dev_priv = data;
4127
4128         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4129
4130         return 0;
4131 }
4132
4133 static int
4134 i915_wedged_set(void *data, u64 val)
4135 {
4136         struct drm_i915_private *i915 = data;
4137         struct intel_engine_cs *engine;
4138         unsigned int tmp;
4139
4140         /*
4141          * There is no safeguard against this debugfs entry colliding
4142          * with the hangcheck calling same i915_handle_error() in
4143          * parallel, causing an explosion. For now we assume that the
4144          * test harness is responsible enough not to inject gpu hangs
4145          * while it is writing to 'i915_wedged'
4146          */
4147
4148         if (i915_reset_backoff(&i915->gpu_error))
4149                 return -EAGAIN;
4150
4151         for_each_engine_masked(engine, i915, val, tmp) {
4152                 engine->hangcheck.seqno = intel_engine_get_seqno(engine);
4153                 engine->hangcheck.stalled = true;
4154         }
4155
4156         i915_handle_error(i915, val, "Manually setting wedged to %llu", val);
4157
4158         wait_on_bit(&i915->gpu_error.flags,
4159                     I915_RESET_HANDOFF,
4160                     TASK_UNINTERRUPTIBLE);
4161
4162         return 0;
4163 }
4164
4165 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4166                         i915_wedged_get, i915_wedged_set,
4167                         "%llu\n");
4168
4169 static int
4170 fault_irq_set(struct drm_i915_private *i915,
4171               unsigned long *irq,
4172               unsigned long val)
4173 {
4174         int err;
4175
4176         err = mutex_lock_interruptible(&i915->drm.struct_mutex);
4177         if (err)
4178                 return err;
4179
4180         err = i915_gem_wait_for_idle(i915,
4181                                      I915_WAIT_LOCKED |
4182                                      I915_WAIT_INTERRUPTIBLE);
4183         if (err)
4184                 goto err_unlock;
4185
4186         *irq = val;
4187         mutex_unlock(&i915->drm.struct_mutex);
4188
4189         /* Flush idle worker to disarm irq */
4190         while (flush_delayed_work(&i915->gt.idle_work))
4191                 ;
4192
4193         return 0;
4194
4195 err_unlock:
4196         mutex_unlock(&i915->drm.struct_mutex);
4197         return err;
4198 }
4199
4200 static int
4201 i915_ring_missed_irq_get(void *data, u64 *val)
4202 {
4203         struct drm_i915_private *dev_priv = data;
4204
4205         *val = dev_priv->gpu_error.missed_irq_rings;
4206         return 0;
4207 }
4208
4209 static int
4210 i915_ring_missed_irq_set(void *data, u64 val)
4211 {
4212         struct drm_i915_private *i915 = data;
4213
4214         return fault_irq_set(i915, &i915->gpu_error.missed_irq_rings, val);
4215 }
4216
4217 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4218                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4219                         "0x%08llx\n");
4220
4221 static int
4222 i915_ring_test_irq_get(void *data, u64 *val)
4223 {
4224         struct drm_i915_private *dev_priv = data;
4225
4226         *val = dev_priv->gpu_error.test_irq_rings;
4227
4228         return 0;
4229 }
4230
4231 static int
4232 i915_ring_test_irq_set(void *data, u64 val)
4233 {
4234         struct drm_i915_private *i915 = data;
4235
4236         val &= INTEL_INFO(i915)->ring_mask;
4237         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4238
4239         return fault_irq_set(i915, &i915->gpu_error.test_irq_rings, val);
4240 }
4241
4242 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4243                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4244                         "0x%08llx\n");
4245
4246 #define DROP_UNBOUND 0x1
4247 #define DROP_BOUND 0x2
4248 #define DROP_RETIRE 0x4
4249 #define DROP_ACTIVE 0x8
4250 #define DROP_FREED 0x10
4251 #define DROP_SHRINK_ALL 0x20
4252 #define DROP_ALL (DROP_UNBOUND  | \
4253                   DROP_BOUND    | \
4254                   DROP_RETIRE   | \
4255                   DROP_ACTIVE   | \
4256                   DROP_FREED    | \
4257                   DROP_SHRINK_ALL)
4258 static int
4259 i915_drop_caches_get(void *data, u64 *val)
4260 {
4261         *val = DROP_ALL;
4262
4263         return 0;
4264 }
4265
4266 static int
4267 i915_drop_caches_set(void *data, u64 val)
4268 {
4269         struct drm_i915_private *dev_priv = data;
4270         struct drm_device *dev = &dev_priv->drm;
4271         int ret;
4272
4273         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4274
4275         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4276          * on ioctls on -EAGAIN. */
4277         ret = mutex_lock_interruptible(&dev->struct_mutex);
4278         if (ret)
4279                 return ret;
4280
4281         if (val & DROP_ACTIVE) {
4282                 ret = i915_gem_wait_for_idle(dev_priv,
4283                                              I915_WAIT_INTERRUPTIBLE |
4284                                              I915_WAIT_LOCKED);
4285                 if (ret)
4286                         goto unlock;
4287         }
4288
4289         if (val & DROP_RETIRE)
4290                 i915_gem_retire_requests(dev_priv);
4291
4292         lockdep_set_current_reclaim_state(GFP_KERNEL);
4293         if (val & DROP_BOUND)
4294                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4295
4296         if (val & DROP_UNBOUND)
4297                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4298
4299         if (val & DROP_SHRINK_ALL)
4300                 i915_gem_shrink_all(dev_priv);
4301         lockdep_clear_current_reclaim_state();
4302
4303 unlock:
4304         mutex_unlock(&dev->struct_mutex);
4305
4306         if (val & DROP_FREED) {
4307                 synchronize_rcu();
4308                 i915_gem_drain_freed_objects(dev_priv);
4309         }
4310
4311         return ret;
4312 }
4313
4314 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4315                         i915_drop_caches_get, i915_drop_caches_set,
4316                         "0x%08llx\n");
4317
4318 static int
4319 i915_max_freq_get(void *data, u64 *val)
4320 {
4321         struct drm_i915_private *dev_priv = data;
4322
4323         if (INTEL_GEN(dev_priv) < 6)
4324                 return -ENODEV;
4325
4326         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4327         return 0;
4328 }
4329
4330 static int
4331 i915_max_freq_set(void *data, u64 val)
4332 {
4333         struct drm_i915_private *dev_priv = data;
4334         u32 hw_max, hw_min;
4335         int ret;
4336
4337         if (INTEL_GEN(dev_priv) < 6)
4338                 return -ENODEV;
4339
4340         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4341
4342         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4343         if (ret)
4344                 return ret;
4345
4346         /*
4347          * Turbo will still be enabled, but won't go above the set value.
4348          */
4349         val = intel_freq_opcode(dev_priv, val);
4350
4351         hw_max = dev_priv->rps.max_freq;
4352         hw_min = dev_priv->rps.min_freq;
4353
4354         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4355                 mutex_unlock(&dev_priv->rps.hw_lock);
4356                 return -EINVAL;
4357         }
4358
4359         dev_priv->rps.max_freq_softlimit = val;
4360
4361         if (intel_set_rps(dev_priv, val))
4362                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4363
4364         mutex_unlock(&dev_priv->rps.hw_lock);
4365
4366         return 0;
4367 }
4368
4369 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4370                         i915_max_freq_get, i915_max_freq_set,
4371                         "%llu\n");
4372
4373 static int
4374 i915_min_freq_get(void *data, u64 *val)
4375 {
4376         struct drm_i915_private *dev_priv = data;
4377
4378         if (INTEL_GEN(dev_priv) < 6)
4379                 return -ENODEV;
4380
4381         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4382         return 0;
4383 }
4384
4385 static int
4386 i915_min_freq_set(void *data, u64 val)
4387 {
4388         struct drm_i915_private *dev_priv = data;
4389         u32 hw_max, hw_min;
4390         int ret;
4391
4392         if (INTEL_GEN(dev_priv) < 6)
4393                 return -ENODEV;
4394
4395         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4396
4397         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4398         if (ret)
4399                 return ret;
4400
4401         /*
4402          * Turbo will still be enabled, but won't go below the set value.
4403          */
4404         val = intel_freq_opcode(dev_priv, val);
4405
4406         hw_max = dev_priv->rps.max_freq;
4407         hw_min = dev_priv->rps.min_freq;
4408
4409         if (val < hw_min ||
4410             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4411                 mutex_unlock(&dev_priv->rps.hw_lock);
4412                 return -EINVAL;
4413         }
4414
4415         dev_priv->rps.min_freq_softlimit = val;
4416
4417         if (intel_set_rps(dev_priv, val))
4418                 DRM_DEBUG_DRIVER("failed to update RPS to new softlimit\n");
4419
4420         mutex_unlock(&dev_priv->rps.hw_lock);
4421
4422         return 0;
4423 }
4424
4425 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4426                         i915_min_freq_get, i915_min_freq_set,
4427                         "%llu\n");
4428
4429 static int
4430 i915_cache_sharing_get(void *data, u64 *val)
4431 {
4432         struct drm_i915_private *dev_priv = data;
4433         u32 snpcr;
4434
4435         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4436                 return -ENODEV;
4437
4438         intel_runtime_pm_get(dev_priv);
4439
4440         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4441
4442         intel_runtime_pm_put(dev_priv);
4443
4444         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4445
4446         return 0;
4447 }
4448
4449 static int
4450 i915_cache_sharing_set(void *data, u64 val)
4451 {
4452         struct drm_i915_private *dev_priv = data;
4453         u32 snpcr;
4454
4455         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4456                 return -ENODEV;
4457
4458         if (val > 3)
4459                 return -EINVAL;
4460
4461         intel_runtime_pm_get(dev_priv);
4462         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4463
4464         /* Update the cache sharing policy here as well */
4465         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4466         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4467         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4468         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4469
4470         intel_runtime_pm_put(dev_priv);
4471         return 0;
4472 }
4473
4474 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4475                         i915_cache_sharing_get, i915_cache_sharing_set,
4476                         "%llu\n");
4477
4478 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4479                                           struct sseu_dev_info *sseu)
4480 {
4481         int ss_max = 2;
4482         int ss;
4483         u32 sig1[ss_max], sig2[ss_max];
4484
4485         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4486         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4487         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4488         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4489
4490         for (ss = 0; ss < ss_max; ss++) {
4491                 unsigned int eu_cnt;
4492
4493                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4494                         /* skip disabled subslice */
4495                         continue;
4496
4497                 sseu->slice_mask = BIT(0);
4498                 sseu->subslice_mask |= BIT(ss);
4499                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4500                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4501                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4502                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4503                 sseu->eu_total += eu_cnt;
4504                 sseu->eu_per_subslice = max_t(unsigned int,
4505                                               sseu->eu_per_subslice, eu_cnt);
4506         }
4507 }
4508
4509 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
4510                                     struct sseu_dev_info *sseu)
4511 {
4512         int s_max = 3, ss_max = 4;
4513         int s, ss;
4514         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4515
4516         /* BXT has a single slice and at most 3 subslices. */
4517         if (IS_GEN9_LP(dev_priv)) {
4518                 s_max = 1;
4519                 ss_max = 3;
4520         }
4521
4522         for (s = 0; s < s_max; s++) {
4523                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4524                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4525                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4526         }
4527
4528         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4529                      GEN9_PGCTL_SSA_EU19_ACK |
4530                      GEN9_PGCTL_SSA_EU210_ACK |
4531                      GEN9_PGCTL_SSA_EU311_ACK;
4532         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4533                      GEN9_PGCTL_SSB_EU19_ACK |
4534                      GEN9_PGCTL_SSB_EU210_ACK |
4535                      GEN9_PGCTL_SSB_EU311_ACK;
4536
4537         for (s = 0; s < s_max; s++) {
4538                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4539                         /* skip disabled slice */
4540                         continue;
4541
4542                 sseu->slice_mask |= BIT(s);
4543
4544                 if (IS_GEN9_BC(dev_priv))
4545                         sseu->subslice_mask =
4546                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
4547
4548                 for (ss = 0; ss < ss_max; ss++) {
4549                         unsigned int eu_cnt;
4550
4551                         if (IS_GEN9_LP(dev_priv)) {
4552                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4553                                         /* skip disabled subslice */
4554                                         continue;
4555
4556                                 sseu->subslice_mask |= BIT(ss);
4557                         }
4558
4559                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4560                                                eu_mask[ss%2]);
4561                         sseu->eu_total += eu_cnt;
4562                         sseu->eu_per_subslice = max_t(unsigned int,
4563                                                       sseu->eu_per_subslice,
4564                                                       eu_cnt);
4565                 }
4566         }
4567 }
4568
4569 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
4570                                          struct sseu_dev_info *sseu)
4571 {
4572         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
4573         int s;
4574
4575         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
4576
4577         if (sseu->slice_mask) {
4578                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
4579                 sseu->eu_per_subslice =
4580                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
4581                 sseu->eu_total = sseu->eu_per_subslice *
4582                                  sseu_subslice_total(sseu);
4583
4584                 /* subtract fused off EU(s) from enabled slice(s) */
4585                 for (s = 0; s < fls(sseu->slice_mask); s++) {
4586                         u8 subslice_7eu =
4587                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
4588
4589                         sseu->eu_total -= hweight8(subslice_7eu);
4590                 }
4591         }
4592 }
4593
4594 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
4595                                  const struct sseu_dev_info *sseu)
4596 {
4597         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4598         const char *type = is_available_info ? "Available" : "Enabled";
4599
4600         seq_printf(m, "  %s Slice Mask: %04x\n", type,
4601                    sseu->slice_mask);
4602         seq_printf(m, "  %s Slice Total: %u\n", type,
4603                    hweight8(sseu->slice_mask));
4604         seq_printf(m, "  %s Subslice Total: %u\n", type,
4605                    sseu_subslice_total(sseu));
4606         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
4607                    sseu->subslice_mask);
4608         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
4609                    hweight8(sseu->subslice_mask));
4610         seq_printf(m, "  %s EU Total: %u\n", type,
4611                    sseu->eu_total);
4612         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
4613                    sseu->eu_per_subslice);
4614
4615         if (!is_available_info)
4616                 return;
4617
4618         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
4619         if (HAS_POOLED_EU(dev_priv))
4620                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
4621
4622         seq_printf(m, "  Has Slice Power Gating: %s\n",
4623                    yesno(sseu->has_slice_pg));
4624         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4625                    yesno(sseu->has_subslice_pg));
4626         seq_printf(m, "  Has EU Power Gating: %s\n",
4627                    yesno(sseu->has_eu_pg));
4628 }
4629
4630 static int i915_sseu_status(struct seq_file *m, void *unused)
4631 {
4632         struct drm_i915_private *dev_priv = node_to_i915(m->private);
4633         struct sseu_dev_info sseu;
4634
4635         if (INTEL_GEN(dev_priv) < 8)
4636                 return -ENODEV;
4637
4638         seq_puts(m, "SSEU Device Info\n");
4639         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
4640
4641         seq_puts(m, "SSEU Device Status\n");
4642         memset(&sseu, 0, sizeof(sseu));
4643
4644         intel_runtime_pm_get(dev_priv);
4645
4646         if (IS_CHERRYVIEW(dev_priv)) {
4647                 cherryview_sseu_device_status(dev_priv, &sseu);
4648         } else if (IS_BROADWELL(dev_priv)) {
4649                 broadwell_sseu_device_status(dev_priv, &sseu);
4650         } else if (INTEL_GEN(dev_priv) >= 9) {
4651                 gen9_sseu_device_status(dev_priv, &sseu);
4652         }
4653
4654         intel_runtime_pm_put(dev_priv);
4655
4656         i915_print_sseu_info(m, false, &sseu);
4657
4658         return 0;
4659 }
4660
4661 static int i915_forcewake_open(struct inode *inode, struct file *file)
4662 {
4663         struct drm_i915_private *dev_priv = inode->i_private;
4664
4665         if (INTEL_GEN(dev_priv) < 6)
4666                 return 0;
4667
4668         intel_runtime_pm_get(dev_priv);
4669         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4670
4671         return 0;
4672 }
4673
4674 static int i915_forcewake_release(struct inode *inode, struct file *file)
4675 {
4676         struct drm_i915_private *dev_priv = inode->i_private;
4677
4678         if (INTEL_GEN(dev_priv) < 6)
4679                 return 0;
4680
4681         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4682         intel_runtime_pm_put(dev_priv);
4683
4684         return 0;
4685 }
4686
4687 static const struct file_operations i915_forcewake_fops = {
4688         .owner = THIS_MODULE,
4689         .open = i915_forcewake_open,
4690         .release = i915_forcewake_release,
4691 };
4692
4693 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
4694 {
4695         struct drm_i915_private *dev_priv = m->private;
4696         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4697
4698         seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
4699         seq_printf(m, "Detected: %s\n",
4700                    yesno(delayed_work_pending(&hotplug->reenable_work)));
4701
4702         return 0;
4703 }
4704
4705 static ssize_t i915_hpd_storm_ctl_write(struct file *file,
4706                                         const char __user *ubuf, size_t len,
4707                                         loff_t *offp)
4708 {
4709         struct seq_file *m = file->private_data;
4710         struct drm_i915_private *dev_priv = m->private;
4711         struct i915_hotplug *hotplug = &dev_priv->hotplug;
4712         unsigned int new_threshold;
4713         int i;
4714         char *newline;
4715         char tmp[16];
4716
4717         if (len >= sizeof(tmp))
4718                 return -EINVAL;
4719
4720         if (copy_from_user(tmp, ubuf, len))
4721                 return -EFAULT;
4722
4723         tmp[len] = '\0';
4724
4725         /* Strip newline, if any */
4726         newline = strchr(tmp, '\n');
4727         if (newline)
4728                 *newline = '\0';
4729
4730         if (strcmp(tmp, "reset") == 0)
4731                 new_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4732         else if (kstrtouint(tmp, 10, &new_threshold) != 0)
4733                 return -EINVAL;
4734
4735         if (new_threshold > 0)
4736                 DRM_DEBUG_KMS("Setting HPD storm detection threshold to %d\n",
4737                               new_threshold);
4738         else
4739                 DRM_DEBUG_KMS("Disabling HPD storm detection\n");
4740
4741         spin_lock_irq(&dev_priv->irq_lock);
4742         hotplug->hpd_storm_threshold = new_threshold;
4743         /* Reset the HPD storm stats so we don't accidentally trigger a storm */
4744         for_each_hpd_pin(i)
4745                 hotplug->stats[i].count = 0;
4746         spin_unlock_irq(&dev_priv->irq_lock);
4747
4748         /* Re-enable hpd immediately if we were in an irq storm */
4749         flush_delayed_work(&dev_priv->hotplug.reenable_work);
4750
4751         return len;
4752 }
4753
4754 static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file)
4755 {
4756         return single_open(file, i915_hpd_storm_ctl_show, inode->i_private);
4757 }
4758
4759 static const struct file_operations i915_hpd_storm_ctl_fops = {
4760         .owner = THIS_MODULE,
4761         .open = i915_hpd_storm_ctl_open,
4762         .read = seq_read,
4763         .llseek = seq_lseek,
4764         .release = single_release,
4765         .write = i915_hpd_storm_ctl_write
4766 };
4767
4768 static const struct drm_info_list i915_debugfs_list[] = {
4769         {"i915_capabilities", i915_capabilities, 0},
4770         {"i915_gem_objects", i915_gem_object_info, 0},
4771         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4772         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
4773         {"i915_gem_stolen", i915_gem_stolen_list_info },
4774         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4775         {"i915_gem_request", i915_gem_request_info, 0},
4776         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4777         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4778         {"i915_gem_interrupt", i915_interrupt_info, 0},
4779         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4780         {"i915_guc_info", i915_guc_info, 0},
4781         {"i915_guc_load_status", i915_guc_load_status_info, 0},
4782         {"i915_guc_log_dump", i915_guc_log_dump, 0},
4783         {"i915_huc_load_status", i915_huc_load_status_info, 0},
4784         {"i915_frequency_info", i915_frequency_info, 0},
4785         {"i915_hangcheck_info", i915_hangcheck_info, 0},
4786         {"i915_drpc_info", i915_drpc_info, 0},
4787         {"i915_emon_status", i915_emon_status, 0},
4788         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4789         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
4790         {"i915_fbc_status", i915_fbc_status, 0},
4791         {"i915_ips_status", i915_ips_status, 0},
4792         {"i915_sr_status", i915_sr_status, 0},
4793         {"i915_opregion", i915_opregion, 0},
4794         {"i915_vbt", i915_vbt, 0},
4795         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4796         {"i915_context_status", i915_context_status, 0},
4797         {"i915_dump_lrc", i915_dump_lrc, 0},
4798         {"i915_forcewake_domains", i915_forcewake_domains, 0},
4799         {"i915_swizzle_info", i915_swizzle_info, 0},
4800         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4801         {"i915_llc", i915_llc, 0},
4802         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4803         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4804         {"i915_energy_uJ", i915_energy_uJ, 0},
4805         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
4806         {"i915_power_domain_info", i915_power_domain_info, 0},
4807         {"i915_dmc_info", i915_dmc_info, 0},
4808         {"i915_display_info", i915_display_info, 0},
4809         {"i915_engine_info", i915_engine_info, 0},
4810         {"i915_semaphore_status", i915_semaphore_status, 0},
4811         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4812         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4813         {"i915_wa_registers", i915_wa_registers, 0},
4814         {"i915_ddb_info", i915_ddb_info, 0},
4815         {"i915_sseu_status", i915_sseu_status, 0},
4816         {"i915_drrs_status", i915_drrs_status, 0},
4817         {"i915_rps_boost_info", i915_rps_boost_info, 0},
4818 };
4819 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4820
4821 static const struct i915_debugfs_files {
4822         const char *name;
4823         const struct file_operations *fops;
4824 } i915_debugfs_files[] = {
4825         {"i915_wedged", &i915_wedged_fops},
4826         {"i915_max_freq", &i915_max_freq_fops},
4827         {"i915_min_freq", &i915_min_freq_fops},
4828         {"i915_cache_sharing", &i915_cache_sharing_fops},
4829         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4830         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4831         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4832 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
4833         {"i915_error_state", &i915_error_state_fops},
4834         {"i915_gpu_info", &i915_gpu_info_fops},
4835 #endif
4836         {"i915_next_seqno", &i915_next_seqno_fops},
4837         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4838         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4839         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4840         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4841         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4842         {"i915_dp_test_data", &i915_displayport_test_data_fops},
4843         {"i915_dp_test_type", &i915_displayport_test_type_fops},
4844         {"i915_dp_test_active", &i915_displayport_test_active_fops},
4845         {"i915_guc_log_control", &i915_guc_log_control_fops},
4846         {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
4847 };
4848
4849 int i915_debugfs_register(struct drm_i915_private *dev_priv)
4850 {
4851         struct drm_minor *minor = dev_priv->drm.primary;
4852         struct dentry *ent;
4853         int ret, i;
4854
4855         ent = debugfs_create_file("i915_forcewake_user", S_IRUSR,
4856                                   minor->debugfs_root, to_i915(minor->dev),
4857                                   &i915_forcewake_fops);
4858         if (!ent)
4859                 return -ENOMEM;
4860
4861         ret = intel_pipe_crc_create(minor);
4862         if (ret)
4863                 return ret;
4864
4865         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4866                 ent = debugfs_create_file(i915_debugfs_files[i].name,
4867                                           S_IRUGO | S_IWUSR,
4868                                           minor->debugfs_root,
4869                                           to_i915(minor->dev),
4870                                           i915_debugfs_files[i].fops);
4871                 if (!ent)
4872                         return -ENOMEM;
4873         }
4874
4875         return drm_debugfs_create_files(i915_debugfs_list,
4876                                         I915_DEBUGFS_ENTRIES,
4877                                         minor->debugfs_root, minor);
4878 }
4879
4880 struct dpcd_block {
4881         /* DPCD dump start address. */
4882         unsigned int offset;
4883         /* DPCD dump end address, inclusive. If unset, .size will be used. */
4884         unsigned int end;
4885         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4886         size_t size;
4887         /* Only valid for eDP. */
4888         bool edp;
4889 };
4890
4891 static const struct dpcd_block i915_dpcd_debug[] = {
4892         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4893         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4894         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4895         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4896         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4897         { .offset = DP_SET_POWER },
4898         { .offset = DP_EDP_DPCD_REV },
4899         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4900         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4901         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4902 };
4903
4904 static int i915_dpcd_show(struct seq_file *m, void *data)
4905 {
4906         struct drm_connector *connector = m->private;
4907         struct intel_dp *intel_dp =
4908                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4909         uint8_t buf[16];
4910         ssize_t err;
4911         int i;
4912
4913         if (connector->status != connector_status_connected)
4914                 return -ENODEV;
4915
4916         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4917                 const struct dpcd_block *b = &i915_dpcd_debug[i];
4918                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4919
4920                 if (b->edp &&
4921                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4922                         continue;
4923
4924                 /* low tech for now */
4925                 if (WARN_ON(size > sizeof(buf)))
4926                         continue;
4927
4928                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4929                 if (err <= 0) {
4930                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4931                                   size, b->offset, err);
4932                         continue;
4933                 }
4934
4935                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4936         }
4937
4938         return 0;
4939 }
4940
4941 static int i915_dpcd_open(struct inode *inode, struct file *file)
4942 {
4943         return single_open(file, i915_dpcd_show, inode->i_private);
4944 }
4945
4946 static const struct file_operations i915_dpcd_fops = {
4947         .owner = THIS_MODULE,
4948         .open = i915_dpcd_open,
4949         .read = seq_read,
4950         .llseek = seq_lseek,
4951         .release = single_release,
4952 };
4953
4954 static int i915_panel_show(struct seq_file *m, void *data)
4955 {
4956         struct drm_connector *connector = m->private;
4957         struct intel_dp *intel_dp =
4958                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4959
4960         if (connector->status != connector_status_connected)
4961                 return -ENODEV;
4962
4963         seq_printf(m, "Panel power up delay: %d\n",
4964                    intel_dp->panel_power_up_delay);
4965         seq_printf(m, "Panel power down delay: %d\n",
4966                    intel_dp->panel_power_down_delay);
4967         seq_printf(m, "Backlight on delay: %d\n",
4968                    intel_dp->backlight_on_delay);
4969         seq_printf(m, "Backlight off delay: %d\n",
4970                    intel_dp->backlight_off_delay);
4971
4972         return 0;
4973 }
4974
4975 static int i915_panel_open(struct inode *inode, struct file *file)
4976 {
4977         return single_open(file, i915_panel_show, inode->i_private);
4978 }
4979
4980 static const struct file_operations i915_panel_fops = {
4981         .owner = THIS_MODULE,
4982         .open = i915_panel_open,
4983         .read = seq_read,
4984         .llseek = seq_lseek,
4985         .release = single_release,
4986 };
4987
4988 /**
4989  * i915_debugfs_connector_add - add i915 specific connector debugfs files
4990  * @connector: pointer to a registered drm_connector
4991  *
4992  * Cleanup will be done by drm_connector_unregister() through a call to
4993  * drm_debugfs_connector_remove().
4994  *
4995  * Returns 0 on success, negative error codes on error.
4996  */
4997 int i915_debugfs_connector_add(struct drm_connector *connector)
4998 {
4999         struct dentry *root = connector->debugfs_entry;
5000
5001         /* The connector must have been registered beforehands. */
5002         if (!root)
5003                 return -ENODEV;
5004
5005         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5006             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5007                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5008                                     connector, &i915_dpcd_fops);
5009
5010         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5011                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5012                                     connector, &i915_panel_fops);
5013
5014         return 0;
5015 }