Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Keith Packard <keithp@keithp.com>
26  *
27  */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
44 {
45         return to_i915(node->minor->dev);
46 }
47
48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
49  * allocated we need to hook into the minor for release. */
50 static int
51 drm_add_fake_info_node(struct drm_minor *minor,
52                        struct dentry *ent,
53                        const void *key)
54 {
55         struct drm_info_node *node;
56
57         node = kmalloc(sizeof(*node), GFP_KERNEL);
58         if (node == NULL) {
59                 debugfs_remove(ent);
60                 return -ENOMEM;
61         }
62
63         node->minor = minor;
64         node->dent = ent;
65         node->info_ent = (void *)key;
66
67         mutex_lock(&minor->debugfs_lock);
68         list_add(&node->list, &minor->debugfs_list);
69         mutex_unlock(&minor->debugfs_lock);
70
71         return 0;
72 }
73
74 static int i915_capabilities(struct seq_file *m, void *data)
75 {
76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
78
79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
83 #undef PRINT_FLAG
84
85         return 0;
86 }
87
88 static char get_active_flag(struct drm_i915_gem_object *obj)
89 {
90         return i915_gem_object_is_active(obj) ? '*' : ' ';
91 }
92
93 static char get_pin_flag(struct drm_i915_gem_object *obj)
94 {
95         return obj->pin_display ? 'p' : ' ';
96 }
97
98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
99 {
100         switch (i915_gem_object_get_tiling(obj)) {
101         default:
102         case I915_TILING_NONE: return ' ';
103         case I915_TILING_X: return 'X';
104         case I915_TILING_Y: return 'Y';
105         }
106 }
107
108 static char get_global_flag(struct drm_i915_gem_object *obj)
109 {
110         return obj->fault_mappable ? 'g' : ' ';
111 }
112
113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
114 {
115         return obj->mapping ? 'M' : ' ';
116 }
117
118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
119 {
120         u64 size = 0;
121         struct i915_vma *vma;
122
123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
125                         size += vma->node.size;
126         }
127
128         return size;
129 }
130
131 static void
132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
133 {
134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
135         struct intel_engine_cs *engine;
136         struct i915_vma *vma;
137         unsigned int frontbuffer_bits;
138         int pin_count = 0;
139         enum intel_engine_id id;
140
141         lockdep_assert_held(&obj->base.dev->struct_mutex);
142
143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
144                    &obj->base,
145                    get_active_flag(obj),
146                    get_pin_flag(obj),
147                    get_tiling_flag(obj),
148                    get_global_flag(obj),
149                    get_pin_mapped_flag(obj),
150                    obj->base.size / 1024,
151                    obj->base.read_domains,
152                    obj->base.write_domain);
153         for_each_engine(engine, dev_priv, id)
154                 seq_printf(m, "%x ",
155                            i915_gem_active_get_seqno(&obj->last_read[id],
156                                                      &obj->base.dev->struct_mutex));
157         seq_printf(m, "] %x %s%s%s",
158                    i915_gem_active_get_seqno(&obj->last_write,
159                                              &obj->base.dev->struct_mutex),
160                    i915_cache_level_str(dev_priv, obj->cache_level),
161                    obj->dirty ? " dirty" : "",
162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
163         if (obj->base.name)
164                 seq_printf(m, " (name: %d)", obj->base.name);
165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
166                 if (i915_vma_is_pinned(vma))
167                         pin_count++;
168         }
169         seq_printf(m, " (pinned x %d)", pin_count);
170         if (obj->pin_display)
171                 seq_printf(m, " (display)");
172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
173                 if (!drm_mm_node_allocated(&vma->node))
174                         continue;
175
176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
178                            vma->node.start, vma->node.size);
179                 if (i915_vma_is_ggtt(vma))
180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
181                 if (vma->fence)
182                         seq_printf(m, " , fence: %d%s",
183                                    vma->fence->id,
184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
185                 seq_puts(m, ")");
186         }
187         if (obj->stolen)
188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
189
190         engine = i915_gem_active_get_engine(&obj->last_write,
191                                             &dev_priv->drm.struct_mutex);
192         if (engine)
193                 seq_printf(m, " (%s)", engine->name);
194
195         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
196         if (frontbuffer_bits)
197                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
198 }
199
200 static int obj_rank_by_stolen(void *priv,
201                               struct list_head *A, struct list_head *B)
202 {
203         struct drm_i915_gem_object *a =
204                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
205         struct drm_i915_gem_object *b =
206                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
207
208         if (a->stolen->start < b->stolen->start)
209                 return -1;
210         if (a->stolen->start > b->stolen->start)
211                 return 1;
212         return 0;
213 }
214
215 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
216 {
217         struct drm_i915_private *dev_priv = node_to_i915(m->private);
218         struct drm_device *dev = &dev_priv->drm;
219         struct drm_i915_gem_object *obj;
220         u64 total_obj_size, total_gtt_size;
221         LIST_HEAD(stolen);
222         int count, ret;
223
224         ret = mutex_lock_interruptible(&dev->struct_mutex);
225         if (ret)
226                 return ret;
227
228         total_obj_size = total_gtt_size = count = 0;
229         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
230                 if (obj->stolen == NULL)
231                         continue;
232
233                 list_add(&obj->obj_exec_link, &stolen);
234
235                 total_obj_size += obj->base.size;
236                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
237                 count++;
238         }
239         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
240                 if (obj->stolen == NULL)
241                         continue;
242
243                 list_add(&obj->obj_exec_link, &stolen);
244
245                 total_obj_size += obj->base.size;
246                 count++;
247         }
248         list_sort(NULL, &stolen, obj_rank_by_stolen);
249         seq_puts(m, "Stolen:\n");
250         while (!list_empty(&stolen)) {
251                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
252                 seq_puts(m, "   ");
253                 describe_obj(m, obj);
254                 seq_putc(m, '\n');
255                 list_del_init(&obj->obj_exec_link);
256         }
257         mutex_unlock(&dev->struct_mutex);
258
259         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
260                    count, total_obj_size, total_gtt_size);
261         return 0;
262 }
263
264 struct file_stats {
265         struct drm_i915_file_private *file_priv;
266         unsigned long count;
267         u64 total, unbound;
268         u64 global, shared;
269         u64 active, inactive;
270 };
271
272 static int per_file_stats(int id, void *ptr, void *data)
273 {
274         struct drm_i915_gem_object *obj = ptr;
275         struct file_stats *stats = data;
276         struct i915_vma *vma;
277
278         stats->count++;
279         stats->total += obj->base.size;
280         if (!obj->bind_count)
281                 stats->unbound += obj->base.size;
282         if (obj->base.name || obj->base.dma_buf)
283                 stats->shared += obj->base.size;
284
285         list_for_each_entry(vma, &obj->vma_list, obj_link) {
286                 if (!drm_mm_node_allocated(&vma->node))
287                         continue;
288
289                 if (i915_vma_is_ggtt(vma)) {
290                         stats->global += vma->node.size;
291                 } else {
292                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
293
294                         if (ppgtt->base.file != stats->file_priv)
295                                 continue;
296                 }
297
298                 if (i915_vma_is_active(vma))
299                         stats->active += vma->node.size;
300                 else
301                         stats->inactive += vma->node.size;
302         }
303
304         return 0;
305 }
306
307 #define print_file_stats(m, name, stats) do { \
308         if (stats.count) \
309                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
310                            name, \
311                            stats.count, \
312                            stats.total, \
313                            stats.active, \
314                            stats.inactive, \
315                            stats.global, \
316                            stats.shared, \
317                            stats.unbound); \
318 } while (0)
319
320 static void print_batch_pool_stats(struct seq_file *m,
321                                    struct drm_i915_private *dev_priv)
322 {
323         struct drm_i915_gem_object *obj;
324         struct file_stats stats;
325         struct intel_engine_cs *engine;
326         enum intel_engine_id id;
327         int j;
328
329         memset(&stats, 0, sizeof(stats));
330
331         for_each_engine(engine, dev_priv, id) {
332                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
333                         list_for_each_entry(obj,
334                                             &engine->batch_pool.cache_list[j],
335                                             batch_pool_link)
336                                 per_file_stats(0, obj, &stats);
337                 }
338         }
339
340         print_file_stats(m, "[k]batch pool", stats);
341 }
342
343 static int per_file_ctx_stats(int id, void *ptr, void *data)
344 {
345         struct i915_gem_context *ctx = ptr;
346         int n;
347
348         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
349                 if (ctx->engine[n].state)
350                         per_file_stats(0, ctx->engine[n].state->obj, data);
351                 if (ctx->engine[n].ring)
352                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
353         }
354
355         return 0;
356 }
357
358 static void print_context_stats(struct seq_file *m,
359                                 struct drm_i915_private *dev_priv)
360 {
361         struct drm_device *dev = &dev_priv->drm;
362         struct file_stats stats;
363         struct drm_file *file;
364
365         memset(&stats, 0, sizeof(stats));
366
367         mutex_lock(&dev->struct_mutex);
368         if (dev_priv->kernel_context)
369                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
370
371         list_for_each_entry(file, &dev->filelist, lhead) {
372                 struct drm_i915_file_private *fpriv = file->driver_priv;
373                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
374         }
375         mutex_unlock(&dev->struct_mutex);
376
377         print_file_stats(m, "[k]contexts", stats);
378 }
379
380 static int i915_gem_object_info(struct seq_file *m, void *data)
381 {
382         struct drm_i915_private *dev_priv = node_to_i915(m->private);
383         struct drm_device *dev = &dev_priv->drm;
384         struct i915_ggtt *ggtt = &dev_priv->ggtt;
385         u32 count, mapped_count, purgeable_count, dpy_count;
386         u64 size, mapped_size, purgeable_size, dpy_size;
387         struct drm_i915_gem_object *obj;
388         struct drm_file *file;
389         int ret;
390
391         ret = mutex_lock_interruptible(&dev->struct_mutex);
392         if (ret)
393                 return ret;
394
395         seq_printf(m, "%u objects, %llu bytes\n",
396                    dev_priv->mm.object_count,
397                    dev_priv->mm.object_memory);
398
399         size = count = 0;
400         mapped_size = mapped_count = 0;
401         purgeable_size = purgeable_count = 0;
402         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
403                 size += obj->base.size;
404                 ++count;
405
406                 if (obj->madv == I915_MADV_DONTNEED) {
407                         purgeable_size += obj->base.size;
408                         ++purgeable_count;
409                 }
410
411                 if (obj->mapping) {
412                         mapped_count++;
413                         mapped_size += obj->base.size;
414                 }
415         }
416         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
417
418         size = count = dpy_size = dpy_count = 0;
419         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
420                 size += obj->base.size;
421                 ++count;
422
423                 if (obj->pin_display) {
424                         dpy_size += obj->base.size;
425                         ++dpy_count;
426                 }
427
428                 if (obj->madv == I915_MADV_DONTNEED) {
429                         purgeable_size += obj->base.size;
430                         ++purgeable_count;
431                 }
432
433                 if (obj->mapping) {
434                         mapped_count++;
435                         mapped_size += obj->base.size;
436                 }
437         }
438         seq_printf(m, "%u bound objects, %llu bytes\n",
439                    count, size);
440         seq_printf(m, "%u purgeable objects, %llu bytes\n",
441                    purgeable_count, purgeable_size);
442         seq_printf(m, "%u mapped objects, %llu bytes\n",
443                    mapped_count, mapped_size);
444         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
445                    dpy_count, dpy_size);
446
447         seq_printf(m, "%llu [%llu] gtt total\n",
448                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
449
450         seq_putc(m, '\n');
451         print_batch_pool_stats(m, dev_priv);
452         mutex_unlock(&dev->struct_mutex);
453
454         mutex_lock(&dev->filelist_mutex);
455         print_context_stats(m, dev_priv);
456         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
457                 struct file_stats stats;
458                 struct drm_i915_file_private *file_priv = file->driver_priv;
459                 struct drm_i915_gem_request *request;
460                 struct task_struct *task;
461
462                 memset(&stats, 0, sizeof(stats));
463                 stats.file_priv = file->driver_priv;
464                 spin_lock(&file->table_lock);
465                 idr_for_each(&file->object_idr, per_file_stats, &stats);
466                 spin_unlock(&file->table_lock);
467                 /*
468                  * Although we have a valid reference on file->pid, that does
469                  * not guarantee that the task_struct who called get_pid() is
470                  * still alive (e.g. get_pid(current) => fork() => exit()).
471                  * Therefore, we need to protect this ->comm access using RCU.
472                  */
473                 mutex_lock(&dev->struct_mutex);
474                 request = list_first_entry_or_null(&file_priv->mm.request_list,
475                                                    struct drm_i915_gem_request,
476                                                    client_list);
477                 rcu_read_lock();
478                 task = pid_task(request && request->ctx->pid ?
479                                 request->ctx->pid : file->pid,
480                                 PIDTYPE_PID);
481                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
482                 rcu_read_unlock();
483                 mutex_unlock(&dev->struct_mutex);
484         }
485         mutex_unlock(&dev->filelist_mutex);
486
487         return 0;
488 }
489
490 static int i915_gem_gtt_info(struct seq_file *m, void *data)
491 {
492         struct drm_info_node *node = m->private;
493         struct drm_i915_private *dev_priv = node_to_i915(node);
494         struct drm_device *dev = &dev_priv->drm;
495         bool show_pin_display_only = !!node->info_ent->data;
496         struct drm_i915_gem_object *obj;
497         u64 total_obj_size, total_gtt_size;
498         int count, ret;
499
500         ret = mutex_lock_interruptible(&dev->struct_mutex);
501         if (ret)
502                 return ret;
503
504         total_obj_size = total_gtt_size = count = 0;
505         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
506                 if (show_pin_display_only && !obj->pin_display)
507                         continue;
508
509                 seq_puts(m, "   ");
510                 describe_obj(m, obj);
511                 seq_putc(m, '\n');
512                 total_obj_size += obj->base.size;
513                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
514                 count++;
515         }
516
517         mutex_unlock(&dev->struct_mutex);
518
519         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
520                    count, total_obj_size, total_gtt_size);
521
522         return 0;
523 }
524
525 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
526 {
527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
528         struct drm_device *dev = &dev_priv->drm;
529         struct intel_crtc *crtc;
530         int ret;
531
532         ret = mutex_lock_interruptible(&dev->struct_mutex);
533         if (ret)
534                 return ret;
535
536         for_each_intel_crtc(dev, crtc) {
537                 const char pipe = pipe_name(crtc->pipe);
538                 const char plane = plane_name(crtc->plane);
539                 struct intel_flip_work *work;
540
541                 spin_lock_irq(&dev->event_lock);
542                 work = crtc->flip_work;
543                 if (work == NULL) {
544                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
545                                    pipe, plane);
546                 } else {
547                         u32 pending;
548                         u32 addr;
549
550                         pending = atomic_read(&work->pending);
551                         if (pending) {
552                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
553                                            pipe, plane);
554                         } else {
555                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
556                                            pipe, plane);
557                         }
558                         if (work->flip_queued_req) {
559                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
560
561                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
562                                            engine->name,
563                                            i915_gem_request_get_seqno(work->flip_queued_req),
564                                            dev_priv->next_seqno,
565                                            intel_engine_get_seqno(engine),
566                                            i915_gem_request_completed(work->flip_queued_req));
567                         } else
568                                 seq_printf(m, "Flip not associated with any ring\n");
569                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
570                                    work->flip_queued_vblank,
571                                    work->flip_ready_vblank,
572                                    intel_crtc_get_vblank_counter(crtc));
573                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
574
575                         if (INTEL_GEN(dev_priv) >= 4)
576                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
577                         else
578                                 addr = I915_READ(DSPADDR(crtc->plane));
579                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
580
581                         if (work->pending_flip_obj) {
582                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
583                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
584                         }
585                 }
586                 spin_unlock_irq(&dev->event_lock);
587         }
588
589         mutex_unlock(&dev->struct_mutex);
590
591         return 0;
592 }
593
594 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
595 {
596         struct drm_i915_private *dev_priv = node_to_i915(m->private);
597         struct drm_device *dev = &dev_priv->drm;
598         struct drm_i915_gem_object *obj;
599         struct intel_engine_cs *engine;
600         enum intel_engine_id id;
601         int total = 0;
602         int ret, j;
603
604         ret = mutex_lock_interruptible(&dev->struct_mutex);
605         if (ret)
606                 return ret;
607
608         for_each_engine(engine, dev_priv, id) {
609                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
610                         int count;
611
612                         count = 0;
613                         list_for_each_entry(obj,
614                                             &engine->batch_pool.cache_list[j],
615                                             batch_pool_link)
616                                 count++;
617                         seq_printf(m, "%s cache[%d]: %d objects\n",
618                                    engine->name, j, count);
619
620                         list_for_each_entry(obj,
621                                             &engine->batch_pool.cache_list[j],
622                                             batch_pool_link) {
623                                 seq_puts(m, "   ");
624                                 describe_obj(m, obj);
625                                 seq_putc(m, '\n');
626                         }
627
628                         total += count;
629                 }
630         }
631
632         seq_printf(m, "total: %d\n", total);
633
634         mutex_unlock(&dev->struct_mutex);
635
636         return 0;
637 }
638
639 static void print_request(struct seq_file *m,
640                           struct drm_i915_gem_request *rq,
641                           const char *prefix)
642 {
643         struct pid *pid = rq->ctx->pid;
644         struct task_struct *task;
645
646         rcu_read_lock();
647         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
648         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
649                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
650                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
651                    task ? task->comm : "<unknown>",
652                    task ? task->pid : -1);
653         rcu_read_unlock();
654 }
655
656 static int i915_gem_request_info(struct seq_file *m, void *data)
657 {
658         struct drm_i915_private *dev_priv = node_to_i915(m->private);
659         struct drm_device *dev = &dev_priv->drm;
660         struct drm_i915_gem_request *req;
661         struct intel_engine_cs *engine;
662         enum intel_engine_id id;
663         int ret, any;
664
665         ret = mutex_lock_interruptible(&dev->struct_mutex);
666         if (ret)
667                 return ret;
668
669         any = 0;
670         for_each_engine(engine, dev_priv, id) {
671                 int count;
672
673                 count = 0;
674                 list_for_each_entry(req, &engine->request_list, link)
675                         count++;
676                 if (count == 0)
677                         continue;
678
679                 seq_printf(m, "%s requests: %d\n", engine->name, count);
680                 list_for_each_entry(req, &engine->request_list, link)
681                         print_request(m, req, "    ");
682
683                 any++;
684         }
685         mutex_unlock(&dev->struct_mutex);
686
687         if (any == 0)
688                 seq_puts(m, "No requests\n");
689
690         return 0;
691 }
692
693 static void i915_ring_seqno_info(struct seq_file *m,
694                                  struct intel_engine_cs *engine)
695 {
696         struct intel_breadcrumbs *b = &engine->breadcrumbs;
697         struct rb_node *rb;
698
699         seq_printf(m, "Current sequence (%s): %x\n",
700                    engine->name, intel_engine_get_seqno(engine));
701
702         spin_lock(&b->lock);
703         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
704                 struct intel_wait *w = container_of(rb, typeof(*w), node);
705
706                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
707                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
708         }
709         spin_unlock(&b->lock);
710 }
711
712 static int i915_gem_seqno_info(struct seq_file *m, void *data)
713 {
714         struct drm_i915_private *dev_priv = node_to_i915(m->private);
715         struct intel_engine_cs *engine;
716         enum intel_engine_id id;
717
718         for_each_engine(engine, dev_priv, id)
719                 i915_ring_seqno_info(m, engine);
720
721         return 0;
722 }
723
724
725 static int i915_interrupt_info(struct seq_file *m, void *data)
726 {
727         struct drm_i915_private *dev_priv = node_to_i915(m->private);
728         struct intel_engine_cs *engine;
729         enum intel_engine_id id;
730         int i, pipe;
731
732         intel_runtime_pm_get(dev_priv);
733
734         if (IS_CHERRYVIEW(dev_priv)) {
735                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
736                            I915_READ(GEN8_MASTER_IRQ));
737
738                 seq_printf(m, "Display IER:\t%08x\n",
739                            I915_READ(VLV_IER));
740                 seq_printf(m, "Display IIR:\t%08x\n",
741                            I915_READ(VLV_IIR));
742                 seq_printf(m, "Display IIR_RW:\t%08x\n",
743                            I915_READ(VLV_IIR_RW));
744                 seq_printf(m, "Display IMR:\t%08x\n",
745                            I915_READ(VLV_IMR));
746                 for_each_pipe(dev_priv, pipe)
747                         seq_printf(m, "Pipe %c stat:\t%08x\n",
748                                    pipe_name(pipe),
749                                    I915_READ(PIPESTAT(pipe)));
750
751                 seq_printf(m, "Port hotplug:\t%08x\n",
752                            I915_READ(PORT_HOTPLUG_EN));
753                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
754                            I915_READ(VLV_DPFLIPSTAT));
755                 seq_printf(m, "DPINVGTT:\t%08x\n",
756                            I915_READ(DPINVGTT));
757
758                 for (i = 0; i < 4; i++) {
759                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
760                                    i, I915_READ(GEN8_GT_IMR(i)));
761                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
762                                    i, I915_READ(GEN8_GT_IIR(i)));
763                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
764                                    i, I915_READ(GEN8_GT_IER(i)));
765                 }
766
767                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
768                            I915_READ(GEN8_PCU_IMR));
769                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
770                            I915_READ(GEN8_PCU_IIR));
771                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
772                            I915_READ(GEN8_PCU_IER));
773         } else if (INTEL_GEN(dev_priv) >= 8) {
774                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775                            I915_READ(GEN8_MASTER_IRQ));
776
777                 for (i = 0; i < 4; i++) {
778                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
779                                    i, I915_READ(GEN8_GT_IMR(i)));
780                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
781                                    i, I915_READ(GEN8_GT_IIR(i)));
782                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
783                                    i, I915_READ(GEN8_GT_IER(i)));
784                 }
785
786                 for_each_pipe(dev_priv, pipe) {
787                         enum intel_display_power_domain power_domain;
788
789                         power_domain = POWER_DOMAIN_PIPE(pipe);
790                         if (!intel_display_power_get_if_enabled(dev_priv,
791                                                                 power_domain)) {
792                                 seq_printf(m, "Pipe %c power disabled\n",
793                                            pipe_name(pipe));
794                                 continue;
795                         }
796                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
797                                    pipe_name(pipe),
798                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
799                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
800                                    pipe_name(pipe),
801                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
802                         seq_printf(m, "Pipe %c IER:\t%08x\n",
803                                    pipe_name(pipe),
804                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
805
806                         intel_display_power_put(dev_priv, power_domain);
807                 }
808
809                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
810                            I915_READ(GEN8_DE_PORT_IMR));
811                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
812                            I915_READ(GEN8_DE_PORT_IIR));
813                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
814                            I915_READ(GEN8_DE_PORT_IER));
815
816                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
817                            I915_READ(GEN8_DE_MISC_IMR));
818                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
819                            I915_READ(GEN8_DE_MISC_IIR));
820                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
821                            I915_READ(GEN8_DE_MISC_IER));
822
823                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
824                            I915_READ(GEN8_PCU_IMR));
825                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
826                            I915_READ(GEN8_PCU_IIR));
827                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
828                            I915_READ(GEN8_PCU_IER));
829         } else if (IS_VALLEYVIEW(dev_priv)) {
830                 seq_printf(m, "Display IER:\t%08x\n",
831                            I915_READ(VLV_IER));
832                 seq_printf(m, "Display IIR:\t%08x\n",
833                            I915_READ(VLV_IIR));
834                 seq_printf(m, "Display IIR_RW:\t%08x\n",
835                            I915_READ(VLV_IIR_RW));
836                 seq_printf(m, "Display IMR:\t%08x\n",
837                            I915_READ(VLV_IMR));
838                 for_each_pipe(dev_priv, pipe)
839                         seq_printf(m, "Pipe %c stat:\t%08x\n",
840                                    pipe_name(pipe),
841                                    I915_READ(PIPESTAT(pipe)));
842
843                 seq_printf(m, "Master IER:\t%08x\n",
844                            I915_READ(VLV_MASTER_IER));
845
846                 seq_printf(m, "Render IER:\t%08x\n",
847                            I915_READ(GTIER));
848                 seq_printf(m, "Render IIR:\t%08x\n",
849                            I915_READ(GTIIR));
850                 seq_printf(m, "Render IMR:\t%08x\n",
851                            I915_READ(GTIMR));
852
853                 seq_printf(m, "PM IER:\t\t%08x\n",
854                            I915_READ(GEN6_PMIER));
855                 seq_printf(m, "PM IIR:\t\t%08x\n",
856                            I915_READ(GEN6_PMIIR));
857                 seq_printf(m, "PM IMR:\t\t%08x\n",
858                            I915_READ(GEN6_PMIMR));
859
860                 seq_printf(m, "Port hotplug:\t%08x\n",
861                            I915_READ(PORT_HOTPLUG_EN));
862                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
863                            I915_READ(VLV_DPFLIPSTAT));
864                 seq_printf(m, "DPINVGTT:\t%08x\n",
865                            I915_READ(DPINVGTT));
866
867         } else if (!HAS_PCH_SPLIT(dev_priv)) {
868                 seq_printf(m, "Interrupt enable:    %08x\n",
869                            I915_READ(IER));
870                 seq_printf(m, "Interrupt identity:  %08x\n",
871                            I915_READ(IIR));
872                 seq_printf(m, "Interrupt mask:      %08x\n",
873                            I915_READ(IMR));
874                 for_each_pipe(dev_priv, pipe)
875                         seq_printf(m, "Pipe %c stat:         %08x\n",
876                                    pipe_name(pipe),
877                                    I915_READ(PIPESTAT(pipe)));
878         } else {
879                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
880                            I915_READ(DEIER));
881                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
882                            I915_READ(DEIIR));
883                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
884                            I915_READ(DEIMR));
885                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
886                            I915_READ(SDEIER));
887                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
888                            I915_READ(SDEIIR));
889                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
890                            I915_READ(SDEIMR));
891                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
892                            I915_READ(GTIER));
893                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
894                            I915_READ(GTIIR));
895                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
896                            I915_READ(GTIMR));
897         }
898         for_each_engine(engine, dev_priv, id) {
899                 if (INTEL_GEN(dev_priv) >= 6) {
900                         seq_printf(m,
901                                    "Graphics Interrupt mask (%s):       %08x\n",
902                                    engine->name, I915_READ_IMR(engine));
903                 }
904                 i915_ring_seqno_info(m, engine);
905         }
906         intel_runtime_pm_put(dev_priv);
907
908         return 0;
909 }
910
911 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
912 {
913         struct drm_i915_private *dev_priv = node_to_i915(m->private);
914         struct drm_device *dev = &dev_priv->drm;
915         int i, ret;
916
917         ret = mutex_lock_interruptible(&dev->struct_mutex);
918         if (ret)
919                 return ret;
920
921         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
922         for (i = 0; i < dev_priv->num_fence_regs; i++) {
923                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
924
925                 seq_printf(m, "Fence %d, pin count = %d, object = ",
926                            i, dev_priv->fence_regs[i].pin_count);
927                 if (!vma)
928                         seq_puts(m, "unused");
929                 else
930                         describe_obj(m, vma->obj);
931                 seq_putc(m, '\n');
932         }
933
934         mutex_unlock(&dev->struct_mutex);
935         return 0;
936 }
937
938 static int i915_hws_info(struct seq_file *m, void *data)
939 {
940         struct drm_info_node *node = m->private;
941         struct drm_i915_private *dev_priv = node_to_i915(node);
942         struct intel_engine_cs *engine;
943         const u32 *hws;
944         int i;
945
946         engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
947         hws = engine->status_page.page_addr;
948         if (hws == NULL)
949                 return 0;
950
951         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
952                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
953                            i * 4,
954                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
955         }
956         return 0;
957 }
958
959 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
960
961 static ssize_t
962 i915_error_state_write(struct file *filp,
963                        const char __user *ubuf,
964                        size_t cnt,
965                        loff_t *ppos)
966 {
967         struct i915_error_state_file_priv *error_priv = filp->private_data;
968
969         DRM_DEBUG_DRIVER("Resetting error state\n");
970         i915_destroy_error_state(error_priv->dev);
971
972         return cnt;
973 }
974
975 static int i915_error_state_open(struct inode *inode, struct file *file)
976 {
977         struct drm_i915_private *dev_priv = inode->i_private;
978         struct i915_error_state_file_priv *error_priv;
979
980         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
981         if (!error_priv)
982                 return -ENOMEM;
983
984         error_priv->dev = &dev_priv->drm;
985
986         i915_error_state_get(&dev_priv->drm, error_priv);
987
988         file->private_data = error_priv;
989
990         return 0;
991 }
992
993 static int i915_error_state_release(struct inode *inode, struct file *file)
994 {
995         struct i915_error_state_file_priv *error_priv = file->private_data;
996
997         i915_error_state_put(error_priv);
998         kfree(error_priv);
999
1000         return 0;
1001 }
1002
1003 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1004                                      size_t count, loff_t *pos)
1005 {
1006         struct i915_error_state_file_priv *error_priv = file->private_data;
1007         struct drm_i915_error_state_buf error_str;
1008         loff_t tmp_pos = 0;
1009         ssize_t ret_count = 0;
1010         int ret;
1011
1012         ret = i915_error_state_buf_init(&error_str,
1013                                         to_i915(error_priv->dev), count, *pos);
1014         if (ret)
1015                 return ret;
1016
1017         ret = i915_error_state_to_str(&error_str, error_priv);
1018         if (ret)
1019                 goto out;
1020
1021         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1022                                             error_str.buf,
1023                                             error_str.bytes);
1024
1025         if (ret_count < 0)
1026                 ret = ret_count;
1027         else
1028                 *pos = error_str.start + ret_count;
1029 out:
1030         i915_error_state_buf_release(&error_str);
1031         return ret ?: ret_count;
1032 }
1033
1034 static const struct file_operations i915_error_state_fops = {
1035         .owner = THIS_MODULE,
1036         .open = i915_error_state_open,
1037         .read = i915_error_state_read,
1038         .write = i915_error_state_write,
1039         .llseek = default_llseek,
1040         .release = i915_error_state_release,
1041 };
1042
1043 #endif
1044
1045 static int
1046 i915_next_seqno_get(void *data, u64 *val)
1047 {
1048         struct drm_i915_private *dev_priv = data;
1049         int ret;
1050
1051         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1052         if (ret)
1053                 return ret;
1054
1055         *val = dev_priv->next_seqno;
1056         mutex_unlock(&dev_priv->drm.struct_mutex);
1057
1058         return 0;
1059 }
1060
1061 static int
1062 i915_next_seqno_set(void *data, u64 val)
1063 {
1064         struct drm_i915_private *dev_priv = data;
1065         struct drm_device *dev = &dev_priv->drm;
1066         int ret;
1067
1068         ret = mutex_lock_interruptible(&dev->struct_mutex);
1069         if (ret)
1070                 return ret;
1071
1072         ret = i915_gem_set_seqno(dev, val);
1073         mutex_unlock(&dev->struct_mutex);
1074
1075         return ret;
1076 }
1077
1078 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1079                         i915_next_seqno_get, i915_next_seqno_set,
1080                         "0x%llx\n");
1081
1082 static int i915_frequency_info(struct seq_file *m, void *unused)
1083 {
1084         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1085         struct drm_device *dev = &dev_priv->drm;
1086         int ret = 0;
1087
1088         intel_runtime_pm_get(dev_priv);
1089
1090         if (IS_GEN5(dev_priv)) {
1091                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1092                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1093
1094                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1095                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1096                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1097                            MEMSTAT_VID_SHIFT);
1098                 seq_printf(m, "Current P-state: %d\n",
1099                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1100         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1101                 u32 freq_sts;
1102
1103                 mutex_lock(&dev_priv->rps.hw_lock);
1104                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1105                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1106                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1107
1108                 seq_printf(m, "actual GPU freq: %d MHz\n",
1109                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1110
1111                 seq_printf(m, "current GPU freq: %d MHz\n",
1112                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1113
1114                 seq_printf(m, "max GPU freq: %d MHz\n",
1115                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1116
1117                 seq_printf(m, "min GPU freq: %d MHz\n",
1118                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1119
1120                 seq_printf(m, "idle GPU freq: %d MHz\n",
1121                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1122
1123                 seq_printf(m,
1124                            "efficient (RPe) frequency: %d MHz\n",
1125                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1126                 mutex_unlock(&dev_priv->rps.hw_lock);
1127         } else if (INTEL_GEN(dev_priv) >= 6) {
1128                 u32 rp_state_limits;
1129                 u32 gt_perf_status;
1130                 u32 rp_state_cap;
1131                 u32 rpmodectl, rpinclimit, rpdeclimit;
1132                 u32 rpstat, cagf, reqf;
1133                 u32 rpupei, rpcurup, rpprevup;
1134                 u32 rpdownei, rpcurdown, rpprevdown;
1135                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1136                 int max_freq;
1137
1138                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1139                 if (IS_BROXTON(dev_priv)) {
1140                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1141                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1142                 } else {
1143                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1144                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1145                 }
1146
1147                 /* RPSTAT1 is in the GT power well */
1148                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149                 if (ret)
1150                         goto out;
1151
1152                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1153
1154                 reqf = I915_READ(GEN6_RPNSWREQ);
1155                 if (IS_GEN9(dev_priv))
1156                         reqf >>= 23;
1157                 else {
1158                         reqf &= ~GEN6_TURBO_DISABLE;
1159                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1160                                 reqf >>= 24;
1161                         else
1162                                 reqf >>= 25;
1163                 }
1164                 reqf = intel_gpu_freq(dev_priv, reqf);
1165
1166                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1167                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1168                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1169
1170                 rpstat = I915_READ(GEN6_RPSTAT1);
1171                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1172                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1173                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1174                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1175                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1176                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1177                 if (IS_GEN9(dev_priv))
1178                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1179                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1180                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1181                 else
1182                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1183                 cagf = intel_gpu_freq(dev_priv, cagf);
1184
1185                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1186                 mutex_unlock(&dev->struct_mutex);
1187
1188                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1189                         pm_ier = I915_READ(GEN6_PMIER);
1190                         pm_imr = I915_READ(GEN6_PMIMR);
1191                         pm_isr = I915_READ(GEN6_PMISR);
1192                         pm_iir = I915_READ(GEN6_PMIIR);
1193                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1194                 } else {
1195                         pm_ier = I915_READ(GEN8_GT_IER(2));
1196                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1197                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1198                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1199                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1200                 }
1201                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1202                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1203                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1204                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1205                 seq_printf(m, "Render p-state ratio: %d\n",
1206                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1207                 seq_printf(m, "Render p-state VID: %d\n",
1208                            gt_perf_status & 0xff);
1209                 seq_printf(m, "Render p-state limit: %d\n",
1210                            rp_state_limits & 0xff);
1211                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1212                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1213                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1214                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1215                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1216                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1217                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1218                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1219                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1220                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1221                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1222                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1223                 seq_printf(m, "Up threshold: %d%%\n",
1224                            dev_priv->rps.up_threshold);
1225
1226                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1227                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1228                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1229                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1230                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1231                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1232                 seq_printf(m, "Down threshold: %d%%\n",
1233                            dev_priv->rps.down_threshold);
1234
1235                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1236                             rp_state_cap >> 16) & 0xff;
1237                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1238                              GEN9_FREQ_SCALER : 1);
1239                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1240                            intel_gpu_freq(dev_priv, max_freq));
1241
1242                 max_freq = (rp_state_cap & 0xff00) >> 8;
1243                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1244                              GEN9_FREQ_SCALER : 1);
1245                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1246                            intel_gpu_freq(dev_priv, max_freq));
1247
1248                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1249                             rp_state_cap >> 0) & 0xff;
1250                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1251                              GEN9_FREQ_SCALER : 1);
1252                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1253                            intel_gpu_freq(dev_priv, max_freq));
1254                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1255                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1256
1257                 seq_printf(m, "Current freq: %d MHz\n",
1258                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1259                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1260                 seq_printf(m, "Idle freq: %d MHz\n",
1261                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1262                 seq_printf(m, "Min freq: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1264                 seq_printf(m, "Boost freq: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1266                 seq_printf(m, "Max freq: %d MHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1268                 seq_printf(m,
1269                            "efficient (RPe) frequency: %d MHz\n",
1270                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1271         } else {
1272                 seq_puts(m, "no P-state info available\n");
1273         }
1274
1275         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1276         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1277         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1278
1279 out:
1280         intel_runtime_pm_put(dev_priv);
1281         return ret;
1282 }
1283
1284 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1285                                struct seq_file *m,
1286                                struct intel_instdone *instdone)
1287 {
1288         int slice;
1289         int subslice;
1290
1291         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1292                    instdone->instdone);
1293
1294         if (INTEL_GEN(dev_priv) <= 3)
1295                 return;
1296
1297         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1298                    instdone->slice_common);
1299
1300         if (INTEL_GEN(dev_priv) <= 6)
1301                 return;
1302
1303         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1304                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1305                            slice, subslice, instdone->sampler[slice][subslice]);
1306
1307         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1308                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1309                            slice, subslice, instdone->row[slice][subslice]);
1310 }
1311
1312 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1313 {
1314         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1315         struct intel_engine_cs *engine;
1316         u64 acthd[I915_NUM_ENGINES];
1317         u32 seqno[I915_NUM_ENGINES];
1318         struct intel_instdone instdone;
1319         enum intel_engine_id id;
1320
1321         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1322                 seq_printf(m, "Wedged\n");
1323         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1324                 seq_printf(m, "Reset in progress\n");
1325         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1326                 seq_printf(m, "Waiter holding struct mutex\n");
1327         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1328                 seq_printf(m, "struct_mutex blocked for reset\n");
1329
1330         if (!i915.enable_hangcheck) {
1331                 seq_printf(m, "Hangcheck disabled\n");
1332                 return 0;
1333         }
1334
1335         intel_runtime_pm_get(dev_priv);
1336
1337         for_each_engine(engine, dev_priv, id) {
1338                 acthd[id] = intel_engine_get_active_head(engine);
1339                 seqno[id] = intel_engine_get_seqno(engine);
1340         }
1341
1342         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1343
1344         intel_runtime_pm_put(dev_priv);
1345
1346         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349                                             jiffies));
1350         } else
1351                 seq_printf(m, "Hangcheck inactive\n");
1352
1353         for_each_engine(engine, dev_priv, id) {
1354                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1355                 struct rb_node *rb;
1356
1357                 seq_printf(m, "%s:\n", engine->name);
1358                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1359                            engine->hangcheck.seqno,
1360                            seqno[id],
1361                            engine->last_submitted_seqno);
1362                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1363                            yesno(intel_engine_has_waiter(engine)),
1364                            yesno(test_bit(engine->id,
1365                                           &dev_priv->gpu_error.missed_irq_rings)));
1366                 spin_lock(&b->lock);
1367                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1368                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1369
1370                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1371                                    w->tsk->comm, w->tsk->pid, w->seqno);
1372                 }
1373                 spin_unlock(&b->lock);
1374
1375                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1376                            (long long)engine->hangcheck.acthd,
1377                            (long long)acthd[id]);
1378                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1379                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1380
1381                 if (engine->id == RCS) {
1382                         seq_puts(m, "\tinstdone read =\n");
1383
1384                         i915_instdone_info(dev_priv, m, &instdone);
1385
1386                         seq_puts(m, "\tinstdone accu =\n");
1387
1388                         i915_instdone_info(dev_priv, m,
1389                                            &engine->hangcheck.instdone);
1390                 }
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ironlake_drpc_info(struct seq_file *m)
1397 {
1398         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1399         struct drm_device *dev = &dev_priv->drm;
1400         u32 rgvmodectl, rstdbyctl;
1401         u16 crstandvid;
1402         int ret;
1403
1404         ret = mutex_lock_interruptible(&dev->struct_mutex);
1405         if (ret)
1406                 return ret;
1407         intel_runtime_pm_get(dev_priv);
1408
1409         rgvmodectl = I915_READ(MEMMODECTL);
1410         rstdbyctl = I915_READ(RSTDBYCTL);
1411         crstandvid = I915_READ16(CRSTANDVID);
1412
1413         intel_runtime_pm_put(dev_priv);
1414         mutex_unlock(&dev->struct_mutex);
1415
1416         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1417         seq_printf(m, "Boost freq: %d\n",
1418                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1419                    MEMMODE_BOOST_FREQ_SHIFT);
1420         seq_printf(m, "HW control enabled: %s\n",
1421                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1422         seq_printf(m, "SW control enabled: %s\n",
1423                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1424         seq_printf(m, "Gated voltage change: %s\n",
1425                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1426         seq_printf(m, "Starting frequency: P%d\n",
1427                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1428         seq_printf(m, "Max P-state: P%d\n",
1429                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1430         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1431         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1432         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1433         seq_printf(m, "Render standby enabled: %s\n",
1434                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1435         seq_puts(m, "Current RS state: ");
1436         switch (rstdbyctl & RSX_STATUS_MASK) {
1437         case RSX_STATUS_ON:
1438                 seq_puts(m, "on\n");
1439                 break;
1440         case RSX_STATUS_RC1:
1441                 seq_puts(m, "RC1\n");
1442                 break;
1443         case RSX_STATUS_RC1E:
1444                 seq_puts(m, "RC1E\n");
1445                 break;
1446         case RSX_STATUS_RS1:
1447                 seq_puts(m, "RS1\n");
1448                 break;
1449         case RSX_STATUS_RS2:
1450                 seq_puts(m, "RS2 (RC6)\n");
1451                 break;
1452         case RSX_STATUS_RS3:
1453                 seq_puts(m, "RC3 (RC6+)\n");
1454                 break;
1455         default:
1456                 seq_puts(m, "unknown\n");
1457                 break;
1458         }
1459
1460         return 0;
1461 }
1462
1463 static int i915_forcewake_domains(struct seq_file *m, void *data)
1464 {
1465         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1466         struct intel_uncore_forcewake_domain *fw_domain;
1467
1468         spin_lock_irq(&dev_priv->uncore.lock);
1469         for_each_fw_domain(fw_domain, dev_priv) {
1470                 seq_printf(m, "%s.wake_count = %u\n",
1471                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1472                            fw_domain->wake_count);
1473         }
1474         spin_unlock_irq(&dev_priv->uncore.lock);
1475
1476         return 0;
1477 }
1478
1479 static int vlv_drpc_info(struct seq_file *m)
1480 {
1481         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1482         u32 rpmodectl1, rcctl1, pw_status;
1483
1484         intel_runtime_pm_get(dev_priv);
1485
1486         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1487         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1488         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1489
1490         intel_runtime_pm_put(dev_priv);
1491
1492         seq_printf(m, "Video Turbo Mode: %s\n",
1493                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1494         seq_printf(m, "Turbo enabled: %s\n",
1495                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1496         seq_printf(m, "HW control enabled: %s\n",
1497                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498         seq_printf(m, "SW control enabled: %s\n",
1499                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1500                           GEN6_RP_MEDIA_SW_MODE));
1501         seq_printf(m, "RC6 Enabled: %s\n",
1502                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1503                                         GEN6_RC_CTL_EI_MODE(1))));
1504         seq_printf(m, "Render Power Well: %s\n",
1505                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1506         seq_printf(m, "Media Power Well: %s\n",
1507                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1508
1509         seq_printf(m, "Render RC6 residency since boot: %u\n",
1510                    I915_READ(VLV_GT_RENDER_RC6));
1511         seq_printf(m, "Media RC6 residency since boot: %u\n",
1512                    I915_READ(VLV_GT_MEDIA_RC6));
1513
1514         return i915_forcewake_domains(m, NULL);
1515 }
1516
1517 static int gen6_drpc_info(struct seq_file *m)
1518 {
1519         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1520         struct drm_device *dev = &dev_priv->drm;
1521         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1522         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1523         unsigned forcewake_count;
1524         int count = 0, ret;
1525
1526         ret = mutex_lock_interruptible(&dev->struct_mutex);
1527         if (ret)
1528                 return ret;
1529         intel_runtime_pm_get(dev_priv);
1530
1531         spin_lock_irq(&dev_priv->uncore.lock);
1532         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1533         spin_unlock_irq(&dev_priv->uncore.lock);
1534
1535         if (forcewake_count) {
1536                 seq_puts(m, "RC information inaccurate because somebody "
1537                             "holds a forcewake reference \n");
1538         } else {
1539                 /* NB: we cannot use forcewake, else we read the wrong values */
1540                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1541                         udelay(10);
1542                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1543         }
1544
1545         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1546         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1547
1548         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1549         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1550         if (INTEL_GEN(dev_priv) >= 9) {
1551                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1552                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1553         }
1554         mutex_unlock(&dev->struct_mutex);
1555         mutex_lock(&dev_priv->rps.hw_lock);
1556         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1557         mutex_unlock(&dev_priv->rps.hw_lock);
1558
1559         intel_runtime_pm_put(dev_priv);
1560
1561         seq_printf(m, "Video Turbo Mode: %s\n",
1562                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1563         seq_printf(m, "HW control enabled: %s\n",
1564                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1565         seq_printf(m, "SW control enabled: %s\n",
1566                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1567                           GEN6_RP_MEDIA_SW_MODE));
1568         seq_printf(m, "RC1e Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1570         seq_printf(m, "RC6 Enabled: %s\n",
1571                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1572         if (INTEL_GEN(dev_priv) >= 9) {
1573                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1574                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1575                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1576                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1577         }
1578         seq_printf(m, "Deep RC6 Enabled: %s\n",
1579                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1580         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1581                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1582         seq_puts(m, "Current RC state: ");
1583         switch (gt_core_status & GEN6_RCn_MASK) {
1584         case GEN6_RC0:
1585                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1586                         seq_puts(m, "Core Power Down\n");
1587                 else
1588                         seq_puts(m, "on\n");
1589                 break;
1590         case GEN6_RC3:
1591                 seq_puts(m, "RC3\n");
1592                 break;
1593         case GEN6_RC6:
1594                 seq_puts(m, "RC6\n");
1595                 break;
1596         case GEN6_RC7:
1597                 seq_puts(m, "RC7\n");
1598                 break;
1599         default:
1600                 seq_puts(m, "Unknown\n");
1601                 break;
1602         }
1603
1604         seq_printf(m, "Core Power Down: %s\n",
1605                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1606         if (INTEL_GEN(dev_priv) >= 9) {
1607                 seq_printf(m, "Render Power Well: %s\n",
1608                         (gen9_powergate_status &
1609                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1610                 seq_printf(m, "Media Power Well: %s\n",
1611                         (gen9_powergate_status &
1612                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1613         }
1614
1615         /* Not exactly sure what this is */
1616         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1617                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1618         seq_printf(m, "RC6 residency since boot: %u\n",
1619                    I915_READ(GEN6_GT_GFX_RC6));
1620         seq_printf(m, "RC6+ residency since boot: %u\n",
1621                    I915_READ(GEN6_GT_GFX_RC6p));
1622         seq_printf(m, "RC6++ residency since boot: %u\n",
1623                    I915_READ(GEN6_GT_GFX_RC6pp));
1624
1625         seq_printf(m, "RC6   voltage: %dmV\n",
1626                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1627         seq_printf(m, "RC6+  voltage: %dmV\n",
1628                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1629         seq_printf(m, "RC6++ voltage: %dmV\n",
1630                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1631         return i915_forcewake_domains(m, NULL);
1632 }
1633
1634 static int i915_drpc_info(struct seq_file *m, void *unused)
1635 {
1636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1639                 return vlv_drpc_info(m);
1640         else if (INTEL_GEN(dev_priv) >= 6)
1641                 return gen6_drpc_info(m);
1642         else
1643                 return ironlake_drpc_info(m);
1644 }
1645
1646 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1647 {
1648         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1649
1650         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1651                    dev_priv->fb_tracking.busy_bits);
1652
1653         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1654                    dev_priv->fb_tracking.flip_bits);
1655
1656         return 0;
1657 }
1658
1659 static int i915_fbc_status(struct seq_file *m, void *unused)
1660 {
1661         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1662
1663         if (!HAS_FBC(dev_priv)) {
1664                 seq_puts(m, "FBC unsupported on this chipset\n");
1665                 return 0;
1666         }
1667
1668         intel_runtime_pm_get(dev_priv);
1669         mutex_lock(&dev_priv->fbc.lock);
1670
1671         if (intel_fbc_is_active(dev_priv))
1672                 seq_puts(m, "FBC enabled\n");
1673         else
1674                 seq_printf(m, "FBC disabled: %s\n",
1675                            dev_priv->fbc.no_fbc_reason);
1676
1677         if (intel_fbc_is_active(dev_priv) &&
1678             INTEL_GEN(dev_priv) >= 7)
1679                 seq_printf(m, "Compressing: %s\n",
1680                            yesno(I915_READ(FBC_STATUS2) &
1681                                  FBC_COMPRESSION_MASK));
1682
1683         mutex_unlock(&dev_priv->fbc.lock);
1684         intel_runtime_pm_put(dev_priv);
1685
1686         return 0;
1687 }
1688
1689 static int i915_fbc_fc_get(void *data, u64 *val)
1690 {
1691         struct drm_i915_private *dev_priv = data;
1692
1693         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1694                 return -ENODEV;
1695
1696         *val = dev_priv->fbc.false_color;
1697
1698         return 0;
1699 }
1700
1701 static int i915_fbc_fc_set(void *data, u64 val)
1702 {
1703         struct drm_i915_private *dev_priv = data;
1704         u32 reg;
1705
1706         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1707                 return -ENODEV;
1708
1709         mutex_lock(&dev_priv->fbc.lock);
1710
1711         reg = I915_READ(ILK_DPFC_CONTROL);
1712         dev_priv->fbc.false_color = val;
1713
1714         I915_WRITE(ILK_DPFC_CONTROL, val ?
1715                    (reg | FBC_CTL_FALSE_COLOR) :
1716                    (reg & ~FBC_CTL_FALSE_COLOR));
1717
1718         mutex_unlock(&dev_priv->fbc.lock);
1719         return 0;
1720 }
1721
1722 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1723                         i915_fbc_fc_get, i915_fbc_fc_set,
1724                         "%llu\n");
1725
1726 static int i915_ips_status(struct seq_file *m, void *unused)
1727 {
1728         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1729
1730         if (!HAS_IPS(dev_priv)) {
1731                 seq_puts(m, "not supported\n");
1732                 return 0;
1733         }
1734
1735         intel_runtime_pm_get(dev_priv);
1736
1737         seq_printf(m, "Enabled by kernel parameter: %s\n",
1738                    yesno(i915.enable_ips));
1739
1740         if (INTEL_GEN(dev_priv) >= 8) {
1741                 seq_puts(m, "Currently: unknown\n");
1742         } else {
1743                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1744                         seq_puts(m, "Currently: enabled\n");
1745                 else
1746                         seq_puts(m, "Currently: disabled\n");
1747         }
1748
1749         intel_runtime_pm_put(dev_priv);
1750
1751         return 0;
1752 }
1753
1754 static int i915_sr_status(struct seq_file *m, void *unused)
1755 {
1756         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1757         bool sr_enabled = false;
1758
1759         intel_runtime_pm_get(dev_priv);
1760
1761         if (HAS_PCH_SPLIT(dev_priv))
1762                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1763         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1764                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1765                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1766         else if (IS_I915GM(dev_priv))
1767                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1768         else if (IS_PINEVIEW(dev_priv))
1769                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1770         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1771                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1772
1773         intel_runtime_pm_put(dev_priv);
1774
1775         seq_printf(m, "self-refresh: %s\n",
1776                    sr_enabled ? "enabled" : "disabled");
1777
1778         return 0;
1779 }
1780
1781 static int i915_emon_status(struct seq_file *m, void *unused)
1782 {
1783         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1784         struct drm_device *dev = &dev_priv->drm;
1785         unsigned long temp, chipset, gfx;
1786         int ret;
1787
1788         if (!IS_GEN5(dev_priv))
1789                 return -ENODEV;
1790
1791         ret = mutex_lock_interruptible(&dev->struct_mutex);
1792         if (ret)
1793                 return ret;
1794
1795         temp = i915_mch_val(dev_priv);
1796         chipset = i915_chipset_val(dev_priv);
1797         gfx = i915_gfx_val(dev_priv);
1798         mutex_unlock(&dev->struct_mutex);
1799
1800         seq_printf(m, "GMCH temp: %ld\n", temp);
1801         seq_printf(m, "Chipset power: %ld\n", chipset);
1802         seq_printf(m, "GFX power: %ld\n", gfx);
1803         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1804
1805         return 0;
1806 }
1807
1808 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1809 {
1810         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1811         int ret = 0;
1812         int gpu_freq, ia_freq;
1813         unsigned int max_gpu_freq, min_gpu_freq;
1814
1815         if (!HAS_LLC(dev_priv)) {
1816                 seq_puts(m, "unsupported on this chipset\n");
1817                 return 0;
1818         }
1819
1820         intel_runtime_pm_get(dev_priv);
1821
1822         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1823         if (ret)
1824                 goto out;
1825
1826         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1827                 /* Convert GT frequency to 50 HZ units */
1828                 min_gpu_freq =
1829                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830                 max_gpu_freq =
1831                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832         } else {
1833                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835         }
1836
1837         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1838
1839         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1840                 ia_freq = gpu_freq;
1841                 sandybridge_pcode_read(dev_priv,
1842                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843                                        &ia_freq);
1844                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1845                            intel_gpu_freq(dev_priv, (gpu_freq *
1846                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1847                                  GEN9_FREQ_SCALER : 1))),
1848                            ((ia_freq >> 0) & 0xff) * 100,
1849                            ((ia_freq >> 8) & 0xff) * 100);
1850         }
1851
1852         mutex_unlock(&dev_priv->rps.hw_lock);
1853
1854 out:
1855         intel_runtime_pm_put(dev_priv);
1856         return ret;
1857 }
1858
1859 static int i915_opregion(struct seq_file *m, void *unused)
1860 {
1861         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1862         struct drm_device *dev = &dev_priv->drm;
1863         struct intel_opregion *opregion = &dev_priv->opregion;
1864         int ret;
1865
1866         ret = mutex_lock_interruptible(&dev->struct_mutex);
1867         if (ret)
1868                 goto out;
1869
1870         if (opregion->header)
1871                 seq_write(m, opregion->header, OPREGION_SIZE);
1872
1873         mutex_unlock(&dev->struct_mutex);
1874
1875 out:
1876         return 0;
1877 }
1878
1879 static int i915_vbt(struct seq_file *m, void *unused)
1880 {
1881         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1882
1883         if (opregion->vbt)
1884                 seq_write(m, opregion->vbt, opregion->vbt_size);
1885
1886         return 0;
1887 }
1888
1889 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1890 {
1891         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1892         struct drm_device *dev = &dev_priv->drm;
1893         struct intel_framebuffer *fbdev_fb = NULL;
1894         struct drm_framebuffer *drm_fb;
1895         int ret;
1896
1897         ret = mutex_lock_interruptible(&dev->struct_mutex);
1898         if (ret)
1899                 return ret;
1900
1901 #ifdef CONFIG_DRM_FBDEV_EMULATION
1902         if (dev_priv->fbdev) {
1903                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1904
1905                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1906                            fbdev_fb->base.width,
1907                            fbdev_fb->base.height,
1908                            fbdev_fb->base.depth,
1909                            fbdev_fb->base.bits_per_pixel,
1910                            fbdev_fb->base.modifier[0],
1911                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1912                 describe_obj(m, fbdev_fb->obj);
1913                 seq_putc(m, '\n');
1914         }
1915 #endif
1916
1917         mutex_lock(&dev->mode_config.fb_lock);
1918         drm_for_each_fb(drm_fb, dev) {
1919                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1920                 if (fb == fbdev_fb)
1921                         continue;
1922
1923                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1924                            fb->base.width,
1925                            fb->base.height,
1926                            fb->base.depth,
1927                            fb->base.bits_per_pixel,
1928                            fb->base.modifier[0],
1929                            drm_framebuffer_read_refcount(&fb->base));
1930                 describe_obj(m, fb->obj);
1931                 seq_putc(m, '\n');
1932         }
1933         mutex_unlock(&dev->mode_config.fb_lock);
1934         mutex_unlock(&dev->struct_mutex);
1935
1936         return 0;
1937 }
1938
1939 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1940 {
1941         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1942                    ring->space, ring->head, ring->tail,
1943                    ring->last_retired_head);
1944 }
1945
1946 static int i915_context_status(struct seq_file *m, void *unused)
1947 {
1948         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1949         struct drm_device *dev = &dev_priv->drm;
1950         struct intel_engine_cs *engine;
1951         struct i915_gem_context *ctx;
1952         enum intel_engine_id id;
1953         int ret;
1954
1955         ret = mutex_lock_interruptible(&dev->struct_mutex);
1956         if (ret)
1957                 return ret;
1958
1959         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1960                 seq_printf(m, "HW context %u ", ctx->hw_id);
1961                 if (ctx->pid) {
1962                         struct task_struct *task;
1963
1964                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1965                         if (task) {
1966                                 seq_printf(m, "(%s [%d]) ",
1967                                            task->comm, task->pid);
1968                                 put_task_struct(task);
1969                         }
1970                 } else if (IS_ERR(ctx->file_priv)) {
1971                         seq_puts(m, "(deleted) ");
1972                 } else {
1973                         seq_puts(m, "(kernel) ");
1974                 }
1975
1976                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1977                 seq_putc(m, '\n');
1978
1979                 for_each_engine(engine, dev_priv, id) {
1980                         struct intel_context *ce = &ctx->engine[engine->id];
1981
1982                         seq_printf(m, "%s: ", engine->name);
1983                         seq_putc(m, ce->initialised ? 'I' : 'i');
1984                         if (ce->state)
1985                                 describe_obj(m, ce->state->obj);
1986                         if (ce->ring)
1987                                 describe_ctx_ring(m, ce->ring);
1988                         seq_putc(m, '\n');
1989                 }
1990
1991                 seq_putc(m, '\n');
1992         }
1993
1994         mutex_unlock(&dev->struct_mutex);
1995
1996         return 0;
1997 }
1998
1999 static void i915_dump_lrc_obj(struct seq_file *m,
2000                               struct i915_gem_context *ctx,
2001                               struct intel_engine_cs *engine)
2002 {
2003         struct i915_vma *vma = ctx->engine[engine->id].state;
2004         struct page *page;
2005         int j;
2006
2007         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2008
2009         if (!vma) {
2010                 seq_puts(m, "\tFake context\n");
2011                 return;
2012         }
2013
2014         if (vma->flags & I915_VMA_GLOBAL_BIND)
2015                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2016                            i915_ggtt_offset(vma));
2017
2018         if (i915_gem_object_get_pages(vma->obj)) {
2019                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2020                 return;
2021         }
2022
2023         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2024         if (page) {
2025                 u32 *reg_state = kmap_atomic(page);
2026
2027                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2028                         seq_printf(m,
2029                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2030                                    j * 4,
2031                                    reg_state[j], reg_state[j + 1],
2032                                    reg_state[j + 2], reg_state[j + 3]);
2033                 }
2034                 kunmap_atomic(reg_state);
2035         }
2036
2037         seq_putc(m, '\n');
2038 }
2039
2040 static int i915_dump_lrc(struct seq_file *m, void *unused)
2041 {
2042         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2043         struct drm_device *dev = &dev_priv->drm;
2044         struct intel_engine_cs *engine;
2045         struct i915_gem_context *ctx;
2046         enum intel_engine_id id;
2047         int ret;
2048
2049         if (!i915.enable_execlists) {
2050                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2051                 return 0;
2052         }
2053
2054         ret = mutex_lock_interruptible(&dev->struct_mutex);
2055         if (ret)
2056                 return ret;
2057
2058         list_for_each_entry(ctx, &dev_priv->context_list, link)
2059                 for_each_engine(engine, dev_priv, id)
2060                         i915_dump_lrc_obj(m, ctx, engine);
2061
2062         mutex_unlock(&dev->struct_mutex);
2063
2064         return 0;
2065 }
2066
2067 static const char *swizzle_string(unsigned swizzle)
2068 {
2069         switch (swizzle) {
2070         case I915_BIT_6_SWIZZLE_NONE:
2071                 return "none";
2072         case I915_BIT_6_SWIZZLE_9:
2073                 return "bit9";
2074         case I915_BIT_6_SWIZZLE_9_10:
2075                 return "bit9/bit10";
2076         case I915_BIT_6_SWIZZLE_9_11:
2077                 return "bit9/bit11";
2078         case I915_BIT_6_SWIZZLE_9_10_11:
2079                 return "bit9/bit10/bit11";
2080         case I915_BIT_6_SWIZZLE_9_17:
2081                 return "bit9/bit17";
2082         case I915_BIT_6_SWIZZLE_9_10_17:
2083                 return "bit9/bit10/bit17";
2084         case I915_BIT_6_SWIZZLE_UNKNOWN:
2085                 return "unknown";
2086         }
2087
2088         return "bug";
2089 }
2090
2091 static int i915_swizzle_info(struct seq_file *m, void *data)
2092 {
2093         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2094         struct drm_device *dev = &dev_priv->drm;
2095         int ret;
2096
2097         ret = mutex_lock_interruptible(&dev->struct_mutex);
2098         if (ret)
2099                 return ret;
2100         intel_runtime_pm_get(dev_priv);
2101
2102         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2103                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2104         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2105                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2106
2107         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2108                 seq_printf(m, "DDC = 0x%08x\n",
2109                            I915_READ(DCC));
2110                 seq_printf(m, "DDC2 = 0x%08x\n",
2111                            I915_READ(DCC2));
2112                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2113                            I915_READ16(C0DRB3));
2114                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2115                            I915_READ16(C1DRB3));
2116         } else if (INTEL_GEN(dev_priv) >= 6) {
2117                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2118                            I915_READ(MAD_DIMM_C0));
2119                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2120                            I915_READ(MAD_DIMM_C1));
2121                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2122                            I915_READ(MAD_DIMM_C2));
2123                 seq_printf(m, "TILECTL = 0x%08x\n",
2124                            I915_READ(TILECTL));
2125                 if (INTEL_GEN(dev_priv) >= 8)
2126                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2127                                    I915_READ(GAMTARBMODE));
2128                 else
2129                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2130                                    I915_READ(ARB_MODE));
2131                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2132                            I915_READ(DISP_ARB_CTL));
2133         }
2134
2135         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2136                 seq_puts(m, "L-shaped memory detected\n");
2137
2138         intel_runtime_pm_put(dev_priv);
2139         mutex_unlock(&dev->struct_mutex);
2140
2141         return 0;
2142 }
2143
2144 static int per_file_ctx(int id, void *ptr, void *data)
2145 {
2146         struct i915_gem_context *ctx = ptr;
2147         struct seq_file *m = data;
2148         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2149
2150         if (!ppgtt) {
2151                 seq_printf(m, "  no ppgtt for context %d\n",
2152                            ctx->user_handle);
2153                 return 0;
2154         }
2155
2156         if (i915_gem_context_is_default(ctx))
2157                 seq_puts(m, "  default context:\n");
2158         else
2159                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2160         ppgtt->debug_dump(ppgtt, m);
2161
2162         return 0;
2163 }
2164
2165 static void gen8_ppgtt_info(struct seq_file *m,
2166                             struct drm_i915_private *dev_priv)
2167 {
2168         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2169         struct intel_engine_cs *engine;
2170         enum intel_engine_id id;
2171         int i;
2172
2173         if (!ppgtt)
2174                 return;
2175
2176         for_each_engine(engine, dev_priv, id) {
2177                 seq_printf(m, "%s\n", engine->name);
2178                 for (i = 0; i < 4; i++) {
2179                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2180                         pdp <<= 32;
2181                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2182                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2183                 }
2184         }
2185 }
2186
2187 static void gen6_ppgtt_info(struct seq_file *m,
2188                             struct drm_i915_private *dev_priv)
2189 {
2190         struct intel_engine_cs *engine;
2191         enum intel_engine_id id;
2192
2193         if (IS_GEN6(dev_priv))
2194                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2195
2196         for_each_engine(engine, dev_priv, id) {
2197                 seq_printf(m, "%s\n", engine->name);
2198                 if (IS_GEN7(dev_priv))
2199                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2200                                    I915_READ(RING_MODE_GEN7(engine)));
2201                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2202                            I915_READ(RING_PP_DIR_BASE(engine)));
2203                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2204                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2205                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2206                            I915_READ(RING_PP_DIR_DCLV(engine)));
2207         }
2208         if (dev_priv->mm.aliasing_ppgtt) {
2209                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2210
2211                 seq_puts(m, "aliasing PPGTT:\n");
2212                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2213
2214                 ppgtt->debug_dump(ppgtt, m);
2215         }
2216
2217         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2218 }
2219
2220 static int i915_ppgtt_info(struct seq_file *m, void *data)
2221 {
2222         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2223         struct drm_device *dev = &dev_priv->drm;
2224         struct drm_file *file;
2225         int ret;
2226
2227         mutex_lock(&dev->filelist_mutex);
2228         ret = mutex_lock_interruptible(&dev->struct_mutex);
2229         if (ret)
2230                 goto out_unlock;
2231
2232         intel_runtime_pm_get(dev_priv);
2233
2234         if (INTEL_GEN(dev_priv) >= 8)
2235                 gen8_ppgtt_info(m, dev_priv);
2236         else if (INTEL_GEN(dev_priv) >= 6)
2237                 gen6_ppgtt_info(m, dev_priv);
2238
2239         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2240                 struct drm_i915_file_private *file_priv = file->driver_priv;
2241                 struct task_struct *task;
2242
2243                 task = get_pid_task(file->pid, PIDTYPE_PID);
2244                 if (!task) {
2245                         ret = -ESRCH;
2246                         goto out_rpm;
2247                 }
2248                 seq_printf(m, "\nproc: %s\n", task->comm);
2249                 put_task_struct(task);
2250                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2251                              (void *)(unsigned long)m);
2252         }
2253
2254 out_rpm:
2255         intel_runtime_pm_put(dev_priv);
2256         mutex_unlock(&dev->struct_mutex);
2257 out_unlock:
2258         mutex_unlock(&dev->filelist_mutex);
2259         return ret;
2260 }
2261
2262 static int count_irq_waiters(struct drm_i915_private *i915)
2263 {
2264         struct intel_engine_cs *engine;
2265         enum intel_engine_id id;
2266         int count = 0;
2267
2268         for_each_engine(engine, i915, id)
2269                 count += intel_engine_has_waiter(engine);
2270
2271         return count;
2272 }
2273
2274 static const char *rps_power_to_str(unsigned int power)
2275 {
2276         static const char * const strings[] = {
2277                 [LOW_POWER] = "low power",
2278                 [BETWEEN] = "mixed",
2279                 [HIGH_POWER] = "high power",
2280         };
2281
2282         if (power >= ARRAY_SIZE(strings) || !strings[power])
2283                 return "unknown";
2284
2285         return strings[power];
2286 }
2287
2288 static int i915_rps_boost_info(struct seq_file *m, void *data)
2289 {
2290         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2291         struct drm_device *dev = &dev_priv->drm;
2292         struct drm_file *file;
2293
2294         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2295         seq_printf(m, "GPU busy? %s [%x]\n",
2296                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2297         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2298         seq_printf(m, "Frequency requested %d\n",
2299                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2300         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2301                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2302                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2303                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2304                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2305         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2306                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2307                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2308                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2309
2310         mutex_lock(&dev->filelist_mutex);
2311         spin_lock(&dev_priv->rps.client_lock);
2312         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2313                 struct drm_i915_file_private *file_priv = file->driver_priv;
2314                 struct task_struct *task;
2315
2316                 rcu_read_lock();
2317                 task = pid_task(file->pid, PIDTYPE_PID);
2318                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2319                            task ? task->comm : "<unknown>",
2320                            task ? task->pid : -1,
2321                            file_priv->rps.boosts,
2322                            list_empty(&file_priv->rps.link) ? "" : ", active");
2323                 rcu_read_unlock();
2324         }
2325         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2326         spin_unlock(&dev_priv->rps.client_lock);
2327         mutex_unlock(&dev->filelist_mutex);
2328
2329         if (INTEL_GEN(dev_priv) >= 6 &&
2330             dev_priv->rps.enabled &&
2331             dev_priv->gt.active_engines) {
2332                 u32 rpup, rpupei;
2333                 u32 rpdown, rpdownei;
2334
2335                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2336                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2337                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2338                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2339                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2340                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2341
2342                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2343                            rps_power_to_str(dev_priv->rps.power));
2344                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2345                            100 * rpup / rpupei,
2346                            dev_priv->rps.up_threshold);
2347                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2348                            100 * rpdown / rpdownei,
2349                            dev_priv->rps.down_threshold);
2350         } else {
2351                 seq_puts(m, "\nRPS Autotuning inactive\n");
2352         }
2353
2354         return 0;
2355 }
2356
2357 static int i915_llc(struct seq_file *m, void *data)
2358 {
2359         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2360         const bool edram = INTEL_GEN(dev_priv) > 8;
2361
2362         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2363         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2364                    intel_uncore_edram_size(dev_priv)/1024/1024);
2365
2366         return 0;
2367 }
2368
2369 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2370 {
2371         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2372         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2373         u32 tmp, i;
2374
2375         if (!HAS_GUC_UCODE(dev_priv))
2376                 return 0;
2377
2378         seq_printf(m, "GuC firmware status:\n");
2379         seq_printf(m, "\tpath: %s\n",
2380                 guc_fw->guc_fw_path);
2381         seq_printf(m, "\tfetch: %s\n",
2382                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2383         seq_printf(m, "\tload: %s\n",
2384                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2385         seq_printf(m, "\tversion wanted: %d.%d\n",
2386                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2387         seq_printf(m, "\tversion found: %d.%d\n",
2388                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2389         seq_printf(m, "\theader: offset is %d; size = %d\n",
2390                 guc_fw->header_offset, guc_fw->header_size);
2391         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2392                 guc_fw->ucode_offset, guc_fw->ucode_size);
2393         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2394                 guc_fw->rsa_offset, guc_fw->rsa_size);
2395
2396         tmp = I915_READ(GUC_STATUS);
2397
2398         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2399         seq_printf(m, "\tBootrom status = 0x%x\n",
2400                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2401         seq_printf(m, "\tuKernel status = 0x%x\n",
2402                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2403         seq_printf(m, "\tMIA Core status = 0x%x\n",
2404                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2405         seq_puts(m, "\nScratch registers:\n");
2406         for (i = 0; i < 16; i++)
2407                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2408
2409         return 0;
2410 }
2411
2412 static void i915_guc_client_info(struct seq_file *m,
2413                                  struct drm_i915_private *dev_priv,
2414                                  struct i915_guc_client *client)
2415 {
2416         struct intel_engine_cs *engine;
2417         enum intel_engine_id id;
2418         uint64_t tot = 0;
2419
2420         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2421                 client->priority, client->ctx_index, client->proc_desc_offset);
2422         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2423                 client->doorbell_id, client->doorbell_offset, client->cookie);
2424         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2425                 client->wq_size, client->wq_offset, client->wq_tail);
2426
2427         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2428         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2429         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2430
2431         for_each_engine(engine, dev_priv, id) {
2432                 u64 submissions = client->submissions[id];
2433                 tot += submissions;
2434                 seq_printf(m, "\tSubmissions: %llu %s\n",
2435                                 submissions, engine->name);
2436         }
2437         seq_printf(m, "\tTotal: %llu\n", tot);
2438 }
2439
2440 static int i915_guc_info(struct seq_file *m, void *data)
2441 {
2442         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2443         struct drm_device *dev = &dev_priv->drm;
2444         struct intel_guc guc;
2445         struct i915_guc_client client = {};
2446         struct intel_engine_cs *engine;
2447         enum intel_engine_id id;
2448         u64 total = 0;
2449
2450         if (!HAS_GUC_SCHED(dev_priv))
2451                 return 0;
2452
2453         if (mutex_lock_interruptible(&dev->struct_mutex))
2454                 return 0;
2455
2456         /* Take a local copy of the GuC data, so we can dump it at leisure */
2457         guc = dev_priv->guc;
2458         if (guc.execbuf_client)
2459                 client = *guc.execbuf_client;
2460
2461         mutex_unlock(&dev->struct_mutex);
2462
2463         seq_printf(m, "Doorbell map:\n");
2464         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2465         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2466
2467         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2468         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2469         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2470         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2471         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2472
2473         seq_printf(m, "\nGuC submissions:\n");
2474         for_each_engine(engine, dev_priv, id) {
2475                 u64 submissions = guc.submissions[id];
2476                 total += submissions;
2477                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2478                         engine->name, submissions, guc.last_seqno[id]);
2479         }
2480         seq_printf(m, "\t%s: %llu\n", "Total", total);
2481
2482         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2483         i915_guc_client_info(m, dev_priv, &client);
2484
2485         /* Add more as required ... */
2486
2487         return 0;
2488 }
2489
2490 static int i915_guc_log_dump(struct seq_file *m, void *data)
2491 {
2492         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2493         struct drm_i915_gem_object *obj;
2494         int i = 0, pg;
2495
2496         if (!dev_priv->guc.log_vma)
2497                 return 0;
2498
2499         obj = dev_priv->guc.log_vma->obj;
2500         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2501                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2502
2503                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2504                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2505                                    *(log + i), *(log + i + 1),
2506                                    *(log + i + 2), *(log + i + 3));
2507
2508                 kunmap_atomic(log);
2509         }
2510
2511         seq_putc(m, '\n');
2512
2513         return 0;
2514 }
2515
2516 static int i915_edp_psr_status(struct seq_file *m, void *data)
2517 {
2518         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2519         u32 psrperf = 0;
2520         u32 stat[3];
2521         enum pipe pipe;
2522         bool enabled = false;
2523
2524         if (!HAS_PSR(dev_priv)) {
2525                 seq_puts(m, "PSR not supported\n");
2526                 return 0;
2527         }
2528
2529         intel_runtime_pm_get(dev_priv);
2530
2531         mutex_lock(&dev_priv->psr.lock);
2532         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2533         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2534         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2535         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2536         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2537                    dev_priv->psr.busy_frontbuffer_bits);
2538         seq_printf(m, "Re-enable work scheduled: %s\n",
2539                    yesno(work_busy(&dev_priv->psr.work.work)));
2540
2541         if (HAS_DDI(dev_priv))
2542                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2543         else {
2544                 for_each_pipe(dev_priv, pipe) {
2545                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2546                                 VLV_EDP_PSR_CURR_STATE_MASK;
2547                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2548                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2549                                 enabled = true;
2550                 }
2551         }
2552
2553         seq_printf(m, "Main link in standby mode: %s\n",
2554                    yesno(dev_priv->psr.link_standby));
2555
2556         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2557
2558         if (!HAS_DDI(dev_priv))
2559                 for_each_pipe(dev_priv, pipe) {
2560                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2561                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2562                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2563                 }
2564         seq_puts(m, "\n");
2565
2566         /*
2567          * VLV/CHV PSR has no kind of performance counter
2568          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2569          */
2570         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2571                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2572                         EDP_PSR_PERF_CNT_MASK;
2573
2574                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2575         }
2576         mutex_unlock(&dev_priv->psr.lock);
2577
2578         intel_runtime_pm_put(dev_priv);
2579         return 0;
2580 }
2581
2582 static int i915_sink_crc(struct seq_file *m, void *data)
2583 {
2584         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2585         struct drm_device *dev = &dev_priv->drm;
2586         struct intel_connector *connector;
2587         struct intel_dp *intel_dp = NULL;
2588         int ret;
2589         u8 crc[6];
2590
2591         drm_modeset_lock_all(dev);
2592         for_each_intel_connector(dev, connector) {
2593                 struct drm_crtc *crtc;
2594
2595                 if (!connector->base.state->best_encoder)
2596                         continue;
2597
2598                 crtc = connector->base.state->crtc;
2599                 if (!crtc->state->active)
2600                         continue;
2601
2602                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2603                         continue;
2604
2605                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2606
2607                 ret = intel_dp_sink_crc(intel_dp, crc);
2608                 if (ret)
2609                         goto out;
2610
2611                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2612                            crc[0], crc[1], crc[2],
2613                            crc[3], crc[4], crc[5]);
2614                 goto out;
2615         }
2616         ret = -ENODEV;
2617 out:
2618         drm_modeset_unlock_all(dev);
2619         return ret;
2620 }
2621
2622 static int i915_energy_uJ(struct seq_file *m, void *data)
2623 {
2624         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2625         u64 power;
2626         u32 units;
2627
2628         if (INTEL_GEN(dev_priv) < 6)
2629                 return -ENODEV;
2630
2631         intel_runtime_pm_get(dev_priv);
2632
2633         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2634         power = (power & 0x1f00) >> 8;
2635         units = 1000000 / (1 << power); /* convert to uJ */
2636         power = I915_READ(MCH_SECP_NRG_STTS);
2637         power *= units;
2638
2639         intel_runtime_pm_put(dev_priv);
2640
2641         seq_printf(m, "%llu", (long long unsigned)power);
2642
2643         return 0;
2644 }
2645
2646 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2647 {
2648         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2649         struct pci_dev *pdev = dev_priv->drm.pdev;
2650
2651         if (!HAS_RUNTIME_PM(dev_priv))
2652                 seq_puts(m, "Runtime power management not supported\n");
2653
2654         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2655         seq_printf(m, "IRQs disabled: %s\n",
2656                    yesno(!intel_irqs_enabled(dev_priv)));
2657 #ifdef CONFIG_PM
2658         seq_printf(m, "Usage count: %d\n",
2659                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2660 #else
2661         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2662 #endif
2663         seq_printf(m, "PCI device power state: %s [%d]\n",
2664                    pci_power_name(pdev->current_state),
2665                    pdev->current_state);
2666
2667         return 0;
2668 }
2669
2670 static int i915_power_domain_info(struct seq_file *m, void *unused)
2671 {
2672         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2673         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2674         int i;
2675
2676         mutex_lock(&power_domains->lock);
2677
2678         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2679         for (i = 0; i < power_domains->power_well_count; i++) {
2680                 struct i915_power_well *power_well;
2681                 enum intel_display_power_domain power_domain;
2682
2683                 power_well = &power_domains->power_wells[i];
2684                 seq_printf(m, "%-25s %d\n", power_well->name,
2685                            power_well->count);
2686
2687                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2688                      power_domain++) {
2689                         if (!(BIT(power_domain) & power_well->domains))
2690                                 continue;
2691
2692                         seq_printf(m, "  %-23s %d\n",
2693                                  intel_display_power_domain_str(power_domain),
2694                                  power_domains->domain_use_count[power_domain]);
2695                 }
2696         }
2697
2698         mutex_unlock(&power_domains->lock);
2699
2700         return 0;
2701 }
2702
2703 static int i915_dmc_info(struct seq_file *m, void *unused)
2704 {
2705         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2706         struct intel_csr *csr;
2707
2708         if (!HAS_CSR(dev_priv)) {
2709                 seq_puts(m, "not supported\n");
2710                 return 0;
2711         }
2712
2713         csr = &dev_priv->csr;
2714
2715         intel_runtime_pm_get(dev_priv);
2716
2717         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2718         seq_printf(m, "path: %s\n", csr->fw_path);
2719
2720         if (!csr->dmc_payload)
2721                 goto out;
2722
2723         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2724                    CSR_VERSION_MINOR(csr->version));
2725
2726         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2727                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2728                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2729                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2730                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2731         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2732                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2733                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2734         }
2735
2736 out:
2737         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2738         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2739         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2740
2741         intel_runtime_pm_put(dev_priv);
2742
2743         return 0;
2744 }
2745
2746 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2747                                  struct drm_display_mode *mode)
2748 {
2749         int i;
2750
2751         for (i = 0; i < tabs; i++)
2752                 seq_putc(m, '\t');
2753
2754         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2755                    mode->base.id, mode->name,
2756                    mode->vrefresh, mode->clock,
2757                    mode->hdisplay, mode->hsync_start,
2758                    mode->hsync_end, mode->htotal,
2759                    mode->vdisplay, mode->vsync_start,
2760                    mode->vsync_end, mode->vtotal,
2761                    mode->type, mode->flags);
2762 }
2763
2764 static void intel_encoder_info(struct seq_file *m,
2765                                struct intel_crtc *intel_crtc,
2766                                struct intel_encoder *intel_encoder)
2767 {
2768         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2769         struct drm_device *dev = &dev_priv->drm;
2770         struct drm_crtc *crtc = &intel_crtc->base;
2771         struct intel_connector *intel_connector;
2772         struct drm_encoder *encoder;
2773
2774         encoder = &intel_encoder->base;
2775         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2776                    encoder->base.id, encoder->name);
2777         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2778                 struct drm_connector *connector = &intel_connector->base;
2779                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2780                            connector->base.id,
2781                            connector->name,
2782                            drm_get_connector_status_name(connector->status));
2783                 if (connector->status == connector_status_connected) {
2784                         struct drm_display_mode *mode = &crtc->mode;
2785                         seq_printf(m, ", mode:\n");
2786                         intel_seq_print_mode(m, 2, mode);
2787                 } else {
2788                         seq_putc(m, '\n');
2789                 }
2790         }
2791 }
2792
2793 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2794 {
2795         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2796         struct drm_device *dev = &dev_priv->drm;
2797         struct drm_crtc *crtc = &intel_crtc->base;
2798         struct intel_encoder *intel_encoder;
2799         struct drm_plane_state *plane_state = crtc->primary->state;
2800         struct drm_framebuffer *fb = plane_state->fb;
2801
2802         if (fb)
2803                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2804                            fb->base.id, plane_state->src_x >> 16,
2805                            plane_state->src_y >> 16, fb->width, fb->height);
2806         else
2807                 seq_puts(m, "\tprimary plane disabled\n");
2808         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2809                 intel_encoder_info(m, intel_crtc, intel_encoder);
2810 }
2811
2812 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2813 {
2814         struct drm_display_mode *mode = panel->fixed_mode;
2815
2816         seq_printf(m, "\tfixed mode:\n");
2817         intel_seq_print_mode(m, 2, mode);
2818 }
2819
2820 static void intel_dp_info(struct seq_file *m,
2821                           struct intel_connector *intel_connector)
2822 {
2823         struct intel_encoder *intel_encoder = intel_connector->encoder;
2824         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2825
2826         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2827         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2828         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2829                 intel_panel_info(m, &intel_connector->panel);
2830
2831         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2832                                 &intel_dp->aux);
2833 }
2834
2835 static void intel_hdmi_info(struct seq_file *m,
2836                             struct intel_connector *intel_connector)
2837 {
2838         struct intel_encoder *intel_encoder = intel_connector->encoder;
2839         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2840
2841         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2842 }
2843
2844 static void intel_lvds_info(struct seq_file *m,
2845                             struct intel_connector *intel_connector)
2846 {
2847         intel_panel_info(m, &intel_connector->panel);
2848 }
2849
2850 static void intel_connector_info(struct seq_file *m,
2851                                  struct drm_connector *connector)
2852 {
2853         struct intel_connector *intel_connector = to_intel_connector(connector);
2854         struct intel_encoder *intel_encoder = intel_connector->encoder;
2855         struct drm_display_mode *mode;
2856
2857         seq_printf(m, "connector %d: type %s, status: %s\n",
2858                    connector->base.id, connector->name,
2859                    drm_get_connector_status_name(connector->status));
2860         if (connector->status == connector_status_connected) {
2861                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2862                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2863                            connector->display_info.width_mm,
2864                            connector->display_info.height_mm);
2865                 seq_printf(m, "\tsubpixel order: %s\n",
2866                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2867                 seq_printf(m, "\tCEA rev: %d\n",
2868                            connector->display_info.cea_rev);
2869         }
2870
2871         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2872                 return;
2873
2874         switch (connector->connector_type) {
2875         case DRM_MODE_CONNECTOR_DisplayPort:
2876         case DRM_MODE_CONNECTOR_eDP:
2877                 intel_dp_info(m, intel_connector);
2878                 break;
2879         case DRM_MODE_CONNECTOR_LVDS:
2880                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2881                         intel_lvds_info(m, intel_connector);
2882                 break;
2883         case DRM_MODE_CONNECTOR_HDMIA:
2884                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2885                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2886                         intel_hdmi_info(m, intel_connector);
2887                 break;
2888         default:
2889                 break;
2890         }
2891
2892         seq_printf(m, "\tmodes:\n");
2893         list_for_each_entry(mode, &connector->modes, head)
2894                 intel_seq_print_mode(m, 2, mode);
2895 }
2896
2897 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2898 {
2899         u32 state;
2900
2901         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2902                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2903         else
2904                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2905
2906         return state;
2907 }
2908
2909 static bool cursor_position(struct drm_i915_private *dev_priv,
2910                             int pipe, int *x, int *y)
2911 {
2912         u32 pos;
2913
2914         pos = I915_READ(CURPOS(pipe));
2915
2916         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2917         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2918                 *x = -*x;
2919
2920         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2921         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2922                 *y = -*y;
2923
2924         return cursor_active(dev_priv, pipe);
2925 }
2926
2927 static const char *plane_type(enum drm_plane_type type)
2928 {
2929         switch (type) {
2930         case DRM_PLANE_TYPE_OVERLAY:
2931                 return "OVL";
2932         case DRM_PLANE_TYPE_PRIMARY:
2933                 return "PRI";
2934         case DRM_PLANE_TYPE_CURSOR:
2935                 return "CUR";
2936         /*
2937          * Deliberately omitting default: to generate compiler warnings
2938          * when a new drm_plane_type gets added.
2939          */
2940         }
2941
2942         return "unknown";
2943 }
2944
2945 static const char *plane_rotation(unsigned int rotation)
2946 {
2947         static char buf[48];
2948         /*
2949          * According to doc only one DRM_ROTATE_ is allowed but this
2950          * will print them all to visualize if the values are misused
2951          */
2952         snprintf(buf, sizeof(buf),
2953                  "%s%s%s%s%s%s(0x%08x)",
2954                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2955                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2956                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2957                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2958                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2959                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2960                  rotation);
2961
2962         return buf;
2963 }
2964
2965 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2966 {
2967         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2968         struct drm_device *dev = &dev_priv->drm;
2969         struct intel_plane *intel_plane;
2970
2971         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2972                 struct drm_plane_state *state;
2973                 struct drm_plane *plane = &intel_plane->base;
2974                 char *format_name;
2975
2976                 if (!plane->state) {
2977                         seq_puts(m, "plane->state is NULL!\n");
2978                         continue;
2979                 }
2980
2981                 state = plane->state;
2982
2983                 if (state->fb) {
2984                         format_name = drm_get_format_name(state->fb->pixel_format);
2985                 } else {
2986                         format_name = kstrdup("N/A", GFP_KERNEL);
2987                 }
2988
2989                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2990                            plane->base.id,
2991                            plane_type(intel_plane->base.type),
2992                            state->crtc_x, state->crtc_y,
2993                            state->crtc_w, state->crtc_h,
2994                            (state->src_x >> 16),
2995                            ((state->src_x & 0xffff) * 15625) >> 10,
2996                            (state->src_y >> 16),
2997                            ((state->src_y & 0xffff) * 15625) >> 10,
2998                            (state->src_w >> 16),
2999                            ((state->src_w & 0xffff) * 15625) >> 10,
3000                            (state->src_h >> 16),
3001                            ((state->src_h & 0xffff) * 15625) >> 10,
3002                            format_name,
3003                            plane_rotation(state->rotation));
3004
3005                 kfree(format_name);
3006         }
3007 }
3008
3009 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3010 {
3011         struct intel_crtc_state *pipe_config;
3012         int num_scalers = intel_crtc->num_scalers;
3013         int i;
3014
3015         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3016
3017         /* Not all platformas have a scaler */
3018         if (num_scalers) {