drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each engine maintains tables of commands and registers which the parser
  69  * uses in scanning batch buffers submitted to that engine.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implemented via a per-engine length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-engine command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 /*
  90  * A command that requires special handling by the command parser.
  91  */
  92 struct drm_i915_cmd_descriptor {
  93         /*
  94          * Flags describing how the command parser processes the command.
  95          *
  96          * CMD_DESC_FIXED: The command has a fixed length if this is set,
  97          *                 a length mask if not set
  98          * CMD_DESC_SKIP: The command is allowed but does not follow the
  99          *                standard length encoding for the opcode range in
 100          *                which it falls
 101          * CMD_DESC_REJECT: The command is never allowed
 102          * CMD_DESC_REGISTER: The command should be checked against the
 103          *                    register whitelist for the appropriate ring
 104          * CMD_DESC_MASTER: The command is allowed if the submitting process
 105          *                  is the DRM master
 106          */
 107         u32 flags;
 108 #define CMD_DESC_FIXED    (1<<0)
 109 #define CMD_DESC_SKIP     (1<<1)
 110 #define CMD_DESC_REJECT   (1<<2)
 111 #define CMD_DESC_REGISTER (1<<3)
 112 #define CMD_DESC_BITMASK  (1<<4)
 113 #define CMD_DESC_MASTER   (1<<5)
 114
 115         /*
 116          * The command's unique identification bits and the bitmask to get them.
 117          * This isn't strictly the opcode field as defined in the spec and may
 118          * also include type, subtype, and/or subop fields.
 119          */
 120         struct {
 121                 u32 value;
 122                 u32 mask;
 123         } cmd;
 124
 125         /*
 126          * The command's length. The command is either fixed length (i.e. does
 127          * not include a length field) or has a length field mask. The flag
 128          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
 129          * a length mask. All command entries in a command table must include
 130          * length information.
 131          */
 132         union {
 133                 u32 fixed;
 134                 u32 mask;
 135         } length;
 136
 137         /*
 138          * Describes where to find a register address in the command to check
 139          * against the ring's register whitelist. Only valid if flags has the
 140          * CMD_DESC_REGISTER bit set.
 141          *
 142          * A non-zero step value implies that the command may access multiple
 143          * registers in sequence (e.g. LRI), in that case step gives the
 144          * distance in dwords between individual offset fields.
 145          */
 146         struct {
 147                 u32 offset;
 148                 u32 mask;
 149                 u32 step;
 150         } reg;
 151
 152 #define MAX_CMD_DESC_BITMASKS 3
 153         /*
 154          * Describes command checks where a particular dword is masked and
 155          * compared against an expected value. If the command does not match
 156          * the expected value, the parser rejects it. Only valid if flags has
 157          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
 158          * are valid.
 159          *
 160          * If the check specifies a non-zero condition_mask then the parser
 161          * only performs the check when the bits specified by condition_mask
 162          * are non-zero.
 163          */
 164         struct {
 165                 u32 offset;
 166                 u32 mask;
 167                 u32 expected;
 168                 u32 condition_offset;
 169                 u32 condition_mask;
 170         } bits[MAX_CMD_DESC_BITMASKS];
 171 };
 172
 173 /*
 174  * A table of commands requiring special handling by the command parser.
 175  *
 176  * Each engine has an array of tables. Each table consists of an array of
 177  * command descriptors, which must be sorted with command opcodes in
 178  * ascending order.
 179  */
 180 struct drm_i915_cmd_table {
 181         const struct drm_i915_cmd_descriptor *table;
 182         int count;
 183 };
 184
 185 #define STD_MI_OPCODE_SHIFT  (32 - 9)
 186 #define STD_3D_OPCODE_SHIFT  (32 - 16)
 187 #define STD_2D_OPCODE_SHIFT  (32 - 10)
 188 #define STD_MFX_OPCODE_SHIFT (32 - 16)
 189 #define MIN_OPCODE_SHIFT 16
 190
 191 #define CMD(op, opm, f, lm, fl, ...)                            \
 192         {                                                       \
 193                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
 194                 .cmd = { (op), ~0u << (opm) },                  \
 195                 .length = { (lm) },                             \
 196                 __VA_ARGS__                                     \
 197         }
 198
 199 /* Convenience macros to compress the tables */
 200 #define SMI STD_MI_OPCODE_SHIFT
 201 #define S3D STD_3D_OPCODE_SHIFT
 202 #define S2D STD_2D_OPCODE_SHIFT
 203 #define SMFX STD_MFX_OPCODE_SHIFT
 204 #define F true
 205 #define S CMD_DESC_SKIP
 206 #define R CMD_DESC_REJECT
 207 #define W CMD_DESC_REGISTER
 208 #define B CMD_DESC_BITMASK
 209 #define M CMD_DESC_MASTER
 210
 211 /*            Command                          Mask   Fixed Len   Action
 212               ---------------------------------------------------------- */
 213 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 214         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 215         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 216         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 217         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 218         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 219         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 220         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 221         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 222         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 223               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
 224         CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,
 225               .reg = { .offset = 1, .mask = 0x007FFFFC },
 226               .bits = {{
 227                         .offset = 0,
 228                         .mask = MI_GLOBAL_GTT,
 229                         .expected = 0,
 230               }},                                                      ),
 231         CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,
 232               .reg = { .offset = 1, .mask = 0x007FFFFC },
 233               .bits = {{
 234                         .offset = 0,
 235                         .mask = MI_GLOBAL_GTT,
 236                         .expected = 0,
 237               }},                                                      ),
 238         /*
 239          * MI_BATCH_BUFFER_START requires some special handling. It's not
 240          * really a 'skip' action but it doesn't seem like it's worth adding
 241          * a new action. See i915_parse_cmds().
 242          */
 243         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 244 };
 245
 246 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 247         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 248         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 249         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 250         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 251         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 252         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 253         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 254         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 255         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 256               .bits = {{
 257                         .offset = 0,
 258                         .mask = MI_GLOBAL_GTT,
 259                         .expected = 0,
 260               }},                                                      ),
 261         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 262         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 263               .bits = {{
 264                         .offset = 0,
 265                         .mask = MI_GLOBAL_GTT,
 266                         .expected = 0,
 267               }},                                                      ),
 268         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 269               .bits = {{
 270                         .offset = 1,
 271                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 272                         .expected = 0,
 273               }},                                                      ),
 274         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 275               .bits = {{
 276                         .offset = 0,
 277                         .mask = MI_GLOBAL_GTT,
 278                         .expected = 0,
 279               }},                                                      ),
 280         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 281         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 282         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 283               .bits = {{
 284                         .offset = 2,
 285                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 286                         .expected = 0,
 287               }},                                                      ),
 288         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 289         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 290         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 291         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 292               .bits = {{
 293                         .offset = 1,
 294                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 295                         .expected = 0,
 296               },
 297               {
 298                         .offset = 1,
 299                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 300                                  PIPE_CONTROL_STORE_DATA_INDEX),
 301                         .expected = 0,
 302                         .condition_offset = 1,
 303                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 304               }},                                                      ),
 305 };
 306
 307 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 308         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 309         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 310         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 311         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 312         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 313         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 314         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 315         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   W,
 316               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 }    ),
 317         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 318         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 319         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 320         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 321         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 322
 323         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 324         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 325         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 326         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 327         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 328 };
 329
 330 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 331         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 332         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 333         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 334               .bits = {{
 335                         .offset = 0,
 336                         .mask = MI_GLOBAL_GTT,
 337                         .expected = 0,
 338               }},                                                      ),
 339         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 340         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 341               .bits = {{
 342                         .offset = 0,
 343                         .mask = MI_FLUSH_DW_NOTIFY,
 344                         .expected = 0,
 345               },
 346               {
 347                         .offset = 1,
 348                         .mask = MI_FLUSH_DW_USE_GTT,
 349                         .expected = 0,
 350                         .condition_offset = 0,
 351                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 352               },
 353               {
 354                         .offset = 0,
 355                         .mask = MI_FLUSH_DW_STORE_INDEX,
 356                         .expected = 0,
 357                         .condition_offset = 0,
 358                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 359               }},                                                      ),
 360         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 361               .bits = {{
 362                         .offset = 0,
 363                         .mask = MI_GLOBAL_GTT,
 364                         .expected = 0,
 365               }},                                                      ),
 366         /*
 367          * MFX_WAIT doesn't fit the way we handle length for most commands.
 368          * It has a length field but it uses a non-standard length bias.
 369          * It is always 1 dword though, so just treat it as fixed length.
 370          */
 371         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 372 };
 373
 374 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 375         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 376         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 377         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 378               .bits = {{
 379                         .offset = 0,
 380                         .mask = MI_GLOBAL_GTT,
 381                         .expected = 0,
 382               }},                                                      ),
 383         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 384         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 385               .bits = {{
 386                         .offset = 0,
 387                         .mask = MI_FLUSH_DW_NOTIFY,
 388                         .expected = 0,
 389               },
 390               {
 391                         .offset = 1,
 392                         .mask = MI_FLUSH_DW_USE_GTT,
 393                         .expected = 0,
 394                         .condition_offset = 0,
 395                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 396               },
 397               {
 398                         .offset = 0,
 399                         .mask = MI_FLUSH_DW_STORE_INDEX,
 400                         .expected = 0,
 401                         .condition_offset = 0,
 402                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 403               }},                                                      ),
 404         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 405               .bits = {{
 406                         .offset = 0,
 407                         .mask = MI_GLOBAL_GTT,
 408                         .expected = 0,
 409               }},                                                      ),
 410 };
 411
 412 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 413         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 414         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 415               .bits = {{
 416                         .offset = 0,
 417                         .mask = MI_GLOBAL_GTT,
 418                         .expected = 0,
 419               }},                                                      ),
 420         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 421         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 422               .bits = {{
 423                         .offset = 0,
 424                         .mask = MI_FLUSH_DW_NOTIFY,
 425                         .expected = 0,
 426               },
 427               {
 428                         .offset = 1,
 429                         .mask = MI_FLUSH_DW_USE_GTT,
 430                         .expected = 0,
 431                         .condition_offset = 0,
 432                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 433               },
 434               {
 435                         .offset = 0,
 436                         .mask = MI_FLUSH_DW_STORE_INDEX,
 437                         .expected = 0,
 438                         .condition_offset = 0,
 439                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 440               }},                                                      ),
 441         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 442         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 443 };
 444
 445 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 446         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 447         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 448 };
 449
 450 static const struct drm_i915_cmd_descriptor noop_desc =
 451         CMD(MI_NOOP, SMI, F, 1, S);
 452
 453 #undef CMD
 454 #undef SMI
 455 #undef S3D
 456 #undef S2D
 457 #undef SMFX
 458 #undef F
 459 #undef S
 460 #undef R
 461 #undef W
 462 #undef B
 463 #undef M
 464
 465 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 466         { common_cmds, ARRAY_SIZE(common_cmds) },
 467         { render_cmds, ARRAY_SIZE(render_cmds) },
 468 };
 469
 470 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 471         { common_cmds, ARRAY_SIZE(common_cmds) },
 472         { render_cmds, ARRAY_SIZE(render_cmds) },
 473         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 474 };
 475
 476 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 477         { common_cmds, ARRAY_SIZE(common_cmds) },
 478         { video_cmds, ARRAY_SIZE(video_cmds) },
 479 };
 480
 481 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 482         { common_cmds, ARRAY_SIZE(common_cmds) },
 483         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 484 };
 485
 486 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 487         { common_cmds, ARRAY_SIZE(common_cmds) },
 488         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 489 };
 490
 491 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 492         { common_cmds, ARRAY_SIZE(common_cmds) },
 493         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 494         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 495 };
 496
 497 /*
 498  * Register whitelists, sorted by increasing register offset.
 499  */
 500
 501 /*
 502  * An individual whitelist entry granting access to register addr.  If
 503  * mask is non-zero the argument of immediate register writes will be
 504  * AND-ed with mask, and the command will be rejected if the result
 505  * doesn't match value.
 506  *
 507  * Registers with non-zero mask are only allowed to be written using
 508  * LRI.
 509  */
 510 struct drm_i915_reg_descriptor {
 511         i915_reg_t addr;
 512         u32 mask;
 513         u32 value;
 514 };
 515
 516 /* Convenience macro for adding 32-bit registers. */
 517 #define REG32(_reg, ...) \
 518         { .addr = (_reg), __VA_ARGS__ }
 519
 520 /*
 521  * Convenience macro for adding 64-bit registers.
 522  *
 523  * Some registers that userspace accesses are 64 bits. The register
 524  * access commands only allow 32-bit accesses. Hence, we have to include
 525  * entries for both halves of the 64-bit registers.
 526  */
 527 #define REG64(_reg) \
 528         { .addr = _reg }, \
 529         { .addr = _reg ## _UDW }
 530
 531 #define REG64_IDX(_reg, idx) \
 532         { .addr = _reg(idx) }, \
 533         { .addr = _reg ## _UDW(idx) }
 534
 535 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 536         REG64(GPGPU_THREADS_DISPATCHED),
 537         REG64(HS_INVOCATION_COUNT),
 538         REG64(DS_INVOCATION_COUNT),
 539         REG64(IA_VERTICES_COUNT),
 540         REG64(IA_PRIMITIVES_COUNT),
 541         REG64(VS_INVOCATION_COUNT),
 542         REG64(GS_INVOCATION_COUNT),
 543         REG64(GS_PRIMITIVES_COUNT),
 544         REG64(CL_INVOCATION_COUNT),
 545         REG64(CL_PRIMITIVES_COUNT),
 546         REG64(PS_INVOCATION_COUNT),
 547         REG64(PS_DEPTH_COUNT),
 548         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 549         REG64(MI_PREDICATE_SRC0),
 550         REG64(MI_PREDICATE_SRC1),
 551         REG32(GEN7_3DPRIM_END_OFFSET),
 552         REG32(GEN7_3DPRIM_START_VERTEX),
 553         REG32(GEN7_3DPRIM_VERTEX_COUNT),
 554         REG32(GEN7_3DPRIM_INSTANCE_COUNT),
 555         REG32(GEN7_3DPRIM_START_INSTANCE),
 556         REG32(GEN7_3DPRIM_BASE_VERTEX),
 557         REG32(GEN7_GPGPU_DISPATCHDIMX),
 558         REG32(GEN7_GPGPU_DISPATCHDIMY),
 559         REG32(GEN7_GPGPU_DISPATCHDIMZ),
 560         REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
 561         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
 562         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
 563         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
 564         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
 565         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
 566         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
 567         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
 568         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
 569         REG32(GEN7_SO_WRITE_OFFSET(0)),
 570         REG32(GEN7_SO_WRITE_OFFSET(1)),
 571         REG32(GEN7_SO_WRITE_OFFSET(2)),
 572         REG32(GEN7_SO_WRITE_OFFSET(3)),
 573         REG32(GEN7_L3SQCREG1),
 574         REG32(GEN7_L3CNTLREG2),
 575         REG32(GEN7_L3CNTLREG3),
 576         REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
 577 };
 578
 579 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
 580         REG64_IDX(HSW_CS_GPR, 0),
 581         REG64_IDX(HSW_CS_GPR, 1),
 582         REG64_IDX(HSW_CS_GPR, 2),
 583         REG64_IDX(HSW_CS_GPR, 3),
 584         REG64_IDX(HSW_CS_GPR, 4),
 585         REG64_IDX(HSW_CS_GPR, 5),
 586         REG64_IDX(HSW_CS_GPR, 6),
 587         REG64_IDX(HSW_CS_GPR, 7),
 588         REG64_IDX(HSW_CS_GPR, 8),
 589         REG64_IDX(HSW_CS_GPR, 9),
 590         REG64_IDX(HSW_CS_GPR, 10),
 591         REG64_IDX(HSW_CS_GPR, 11),
 592         REG64_IDX(HSW_CS_GPR, 12),
 593         REG64_IDX(HSW_CS_GPR, 13),
 594         REG64_IDX(HSW_CS_GPR, 14),
 595         REG64_IDX(HSW_CS_GPR, 15),
 596         REG32(HSW_SCRATCH1,
 597               .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
 598               .value = 0),
 599         REG32(HSW_ROW_CHICKEN3,
 600               .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
 601                         HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 602               .value = 0),
 603 };
 604
 605 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
 606         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 607         REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
 608         REG32(BCS_SWCTRL),
 609         REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
 610 };
 611
 612 static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
 613         REG32(FORCEWAKE_MT),
 614         REG32(DERRMR),
 615         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
 616         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
 617         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
 618 };
 619
 620 static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
 621         REG32(FORCEWAKE_MT),
 622         REG32(DERRMR),
 623 };
 624
 625 #undef REG64
 626 #undef REG32
 627
 628 struct drm_i915_reg_table {
 629         const struct drm_i915_reg_descriptor *regs;
 630         int num_regs;
 631         bool master;
 632 };
 633
 634 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
 635         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
 636         { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
 637 };
 638
 639 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
 640         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
 641         { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
 642 };
 643
 644 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
 645         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
 646         { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
 647         { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
 648 };
 649
 650 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
 651         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
 652         { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
 653 };
 654
 655 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 656 {
 657         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 658         u32 subclient =
 659                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 660
 661         if (client == INSTR_MI_CLIENT)
 662                 return 0x3F;
 663         else if (client == INSTR_RC_CLIENT) {
 664                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 665                         return 0xFFFF;
 666                 else
 667                         return 0xFF;
 668         }
 669
 670         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 671         return 0;
 672 }
 673
 674 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 675 {
 676         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 677         u32 subclient =
 678                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 679         u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
 680
 681         if (client == INSTR_MI_CLIENT)
 682                 return 0x3F;
 683         else if (client == INSTR_RC_CLIENT) {
 684                 if (subclient == INSTR_MEDIA_SUBCLIENT) {
 685                         if (op == 6)
 686                                 return 0xFFFF;
 687                         else
 688                                 return 0xFFF;
 689                 } else
 690                         return 0xFF;
 691         }
 692
 693         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 694         return 0;
 695 }
 696
 697 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 698 {
 699         u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
 700
 701         if (client == INSTR_MI_CLIENT)
 702                 return 0x3F;
 703         else if (client == INSTR_BC_CLIENT)
 704                 return 0xFF;
 705
 706         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 707         return 0;
 708 }
 709
 710 static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
 711                                  const struct drm_i915_cmd_table *cmd_tables,
 712                                  int cmd_table_count)
 713 {
 714         int i;
 715         bool ret = true;
 716
 717         if (!cmd_tables || cmd_table_count == 0)
 718                 return true;
 719
 720         for (i = 0; i < cmd_table_count; i++) {
 721                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 722                 u32 previous = 0;
 723                 int j;
 724
 725                 for (j = 0; j < table->count; j++) {
 726                         const struct drm_i915_cmd_descriptor *desc =
 727                                 &table->table[j];
 728                         u32 curr = desc->cmd.value & desc->cmd.mask;
 729
 730                         if (curr < previous) {
 731                                 DRM_ERROR("CMD: %s [%d] command table not sorted: "
 732                                           "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 733                                           engine->name, engine->id,
 734                                           i, j, curr, previous);
 735                                 ret = false;
 736                         }
 737
 738                         previous = curr;
 739                 }
 740         }
 741
 742         return ret;
 743 }
 744
 745 static bool check_sorted(const struct intel_engine_cs *engine,
 746                          const struct drm_i915_reg_descriptor *reg_table,
 747                          int reg_count)
 748 {
 749         int i;
 750         u32 previous = 0;
 751         bool ret = true;
 752
 753         for (i = 0; i < reg_count; i++) {
 754                 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
 755
 756                 if (curr < previous) {
 757                         DRM_ERROR("CMD: %s [%d] register table not sorted: "
 758                                   "entry=%d reg=0x%08X prev=0x%08X\n",
 759                                   engine->name, engine->id,
 760                                   i, curr, previous);
 761                         ret = false;
 762                 }
 763
 764                 previous = curr;
 765         }
 766
 767         return ret;
 768 }
 769
 770 static bool validate_regs_sorted(struct intel_engine_cs *engine)
 771 {
 772         int i;
 773         const struct drm_i915_reg_table *table;
 774
 775         for (i = 0; i < engine->reg_table_count; i++) {
 776                 table = &engine->reg_tables[i];
 777                 if (!check_sorted(engine, table->regs, table->num_regs))
 778                         return false;
 779         }
 780
 781         return true;
 782 }
 783
 784 struct cmd_node {
 785         const struct drm_i915_cmd_descriptor *desc;
 786         struct hlist_node node;
 787 };
 788
 789 /*
 790  * Different command ranges have different numbers of bits for the opcode. For
 791  * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
 792  * problem is that, for example, MI commands use bits 22:16 for other fields
 793  * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
 794  * we mask a command from a batch it could hash to the wrong bucket due to
 795  * non-opcode bits being set. But if we don't include those bits, some 3D
 796  * commands may hash to the same bucket due to not including opcode bits that
 797  * make the command unique. For now, we will risk hashing to the same bucket.
 798  */
 799 static inline u32 cmd_header_key(u32 x)
 800 {
 801         u32 shift;
 802
 803         switch (x >> INSTR_CLIENT_SHIFT) {
 804         default:
 805         case INSTR_MI_CLIENT:
 806                 shift = STD_MI_OPCODE_SHIFT;
 807                 break;
 808         case INSTR_RC_CLIENT:
 809                 shift = STD_3D_OPCODE_SHIFT;
 810                 break;
 811         case INSTR_BC_CLIENT:
 812                 shift = STD_2D_OPCODE_SHIFT;
 813                 break;
 814         }
 815
 816         return x >> shift;
 817 }
 818
 819 static int init_hash_table(struct intel_engine_cs *engine,
 820                            const struct drm_i915_cmd_table *cmd_tables,
 821                            int cmd_table_count)
 822 {
 823         int i, j;
 824
 825         hash_init(engine->cmd_hash);
 826
 827         for (i = 0; i < cmd_table_count; i++) {
 828                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 829
 830                 for (j = 0; j < table->count; j++) {
 831                         const struct drm_i915_cmd_descriptor *desc =
 832                                 &table->table[j];
 833                         struct cmd_node *desc_node =
 834                                 kmalloc(sizeof(*desc_node), GFP_KERNEL);
 835
 836                         if (!desc_node)
 837                                 return -ENOMEM;
 838
 839                         desc_node->desc = desc;
 840                         hash_add(engine->cmd_hash, &desc_node->node,
 841                                  cmd_header_key(desc->cmd.value));
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847
 848 static void fini_hash_table(struct intel_engine_cs *engine)
 849 {
 850         struct hlist_node *tmp;
 851         struct cmd_node *desc_node;
 852         int i;
 853
 854         hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
 855                 hash_del(&desc_node->node);
 856                 kfree(desc_node);
 857         }
 858 }
 859
 860 /**
 861  * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
 862  * @engine: the engine to initialize
 863  *
 864  * Optionally initializes fields related to batch buffer command parsing in the
 865  * struct intel_engine_cs based on whether the platform requires software
 866  * command parsing.
 867  */
 868 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
 869 {
 870         const struct drm_i915_cmd_table *cmd_tables;
 871         int cmd_table_count;
 872         int ret;
 873
 874         if (!IS_GEN7(engine->i915))
 875                 return;
 876
 877         switch (engine->id) {
 878         case RCS:
 879                 if (IS_HASWELL(engine->i915)) {
 880                         cmd_tables = hsw_render_ring_cmds;
 881                         cmd_table_count =
 882                                 ARRAY_SIZE(hsw_render_ring_cmds);
 883                 } else {
 884                         cmd_tables = gen7_render_cmds;
 885                         cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 886                 }
 887
 888                 if (IS_HASWELL(engine->i915)) {
 889                         engine->reg_tables = hsw_render_reg_tables;
 890                         engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
 891                 } else {
 892                         engine->reg_tables = ivb_render_reg_tables;
 893                         engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
 894                 }
 895
 896                 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 897                 break;
 898         case VCS:
 899                 cmd_tables = gen7_video_cmds;
 900                 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 901                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 902                 break;
 903         case BCS:
 904                 if (IS_HASWELL(engine->i915)) {
 905                         cmd_tables = hsw_blt_ring_cmds;
 906                         cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 907                 } else {
 908                         cmd_tables = gen7_blt_cmds;
 909                         cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 910                 }
 911
 912                 if (IS_HASWELL(engine->i915)) {
 913                         engine->reg_tables = hsw_blt_reg_tables;
 914                         engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
 915                 } else {
 916                         engine->reg_tables = ivb_blt_reg_tables;
 917                         engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
 918                 }
 919
 920                 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 921                 break;
 922         case VECS:
 923                 cmd_tables = hsw_vebox_cmds;
 924                 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 925                 /* VECS can use the same length_mask function as VCS */
 926                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 927                 break;
 928         default:
 929                 MISSING_CASE(engine->id);
 930                 return;
 931         }
 932
 933         if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
 934                 DRM_ERROR("%s: command descriptions are not sorted\n",
 935                           engine->name);
 936                 return;
 937         }
 938         if (!validate_regs_sorted(engine)) {
 939                 DRM_ERROR("%s: registers are not sorted\n", engine->name);
 940                 return;
 941         }
 942
 943         ret = init_hash_table(engine, cmd_tables, cmd_table_count);
 944         if (ret) {
 945                 DRM_ERROR("%s: initialised failed!\n", engine->name);
 946                 fini_hash_table(engine);
 947                 return;
 948         }
 949
 950         engine->needs_cmd_parser = true;
 951 }
 952
 953 /**
 954  * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
 955  * @engine: the engine to clean up
 956  *
 957  * Releases any resources related to command parsing that may have been
 958  * initialized for the specified engine.
 959  */
 960 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
 961 {
 962         if (!engine->needs_cmd_parser)
 963                 return;
 964
 965         fini_hash_table(engine);
 966 }
 967
 968 static const struct drm_i915_cmd_descriptor*
 969 find_cmd_in_table(struct intel_engine_cs *engine,
 970                   u32 cmd_header)
 971 {
 972         struct cmd_node *desc_node;
 973
 974         hash_for_each_possible(engine->cmd_hash, desc_node, node,
 975                                cmd_header_key(cmd_header)) {
 976                 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
 977                 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
 978                         return desc;
 979         }
 980
 981         return NULL;
 982 }
 983
 984 /*
 985  * Returns a pointer to a descriptor for the command specified by cmd_header.
 986  *
 987  * The caller must supply space for a default descriptor via the default_desc
 988  * parameter. If no descriptor for the specified command exists in the engine's
 989  * command parser tables, this function fills in default_desc based on the
 990  * engine's default length encoding and returns default_desc.
 991  */
 992 static const struct drm_i915_cmd_descriptor*
 993 find_cmd(struct intel_engine_cs *engine,
 994          u32 cmd_header,
 995          const struct drm_i915_cmd_descriptor *desc,
 996          struct drm_i915_cmd_descriptor *default_desc)
 997 {
 998         u32 mask;
 999
1000         if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1001                 return desc;
1002
1003         desc = find_cmd_in_table(engine, cmd_header);
1004         if (desc)
1005                 return desc;
1006
1007         mask = engine->get_cmd_length_mask(cmd_header);
1008         if (!mask)
1009                 return NULL;
1010
1011         default_desc->cmd.value = cmd_header;
1012         default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1013         default_desc->length.mask = mask;
1014         default_desc->flags = CMD_DESC_SKIP;
1015         return default_desc;
1016 }
1017
1018 static const struct drm_i915_reg_descriptor *
1019 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1020 {
1021         int start = 0, end = count;
1022         while (start < end) {
1023                 int mid = start + (end - start) / 2;
1024                 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1025                 if (ret < 0)
1026                         end = mid;
1027                 else if (ret > 0)
1028                         start = mid + 1;
1029                 else
1030                         return &table[mid];
1031         }
1032         return NULL;
1033 }
1034
1035 static const struct drm_i915_reg_descriptor *
1036 find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr)
1037 {
1038         const struct drm_i915_reg_table *table = engine->reg_tables;
1039         int count = engine->reg_table_count;
1040
1041         do {
1042                 if (!table->master || is_master) {
1043                         const struct drm_i915_reg_descriptor *reg;
1044
1045                         reg = __find_reg(table->regs, table->num_regs, addr);
1046                         if (reg != NULL)
1047                                 return reg;
1048                 }
1049         } while (table++, --count);
1050
1051         return NULL;
1052 }
1053
1054 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1055 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1056                        struct drm_i915_gem_object *src_obj,
1057                        u32 batch_start_offset,
1058                        u32 batch_len,
1059                        bool *needs_clflush_after)
1060 {
1061         unsigned int src_needs_clflush;
1062         unsigned int dst_needs_clflush;
1063         void *dst, *src;
1064         int ret;
1065
1066         ret = i915_gem_obj_prepare_shmem_read(src_obj, &src_needs_clflush);
1067         if (ret)
1068                 return ERR_PTR(ret);
1069
1070         ret = i915_gem_obj_prepare_shmem_write(dst_obj, &dst_needs_clflush);
1071         if (ret) {
1072                 dst = ERR_PTR(ret);
1073                 goto unpin_src;
1074         }
1075
1076         dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
1077         if (IS_ERR(dst))
1078                 goto unpin_dst;
1079
1080         src = ERR_PTR(-ENODEV);
1081         if (src_needs_clflush &&
1082             i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {
1083                 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1084                 if (!IS_ERR(src)) {
1085                         i915_memcpy_from_wc(dst,
1086                                             src + batch_start_offset,
1087                                             ALIGN(batch_len, 16));
1088                         i915_gem_object_unpin_map(src_obj);
1089                 }
1090         }
1091         if (IS_ERR(src)) {
1092                 void *ptr;
1093                 int offset, n;
1094
1095                 offset = offset_in_page(batch_start_offset);
1096
1097                 /* We can avoid clflushing partial cachelines before the write
1098                  * if we only every write full cache-lines. Since we know that
1099                  * both the source and destination are in multiples of
1100                  * PAGE_SIZE, we can simply round up to the next cacheline.
1101                  * We don't care about copying too much here as we only
1102                  * validate up to the end of the batch.
1103                  */
1104                 if (dst_needs_clflush & CLFLUSH_BEFORE)
1105                         batch_len = roundup(batch_len,
1106                                             boot_cpu_data.x86_clflush_size);
1107
1108                 ptr = dst;
1109                 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) {
1110                         int len = min_t(int, batch_len, PAGE_SIZE - offset);
1111
1112                         src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1113                         if (src_needs_clflush)
1114                                 drm_clflush_virt_range(src + offset, len);
1115                         memcpy(ptr, src + offset, len);
1116                         kunmap_atomic(src);
1117
1118                         ptr += len;
1119                         batch_len -= len;
1120                         offset = 0;
1121                 }
1122         }
1123
1124         /* dst_obj is returned with vmap pinned */
1125         *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1126
1127 unpin_dst:
1128         i915_gem_obj_finish_shmem_access(dst_obj);
1129 unpin_src:
1130         i915_gem_obj_finish_shmem_access(src_obj);
1131         return dst;
1132 }
1133
1134 static bool check_cmd(const struct intel_engine_cs *engine,
1135                       const struct drm_i915_cmd_descriptor *desc,
1136                       const u32 *cmd, u32 length,
1137                       const bool is_master)
1138 {
1139         if (desc->flags & CMD_DESC_SKIP)
1140                 return true;
1141
1142         if (desc->flags & CMD_DESC_REJECT) {
1143                 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1144                 return false;
1145         }
1146
1147         if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
1148                 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
1149                                  *cmd);
1150                 return false;
1151         }
1152
1153         if (desc->flags & CMD_DESC_REGISTER) {
1154                 /*
1155                  * Get the distance between individual register offset
1156                  * fields if the command can perform more than one
1157                  * access at a time.
1158                  */
1159                 const u32 step = desc->reg.step ? desc->reg.step : length;
1160                 u32 offset;
1161
1162                 for (offset = desc->reg.offset; offset < length;
1163                      offset += step) {
1164                         const u32 reg_addr = cmd[offset] & desc->reg.mask;
1165                         const struct drm_i915_reg_descriptor *reg =
1166                                 find_reg(engine, is_master, reg_addr);
1167
1168                         if (!reg) {
1169                                 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1170                                                  reg_addr, *cmd, engine->name);
1171                                 return false;
1172                         }
1173
1174                         /*
1175                          * Check the value written to the register against the
1176                          * allowed mask/value pair given in the whitelist entry.
1177                          */
1178                         if (reg->mask) {
1179                                 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1180                                         DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1181                                                          reg_addr);
1182                                         return false;
1183                                 }
1184
1185                                 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1186                                         DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
1187                                                          reg_addr);
1188                                         return false;
1189                                 }
1190
1191                                 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1192                                     (offset + 2 > length ||
1193                                      (cmd[offset + 1] & reg->mask) != reg->value)) {
1194                                         DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1195                                                          reg_addr);
1196                                         return false;
1197                                 }
1198                         }
1199                 }
1200         }
1201
1202         if (desc->flags & CMD_DESC_BITMASK) {
1203                 int i;
1204
1205                 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1206                         u32 dword;
1207
1208                         if (desc->bits[i].mask == 0)
1209                                 break;
1210
1211                         if (desc->bits[i].condition_mask != 0) {
1212                                 u32 offset =
1213                                         desc->bits[i].condition_offset;
1214                                 u32 condition = cmd[offset] &
1215                                         desc->bits[i].condition_mask;
1216
1217                                 if (condition == 0)
1218                                         continue;
1219                         }
1220
1221                         dword = cmd[desc->bits[i].offset] &
1222                                 desc->bits[i].mask;
1223
1224                         if (dword != desc->bits[i].expected) {
1225                                 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1226                                                  *cmd,
1227                                                  desc->bits[i].mask,
1228                                                  desc->bits[i].expected,
1229                                                  dword, engine->name);
1230                                 return false;
1231                         }
1232                 }
1233         }
1234
1235         return true;
1236 }
1237
1238 #define LENGTH_BIAS 2
1239
1240 /**
1241  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1242  * @engine: the engine on which the batch is to execute
1243  * @batch_obj: the batch buffer in question
1244  * @shadow_batch_obj: copy of the batch buffer in question
1245  * @batch_start_offset: byte offset in the batch at which execution starts
1246  * @batch_len: length of the commands in batch_obj
1247  * @is_master: is the submitting process the drm master?
1248  *
1249  * Parses the specified batch buffer looking for privilege violations as
1250  * described in the overview.
1251  *
1252  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1253  * if the batch appears legal but should use hardware parsing
1254  */
1255 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1256                             struct drm_i915_gem_object *batch_obj,
1257                             struct drm_i915_gem_object *shadow_batch_obj,
1258                             u32 batch_start_offset,
1259                             u32 batch_len,
1260                             bool is_master)
1261 {
1262         u32 *cmd, *batch_end;
1263         struct drm_i915_cmd_descriptor default_desc = noop_desc;
1264         const struct drm_i915_cmd_descriptor *desc = &default_desc;
1265         bool needs_clflush_after = false;
1266         int ret = 0;
1267
1268         cmd = copy_batch(shadow_batch_obj, batch_obj,
1269                          batch_start_offset, batch_len,
1270                          &needs_clflush_after);
1271         if (IS_ERR(cmd)) {
1272                 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1273                 return PTR_ERR(cmd);
1274         }
1275
1276         /*
1277          * We use the batch length as size because the shadow object is as
1278          * large or larger and copy_batch() will write MI_NOPs to the extra
1279          * space. Parsing should be faster in some cases this way.
1280          */
1281         batch_end = cmd + (batch_len / sizeof(*batch_end));
1282         do {
1283                 u32 length;
1284
1285                 if (*cmd == MI_BATCH_BUFFER_END) {
1286                         if (needs_clflush_after) {
1287                                 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);
1288                                 drm_clflush_virt_range(ptr,
1289                                                        (void *)(cmd + 1) - ptr);
1290                         }
1291                         break;
1292                 }
1293
1294                 desc = find_cmd(engine, *cmd, desc, &default_desc);
1295                 if (!desc) {
1296                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1297                                          *cmd);
1298                         ret = -EINVAL;
1299                         break;
1300                 }
1301
1302                 /*
1303                  * If the batch buffer contains a chained batch, return an
1304                  * error that tells the caller to abort and dispatch the
1305                  * workload as a non-secure batch.
1306                  */
1307                 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1308                         ret = -EACCES;
1309                         break;
1310                 }
1311
1312                 if (desc->flags & CMD_DESC_FIXED)
1313                         length = desc->length.fixed;
1314                 else
1315                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1316
1317                 if ((batch_end - cmd) < length) {
1318                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1319                                          *cmd,
1320                                          length,
1321                                          batch_end - cmd);
1322                         ret = -EINVAL;
1323                         break;
1324                 }
1325
1326                 if (!check_cmd(engine, desc, cmd, length, is_master)) {
1327                         ret = -EACCES;
1328                         break;
1329                 }
1330
1331                 cmd += length;
1332                 if  (cmd >= batch_end) {
1333                         DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1334                         ret = -EINVAL;
1335                         break;
1336                 }
1337         } while (1);
1338
1339         i915_gem_object_unpin_map(shadow_batch_obj);
1340         return ret;
1341 }
1342
1343 /**
1344  * i915_cmd_parser_get_version() - get the cmd parser version number
1345  * @dev_priv: i915 device private
1346  *
1347  * The cmd parser maintains a simple increasing integer version number suitable
1348  * for passing to userspace clients to determine what operations are permitted.
1349  *
1350  * Return: the current version number of the cmd parser
1351  */
1352 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1353 {
1354         struct intel_engine_cs *engine;
1355         enum intel_engine_id id;
1356         bool active = false;
1357
1358         /* If the command parser is not enabled, report 0 - unsupported */
1359         for_each_engine(engine, dev_priv, id) {
1360                 if (engine->needs_cmd_parser) {
1361                         active = true;
1362                         break;
1363                 }
1364         }
1365         if (!active)
1366                 return 0;
1367
1368         /*
1369          * Command parser version history
1370          *
1371          * 1. Initial version. Checks batches and reports violations, but leaves
1372          *    hardware parsing enabled (so does not allow new use cases).
1373          * 2. Allow access to the MI_PREDICATE_SRC0 and
1374          *    MI_PREDICATE_SRC1 registers.
1375          * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1376          * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1377          * 5. GPGPU dispatch compute indirect registers.
1378          * 6. TIMESTAMP register and Haswell CS GPR registers
1379          * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1380          * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1381          *    rely on the HW to NOOP disallowed commands as it would without
1382          *    the parser enabled.
1383          * 9. Don't whitelist or handle oacontrol specially, as ownership
1384          *    for oacontrol state is moving to i915-perf.
1385          */
1386         return 9;
1387 }