drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "i915_drv.h"
  39 #include "i915_gem_pm.h"
  40 #include "gvt.h"
  41
  42 #define RING_CTX_OFF(x) \
  43         offsetof(struct execlist_ring_context, x)
  44
  45 static void set_context_pdp_root_pointer(
  46                 struct execlist_ring_context *ring_context,
  47                 u32 pdp[8])
  48 {
  49         int i;
  50
  51         for (i = 0; i < 8; i++)
  52                 ring_context->pdps[i].val = pdp[7 - i];
  53 }
  54
  55 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  56 {
  57         struct drm_i915_gem_object *ctx_obj =
  58                 workload->req->hw_context->state->obj;
  59         struct execlist_ring_context *shadow_ring_context;
  60         struct page *page;
  61
  62         if (WARN_ON(!workload->shadow_mm))
  63                 return;
  64
  65         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  66                 return;
  67
  68         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
  69         shadow_ring_context = kmap(page);
  70         set_context_pdp_root_pointer(shadow_ring_context,
  71                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  72         kunmap(page);
  73 }
  74
  75 /*
  76  * when populating shadow ctx from guest, we should not overrride oa related
  77  * registers, so that they will not be overlapped by guest oa configs. Thus
  78  * made it possible to capture oa data from host for both host and guests.
  79  */
  80 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  81                 u32 *reg_state, bool save)
  82 {
  83         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
  84         u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
  85         u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
  86         int i = 0;
  87         u32 flex_mmio[] = {
  88                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  89                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  90                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  91                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  92                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  94                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  95         };
  96
  97         if (workload->ring_id != RCS0)
  98                 return;
  99
 100         if (save) {
 101                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 102
 103                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 104                         u32 state_offset = ctx_flexeu0 + i * 2;
 105
 106                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 107                 }
 108         } else {
 109                 reg_state[ctx_oactxctrl] =
 110                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 111                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 112
 113                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 114                         u32 state_offset = ctx_flexeu0 + i * 2;
 115                         u32 mmio = flex_mmio[i];
 116
 117                         reg_state[state_offset] = mmio;
 118                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 119                 }
 120         }
 121 }
 122
 123 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 124 {
 125         struct intel_vgpu *vgpu = workload->vgpu;
 126         struct intel_gvt *gvt = vgpu->gvt;
 127         int ring_id = workload->ring_id;
 128         struct drm_i915_gem_object *ctx_obj =
 129                 workload->req->hw_context->state->obj;
 130         struct execlist_ring_context *shadow_ring_context;
 131         struct page *page;
 132         void *dst;
 133         unsigned long context_gpa, context_page_num;
 134         int i;
 135
 136         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 137         shadow_ring_context = kmap(page);
 138
 139         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 140 #define COPY_REG(name) \
 141         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 142                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 143 #define COPY_REG_MASKED(name) {\
 144                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 145                                               + RING_CTX_OFF(name.val),\
 146                                               &shadow_ring_context->name.val, 4);\
 147                 shadow_ring_context->name.val |= 0xffff << 16;\
 148         }
 149
 150         COPY_REG_MASKED(ctx_ctrl);
 151         COPY_REG(ctx_timestamp);
 152
 153         if (ring_id == RCS0) {
 154                 COPY_REG(bb_per_ctx_ptr);
 155                 COPY_REG(rcs_indirect_ctx);
 156                 COPY_REG(rcs_indirect_ctx_offset);
 157         }
 158 #undef COPY_REG
 159 #undef COPY_REG_MASKED
 160
 161         intel_gvt_hypervisor_read_gpa(vgpu,
 162                         workload->ring_context_gpa +
 163                         sizeof(*shadow_ring_context),
 164                         (void *)shadow_ring_context +
 165                         sizeof(*shadow_ring_context),
 166                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 167
 168         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 169         kunmap(page);
 170
 171         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
 172                 return 0;
 173
 174         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
 175                         workload->ctx_desc.lrca);
 176
 177         context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
 178
 179         context_page_num = context_page_num >> PAGE_SHIFT;
 180
 181         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
 182                 context_page_num = 19;
 183
 184         i = 2;
 185         while (i < context_page_num) {
 186                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 187                                 (u32)((workload->ctx_desc.lrca + i) <<
 188                                 I915_GTT_PAGE_SHIFT));
 189                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 190                         gvt_vgpu_err("Invalid guest context descriptor\n");
 191                         return -EFAULT;
 192                 }
 193
 194                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
 195                 dst = kmap(page);
 196                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
 197                                 I915_GTT_PAGE_SIZE);
 198                 kunmap(page);
 199                 i++;
 200         }
 201         return 0;
 202 }
 203
 204 static inline bool is_gvt_request(struct i915_request *req)
 205 {
 206         return i915_gem_context_force_single_submission(req->gem_context);
 207 }
 208
 209 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
 210 {
 211         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 212         u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
 213         i915_reg_t reg;
 214
 215         reg = RING_INSTDONE(ring_base);
 216         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 217         reg = RING_ACTHD(ring_base);
 218         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 219         reg = RING_ACTHD_UDW(ring_base);
 220         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
 221 }
 222
 223 static int shadow_context_status_change(struct notifier_block *nb,
 224                 unsigned long action, void *data)
 225 {
 226         struct i915_request *req = data;
 227         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 228                                 shadow_ctx_notifier_block[req->engine->id]);
 229         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 230         enum intel_engine_id ring_id = req->engine->id;
 231         struct intel_vgpu_workload *workload;
 232         unsigned long flags;
 233
 234         if (!is_gvt_request(req)) {
 235                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 236                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 237                     scheduler->engine_owner[ring_id]) {
 238                         /* Switch ring from vGPU to host. */
 239                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 240                                               NULL, ring_id);
 241                         scheduler->engine_owner[ring_id] = NULL;
 242                 }
 243                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 244
 245                 return NOTIFY_OK;
 246         }
 247
 248         workload = scheduler->current_workload[ring_id];
 249         if (unlikely(!workload))
 250                 return NOTIFY_OK;
 251
 252         switch (action) {
 253         case INTEL_CONTEXT_SCHEDULE_IN:
 254                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 255                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 256                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 257                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 258                                               workload->vgpu, ring_id);
 259                         scheduler->engine_owner[ring_id] = workload->vgpu;
 260                 } else
 261                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 262                                       ring_id, workload->vgpu->id);
 263                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 264                 atomic_set(&workload->shadow_ctx_active, 1);
 265                 break;
 266         case INTEL_CONTEXT_SCHEDULE_OUT:
 267                 save_ring_hw_state(workload->vgpu, ring_id);
 268                 atomic_set(&workload->shadow_ctx_active, 0);
 269                 break;
 270         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 271                 save_ring_hw_state(workload->vgpu, ring_id);
 272                 break;
 273         default:
 274                 WARN_ON(1);
 275                 return NOTIFY_OK;
 276         }
 277         wake_up(&workload->shadow_ctx_status_wq);
 278         return NOTIFY_OK;
 279 }
 280
 281 static void
 282 shadow_context_descriptor_update(struct intel_context *ce,
 283                                  struct intel_vgpu_workload *workload)
 284 {
 285         u64 desc = ce->lrc_desc;
 286
 287         /*
 288          * Update bits 0-11 of the context descriptor which includes flags
 289          * like GEN8_CTX_* cached in desc_template
 290          */
 291         desc &= U64_MAX << 12;
 292         desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
 293
 294         desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 295         desc |= workload->ctx_desc.addressing_mode <<
 296                 GEN8_CTX_ADDRESSING_MODE_SHIFT;
 297
 298         ce->lrc_desc = desc;
 299 }
 300
 301 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 302 {
 303         struct intel_vgpu *vgpu = workload->vgpu;
 304         struct i915_request *req = workload->req;
 305         void *shadow_ring_buffer_va;
 306         u32 *cs;
 307         int err;
 308
 309         if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context))
 310                 intel_vgpu_restore_inhibit_context(vgpu, req);
 311
 312         /*
 313          * To track whether a request has started on HW, we can emit a
 314          * breadcrumb at the beginning of the request and check its
 315          * timeline's HWSP to see if the breadcrumb has advanced past the
 316          * start of this request. Actually, the request must have the
 317          * init_breadcrumb if its timeline set has_init_bread_crumb, or the
 318          * scheduler might get a wrong state of it during reset. Since the
 319          * requests from gvt always set the has_init_breadcrumb flag, here
 320          * need to do the emit_init_breadcrumb for all the requests.
 321          */
 322         if (req->engine->emit_init_breadcrumb) {
 323                 err = req->engine->emit_init_breadcrumb(req);
 324                 if (err) {
 325                         gvt_vgpu_err("fail to emit init breadcrumb\n");
 326                         return err;
 327                 }
 328         }
 329
 330         /* allocate shadow ring buffer */
 331         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 332         if (IS_ERR(cs)) {
 333                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 334                         workload->rb_len);
 335                 return PTR_ERR(cs);
 336         }
 337
 338         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 339
 340         /* get shadow ring buffer va */
 341         workload->shadow_ring_buffer_va = cs;
 342
 343         memcpy(cs, shadow_ring_buffer_va,
 344                         workload->rb_len);
 345
 346         cs += workload->rb_len / sizeof(u32);
 347         intel_ring_advance(workload->req, cs);
 348
 349         return 0;
 350 }
 351
 352 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 353 {
 354         if (!wa_ctx->indirect_ctx.obj)
 355                 return;
 356
 357         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 358         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 359
 360         wa_ctx->indirect_ctx.obj = NULL;
 361         wa_ctx->indirect_ctx.shadow_va = NULL;
 362 }
 363
 364 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 365                                          struct i915_gem_context *ctx)
 366 {
 367         struct intel_vgpu_mm *mm = workload->shadow_mm;
 368         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
 369         int i = 0;
 370
 371         if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
 372                 return -EINVAL;
 373
 374         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 375                 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0];
 376         } else {
 377                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 378                         px_dma(ppgtt->pdp.page_directory[i]) =
 379                                 mm->ppgtt_mm.shadow_pdps[i];
 380                 }
 381         }
 382
 383         return 0;
 384 }
 385
 386 static int
 387 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
 388 {
 389         struct intel_vgpu *vgpu = workload->vgpu;
 390         struct intel_vgpu_submission *s = &vgpu->submission;
 391         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 392         struct i915_request *rq;
 393
 394         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 395
 396         if (workload->req)
 397                 return 0;
 398
 399         rq = i915_request_create(s->shadow[workload->ring_id]);
 400         if (IS_ERR(rq)) {
 401                 gvt_vgpu_err("fail to allocate gem request\n");
 402                 return PTR_ERR(rq);
 403         }
 404
 405         workload->req = i915_request_get(rq);
 406         return 0;
 407 }
 408
 409 /**
 410  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 411  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 412  * @workload: an abstract entity for each execlist submission.
 413  *
 414  * This function is called before the workload submitting to i915, to make
 415  * sure the content of the workload is valid.
 416  */
 417 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 418 {
 419         struct intel_vgpu *vgpu = workload->vgpu;
 420         struct intel_vgpu_submission *s = &vgpu->submission;
 421         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 422         int ret;
 423
 424         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 425
 426         if (workload->shadow)
 427                 return 0;
 428
 429         if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
 430                 shadow_context_descriptor_update(s->shadow[workload->ring_id],
 431                                                  workload);
 432
 433         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 434         if (ret)
 435                 return ret;
 436
 437         if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
 438                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 439                 if (ret)
 440                         goto err_shadow;
 441         }
 442
 443         workload->shadow = true;
 444         return 0;
 445 err_shadow:
 446         release_shadow_wa_ctx(&workload->wa_ctx);
 447         return ret;
 448 }
 449
 450 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 451
 452 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 453 {
 454         struct intel_gvt *gvt = workload->vgpu->gvt;
 455         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 456         struct intel_vgpu_shadow_bb *bb;
 457         int ret;
 458
 459         list_for_each_entry(bb, &workload->shadow_bb, list) {
 460                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 461                  * is only updated into ring_scan_buffer, not real ring address
 462                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 463                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 464                  * in copy_workload_to_ring_buffer.
 465                  */
 466
 467                 if (bb->bb_offset)
 468                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 469                                 + bb->bb_offset;
 470
 471                 if (bb->ppgtt) {
 472                         /* for non-priv bb, scan&shadow is only for
 473                          * debugging purpose, so the content of shadow bb
 474                          * is the same as original bb. Therefore,
 475                          * here, rather than switch to shadow bb's gma
 476                          * address, we directly use original batch buffer's
 477                          * gma address, and send original bb to hardware
 478                          * directly
 479                          */
 480                         if (bb->clflush & CLFLUSH_AFTER) {
 481                                 drm_clflush_virt_range(bb->va,
 482                                                 bb->obj->base.size);
 483                                 bb->clflush &= ~CLFLUSH_AFTER;
 484                         }
 485                         i915_gem_obj_finish_shmem_access(bb->obj);
 486                         bb->accessing = false;
 487
 488                 } else {
 489                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
 490                                         NULL, 0, 0, 0);
 491                         if (IS_ERR(bb->vma)) {
 492                                 ret = PTR_ERR(bb->vma);
 493                                 goto err;
 494                         }
 495
 496                         /* relocate shadow batch buffer */
 497                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 498                         if (gmadr_bytes == 8)
 499                                 bb->bb_start_cmd_va[2] = 0;
 500
 501                         /* No one is going to touch shadow bb from now on. */
 502                         if (bb->clflush & CLFLUSH_AFTER) {
 503                                 drm_clflush_virt_range(bb->va,
 504                                                 bb->obj->base.size);
 505                                 bb->clflush &= ~CLFLUSH_AFTER;
 506                         }
 507
 508                         ret = i915_gem_object_set_to_gtt_domain(bb->obj,
 509                                         false);
 510                         if (ret)
 511                                 goto err;
 512
 513                         i915_gem_obj_finish_shmem_access(bb->obj);
 514                         bb->accessing = false;
 515
 516                         ret = i915_vma_move_to_active(bb->vma,
 517                                                       workload->req,
 518                                                       0);
 519                         if (ret)
 520                                 goto err;
 521                 }
 522         }
 523         return 0;
 524 err:
 525         release_shadow_batch_buffer(workload);
 526         return ret;
 527 }
 528
 529 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 530 {
 531         struct intel_vgpu_workload *workload =
 532                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 533         struct i915_request *rq = workload->req;
 534         struct execlist_ring_context *shadow_ring_context =
 535                 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
 536
 537         shadow_ring_context->bb_per_ctx_ptr.val =
 538                 (shadow_ring_context->bb_per_ctx_ptr.val &
 539                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 540         shadow_ring_context->rcs_indirect_ctx.val =
 541                 (shadow_ring_context->rcs_indirect_ctx.val &
 542                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 543 }
 544
 545 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 546 {
 547         struct i915_vma *vma;
 548         unsigned char *per_ctx_va =
 549                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 550                 wa_ctx->indirect_ctx.size;
 551
 552         if (wa_ctx->indirect_ctx.size == 0)
 553                 return 0;
 554
 555         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 556                                        0, CACHELINE_BYTES, 0);
 557         if (IS_ERR(vma))
 558                 return PTR_ERR(vma);
 559
 560         /* FIXME: we are not tracking our pinned VMA leaving it
 561          * up to the core to fix up the stray pin_count upon
 562          * free.
 563          */
 564
 565         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 566
 567         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 568         memset(per_ctx_va, 0, CACHELINE_BYTES);
 569
 570         update_wa_ctx_2_shadow_ctx(wa_ctx);
 571         return 0;
 572 }
 573
 574 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 575 {
 576         struct intel_vgpu *vgpu = workload->vgpu;
 577         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 578         struct intel_vgpu_shadow_bb *bb, *pos;
 579
 580         if (list_empty(&workload->shadow_bb))
 581                 return;
 582
 583         bb = list_first_entry(&workload->shadow_bb,
 584                         struct intel_vgpu_shadow_bb, list);
 585
 586         mutex_lock(&dev_priv->drm.struct_mutex);
 587
 588         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 589                 if (bb->obj) {
 590                         if (bb->accessing)
 591                                 i915_gem_obj_finish_shmem_access(bb->obj);
 592
 593                         if (bb->va && !IS_ERR(bb->va))
 594                                 i915_gem_object_unpin_map(bb->obj);
 595
 596                         if (bb->vma && !IS_ERR(bb->vma)) {
 597                                 i915_vma_unpin(bb->vma);
 598                                 i915_vma_close(bb->vma);
 599                         }
 600                         __i915_gem_object_release_unless_active(bb->obj);
 601                 }
 602                 list_del(&bb->list);
 603                 kfree(bb);
 604         }
 605
 606         mutex_unlock(&dev_priv->drm.struct_mutex);
 607 }
 608
 609 static int prepare_workload(struct intel_vgpu_workload *workload)
 610 {
 611         struct intel_vgpu *vgpu = workload->vgpu;
 612         int ret = 0;
 613
 614         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 615         if (ret) {
 616                 gvt_vgpu_err("fail to vgpu pin mm\n");
 617                 return ret;
 618         }
 619
 620         update_shadow_pdps(workload);
 621
 622         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 623         if (ret) {
 624                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 625                 goto err_unpin_mm;
 626         }
 627
 628         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 629         if (ret) {
 630                 gvt_vgpu_err("fail to flush post shadow\n");
 631                 goto err_unpin_mm;
 632         }
 633
 634         ret = copy_workload_to_ring_buffer(workload);
 635         if (ret) {
 636                 gvt_vgpu_err("fail to generate request\n");
 637                 goto err_unpin_mm;
 638         }
 639
 640         ret = prepare_shadow_batch_buffer(workload);
 641         if (ret) {
 642                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 643                 goto err_unpin_mm;
 644         }
 645
 646         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 647         if (ret) {
 648                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 649                 goto err_shadow_batch;
 650         }
 651
 652         if (workload->prepare) {
 653                 ret = workload->prepare(workload);
 654                 if (ret)
 655                         goto err_shadow_wa_ctx;
 656         }
 657
 658         return 0;
 659 err_shadow_wa_ctx:
 660         release_shadow_wa_ctx(&workload->wa_ctx);
 661 err_shadow_batch:
 662         release_shadow_batch_buffer(workload);
 663 err_unpin_mm:
 664         intel_vgpu_unpin_mm(workload->shadow_mm);
 665         return ret;
 666 }
 667
 668 static int dispatch_workload(struct intel_vgpu_workload *workload)
 669 {
 670         struct intel_vgpu *vgpu = workload->vgpu;
 671         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 672         struct intel_vgpu_submission *s = &vgpu->submission;
 673         struct i915_request *rq;
 674         int ring_id = workload->ring_id;
 675         int ret;
 676
 677         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 678                 ring_id, workload);
 679
 680         mutex_lock(&vgpu->vgpu_lock);
 681         mutex_lock(&dev_priv->drm.struct_mutex);
 682
 683         ret = set_context_ppgtt_from_shadow(workload,
 684                                             s->shadow[ring_id]->gem_context);
 685         if (ret < 0) {
 686                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 687                 goto err_req;
 688         }
 689
 690         ret = intel_gvt_workload_req_alloc(workload);
 691         if (ret)
 692                 goto err_req;
 693
 694         ret = intel_gvt_scan_and_shadow_workload(workload);
 695         if (ret)
 696                 goto out;
 697
 698         ret = populate_shadow_context(workload);
 699         if (ret) {
 700                 release_shadow_wa_ctx(&workload->wa_ctx);
 701                 goto out;
 702         }
 703
 704         ret = prepare_workload(workload);
 705 out:
 706         if (ret) {
 707                 /* We might still need to add request with
 708                  * clean ctx to retire it properly..
 709                  */
 710                 rq = fetch_and_zero(&workload->req);
 711                 i915_request_put(rq);
 712         }
 713
 714         if (!IS_ERR_OR_NULL(workload->req)) {
 715                 gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 716                                 ring_id, workload->req);
 717                 i915_request_add(workload->req);
 718                 workload->dispatched = true;
 719         }
 720 err_req:
 721         if (ret)
 722                 workload->status = ret;
 723         mutex_unlock(&dev_priv->drm.struct_mutex);
 724         mutex_unlock(&vgpu->vgpu_lock);
 725         return ret;
 726 }
 727
 728 static struct intel_vgpu_workload *pick_next_workload(
 729                 struct intel_gvt *gvt, int ring_id)
 730 {
 731         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 732         struct intel_vgpu_workload *workload = NULL;
 733
 734         mutex_lock(&gvt->sched_lock);
 735
 736         /*
 737          * no current vgpu / will be scheduled out / no workload
 738          * bail out
 739          */
 740         if (!scheduler->current_vgpu) {
 741                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 742                 goto out;
 743         }
 744
 745         if (scheduler->need_reschedule) {
 746                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 747                 goto out;
 748         }
 749
 750         if (!scheduler->current_vgpu->active ||
 751             list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
 752                 goto out;
 753
 754         /*
 755          * still have current workload, maybe the workload disptacher
 756          * fail to submit it for some reason, resubmit it.
 757          */
 758         if (scheduler->current_workload[ring_id]) {
 759                 workload = scheduler->current_workload[ring_id];
 760                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 761                                 ring_id, workload);
 762                 goto out;
 763         }
 764
 765         /*
 766          * pick a workload as current workload
 767          * once current workload is set, schedule policy routines
 768          * will wait the current workload is finished when trying to
 769          * schedule out a vgpu.
 770          */
 771         scheduler->current_workload[ring_id] = container_of(
 772                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 773                         struct intel_vgpu_workload, list);
 774
 775         workload = scheduler->current_workload[ring_id];
 776
 777         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 778
 779         atomic_inc(&workload->vgpu->submission.running_workload_num);
 780 out:
 781         mutex_unlock(&gvt->sched_lock);
 782         return workload;
 783 }
 784
 785 static void update_guest_context(struct intel_vgpu_workload *workload)
 786 {
 787         struct i915_request *rq = workload->req;
 788         struct intel_vgpu *vgpu = workload->vgpu;
 789         struct intel_gvt *gvt = vgpu->gvt;
 790         struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
 791         struct execlist_ring_context *shadow_ring_context;
 792         struct page *page;
 793         void *src;
 794         unsigned long context_gpa, context_page_num;
 795         int i;
 796
 797         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 798                       workload->ctx_desc.lrca);
 799
 800         context_page_num = rq->engine->context_size;
 801         context_page_num = context_page_num >> PAGE_SHIFT;
 802
 803         if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
 804                 context_page_num = 19;
 805
 806         i = 2;
 807
 808         while (i < context_page_num) {
 809                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 810                                 (u32)((workload->ctx_desc.lrca + i) <<
 811                                         I915_GTT_PAGE_SHIFT));
 812                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 813                         gvt_vgpu_err("invalid guest context descriptor\n");
 814                         return;
 815                 }
 816
 817                 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
 818                 src = kmap(page);
 819                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 820                                 I915_GTT_PAGE_SIZE);
 821                 kunmap(page);
 822                 i++;
 823         }
 824
 825         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 826                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 827
 828         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 829         shadow_ring_context = kmap(page);
 830
 831 #define COPY_REG(name) \
 832         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 833                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 834
 835         COPY_REG(ctx_ctrl);
 836         COPY_REG(ctx_timestamp);
 837
 838 #undef COPY_REG
 839
 840         intel_gvt_hypervisor_write_gpa(vgpu,
 841                         workload->ring_context_gpa +
 842                         sizeof(*shadow_ring_context),
 843                         (void *)shadow_ring_context +
 844                         sizeof(*shadow_ring_context),
 845                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 846
 847         kunmap(page);
 848 }
 849
 850 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
 851                                 intel_engine_mask_t engine_mask)
 852 {
 853         struct intel_vgpu_submission *s = &vgpu->submission;
 854         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 855         struct intel_engine_cs *engine;
 856         struct intel_vgpu_workload *pos, *n;
 857         intel_engine_mask_t tmp;
 858
 859         /* free the unsubmited workloads in the queues. */
 860         for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
 861                 list_for_each_entry_safe(pos, n,
 862                         &s->workload_q_head[engine->id], list) {
 863                         list_del_init(&pos->list);
 864                         intel_vgpu_destroy_workload(pos);
 865                 }
 866                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
 867         }
 868 }
 869
 870 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 871 {
 872         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 873         struct intel_vgpu_workload *workload =
 874                 scheduler->current_workload[ring_id];
 875         struct intel_vgpu *vgpu = workload->vgpu;
 876         struct intel_vgpu_submission *s = &vgpu->submission;
 877         struct i915_request *rq = workload->req;
 878         int event;
 879
 880         mutex_lock(&vgpu->vgpu_lock);
 881         mutex_lock(&gvt->sched_lock);
 882
 883         /* For the workload w/ request, needs to wait for the context
 884          * switch to make sure request is completed.
 885          * For the workload w/o request, directly complete the workload.
 886          */
 887         if (rq) {
 888                 wait_event(workload->shadow_ctx_status_wq,
 889                            !atomic_read(&workload->shadow_ctx_active));
 890
 891                 /* If this request caused GPU hang, req->fence.error will
 892                  * be set to -EIO. Use -EIO to set workload status so
 893                  * that when this request caused GPU hang, didn't trigger
 894                  * context switch interrupt to guest.
 895                  */
 896                 if (likely(workload->status == -EINPROGRESS)) {
 897                         if (workload->req->fence.error == -EIO)
 898                                 workload->status = -EIO;
 899                         else
 900                                 workload->status = 0;
 901                 }
 902
 903                 if (!workload->status &&
 904                     !(vgpu->resetting_eng & BIT(ring_id))) {
 905                         update_guest_context(workload);
 906
 907                         for_each_set_bit(event, workload->pending_events,
 908                                          INTEL_GVT_EVENT_MAX)
 909                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 910                 }
 911
 912                 i915_request_put(fetch_and_zero(&workload->req));
 913         }
 914
 915         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 916                         ring_id, workload, workload->status);
 917
 918         scheduler->current_workload[ring_id] = NULL;
 919
 920         list_del_init(&workload->list);
 921
 922         if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
 923                 /* if workload->status is not successful means HW GPU
 924                  * has occurred GPU hang or something wrong with i915/GVT,
 925                  * and GVT won't inject context switch interrupt to guest.
 926                  * So this error is a vGPU hang actually to the guest.
 927                  * According to this we should emunlate a vGPU hang. If
 928                  * there are pending workloads which are already submitted
 929                  * from guest, we should clean them up like HW GPU does.
 930                  *
 931                  * if it is in middle of engine resetting, the pending
 932                  * workloads won't be submitted to HW GPU and will be
 933                  * cleaned up during the resetting process later, so doing
 934                  * the workload clean up here doesn't have any impact.
 935                  **/
 936                 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
 937         }
 938
 939         workload->complete(workload);
 940
 941         atomic_dec(&s->running_workload_num);
 942         wake_up(&scheduler->workload_complete_wq);
 943
 944         if (gvt->scheduler.need_reschedule)
 945                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
 946
 947         mutex_unlock(&gvt->sched_lock);
 948         mutex_unlock(&vgpu->vgpu_lock);
 949 }
 950
 951 struct workload_thread_param {
 952         struct intel_gvt *gvt;
 953         int ring_id;
 954 };
 955
 956 static int workload_thread(void *priv)
 957 {
 958         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 959         struct intel_gvt *gvt = p->gvt;
 960         int ring_id = p->ring_id;
 961         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 962         struct intel_vgpu_workload *workload = NULL;
 963         struct intel_vgpu *vgpu = NULL;
 964         int ret;
 965         bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
 966         DEFINE_WAIT_FUNC(wait, woken_wake_function);
 967
 968         kfree(p);
 969
 970         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 971
 972         while (!kthread_should_stop()) {
 973                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
 974                 do {
 975                         workload = pick_next_workload(gvt, ring_id);
 976                         if (workload)
 977                                 break;
 978                         wait_woken(&wait, TASK_INTERRUPTIBLE,
 979                                    MAX_SCHEDULE_TIMEOUT);
 980                 } while (!kthread_should_stop());
 981                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
 982
 983                 if (!workload)
 984                         break;
 985
 986                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
 987                                 workload->ring_id, workload,
 988                                 workload->vgpu->id);
 989
 990                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
 991                                 workload->ring_id, workload);
 992
 993                 if (need_force_wake)
 994                         intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
 995                                         FORCEWAKE_ALL);
 996
 997                 ret = dispatch_workload(workload);
 998
 999                 if (ret) {
1000                         vgpu = workload->vgpu;
1001                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1002                         goto complete;
1003                 }
1004
1005                 gvt_dbg_sched("ring id %d wait workload %p\n",
1006                                 workload->ring_id, workload);
1007                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1008
1009 complete:
1010                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1011                                 workload, workload->status);
1012
1013                 complete_current_workload(gvt, ring_id);
1014
1015                 if (need_force_wake)
1016                         intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1017                                         FORCEWAKE_ALL);
1018
1019                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1020                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1021         }
1022         return 0;
1023 }
1024
1025 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1026 {
1027         struct intel_vgpu_submission *s = &vgpu->submission;
1028         struct intel_gvt *gvt = vgpu->gvt;
1029         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1030
1031         if (atomic_read(&s->running_workload_num)) {
1032                 gvt_dbg_sched("wait vgpu idle\n");
1033
1034                 wait_event(scheduler->workload_complete_wq,
1035                                 !atomic_read(&s->running_workload_num));
1036         }
1037 }
1038
1039 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1040 {
1041         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1042         struct intel_engine_cs *engine;
1043         enum intel_engine_id i;
1044
1045         gvt_dbg_core("clean workload scheduler\n");
1046
1047         for_each_engine(engine, gvt->dev_priv, i) {
1048                 atomic_notifier_chain_unregister(
1049                                         &engine->context_status_notifier,
1050                                         &gvt->shadow_ctx_notifier_block[i]);
1051                 kthread_stop(scheduler->thread[i]);
1052         }
1053 }
1054
1055 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1056 {
1057         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1058         struct workload_thread_param *param = NULL;
1059         struct intel_engine_cs *engine;
1060         enum intel_engine_id i;
1061         int ret;
1062
1063         gvt_dbg_core("init workload scheduler\n");
1064
1065         init_waitqueue_head(&scheduler->workload_complete_wq);
1066
1067         for_each_engine(engine, gvt->dev_priv, i) {
1068                 init_waitqueue_head(&scheduler->waitq[i]);
1069
1070                 param = kzalloc(sizeof(*param), GFP_KERNEL);
1071                 if (!param) {
1072                         ret = -ENOMEM;
1073                         goto err;
1074                 }
1075
1076                 param->gvt = gvt;
1077                 param->ring_id = i;
1078
1079                 scheduler->thread[i] = kthread_run(workload_thread, param,
1080                         "gvt workload %d", i);
1081                 if (IS_ERR(scheduler->thread[i])) {
1082                         gvt_err("fail to create workload thread\n");
1083                         ret = PTR_ERR(scheduler->thread[i]);
1084                         goto err;
1085                 }
1086
1087                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1088                                         shadow_context_status_change;
1089                 atomic_notifier_chain_register(&engine->context_status_notifier,
1090                                         &gvt->shadow_ctx_notifier_block[i]);
1091         }
1092         return 0;
1093 err:
1094         intel_gvt_clean_workload_scheduler(gvt);
1095         kfree(param);
1096         param = NULL;
1097         return ret;
1098 }
1099
1100 static void
1101 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1102                                 struct i915_hw_ppgtt *ppgtt)
1103 {
1104         int i;
1105
1106         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1107                 px_dma(&ppgtt->pml4) = s->i915_context_pml4;
1108         } else {
1109                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1110                         px_dma(ppgtt->pdp.page_directory[i]) =
1111                                 s->i915_context_pdps[i];
1112         }
1113 }
1114
1115 /**
1116  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1117  * @vgpu: a vGPU
1118  *
1119  * This function is called when a vGPU is being destroyed.
1120  *
1121  */
1122 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1123 {
1124         struct intel_vgpu_submission *s = &vgpu->submission;
1125         struct intel_engine_cs *engine;
1126         enum intel_engine_id id;
1127
1128         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1129
1130         i915_context_ppgtt_root_restore(s, s->shadow[0]->gem_context->ppgtt);
1131         for_each_engine(engine, vgpu->gvt->dev_priv, id)
1132                 intel_context_unpin(s->shadow[id]);
1133
1134         kmem_cache_destroy(s->workloads);
1135 }
1136
1137
1138 /**
1139  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1140  * @vgpu: a vGPU
1141  * @engine_mask: engines expected to be reset
1142  *
1143  * This function is called when a vGPU is being destroyed.
1144  *
1145  */
1146 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1147                                  intel_engine_mask_t engine_mask)
1148 {
1149         struct intel_vgpu_submission *s = &vgpu->submission;
1150
1151         if (!s->active)
1152                 return;
1153
1154         intel_vgpu_clean_workloads(vgpu, engine_mask);
1155         s->ops->reset(vgpu, engine_mask);
1156 }
1157
1158 static void
1159 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1160                              struct i915_hw_ppgtt *ppgtt)
1161 {
1162         int i;
1163
1164         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1165                 s->i915_context_pml4 = px_dma(&ppgtt->pml4);
1166         } else {
1167                 for (i = 0; i < GEN8_3LVL_PDPES; i++)
1168                         s->i915_context_pdps[i] =
1169                                 px_dma(ppgtt->pdp.page_directory[i]);
1170         }
1171 }
1172
1173 /**
1174  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1175  * @vgpu: a vGPU
1176  *
1177  * This function is called when a vGPU is being created.
1178  *
1179  * Returns:
1180  * Zero on success, negative error code if failed.
1181  *
1182  */
1183 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1184 {
1185         struct intel_vgpu_submission *s = &vgpu->submission;
1186         struct intel_engine_cs *engine;
1187         struct i915_gem_context *ctx;
1188         enum intel_engine_id i;
1189         int ret;
1190
1191         ctx = i915_gem_context_create_gvt(&vgpu->gvt->dev_priv->drm);
1192         if (IS_ERR(ctx))
1193                 return PTR_ERR(ctx);
1194
1195         i915_context_ppgtt_root_save(s, ctx->ppgtt);
1196
1197         for_each_engine(engine, vgpu->gvt->dev_priv, i) {
1198                 struct intel_context *ce;
1199
1200                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1201                 s->shadow[i] = ERR_PTR(-EINVAL);
1202
1203                 ce = i915_gem_context_get_engine(ctx, i);
1204                 if (IS_ERR(ce)) {
1205                         ret = PTR_ERR(ce);
1206                         goto out_shadow_ctx;
1207                 }
1208
1209                 ret = intel_context_pin(ce);
1210                 intel_context_put(ce);
1211                 if (ret)
1212                         goto out_shadow_ctx;
1213
1214                 s->shadow[i] = ce;
1215         }
1216
1217         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1218
1219         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1220                                                   sizeof(struct intel_vgpu_workload), 0,
1221                                                   SLAB_HWCACHE_ALIGN,
1222                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1223                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1224                                                   NULL);
1225
1226         if (!s->workloads) {
1227                 ret = -ENOMEM;
1228                 goto out_shadow_ctx;
1229         }
1230
1231         atomic_set(&s->running_workload_num, 0);
1232         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1233
1234         i915_gem_context_put(ctx);
1235         return 0;
1236
1237 out_shadow_ctx:
1238         i915_context_ppgtt_root_restore(s, ctx->ppgtt);
1239         for_each_engine(engine, vgpu->gvt->dev_priv, i) {
1240                 if (IS_ERR(s->shadow[i]))
1241                         break;
1242
1243                 intel_context_unpin(s->shadow[i]);
1244         }
1245         i915_gem_context_put(ctx);
1246         return ret;
1247 }
1248
1249 /**
1250  * intel_vgpu_select_submission_ops - select virtual submission interface
1251  * @vgpu: a vGPU
1252  * @engine_mask: either ALL_ENGINES or target engine mask
1253  * @interface: expected vGPU virtual submission interface
1254  *
1255  * This function is called when guest configures submission interface.
1256  *
1257  * Returns:
1258  * Zero on success, negative error code if failed.
1259  *
1260  */
1261 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1262                                      intel_engine_mask_t engine_mask,
1263                                      unsigned int interface)
1264 {
1265         struct intel_vgpu_submission *s = &vgpu->submission;
1266         const struct intel_vgpu_submission_ops *ops[] = {
1267                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1268                         &intel_vgpu_execlist_submission_ops,
1269         };
1270         int ret;
1271
1272         if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1273                 return -EINVAL;
1274
1275         if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1276                 return -EINVAL;
1277
1278         if (s->active)
1279                 s->ops->clean(vgpu, engine_mask);
1280
1281         if (interface == 0) {
1282                 s->ops = NULL;
1283                 s->virtual_submission_interface = 0;
1284                 s->active = false;
1285                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1286                 return 0;
1287         }
1288
1289         ret = ops[interface]->init(vgpu, engine_mask);
1290         if (ret)
1291                 return ret;
1292
1293         s->ops = ops[interface];
1294         s->virtual_submission_interface = interface;
1295         s->active = true;
1296
1297         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1298                         vgpu->id, s->ops->name);
1299
1300         return 0;
1301 }
1302
1303 /**
1304  * intel_vgpu_destroy_workload - destroy a vGPU workload
1305  * @workload: workload to destroy
1306  *
1307  * This function is called when destroy a vGPU workload.
1308  *
1309  */
1310 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1311 {
1312         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1313
1314         release_shadow_batch_buffer(workload);
1315         release_shadow_wa_ctx(&workload->wa_ctx);
1316
1317         if (workload->shadow_mm)
1318                 intel_vgpu_mm_put(workload->shadow_mm);
1319
1320         kmem_cache_free(s->workloads, workload);
1321 }
1322
1323 static struct intel_vgpu_workload *
1324 alloc_workload(struct intel_vgpu *vgpu)
1325 {
1326         struct intel_vgpu_submission *s = &vgpu->submission;
1327         struct intel_vgpu_workload *workload;
1328
1329         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1330         if (!workload)
1331                 return ERR_PTR(-ENOMEM);
1332
1333         INIT_LIST_HEAD(&workload->list);
1334         INIT_LIST_HEAD(&workload->shadow_bb);
1335
1336         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1337         atomic_set(&workload->shadow_ctx_active, 0);
1338
1339         workload->status = -EINPROGRESS;
1340         workload->vgpu = vgpu;
1341
1342         return workload;
1343 }
1344
1345 #define RING_CTX_OFF(x) \
1346         offsetof(struct execlist_ring_context, x)
1347
1348 static void read_guest_pdps(struct intel_vgpu *vgpu,
1349                 u64 ring_context_gpa, u32 pdp[8])
1350 {
1351         u64 gpa;
1352         int i;
1353
1354         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1355
1356         for (i = 0; i < 8; i++)
1357                 intel_gvt_hypervisor_read_gpa(vgpu,
1358                                 gpa + i * 8, &pdp[7 - i], 4);
1359 }
1360
1361 static int prepare_mm(struct intel_vgpu_workload *workload)
1362 {
1363         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1364         struct intel_vgpu_mm *mm;
1365         struct intel_vgpu *vgpu = workload->vgpu;
1366         enum intel_gvt_gtt_type root_entry_type;
1367         u64 pdps[GVT_RING_CTX_NR_PDPS];
1368
1369         switch (desc->addressing_mode) {
1370         case 1: /* legacy 32-bit */
1371                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1372                 break;
1373         case 3: /* legacy 64-bit */
1374                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1375                 break;
1376         default:
1377                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1378                 return -EINVAL;
1379         }
1380
1381         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1382
1383         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1384         if (IS_ERR(mm))
1385                 return PTR_ERR(mm);
1386
1387         workload->shadow_mm = mm;
1388         return 0;
1389 }
1390
1391 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1392                 ((a)->lrca == (b)->lrca))
1393
1394 #define get_last_workload(q) \
1395         (list_empty(q) ? NULL : container_of(q->prev, \
1396         struct intel_vgpu_workload, list))
1397 /**
1398  * intel_vgpu_create_workload - create a vGPU workload
1399  * @vgpu: a vGPU
1400  * @ring_id: ring index
1401  * @desc: a guest context descriptor
1402  *
1403  * This function is called when creating a vGPU workload.
1404  *
1405  * Returns:
1406  * struct intel_vgpu_workload * on success, negative error code in
1407  * pointer if failed.
1408  *
1409  */
1410 struct intel_vgpu_workload *
1411 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1412                            struct execlist_ctx_descriptor_format *desc)
1413 {
1414         struct intel_vgpu_submission *s = &vgpu->submission;
1415         struct list_head *q = workload_q_head(vgpu, ring_id);
1416         struct intel_vgpu_workload *last_workload = get_last_workload(q);
1417         struct intel_vgpu_workload *workload = NULL;
1418         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1419         u64 ring_context_gpa;
1420         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1421         int ret;
1422
1423         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1424                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1425         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1426                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1427                 return ERR_PTR(-EINVAL);
1428         }
1429
1430         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1431                         RING_CTX_OFF(ring_header.val), &head, 4);
1432
1433         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1434                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1435
1436         head &= RB_HEAD_OFF_MASK;
1437         tail &= RB_TAIL_OFF_MASK;
1438
1439         if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1440                 gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1441                 gvt_dbg_el("ctx head %x real head %lx\n", head,
1442                                 last_workload->rb_tail);
1443                 /*
1444                  * cannot use guest context head pointer here,
1445                  * as it might not be updated at this time
1446                  */
1447                 head = last_workload->rb_tail;
1448         }
1449
1450         gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1451
1452         /* record some ring buffer register values for scan and shadow */
1453         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1454                         RING_CTX_OFF(rb_start.val), &start, 4);
1455         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1456                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1457         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1458                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1459
1460         workload = alloc_workload(vgpu);
1461         if (IS_ERR(workload))
1462                 return workload;
1463
1464         workload->ring_id = ring_id;
1465         workload->ctx_desc = *desc;
1466         workload->ring_context_gpa = ring_context_gpa;
1467         workload->rb_head = head;
1468         workload->rb_tail = tail;
1469         workload->rb_start = start;
1470         workload->rb_ctl = ctl;
1471
1472         if (ring_id == RCS0) {
1473                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1474                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1475                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1476                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1477
1478                 workload->wa_ctx.indirect_ctx.guest_gma =
1479                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1480                 workload->wa_ctx.indirect_ctx.size =
1481                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1482                         CACHELINE_BYTES;
1483                 workload->wa_ctx.per_ctx.guest_gma =
1484                         per_ctx & PER_CTX_ADDR_MASK;
1485                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1486         }
1487
1488         gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1489                         workload, ring_id, head, tail, start, ctl);
1490
1491         ret = prepare_mm(workload);
1492         if (ret) {
1493                 kmem_cache_free(s->workloads, workload);
1494                 return ERR_PTR(ret);
1495         }
1496
1497         /* Only scan and shadow the first workload in the queue
1498          * as there is only one pre-allocated buf-obj for shadow.
1499          */
1500         if (list_empty(workload_q_head(vgpu, ring_id))) {
1501                 intel_runtime_pm_get(dev_priv);
1502                 mutex_lock(&dev_priv->drm.struct_mutex);
1503                 ret = intel_gvt_scan_and_shadow_workload(workload);
1504                 mutex_unlock(&dev_priv->drm.struct_mutex);
1505                 intel_runtime_pm_put_unchecked(dev_priv);
1506         }
1507
1508         if (ret) {
1509                 if (vgpu_is_vm_unhealthy(ret))
1510                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1511                 intel_vgpu_destroy_workload(workload);
1512                 return ERR_PTR(ret);
1513         }
1514
1515         return workload;
1516 }
1517
1518 /**
1519  * intel_vgpu_queue_workload - Qeue a vGPU workload
1520  * @workload: the workload to queue in
1521  */
1522 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1523 {
1524         list_add_tail(&workload->list,
1525                 workload_q_head(workload->vgpu, workload->ring_id));
1526         intel_gvt_kick_schedule(workload->vgpu->gvt);
1527         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1528 }