drm/i915/gvt: correct the emulation in TLB control handler
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / render.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Eddie Dong <eddie.dong@intel.com>
25  *    Kevin Tian <kevin.tian@intel.com>
26  *
27  * Contributors:
28  *    Zhi Wang <zhi.a.wang@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Bing Niu <bing.niu@intel.com>
33  *
34  */
35
36 #include "i915_drv.h"
37 #include "gvt.h"
38
39 struct render_mmio {
40         int ring_id;
41         i915_reg_t reg;
42         u32 mask;
43         bool in_context;
44         u32 value;
45 };
46
47 static struct render_mmio gen8_render_mmio_list[] = {
48         {RCS, _MMIO(0x229c), 0xffff, false},
49         {RCS, _MMIO(0x2248), 0x0, false},
50         {RCS, _MMIO(0x2098), 0x0, false},
51         {RCS, _MMIO(0x20c0), 0xffff, true},
52         {RCS, _MMIO(0x24d0), 0, false},
53         {RCS, _MMIO(0x24d4), 0, false},
54         {RCS, _MMIO(0x24d8), 0, false},
55         {RCS, _MMIO(0x24dc), 0, false},
56         {RCS, _MMIO(0x7004), 0xffff, true},
57         {RCS, _MMIO(0x7008), 0xffff, true},
58         {RCS, _MMIO(0x7000), 0xffff, true},
59         {RCS, _MMIO(0x7010), 0xffff, true},
60         {RCS, _MMIO(0x7300), 0xffff, true},
61         {RCS, _MMIO(0x83a4), 0xffff, true},
62
63         {BCS, _MMIO(0x2229c), 0xffff, false},
64         {BCS, _MMIO(0x2209c), 0xffff, false},
65         {BCS, _MMIO(0x220c0), 0xffff, false},
66         {BCS, _MMIO(0x22098), 0x0, false},
67         {BCS, _MMIO(0x22028), 0x0, false},
68 };
69
70 static struct render_mmio gen9_render_mmio_list[] = {
71         {RCS, _MMIO(0x229c), 0xffff, false},
72         {RCS, _MMIO(0x2248), 0x0, false},
73         {RCS, _MMIO(0x2098), 0x0, false},
74         {RCS, _MMIO(0x20c0), 0xffff, true},
75         {RCS, _MMIO(0x24d0), 0, false},
76         {RCS, _MMIO(0x24d4), 0, false},
77         {RCS, _MMIO(0x24d8), 0, false},
78         {RCS, _MMIO(0x24dc), 0, false},
79         {RCS, _MMIO(0x7004), 0xffff, true},
80         {RCS, _MMIO(0x7008), 0xffff, true},
81         {RCS, _MMIO(0x7000), 0xffff, true},
82         {RCS, _MMIO(0x7010), 0xffff, true},
83         {RCS, _MMIO(0x7300), 0xffff, true},
84         {RCS, _MMIO(0x83a4), 0xffff, true},
85
86         {RCS, _MMIO(0x40e0), 0, false},
87         {RCS, _MMIO(0x40e4), 0, false},
88         {RCS, _MMIO(0x2580), 0xffff, true},
89         {RCS, _MMIO(0x7014), 0xffff, true},
90         {RCS, _MMIO(0x20ec), 0xffff, false},
91         {RCS, _MMIO(0xb118), 0, false},
92         {RCS, _MMIO(0xe100), 0xffff, true},
93         {RCS, _MMIO(0xe180), 0xffff, true},
94         {RCS, _MMIO(0xe184), 0xffff, true},
95         {RCS, _MMIO(0xe188), 0xffff, true},
96         {RCS, _MMIO(0xe194), 0xffff, true},
97         {RCS, _MMIO(0x4de0), 0, false},
98         {RCS, _MMIO(0x4de4), 0, false},
99         {RCS, _MMIO(0x4de8), 0, false},
100         {RCS, _MMIO(0x4dec), 0, false},
101         {RCS, _MMIO(0x4df0), 0, false},
102         {RCS, _MMIO(0x4df4), 0, false},
103
104         {BCS, _MMIO(0x2229c), 0xffff, false},
105         {BCS, _MMIO(0x2209c), 0xffff, false},
106         {BCS, _MMIO(0x220c0), 0xffff, false},
107         {BCS, _MMIO(0x22098), 0x0, false},
108         {BCS, _MMIO(0x22028), 0x0, false},
109
110         {VCS2, _MMIO(0x1c028), 0xffff, false},
111
112         {VECS, _MMIO(0x1a028), 0xffff, false},
113 };
114
115 static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
116 static u32 gen9_render_mocs_L3[32];
117
118 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
119 {
120         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
121         enum forcewake_domains fw;
122         i915_reg_t reg;
123         u32 regs[] = {
124                 [RCS] = 0x4260,
125                 [VCS] = 0x4264,
126                 [VCS2] = 0x4268,
127                 [BCS] = 0x426c,
128                 [VECS] = 0x4270,
129         };
130
131         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
132                 return;
133
134         if (!test_and_clear_bit(ring_id, (void *)vgpu->tlb_handle_pending))
135                 return;
136
137         reg = _MMIO(regs[ring_id]);
138
139         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
140          * we need to put a forcewake when invalidating RCS TLB caches,
141          * otherwise device can go to RC6 state and interrupt invalidation
142          * process
143          */
144         fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
145                                             FW_REG_READ | FW_REG_WRITE);
146         if (ring_id == RCS && IS_SKYLAKE(dev_priv))
147                 fw |= FORCEWAKE_RENDER;
148
149         intel_uncore_forcewake_get(dev_priv, fw);
150
151         I915_WRITE_FW(reg, 0x1);
152
153         if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
154                 gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id);
155         else
156                 vgpu_vreg(vgpu, regs[ring_id]) = 0;
157
158         intel_uncore_forcewake_put(dev_priv, fw);
159
160         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
161 }
162
163 static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
164 {
165         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
166         i915_reg_t offset, l3_offset;
167         u32 regs[] = {
168                 [RCS] = 0xc800,
169                 [VCS] = 0xc900,
170                 [VCS2] = 0xca00,
171                 [BCS] = 0xcc00,
172                 [VECS] = 0xcb00,
173         };
174         int i;
175
176         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
177                 return;
178
179         if (!IS_SKYLAKE(dev_priv))
180                 return;
181
182         offset.reg = regs[ring_id];
183         for (i = 0; i < 64; i++) {
184                 gen9_render_mocs[ring_id][i] = I915_READ(offset);
185                 I915_WRITE(offset, vgpu_vreg(vgpu, offset));
186                 POSTING_READ(offset);
187                 offset.reg += 4;
188         }
189
190         if (ring_id == RCS) {
191                 l3_offset.reg = 0xb020;
192                 for (i = 0; i < 32; i++) {
193                         gen9_render_mocs_L3[i] = I915_READ(l3_offset);
194                         I915_WRITE(l3_offset, vgpu_vreg(vgpu, offset));
195                         POSTING_READ(l3_offset);
196                         l3_offset.reg += 4;
197                 }
198         }
199 }
200
201 static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
202 {
203         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
204         i915_reg_t offset, l3_offset;
205         u32 regs[] = {
206                 [RCS] = 0xc800,
207                 [VCS] = 0xc900,
208                 [VCS2] = 0xca00,
209                 [BCS] = 0xcc00,
210                 [VECS] = 0xcb00,
211         };
212         int i;
213
214         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
215                 return;
216
217         if (!IS_SKYLAKE(dev_priv))
218                 return;
219
220         offset.reg = regs[ring_id];
221         for (i = 0; i < 64; i++) {
222                 vgpu_vreg(vgpu, offset) = I915_READ(offset);
223                 I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
224                 POSTING_READ(offset);
225                 offset.reg += 4;
226         }
227
228         if (ring_id == RCS) {
229                 l3_offset.reg = 0xb020;
230                 for (i = 0; i < 32; i++) {
231                         vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset);
232                         I915_WRITE(l3_offset, gen9_render_mocs_L3[i]);
233                         POSTING_READ(l3_offset);
234                         l3_offset.reg += 4;
235                 }
236         }
237 }
238
239 void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)
240 {
241         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
242         struct render_mmio *mmio;
243         u32 v;
244         int i, array_size;
245
246         if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
247                 mmio = gen9_render_mmio_list;
248                 array_size = ARRAY_SIZE(gen9_render_mmio_list);
249                 load_mocs(vgpu, ring_id);
250         } else {
251                 mmio = gen8_render_mmio_list;
252                 array_size = ARRAY_SIZE(gen8_render_mmio_list);
253         }
254
255         for (i = 0; i < array_size; i++, mmio++) {
256                 if (mmio->ring_id != ring_id)
257                         continue;
258
259                 mmio->value = I915_READ(mmio->reg);
260                 if (mmio->mask)
261                         v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
262                 else
263                         v = vgpu_vreg(vgpu, mmio->reg);
264
265                 I915_WRITE(mmio->reg, v);
266                 POSTING_READ(mmio->reg);
267
268                 gvt_dbg_render("load reg %x old %x new %x\n",
269                                 i915_mmio_reg_offset(mmio->reg),
270                                 mmio->value, v);
271         }
272         handle_tlb_pending_event(vgpu, ring_id);
273 }
274
275 void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id)
276 {
277         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
278         struct render_mmio *mmio;
279         u32 v;
280         int i, array_size;
281
282         if (IS_SKYLAKE(dev_priv)) {
283                 mmio = gen9_render_mmio_list;
284                 array_size = ARRAY_SIZE(gen9_render_mmio_list);
285                 restore_mocs(vgpu, ring_id);
286         } else {
287                 mmio = gen8_render_mmio_list;
288                 array_size = ARRAY_SIZE(gen8_render_mmio_list);
289         }
290
291         for (i = 0; i < array_size; i++, mmio++) {
292                 if (mmio->ring_id != ring_id)
293                         continue;
294
295                 vgpu_vreg(vgpu, mmio->reg) = I915_READ(mmio->reg);
296
297                 if (mmio->mask) {
298                         vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
299                         v = mmio->value | (mmio->mask << 16);
300                 } else
301                         v = mmio->value;
302
303                 I915_WRITE(mmio->reg, v);
304                 POSTING_READ(mmio->reg);
305
306                 gvt_dbg_render("restore reg %x old %x new %x\n",
307                                 i915_mmio_reg_offset(mmio->reg),
308                                 mmio->value, v);
309         }
310 }