drivers/gpu/drm/i915/gvt/render.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eddie Dong <eddie.dong@intel.com>
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *
  27  * Contributors:
  28  *    Zhi Wang <zhi.a.wang@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35
  36 #include "i915_drv.h"
  37 #include "gvt.h"
  38
  39 struct render_mmio {
  40         int ring_id;
  41         i915_reg_t reg;
  42         u32 mask;
  43         bool in_context;
  44         u32 value;
  45 };
  46
  47 static struct render_mmio gen8_render_mmio_list[] = {
  48         {RCS, _MMIO(0x229c), 0xffff, false},
  49         {RCS, _MMIO(0x2248), 0x0, false},
  50         {RCS, _MMIO(0x2098), 0x0, false},
  51         {RCS, _MMIO(0x20c0), 0xffff, true},
  52         {RCS, _MMIO(0x24d0), 0, false},
  53         {RCS, _MMIO(0x24d4), 0, false},
  54         {RCS, _MMIO(0x24d8), 0, false},
  55         {RCS, _MMIO(0x24dc), 0, false},
  56         {RCS, _MMIO(0x24e0), 0, false},
  57         {RCS, _MMIO(0x24e4), 0, false},
  58         {RCS, _MMIO(0x24e8), 0, false},
  59         {RCS, _MMIO(0x24ec), 0, false},
  60         {RCS, _MMIO(0x24f0), 0, false},
  61         {RCS, _MMIO(0x24f4), 0, false},
  62         {RCS, _MMIO(0x24f8), 0, false},
  63         {RCS, _MMIO(0x24fc), 0, false},
  64         {RCS, _MMIO(0x7004), 0xffff, true},
  65         {RCS, _MMIO(0x7008), 0xffff, true},
  66         {RCS, _MMIO(0x7000), 0xffff, true},
  67         {RCS, _MMIO(0x7010), 0xffff, true},
  68         {RCS, _MMIO(0x7300), 0xffff, true},
  69         {RCS, _MMIO(0x83a4), 0xffff, true},
  70
  71         {BCS, _MMIO(0x2229c), 0xffff, false},
  72         {BCS, _MMIO(0x2209c), 0xffff, false},
  73         {BCS, _MMIO(0x220c0), 0xffff, false},
  74         {BCS, _MMIO(0x22098), 0x0, false},
  75         {BCS, _MMIO(0x22028), 0x0, false},
  76 };
  77
  78 static struct render_mmio gen9_render_mmio_list[] = {
  79         {RCS, _MMIO(0x229c), 0xffff, false},
  80         {RCS, _MMIO(0x2248), 0x0, false},
  81         {RCS, _MMIO(0x2098), 0x0, false},
  82         {RCS, _MMIO(0x20c0), 0xffff, true},
  83         {RCS, _MMIO(0x24d0), 0, false},
  84         {RCS, _MMIO(0x24d4), 0, false},
  85         {RCS, _MMIO(0x24d8), 0, false},
  86         {RCS, _MMIO(0x24dc), 0, false},
  87         {RCS, _MMIO(0x24e0), 0, false},
  88         {RCS, _MMIO(0x24e4), 0, false},
  89         {RCS, _MMIO(0x24e8), 0, false},
  90         {RCS, _MMIO(0x24ec), 0, false},
  91         {RCS, _MMIO(0x24f0), 0, false},
  92         {RCS, _MMIO(0x24f4), 0, false},
  93         {RCS, _MMIO(0x24f8), 0, false},
  94         {RCS, _MMIO(0x24fc), 0, false},
  95         {RCS, _MMIO(0x7004), 0xffff, true},
  96         {RCS, _MMIO(0x7008), 0xffff, true},
  97         {RCS, _MMIO(0x7000), 0xffff, true},
  98         {RCS, _MMIO(0x7010), 0xffff, true},
  99         {RCS, _MMIO(0x7300), 0xffff, true},
 100         {RCS, _MMIO(0x83a4), 0xffff, true},
 101
 102         {RCS, _MMIO(0x40e0), 0, false},
 103         {RCS, _MMIO(0x40e4), 0, false},
 104         {RCS, _MMIO(0x2580), 0xffff, true},
 105         {RCS, _MMIO(0x7014), 0xffff, true},
 106         {RCS, _MMIO(0x20ec), 0xffff, false},
 107         {RCS, _MMIO(0xb118), 0, false},
 108         {RCS, _MMIO(0xe100), 0xffff, true},
 109         {RCS, _MMIO(0xe180), 0xffff, true},
 110         {RCS, _MMIO(0xe184), 0xffff, true},
 111         {RCS, _MMIO(0xe188), 0xffff, true},
 112         {RCS, _MMIO(0xe194), 0xffff, true},
 113         {RCS, _MMIO(0x4de0), 0, false},
 114         {RCS, _MMIO(0x4de4), 0, false},
 115         {RCS, _MMIO(0x4de8), 0, false},
 116         {RCS, _MMIO(0x4dec), 0, false},
 117         {RCS, _MMIO(0x4df0), 0, false},
 118         {RCS, _MMIO(0x4df4), 0, false},
 119
 120         {BCS, _MMIO(0x2229c), 0xffff, false},
 121         {BCS, _MMIO(0x2209c), 0xffff, false},
 122         {BCS, _MMIO(0x220c0), 0xffff, false},
 123         {BCS, _MMIO(0x22098), 0x0, false},
 124         {BCS, _MMIO(0x22028), 0x0, false},
 125
 126         {VCS2, _MMIO(0x1c028), 0xffff, false},
 127
 128         {VECS, _MMIO(0x1a028), 0xffff, false},
 129 };
 130
 131 static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
 132 static u32 gen9_render_mocs_L3[32];
 133
 134 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
 135 {
 136         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 137         enum forcewake_domains fw;
 138         i915_reg_t reg;
 139         u32 regs[] = {
 140                 [RCS] = 0x4260,
 141                 [VCS] = 0x4264,
 142                 [VCS2] = 0x4268,
 143                 [BCS] = 0x426c,
 144                 [VECS] = 0x4270,
 145         };
 146
 147         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 148                 return;
 149
 150         if (!test_and_clear_bit(ring_id, (void *)vgpu->tlb_handle_pending))
 151                 return;
 152
 153         reg = _MMIO(regs[ring_id]);
 154
 155         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
 156          * we need to put a forcewake when invalidating RCS TLB caches,
 157          * otherwise device can go to RC6 state and interrupt invalidation
 158          * process
 159          */
 160         fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
 161                                             FW_REG_READ | FW_REG_WRITE);
 162         if (ring_id == RCS && IS_SKYLAKE(dev_priv))
 163                 fw |= FORCEWAKE_RENDER;
 164
 165         intel_uncore_forcewake_get(dev_priv, fw);
 166
 167         I915_WRITE_FW(reg, 0x1);
 168
 169         if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
 170                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
 171         else
 172                 vgpu_vreg(vgpu, regs[ring_id]) = 0;
 173
 174         intel_uncore_forcewake_put(dev_priv, fw);
 175
 176         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
 177 }
 178
 179 static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
 180 {
 181         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 182         i915_reg_t offset, l3_offset;
 183         u32 regs[] = {
 184                 [RCS] = 0xc800,
 185                 [VCS] = 0xc900,
 186                 [VCS2] = 0xca00,
 187                 [BCS] = 0xcc00,
 188                 [VECS] = 0xcb00,
 189         };
 190         int i;
 191
 192         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 193                 return;
 194
 195         if (!IS_SKYLAKE(dev_priv))
 196                 return;
 197
 198         offset.reg = regs[ring_id];
 199         for (i = 0; i < 64; i++) {
 200                 gen9_render_mocs[ring_id][i] = I915_READ(offset);
 201                 I915_WRITE(offset, vgpu_vreg(vgpu, offset));
 202                 POSTING_READ(offset);
 203                 offset.reg += 4;
 204         }
 205
 206         if (ring_id == RCS) {
 207                 l3_offset.reg = 0xb020;
 208                 for (i = 0; i < 32; i++) {
 209                         gen9_render_mocs_L3[i] = I915_READ(l3_offset);
 210                         I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset));
 211                         POSTING_READ(l3_offset);
 212                         l3_offset.reg += 4;
 213                 }
 214         }
 215 }
 216
 217 static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
 218 {
 219         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 220         i915_reg_t offset, l3_offset;
 221         u32 regs[] = {
 222                 [RCS] = 0xc800,
 223                 [VCS] = 0xc900,
 224                 [VCS2] = 0xca00,
 225                 [BCS] = 0xcc00,
 226                 [VECS] = 0xcb00,
 227         };
 228         int i;
 229
 230         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 231                 return;
 232
 233         if (!IS_SKYLAKE(dev_priv))
 234                 return;
 235
 236         offset.reg = regs[ring_id];
 237         for (i = 0; i < 64; i++) {
 238                 vgpu_vreg(vgpu, offset) = I915_READ(offset);
 239                 I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
 240                 POSTING_READ(offset);
 241                 offset.reg += 4;
 242         }
 243
 244         if (ring_id == RCS) {
 245                 l3_offset.reg = 0xb020;
 246                 for (i = 0; i < 32; i++) {
 247                         vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset);
 248                         I915_WRITE(l3_offset, gen9_render_mocs_L3[i]);
 249                         POSTING_READ(l3_offset);
 250                         l3_offset.reg += 4;
 251                 }
 252         }
 253 }
 254
 255 #define CTX_CONTEXT_CONTROL_VAL 0x03
 256
 257 void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, int ring_id)
 258 {
 259         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 260         struct render_mmio *mmio;
 261         u32 v;
 262         int i, array_size;
 263         u32 *reg_state = vgpu->shadow_ctx->engine[ring_id].lrc_reg_state;
 264         u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
 265         u32 inhibit_mask =
 266                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
 267
 268         if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
 269                 mmio = gen9_render_mmio_list;
 270                 array_size = ARRAY_SIZE(gen9_render_mmio_list);
 271                 load_mocs(vgpu, ring_id);
 272         } else {
 273                 mmio = gen8_render_mmio_list;
 274                 array_size = ARRAY_SIZE(gen8_render_mmio_list);
 275         }
 276
 277         for (i = 0; i < array_size; i++, mmio++) {
 278                 if (mmio->ring_id != ring_id)
 279                         continue;
 280
 281                 mmio->value = I915_READ(mmio->reg);
 282
 283                 /*
 284                  * if it is an inhibit context, load in_context mmio
 285                  * into HW by mmio write. If it is not, skip this mmio
 286                  * write.
 287                  */
 288                 if (mmio->in_context &&
 289                                 ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
 290                                 i915.enable_execlists)
 291                         continue;
 292
 293                 if (mmio->mask)
 294                         v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
 295                 else
 296                         v = vgpu_vreg(vgpu, mmio->reg);
 297
 298                 I915_WRITE(mmio->reg, v);
 299                 POSTING_READ(mmio->reg);
 300
 301                 gvt_dbg_render("load reg %x old %x new %x\n",
 302                                 i915_mmio_reg_offset(mmio->reg),
 303                                 mmio->value, v);
 304         }
 305         handle_tlb_pending_event(vgpu, ring_id);
 306 }
 307
 308 void intel_gvt_restore_render_mmio(struct intel_vgpu *vgpu, int ring_id)
 309 {
 310         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 311         struct render_mmio *mmio;
 312         u32 v;
 313         int i, array_size;
 314
 315         if (IS_SKYLAKE(dev_priv)) {
 316                 mmio = gen9_render_mmio_list;
 317                 array_size = ARRAY_SIZE(gen9_render_mmio_list);
 318                 restore_mocs(vgpu, ring_id);
 319         } else {
 320                 mmio = gen8_render_mmio_list;
 321                 array_size = ARRAY_SIZE(gen8_render_mmio_list);
 322         }
 323
 324         for (i = 0; i < array_size; i++, mmio++) {
 325                 if (mmio->ring_id != ring_id)
 326                         continue;
 327
 328                 vgpu_vreg(vgpu, mmio->reg) = I915_READ(mmio->reg);
 329
 330                 if (mmio->mask) {
 331                         vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
 332                         v = mmio->value | (mmio->mask << 16);
 333                 } else
 334                         v = mmio->value;
 335
 336                 I915_WRITE(mmio->reg, v);
 337                 POSTING_READ(mmio->reg);
 338
 339                 gvt_dbg_render("restore reg %x old %x new %x\n",
 340                                 i915_mmio_reg_offset(mmio->reg),
 341                                 mmio->value, v);
 342         }
 343 }