Merge tag 'gvt-next-2017-12-14' of https://github.com/intel/gvt-linux into drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / mmio_context.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Eddie Dong <eddie.dong@intel.com>
25  *    Kevin Tian <kevin.tian@intel.com>
26  *
27  * Contributors:
28  *    Zhi Wang <zhi.a.wang@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Bing Niu <bing.niu@intel.com>
33  *
34  */
35
36 #include "i915_drv.h"
37 #include "gvt.h"
38 #include "trace.h"
39
40 /**
41  * Defined in Intel Open Source PRM.
42  * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
43  */
44 #define TRVATTL3PTRDW(i)        _MMIO(0x4de0 + (i)*4)
45 #define TRNULLDETCT             _MMIO(0x4de8)
46 #define TRINVTILEDETCT          _MMIO(0x4dec)
47 #define TRVADR                  _MMIO(0x4df0)
48 #define TRTTE                   _MMIO(0x4df4)
49 #define RING_EXCC(base)         _MMIO((base) + 0x28)
50 #define RING_GFX_MODE(base)     _MMIO((base) + 0x29c)
51 #define VF_GUARDBAND            _MMIO(0x83a4)
52
53 /* Raw offset is appened to each line for convenience. */
54 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
55         {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
56         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
57         {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
58         {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
59         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
60         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
61         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
62         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
63         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
64         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
65         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
66         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
67         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
68         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
69         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
70         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
71         {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
72         {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
73         {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
74         {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
75         {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
76         {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
77
78         {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
79         {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
80         {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
81         {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
82         {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
83         { /* Terminated */ }
84 };
85
86 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
87         {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
88         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
89         {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
90         {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
91         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
92         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
93         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
94         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
95         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
96         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
97         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
98         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
99         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
100         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
101         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
102         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
103         {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
104         {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
105         {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
106         {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
107         {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
108         {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
109
110         {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
111         {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
112         {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
113         {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
114         {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
115         {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
116         {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
117         {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
118         {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
119         {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
120         {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
121         {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
122         {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
123         {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
124         {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
125         {RCS, TRVADR, 0, false}, /* 0x4df0 */
126         {RCS, TRTTE, 0, false}, /* 0x4df4 */
127
128         {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
129         {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
130         {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
131         {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
132         {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
133
134         {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
135
136         {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
137
138         {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
139         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
140         {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
141         {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
142
143         {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
144         {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
145
146         {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
147         {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
148         {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
149         { /* Terminated */ }
150 };
151
152 static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
153 static u32 gen9_render_mocs_L3[32];
154
155 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
156 {
157         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
158         struct intel_vgpu_submission *s = &vgpu->submission;
159         enum forcewake_domains fw;
160         i915_reg_t reg;
161         u32 regs[] = {
162                 [RCS] = 0x4260,
163                 [VCS] = 0x4264,
164                 [VCS2] = 0x4268,
165                 [BCS] = 0x426c,
166                 [VECS] = 0x4270,
167         };
168
169         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
170                 return;
171
172         if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
173                 return;
174
175         reg = _MMIO(regs[ring_id]);
176
177         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
178          * we need to put a forcewake when invalidating RCS TLB caches,
179          * otherwise device can go to RC6 state and interrupt invalidation
180          * process
181          */
182         fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
183                                             FW_REG_READ | FW_REG_WRITE);
184         if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
185                 fw |= FORCEWAKE_RENDER;
186
187         intel_uncore_forcewake_get(dev_priv, fw);
188
189         I915_WRITE_FW(reg, 0x1);
190
191         if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
192                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
193         else
194                 vgpu_vreg(vgpu, regs[ring_id]) = 0;
195
196         intel_uncore_forcewake_put(dev_priv, fw);
197
198         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
199 }
200
201 static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
202 {
203         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
204         i915_reg_t offset, l3_offset;
205         u32 regs[] = {
206                 [RCS] = 0xc800,
207                 [VCS] = 0xc900,
208                 [VCS2] = 0xca00,
209                 [BCS] = 0xcc00,
210                 [VECS] = 0xcb00,
211         };
212         int i;
213
214         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
215                 return;
216
217         offset.reg = regs[ring_id];
218         for (i = 0; i < 64; i++) {
219                 gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
220                 I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
221                 offset.reg += 4;
222         }
223
224         if (ring_id == RCS) {
225                 l3_offset.reg = 0xb020;
226                 for (i = 0; i < 32; i++) {
227                         gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
228                         I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
229                         l3_offset.reg += 4;
230                 }
231         }
232 }
233
234 static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
235 {
236         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
237         i915_reg_t offset, l3_offset;
238         u32 regs[] = {
239                 [RCS] = 0xc800,
240                 [VCS] = 0xc900,
241                 [VCS2] = 0xca00,
242                 [BCS] = 0xcc00,
243                 [VECS] = 0xcb00,
244         };
245         int i;
246
247         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
248                 return;
249
250         offset.reg = regs[ring_id];
251         for (i = 0; i < 64; i++) {
252                 vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
253                 I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
254                 offset.reg += 4;
255         }
256
257         if (ring_id == RCS) {
258                 l3_offset.reg = 0xb020;
259                 for (i = 0; i < 32; i++) {
260                         vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
261                         I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
262                         l3_offset.reg += 4;
263                 }
264         }
265 }
266
267 #define CTX_CONTEXT_CONTROL_VAL 0x03
268
269 /* Switch ring mmio values (context) from host to a vgpu. */
270 static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
271 {
272         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
273         struct intel_vgpu_submission *s = &vgpu->submission;
274         u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
275         u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
276         u32 inhibit_mask =
277                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
278         struct engine_mmio *mmio;
279         u32 v;
280
281         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
282                 load_mocs(vgpu, ring_id);
283
284         mmio = vgpu->gvt->engine_mmio_list;
285         while (i915_mmio_reg_offset((mmio++)->reg)) {
286                 if (mmio->ring_id != ring_id)
287                         continue;
288
289                 mmio->value = I915_READ_FW(mmio->reg);
290
291                 /*
292                  * if it is an inhibit context, load in_context mmio
293                  * into HW by mmio write. If it is not, skip this mmio
294                  * write.
295                  */
296                 if (mmio->in_context &&
297                     (ctx_ctrl & inhibit_mask) != inhibit_mask)
298                         continue;
299
300                 if (mmio->mask)
301                         v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
302                 else
303                         v = vgpu_vreg(vgpu, mmio->reg);
304
305                 I915_WRITE_FW(mmio->reg, v);
306
307                 trace_render_mmio(vgpu->id, "load",
308                                   i915_mmio_reg_offset(mmio->reg),
309                                   mmio->value, v);
310         }
311
312         handle_tlb_pending_event(vgpu, ring_id);
313 }
314
315 /* Switch ring mmio values (context) from vgpu to host. */
316 static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
317 {
318         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
319         struct engine_mmio *mmio;
320         u32 v;
321
322         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
323                 restore_mocs(vgpu, ring_id);
324
325         mmio = vgpu->gvt->engine_mmio_list;
326         while (i915_mmio_reg_offset((mmio++)->reg)) {
327                 if (mmio->ring_id != ring_id)
328                         continue;
329
330                 vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg);
331
332                 if (mmio->mask) {
333                         vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
334                         v = mmio->value | (mmio->mask << 16);
335                 } else
336                         v = mmio->value;
337
338                 if (mmio->in_context)
339                         continue;
340
341                 I915_WRITE_FW(mmio->reg, v);
342
343                 trace_render_mmio(vgpu->id, "restore",
344                                   i915_mmio_reg_offset(mmio->reg),
345                                   mmio->value, v);
346         }
347 }
348
349 /**
350  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
351  * @pre: the last vGPU that own the engine
352  * @next: the vGPU to switch to
353  * @ring_id: specify the engine
354  *
355  * If pre is null indicates that host own the engine. If next is null
356  * indicates that we are switching to host workload.
357  */
358 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
359                            struct intel_vgpu *next, int ring_id)
360 {
361         struct drm_i915_private *dev_priv;
362
363         if (WARN_ON(!pre && !next))
364                 return;
365
366         gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
367                        pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
368
369         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
370
371         /**
372          * We are using raw mmio access wrapper to improve the
373          * performace for batch mmio read/write, so we need
374          * handle forcewake mannually.
375          */
376         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
377
378         /**
379          * TODO: Optimize for vGPU to vGPU switch by merging
380          * switch_mmio_to_host() and switch_mmio_to_vgpu().
381          */
382         if (pre)
383                 switch_mmio_to_host(pre, ring_id);
384
385         if (next)
386                 switch_mmio_to_vgpu(next, ring_id);
387
388         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
389 }
390
391 /**
392  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
393  * @gvt: GVT device
394  *
395  */
396 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
397 {
398         if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv))
399                 gvt->engine_mmio_list = gen9_engine_mmio_list;
400         else
401                 gvt->engine_mmio_list = gen8_engine_mmio_list;
402 }