Merge tag 'gvt-fixes-2019-03-21' of https://github.com/intel/gvt-linux into drm-intel...
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / mmio_context.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Eddie Dong <eddie.dong@intel.com>
25  *    Kevin Tian <kevin.tian@intel.com>
26  *
27  * Contributors:
28  *    Zhi Wang <zhi.a.wang@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Bing Niu <bing.niu@intel.com>
33  *
34  */
35
36 #include "i915_drv.h"
37 #include "gvt.h"
38 #include "trace.h"
39
40 #define GEN9_MOCS_SIZE          64
41
42 /* Raw offset is appened to each line for convenience. */
43 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
44         {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
45         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
46         {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
47         {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
48         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
49         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
50         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
51         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
52         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
53         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
54         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
55         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
56         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
57         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
58         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
59         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
60         {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
61         {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
62         {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
63         {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
64         {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
65         {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
66
67         {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
68         {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
69         {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
70         {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
71         {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
72         {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
73 };
74
75 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
76         {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
77         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
78         {RCS, HWSTAM, 0x0, false}, /* 0x2098 */
79         {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
80         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
81         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
82         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
83         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
84         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
85         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
86         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
87         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
88         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
89         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
90         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
91         {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
92         {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
93         {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
94         {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
95         {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
96         {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
97         {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
98
99         {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
100         {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
101         {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
102         {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
103         {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
104         {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
105         {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
106         {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
107         {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
108         {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
109         {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
110         {RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
111         {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
112         {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
113         {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
114         {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
115         {RCS, TRVADR, 0, false}, /* 0x4df0 */
116         {RCS, TRTTE, 0, false}, /* 0x4df4 */
117
118         {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
119         {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
120         {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
121         {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
122         {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
123
124         {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
125
126         {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
127
128         {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
129         {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
130         {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
131         {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
132
133         {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
134         {RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
135         {RCS, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
136
137         {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
138         {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
139         {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
140         {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
141 };
142
143 static struct {
144         bool initialized;
145         u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
146         u32 l3cc_table[GEN9_MOCS_SIZE / 2];
147 } gen9_render_mocs;
148
149 static void load_render_mocs(struct drm_i915_private *dev_priv)
150 {
151         i915_reg_t offset;
152         u32 regs[] = {
153                 [RCS] = 0xc800,
154                 [VCS] = 0xc900,
155                 [VCS2] = 0xca00,
156                 [BCS] = 0xcc00,
157                 [VECS] = 0xcb00,
158         };
159         int ring_id, i;
160
161         for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
162                 if (!HAS_ENGINE(dev_priv, ring_id))
163                         continue;
164                 offset.reg = regs[ring_id];
165                 for (i = 0; i < GEN9_MOCS_SIZE; i++) {
166                         gen9_render_mocs.control_table[ring_id][i] =
167                                 I915_READ_FW(offset);
168                         offset.reg += 4;
169                 }
170         }
171
172         offset.reg = 0xb020;
173         for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
174                 gen9_render_mocs.l3cc_table[i] =
175                         I915_READ_FW(offset);
176                 offset.reg += 4;
177         }
178         gen9_render_mocs.initialized = true;
179 }
180
181 static int
182 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
183                                  struct i915_request *req)
184 {
185         u32 *cs;
186         int ret;
187         struct engine_mmio *mmio;
188         struct intel_gvt *gvt = vgpu->gvt;
189         int ring_id = req->engine->id;
190         int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
191
192         if (count == 0)
193                 return 0;
194
195         ret = req->engine->emit_flush(req, EMIT_BARRIER);
196         if (ret)
197                 return ret;
198
199         cs = intel_ring_begin(req, count * 2 + 2);
200         if (IS_ERR(cs))
201                 return PTR_ERR(cs);
202
203         *cs++ = MI_LOAD_REGISTER_IMM(count);
204         for (mmio = gvt->engine_mmio_list.mmio;
205              i915_mmio_reg_valid(mmio->reg); mmio++) {
206                 if (mmio->ring_id != ring_id ||
207                     !mmio->in_context)
208                         continue;
209
210                 *cs++ = i915_mmio_reg_offset(mmio->reg);
211                 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
212                                 (mmio->mask << 16);
213                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
214                               *(cs-2), *(cs-1), vgpu->id, ring_id);
215         }
216
217         *cs++ = MI_NOOP;
218         intel_ring_advance(req, cs);
219
220         ret = req->engine->emit_flush(req, EMIT_BARRIER);
221         if (ret)
222                 return ret;
223
224         return 0;
225 }
226
227 static int
228 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
229                                         struct i915_request *req)
230 {
231         unsigned int index;
232         u32 *cs;
233
234         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
235         if (IS_ERR(cs))
236                 return PTR_ERR(cs);
237
238         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
239
240         for (index = 0; index < GEN9_MOCS_SIZE; index++) {
241                 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
242                 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
243                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
244                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
245
246         }
247
248         *cs++ = MI_NOOP;
249         intel_ring_advance(req, cs);
250
251         return 0;
252 }
253
254 static int
255 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
256                                      struct i915_request *req)
257 {
258         unsigned int index;
259         u32 *cs;
260
261         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
262         if (IS_ERR(cs))
263                 return PTR_ERR(cs);
264
265         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
266
267         for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
268                 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
269                 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
270                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
271                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
272
273         }
274
275         *cs++ = MI_NOOP;
276         intel_ring_advance(req, cs);
277
278         return 0;
279 }
280
281 /*
282  * Use lri command to initialize the mmio which is in context state image for
283  * inhibit context, it contains tracked engine mmio, render_mocs and
284  * render_mocs_l3cc.
285  */
286 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
287                                        struct i915_request *req)
288 {
289         int ret;
290         u32 *cs;
291
292         cs = intel_ring_begin(req, 2);
293         if (IS_ERR(cs))
294                 return PTR_ERR(cs);
295
296         *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
297         *cs++ = MI_NOOP;
298         intel_ring_advance(req, cs);
299
300         ret = restore_context_mmio_for_inhibit(vgpu, req);
301         if (ret)
302                 goto out;
303
304         /* no MOCS register in context except render engine */
305         if (req->engine->id != RCS)
306                 goto out;
307
308         ret = restore_render_mocs_control_for_inhibit(vgpu, req);
309         if (ret)
310                 goto out;
311
312         ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
313         if (ret)
314                 goto out;
315
316 out:
317         cs = intel_ring_begin(req, 2);
318         if (IS_ERR(cs))
319                 return PTR_ERR(cs);
320
321         *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
322         *cs++ = MI_NOOP;
323         intel_ring_advance(req, cs);
324
325         return ret;
326 }
327
328 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
329 {
330         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
331         struct intel_vgpu_submission *s = &vgpu->submission;
332         enum forcewake_domains fw;
333         i915_reg_t reg;
334         u32 regs[] = {
335                 [RCS] = 0x4260,
336                 [VCS] = 0x4264,
337                 [VCS2] = 0x4268,
338                 [BCS] = 0x426c,
339                 [VECS] = 0x4270,
340         };
341
342         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
343                 return;
344
345         if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
346                 return;
347
348         reg = _MMIO(regs[ring_id]);
349
350         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
351          * we need to put a forcewake when invalidating RCS TLB caches,
352          * otherwise device can go to RC6 state and interrupt invalidation
353          * process
354          */
355         fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
356                                             FW_REG_READ | FW_REG_WRITE);
357         if (ring_id == RCS && (INTEL_GEN(dev_priv) >= 9))
358                 fw |= FORCEWAKE_RENDER;
359
360         intel_uncore_forcewake_get(dev_priv, fw);
361
362         I915_WRITE_FW(reg, 0x1);
363
364         if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
365                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
366         else
367                 vgpu_vreg_t(vgpu, reg) = 0;
368
369         intel_uncore_forcewake_put(dev_priv, fw);
370
371         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
372 }
373
374 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
375                         int ring_id)
376 {
377         struct drm_i915_private *dev_priv;
378         i915_reg_t offset, l3_offset;
379         u32 old_v, new_v;
380
381         u32 regs[] = {
382                 [RCS] = 0xc800,
383                 [VCS] = 0xc900,
384                 [VCS2] = 0xca00,
385                 [BCS] = 0xcc00,
386                 [VECS] = 0xcb00,
387         };
388         int i;
389
390         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
391         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
392                 return;
393
394         if ((IS_KABYLAKE(dev_priv)  || IS_BROXTON(dev_priv)
395                 || IS_COFFEELAKE(dev_priv)) && ring_id == RCS)
396                 return;
397
398         if (!pre && !gen9_render_mocs.initialized)
399                 load_render_mocs(dev_priv);
400
401         offset.reg = regs[ring_id];
402         for (i = 0; i < GEN9_MOCS_SIZE; i++) {
403                 if (pre)
404                         old_v = vgpu_vreg_t(pre, offset);
405                 else
406                         old_v = gen9_render_mocs.control_table[ring_id][i];
407                 if (next)
408                         new_v = vgpu_vreg_t(next, offset);
409                 else
410                         new_v = gen9_render_mocs.control_table[ring_id][i];
411
412                 if (old_v != new_v)
413                         I915_WRITE_FW(offset, new_v);
414
415                 offset.reg += 4;
416         }
417
418         if (ring_id == RCS) {
419                 l3_offset.reg = 0xb020;
420                 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
421                         if (pre)
422                                 old_v = vgpu_vreg_t(pre, l3_offset);
423                         else
424                                 old_v = gen9_render_mocs.l3cc_table[i];
425                         if (next)
426                                 new_v = vgpu_vreg_t(next, l3_offset);
427                         else
428                                 new_v = gen9_render_mocs.l3cc_table[i];
429
430                         if (old_v != new_v)
431                                 I915_WRITE_FW(l3_offset, new_v);
432
433                         l3_offset.reg += 4;
434                 }
435         }
436 }
437
438 #define CTX_CONTEXT_CONTROL_VAL 0x03
439
440 bool is_inhibit_context(struct intel_context *ce)
441 {
442         const u32 *reg_state = ce->lrc_reg_state;
443         u32 inhibit_mask =
444                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
445
446         return inhibit_mask ==
447                 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
448 }
449
450 /* Switch ring mmio values (context). */
451 static void switch_mmio(struct intel_vgpu *pre,
452                         struct intel_vgpu *next,
453                         int ring_id)
454 {
455         struct drm_i915_private *dev_priv;
456         struct intel_vgpu_submission *s;
457         struct engine_mmio *mmio;
458         u32 old_v, new_v;
459
460         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
461         if (INTEL_GEN(dev_priv) >= 9)
462                 switch_mocs(pre, next, ring_id);
463
464         for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
465              i915_mmio_reg_valid(mmio->reg); mmio++) {
466                 if (mmio->ring_id != ring_id)
467                         continue;
468                 /*
469                  * No need to do save or restore of the mmio which is in context
470                  * state image on kabylake, it's initialized by lri command and
471                  * save or restore with context together.
472                  */
473                 if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)
474                         || IS_COFFEELAKE(dev_priv)) && mmio->in_context)
475                         continue;
476
477                 // save
478                 if (pre) {
479                         vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
480                         if (mmio->mask)
481                                 vgpu_vreg_t(pre, mmio->reg) &=
482                                                 ~(mmio->mask << 16);
483                         old_v = vgpu_vreg_t(pre, mmio->reg);
484                 } else
485                         old_v = mmio->value = I915_READ_FW(mmio->reg);
486
487                 // restore
488                 if (next) {
489                         s = &next->submission;
490                         /*
491                          * No need to restore the mmio which is in context state
492                          * image if it's not inhibit context, it will restore
493                          * itself.
494                          */
495                         if (mmio->in_context &&
496                             !is_inhibit_context(&s->shadow_ctx->__engine[ring_id]))
497                                 continue;
498
499                         if (mmio->mask)
500                                 new_v = vgpu_vreg_t(next, mmio->reg) |
501                                                         (mmio->mask << 16);
502                         else
503                                 new_v = vgpu_vreg_t(next, mmio->reg);
504                 } else {
505                         if (mmio->in_context)
506                                 continue;
507                         if (mmio->mask)
508                                 new_v = mmio->value | (mmio->mask << 16);
509                         else
510                                 new_v = mmio->value;
511                 }
512
513                 I915_WRITE_FW(mmio->reg, new_v);
514
515                 trace_render_mmio(pre ? pre->id : 0,
516                                   next ? next->id : 0,
517                                   "switch",
518                                   i915_mmio_reg_offset(mmio->reg),
519                                   old_v, new_v);
520         }
521
522         if (next)
523                 handle_tlb_pending_event(next, ring_id);
524 }
525
526 /**
527  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
528  * @pre: the last vGPU that own the engine
529  * @next: the vGPU to switch to
530  * @ring_id: specify the engine
531  *
532  * If pre is null indicates that host own the engine. If next is null
533  * indicates that we are switching to host workload.
534  */
535 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
536                            struct intel_vgpu *next, int ring_id)
537 {
538         struct drm_i915_private *dev_priv;
539
540         if (WARN_ON(!pre && !next))
541                 return;
542
543         gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
544                        pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
545
546         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
547
548         /**
549          * We are using raw mmio access wrapper to improve the
550          * performace for batch mmio read/write, so we need
551          * handle forcewake mannually.
552          */
553         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
554         switch_mmio(pre, next, ring_id);
555         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
556 }
557
558 /**
559  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
560  * @gvt: GVT device
561  *
562  */
563 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
564 {
565         struct engine_mmio *mmio;
566
567         if (INTEL_GEN(gvt->dev_priv) >= 9)
568                 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
569         else
570                 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
571
572         for (mmio = gvt->engine_mmio_list.mmio;
573              i915_mmio_reg_valid(mmio->reg); mmio++) {
574                 if (mmio->in_context) {
575                         gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
576                         intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
577                 }
578         }
579 }