2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Kevin Tian <kevin.tian@intel.com>
29 * Tina Zhang <tina.zhang@intel.com>
30 * Min He <min.he@intel.com>
31 * Niu Bing <bing.niu@intel.com>
32 * Zhi Wang <zhi.a.wang@intel.com>
42 #define D_BDW (1 << 0)
43 #define D_SKL (1 << 1)
44 #define D_KBL (1 << 2)
46 #define D_GEN9PLUS (D_SKL | D_KBL)
47 #define D_GEN8PLUS (D_BDW | D_SKL | D_KBL)
49 #define D_SKL_PLUS (D_SKL | D_KBL)
50 #define D_BDW_PLUS (D_BDW | D_SKL | D_KBL)
52 #define D_PRE_SKL (D_BDW)
53 #define D_ALL (D_BDW | D_SKL | D_KBL)
55 typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *,
58 struct intel_gvt_mmio_info {
65 struct hlist_node node;
68 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
70 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
71 bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
73 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
74 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
75 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
76 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
80 #define INTEL_GVT_MMIO_OFFSET(reg) ({ \
81 typeof(reg) __reg = reg; \
82 u32 *offset = (u32 *)&__reg; \
86 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
87 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
88 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
90 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
92 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
93 void *p_data, unsigned int bytes);
94 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
95 void *p_data, unsigned int bytes);
97 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
98 void *p_data, unsigned int bytes);
99 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
100 void *p_data, unsigned int bytes);
102 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
103 unsigned int offset);
105 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
106 void *pdata, unsigned int bytes, bool is_read);