drm/i915: properly init lockdep class
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / fb_decoder.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *
26  * Contributors:
27  *    Bing Niu <bing.niu@intel.com>
28  *    Xu Han <xu.han@intel.com>
29  *    Ping Gao <ping.a.gao@intel.com>
30  *    Xiaoguang Chen <xiaoguang.chen@intel.com>
31  *    Yang Liu <yang2.liu@intel.com>
32  *    Tina Zhang <tina.zhang@intel.com>
33  *
34  */
35
36 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_drv.h"
38 #include "gvt.h"
39
40 #define PRIMARY_FORMAT_NUM      16
41 struct pixel_format {
42         int     drm_format;     /* Pixel format in DRM definition */
43         int     bpp;            /* Bits per pixel, 0 indicates invalid */
44         char    *desc;          /* The description */
45 };
46
47 static struct pixel_format bdw_pixel_formats[] = {
48         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
49         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
50         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
51         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
52
53         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
54         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
55
56         /* non-supported format has bpp default to 0 */
57         {0, 0, NULL},
58 };
59
60 static struct pixel_format skl_pixel_formats[] = {
61         {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
62         {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
63         {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
64         {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
65
66         {DRM_FORMAT_C8, 8, "8-bit Indexed"},
67         {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
68         {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
69         {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
70
71         {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
72         {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
73         {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
74         {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
75
76         /* non-supported format has bpp default to 0 */
77         {0, 0, NULL},
78 };
79
80 static int bdw_format_to_drm(int format)
81 {
82         int bdw_pixel_formats_index = 6;
83
84         switch (format) {
85         case DISPPLANE_8BPP:
86                 bdw_pixel_formats_index = 0;
87                 break;
88         case DISPPLANE_BGRX565:
89                 bdw_pixel_formats_index = 1;
90                 break;
91         case DISPPLANE_BGRX888:
92                 bdw_pixel_formats_index = 2;
93                 break;
94         case DISPPLANE_RGBX101010:
95                 bdw_pixel_formats_index = 3;
96                 break;
97         case DISPPLANE_BGRX101010:
98                 bdw_pixel_formats_index = 4;
99                 break;
100         case DISPPLANE_RGBX888:
101                 bdw_pixel_formats_index = 5;
102                 break;
103
104         default:
105                 break;
106         }
107
108         return bdw_pixel_formats_index;
109 }
110
111 static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
112         int yuv_order)
113 {
114         int skl_pixel_formats_index = 12;
115
116         switch (format) {
117         case PLANE_CTL_FORMAT_INDEXED:
118                 skl_pixel_formats_index = 4;
119                 break;
120         case PLANE_CTL_FORMAT_RGB_565:
121                 skl_pixel_formats_index = 5;
122                 break;
123         case PLANE_CTL_FORMAT_XRGB_8888:
124                 if (rgb_order)
125                         skl_pixel_formats_index = alpha ? 6 : 7;
126                 else
127                         skl_pixel_formats_index = alpha ? 8 : 9;
128                 break;
129         case PLANE_CTL_FORMAT_XRGB_2101010:
130                 skl_pixel_formats_index = rgb_order ? 10 : 11;
131                 break;
132         case PLANE_CTL_FORMAT_YUV422:
133                 skl_pixel_formats_index = yuv_order >> 16;
134                 if (skl_pixel_formats_index > 3)
135                         return -EINVAL;
136                 break;
137
138         default:
139                 break;
140         }
141
142         return skl_pixel_formats_index;
143 }
144
145 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
146         u32 tiled, int stride_mask, int bpp)
147 {
148         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
149
150         u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
151         u32 stride = stride_reg;
152
153         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
154                 switch (tiled) {
155                 case PLANE_CTL_TILED_LINEAR:
156                         stride = stride_reg * 64;
157                         break;
158                 case PLANE_CTL_TILED_X:
159                         stride = stride_reg * 512;
160                         break;
161                 case PLANE_CTL_TILED_Y:
162                         stride = stride_reg * 128;
163                         break;
164                 case PLANE_CTL_TILED_YF:
165                         if (bpp == 8)
166                                 stride = stride_reg * 64;
167                         else if (bpp == 16 || bpp == 32 || bpp == 64)
168                                 stride = stride_reg * 128;
169                         else
170                                 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
171                         break;
172                 default:
173                         gvt_dbg_core("skl: unsupported tile format:%x\n",
174                                 tiled);
175                 }
176         }
177
178         return stride;
179 }
180
181 static int get_active_pipe(struct intel_vgpu *vgpu)
182 {
183         int i;
184
185         for (i = 0; i < I915_MAX_PIPES; i++)
186                 if (pipe_is_enabled(vgpu, i))
187                         break;
188
189         return i;
190 }
191
192 /**
193  * intel_vgpu_decode_primary_plane - Decode primary plane
194  * @vgpu: input vgpu
195  * @plane: primary plane to save decoded info
196  * This function is called for decoding plane
197  *
198  * Returns:
199  * 0 on success, non-zero if failed.
200  */
201 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
202         struct intel_vgpu_primary_plane_format *plane)
203 {
204         u32 val, fmt;
205         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
206         int pipe;
207
208         pipe = get_active_pipe(vgpu);
209         if (pipe >= I915_MAX_PIPES)
210                 return -ENODEV;
211
212         val = vgpu_vreg(vgpu, DSPCNTR(pipe));
213         plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
214         if (!plane->enabled)
215                 return -ENODEV;
216
217         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
218                 plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
219                 _PLANE_CTL_TILED_SHIFT;
220                 fmt = skl_format_to_drm(
221                         val & PLANE_CTL_FORMAT_MASK,
222                         val & PLANE_CTL_ORDER_RGBX,
223                         val & PLANE_CTL_ALPHA_MASK,
224                         val & PLANE_CTL_YUV422_ORDER_MASK);
225                 plane->bpp = skl_pixel_formats[fmt].bpp;
226                 plane->drm_format = skl_pixel_formats[fmt].drm_format;
227         } else {
228                 plane->tiled = !!(val & DISPPLANE_TILED);
229                 fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
230                 plane->bpp = bdw_pixel_formats[fmt].bpp;
231                 plane->drm_format = bdw_pixel_formats[fmt].drm_format;
232         }
233
234         if (!plane->bpp) {
235                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
236                 return -EINVAL;
237         }
238
239         plane->hw_format = fmt;
240
241         plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
242         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
243                 gvt_vgpu_err("invalid gma address: %lx\n",
244                              (unsigned long)plane->base);
245                 return  -EINVAL;
246         }
247
248         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
249         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
250                 gvt_vgpu_err("invalid gma address: %lx\n",
251                                 (unsigned long)plane->base);
252                 return  -EINVAL;
253         }
254
255         plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
256                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ?
257                         (_PRI_PLANE_STRIDE_MASK >> 6) :
258                                 _PRI_PLANE_STRIDE_MASK, plane->bpp);
259
260         plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
261                 _PIPE_H_SRCSZ_SHIFT;
262         plane->width += 1;
263         plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) &
264                         _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
265         plane->height += 1;     /* raw height is one minus the real value */
266
267         val = vgpu_vreg(vgpu, DSPTILEOFF(pipe));
268         plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
269                 _PRI_PLANE_X_OFF_SHIFT;
270         plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
271                 _PRI_PLANE_Y_OFF_SHIFT;
272
273         return 0;
274 }
275
276 #define CURSOR_FORMAT_NUM       (1 << 6)
277 struct cursor_mode_format {
278         int     drm_format;     /* Pixel format in DRM definition */
279         u8      bpp;            /* Bits per pixel; 0 indicates invalid */
280         u32     width;          /* In pixel */
281         u32     height;         /* In lines */
282         char    *desc;          /* The description */
283 };
284
285 static struct cursor_mode_format cursor_pixel_formats[] = {
286         {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
287         {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
288         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
289         {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
290
291         /* non-supported format has bpp default to 0 */
292         {0, 0, 0, 0, NULL},
293 };
294
295 static int cursor_mode_to_drm(int mode)
296 {
297         int cursor_pixel_formats_index = 4;
298
299         switch (mode) {
300         case CURSOR_MODE_128_ARGB_AX:
301                 cursor_pixel_formats_index = 0;
302                 break;
303         case CURSOR_MODE_256_ARGB_AX:
304                 cursor_pixel_formats_index = 1;
305                 break;
306         case CURSOR_MODE_64_ARGB_AX:
307                 cursor_pixel_formats_index = 2;
308                 break;
309         case CURSOR_MODE_64_32B_AX:
310                 cursor_pixel_formats_index = 3;
311                 break;
312
313         default:
314                 break;
315         }
316
317         return cursor_pixel_formats_index;
318 }
319
320 /**
321  * intel_vgpu_decode_cursor_plane - Decode sprite plane
322  * @vgpu: input vgpu
323  * @plane: cursor plane to save decoded info
324  * This function is called for decoding plane
325  *
326  * Returns:
327  * 0 on success, non-zero if failed.
328  */
329 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
330         struct intel_vgpu_cursor_plane_format *plane)
331 {
332         u32 val, mode, index;
333         u32 alpha_plane, alpha_force;
334         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
335         int pipe;
336
337         pipe = get_active_pipe(vgpu);
338         if (pipe >= I915_MAX_PIPES)
339                 return -ENODEV;
340
341         val = vgpu_vreg(vgpu, CURCNTR(pipe));
342         mode = val & CURSOR_MODE;
343         plane->enabled = (mode != CURSOR_MODE_DISABLE);
344         if (!plane->enabled)
345                 return -ENODEV;
346
347         index = cursor_mode_to_drm(mode);
348
349         if (!cursor_pixel_formats[index].bpp) {
350                 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
351                 return -EINVAL;
352         }
353         plane->mode = mode;
354         plane->bpp = cursor_pixel_formats[index].bpp;
355         plane->drm_format = cursor_pixel_formats[index].drm_format;
356         plane->width = cursor_pixel_formats[index].width;
357         plane->height = cursor_pixel_formats[index].height;
358
359         alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
360                                 _CURSOR_ALPHA_PLANE_SHIFT;
361         alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
362                                 _CURSOR_ALPHA_FORCE_SHIFT;
363         if (alpha_plane || alpha_force)
364                 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
365                         alpha_plane, alpha_force);
366
367         plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
368         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
369                 gvt_vgpu_err("invalid gma address: %lx\n",
370                              (unsigned long)plane->base);
371                 return  -EINVAL;
372         }
373
374         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
375         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
376                 gvt_vgpu_err("invalid gma address: %lx\n",
377                                 (unsigned long)plane->base);
378                 return  -EINVAL;
379         }
380
381         val = vgpu_vreg(vgpu, CURPOS(pipe));
382         plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
383         plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
384         plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
385         plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
386
387         return 0;
388 }
389
390 #define SPRITE_FORMAT_NUM       (1 << 3)
391
392 static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
393         [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
394         [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
395         [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
396         [0x4] = {DRM_FORMAT_AYUV, 32,
397                 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
398 };
399
400 /**
401  * intel_vgpu_decode_sprite_plane - Decode sprite plane
402  * @vgpu: input vgpu
403  * @plane: sprite plane to save decoded info
404  * This function is called for decoding plane
405  *
406  * Returns:
407  * 0 on success, non-zero if failed.
408  */
409 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
410         struct intel_vgpu_sprite_plane_format *plane)
411 {
412         u32 val, fmt;
413         u32 color_order, yuv_order;
414         int drm_format;
415         int pipe;
416
417         pipe = get_active_pipe(vgpu);
418         if (pipe >= I915_MAX_PIPES)
419                 return -ENODEV;
420
421         val = vgpu_vreg(vgpu, SPRCTL(pipe));
422         plane->enabled = !!(val & SPRITE_ENABLE);
423         if (!plane->enabled)
424                 return -ENODEV;
425
426         plane->tiled = !!(val & SPRITE_TILED);
427         color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
428         yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
429                                 _SPRITE_YUV_ORDER_SHIFT;
430
431         fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
432         if (!sprite_pixel_formats[fmt].bpp) {
433                 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
434                 return -EINVAL;
435         }
436         plane->hw_format = fmt;
437         plane->bpp = sprite_pixel_formats[fmt].bpp;
438         drm_format = sprite_pixel_formats[fmt].drm_format;
439
440         /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
441          * BGR depending on the state of the color_order field
442          */
443         if (!color_order) {
444                 if (drm_format == DRM_FORMAT_XRGB2101010)
445                         drm_format = DRM_FORMAT_XBGR2101010;
446                 else if (drm_format == DRM_FORMAT_XRGB8888)
447                         drm_format = DRM_FORMAT_XBGR8888;
448         }
449
450         if (drm_format == DRM_FORMAT_YUV422) {
451                 switch (yuv_order) {
452                 case 0:
453                         drm_format = DRM_FORMAT_YUYV;
454                         break;
455                 case 1:
456                         drm_format = DRM_FORMAT_UYVY;
457                         break;
458                 case 2:
459                         drm_format = DRM_FORMAT_YVYU;
460                         break;
461                 case 3:
462                         drm_format = DRM_FORMAT_VYUY;
463                         break;
464                 default:
465                         /* yuv_order has only 2 bits */
466                         break;
467                 }
468         }
469
470         plane->drm_format = drm_format;
471
472         plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
473         if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {
474                 gvt_vgpu_err("invalid gma address: %lx\n",
475                              (unsigned long)plane->base);
476                 return  -EINVAL;
477         }
478
479         plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
480         if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
481                 gvt_vgpu_err("invalid gma address: %lx\n",
482                                 (unsigned long)plane->base);
483                 return  -EINVAL;
484         }
485
486         plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) &
487                                 _SPRITE_STRIDE_MASK;
488
489         val = vgpu_vreg(vgpu, SPRSIZE(pipe));
490         plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
491                 _SPRITE_SIZE_HEIGHT_SHIFT;
492         plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
493                 _SPRITE_SIZE_WIDTH_SHIFT;
494         plane->height += 1;     /* raw height is one minus the real value */
495         plane->width += 1;      /* raw width is one minus the real value */
496
497         val = vgpu_vreg(vgpu, SPRPOS(pipe));
498         plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
499         plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
500
501         val = vgpu_vreg(vgpu, SPROFFSET(pipe));
502         plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
503                            _SPRITE_OFFSET_START_X_SHIFT;
504         plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
505                            _SPRITE_OFFSET_START_Y_SHIFT;
506
507         return 0;
508 }