drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40 #include "i915_pvinfo.h"
  41 #include "trace.h"
  42
  43 #define INVALID_OP    (~0U)
  44
  45 #define OP_LEN_MI           9
  46 #define OP_LEN_2D           10
  47 #define OP_LEN_3D_MEDIA     16
  48 #define OP_LEN_MFX_VC       16
  49 #define OP_LEN_VEBOX        16
  50
  51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  52
  53 struct sub_op_bits {
  54         int hi;
  55         int low;
  56 };
  57 struct decode_info {
  58         char *name;
  59         int op_len;
  60         int nr_sub_op;
  61         struct sub_op_bits *sub_op;
  62 };
  63
  64 #define   MAX_CMD_BUDGET                        0x7fffffff
  65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  68
  69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  72
  73 /* Render Command Map */
  74
  75 /* MI_* command Opcode (28:23) */
  76 #define OP_MI_NOOP                          0x0
  77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  78 #define OP_MI_USER_INTERRUPT                0x2
  79 #define OP_MI_WAIT_FOR_EVENT                0x3
  80 #define OP_MI_FLUSH                         0x4
  81 #define OP_MI_ARB_CHECK                     0x5
  82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  83 #define OP_MI_REPORT_HEAD                   0x7
  84 #define OP_MI_ARB_ON_OFF                    0x8
  85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  86 #define OP_MI_BATCH_BUFFER_END              0xA
  87 #define OP_MI_SUSPEND_FLUSH                 0xB
  88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  93 #define OP_MI_DISPLAY_FLIP                  0x14
  94 #define OP_MI_SEMAPHORE_MBOX                0x16
  95 #define OP_MI_SET_CONTEXT                   0x18
  96 #define OP_MI_MATH                          0x1A
  97 #define OP_MI_URB_CLEAR                     0x19
  98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
  99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 100
 101 #define OP_MI_STORE_DATA_IMM                0x20
 102 #define OP_MI_STORE_DATA_INDEX              0x21
 103 #define OP_MI_LOAD_REGISTER_IMM             0x22
 104 #define OP_MI_UPDATE_GTT                    0x23
 105 #define OP_MI_STORE_REGISTER_MEM            0x24
 106 #define OP_MI_FLUSH_DW                      0x26
 107 #define OP_MI_CLFLUSH                       0x27
 108 #define OP_MI_REPORT_PERF_COUNT             0x28
 109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 114 #define OP_MI_2E                            0x2E  /* BDW+ */
 115 #define OP_MI_2F                            0x2F  /* BDW+ */
 116 #define OP_MI_BATCH_BUFFER_START            0x31
 117
 118 /* Bit definition for dword 0 */
 119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 120
 121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 122
 123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 127
 128 /* 2D command: Opcode (28:22) */
 129 #define OP_2D(x)    ((2<<7) | x)
 130
 131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 155
 156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 159
 160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 161
 162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 165
 166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 167
 168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 169
 170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 175
 176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 180
 181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 247
 248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 259
 260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 288
 289 /* VCCP Command Parser */
 290
 291 /*
 292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 293  * git://anongit.freedesktop.org/vaapi/intel-driver
 294  * src/i965_defines.h
 295  *
 296  */
 297
 298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 299         (3 << 13 | \
 300          (pipeline) << 11 | \
 301          (op) << 8 | \
 302          (sub_opa) << 5 | \
 303          (sub_opb))
 304
 305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 316
 317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 318
 319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 331
 332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 337
 338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 343
 344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 347
 348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 351
 352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 353         (3 << 13 | \
 354          (pipeline) << 11 | \
 355          (op) << 8 | \
 356          (sub_opa) << 5 | \
 357          (sub_opb))
 358
 359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 362
 363 struct parser_exec_state;
 364
 365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 366
 367 #define GVT_CMD_HASH_BITS   7
 368
 369 /* which DWords need address fix */
 370 #define ADDR_FIX_1(x1)                  (1 << (x1))
 371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 375
 376 struct cmd_info {
 377         char *name;
 378         u32 opcode;
 379
 380 #define F_LEN_MASK      (1U<<0)
 381 #define F_LEN_CONST  1U
 382 #define F_LEN_VAR    0U
 383
 384 /*
 385  * command has its own ip advance logic
 386  * e.g. MI_BATCH_START, MI_BATCH_END
 387  */
 388 #define F_IP_ADVANCE_CUSTOM (1<<1)
 389
 390 #define F_POST_HANDLE   (1<<2)
 391         u32 flag;
 392
 393 #define R_RCS   (1 << RCS)
 394 #define R_VCS1  (1 << VCS)
 395 #define R_VCS2  (1 << VCS2)
 396 #define R_VCS   (R_VCS1 | R_VCS2)
 397 #define R_BCS   (1 << BCS)
 398 #define R_VECS  (1 << VECS)
 399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 401         uint16_t rings;
 402
 403         /* devices that support this cmd: SNB/IVB/HSW/... */
 404         uint16_t devices;
 405
 406         /* which DWords are address that need fix up.
 407          * bit 0 means a 32-bit non address operand in command
 408          * bit 1 means address operand, which could be 32-bit
 409          * or 64-bit depending on different architectures.(
 410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 411          * No matter the address length, each address only takes
 412          * one bit in the bitmap.
 413          */
 414         uint16_t addr_bitmap;
 415
 416         /* flag == F_LEN_CONST : command length
 417          * flag == F_LEN_VAR : length bias bits
 418          * Note: length is in DWord
 419          */
 420         uint8_t len;
 421
 422         parser_cmd_handler handler;
 423 };
 424
 425 struct cmd_entry {
 426         struct hlist_node hlist;
 427         struct cmd_info *info;
 428 };
 429
 430 enum {
 431         RING_BUFFER_INSTRUCTION,
 432         BATCH_BUFFER_INSTRUCTION,
 433         BATCH_BUFFER_2ND_LEVEL,
 434 };
 435
 436 enum {
 437         GTT_BUFFER,
 438         PPGTT_BUFFER
 439 };
 440
 441 struct parser_exec_state {
 442         struct intel_vgpu *vgpu;
 443         int ring_id;
 444
 445         int buf_type;
 446
 447         /* batch buffer address type */
 448         int buf_addr_type;
 449
 450         /* graphics memory address of ring buffer start */
 451         unsigned long ring_start;
 452         unsigned long ring_size;
 453         unsigned long ring_head;
 454         unsigned long ring_tail;
 455
 456         /* instruction graphics memory address */
 457         unsigned long ip_gma;
 458
 459         /* mapped va of the instr_gma */
 460         void *ip_va;
 461         void *rb_va;
 462
 463         void *ret_bb_va;
 464         /* next instruction when return from  batch buffer to ring buffer */
 465         unsigned long ret_ip_gma_ring;
 466
 467         /* next instruction when return from 2nd batch buffer to batch buffer */
 468         unsigned long ret_ip_gma_bb;
 469
 470         /* batch buffer address type (GTT or PPGTT)
 471          * used when ret from 2nd level batch buffer
 472          */
 473         int saved_buf_addr_type;
 474         bool is_ctx_wa;
 475
 476         struct cmd_info *info;
 477
 478         struct intel_vgpu_workload *workload;
 479 };
 480
 481 #define gmadr_dw_number(s)      \
 482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 483
 484 static unsigned long bypass_scan_mask = 0;
 485
 486 /* ring ALL, type = 0 */
 487 static struct sub_op_bits sub_op_mi[] = {
 488         {31, 29},
 489         {28, 23},
 490 };
 491
 492 static struct decode_info decode_info_mi = {
 493         "MI",
 494         OP_LEN_MI,
 495         ARRAY_SIZE(sub_op_mi),
 496         sub_op_mi,
 497 };
 498
 499 /* ring RCS, command type 2 */
 500 static struct sub_op_bits sub_op_2d[] = {
 501         {31, 29},
 502         {28, 22},
 503 };
 504
 505 static struct decode_info decode_info_2d = {
 506         "2D",
 507         OP_LEN_2D,
 508         ARRAY_SIZE(sub_op_2d),
 509         sub_op_2d,
 510 };
 511
 512 /* ring RCS, command type 3 */
 513 static struct sub_op_bits sub_op_3d_media[] = {
 514         {31, 29},
 515         {28, 27},
 516         {26, 24},
 517         {23, 16},
 518 };
 519
 520 static struct decode_info decode_info_3d_media = {
 521         "3D_Media",
 522         OP_LEN_3D_MEDIA,
 523         ARRAY_SIZE(sub_op_3d_media),
 524         sub_op_3d_media,
 525 };
 526
 527 /* ring VCS, command type 3 */
 528 static struct sub_op_bits sub_op_mfx_vc[] = {
 529         {31, 29},
 530         {28, 27},
 531         {26, 24},
 532         {23, 21},
 533         {20, 16},
 534 };
 535
 536 static struct decode_info decode_info_mfx_vc = {
 537         "MFX_VC",
 538         OP_LEN_MFX_VC,
 539         ARRAY_SIZE(sub_op_mfx_vc),
 540         sub_op_mfx_vc,
 541 };
 542
 543 /* ring VECS, command type 3 */
 544 static struct sub_op_bits sub_op_vebox[] = {
 545         {31, 29},
 546         {28, 27},
 547         {26, 24},
 548         {23, 21},
 549         {20, 16},
 550 };
 551
 552 static struct decode_info decode_info_vebox = {
 553         "VEBOX",
 554         OP_LEN_VEBOX,
 555         ARRAY_SIZE(sub_op_vebox),
 556         sub_op_vebox,
 557 };
 558
 559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 560         [RCS] = {
 561                 &decode_info_mi,
 562                 NULL,
 563                 NULL,
 564                 &decode_info_3d_media,
 565                 NULL,
 566                 NULL,
 567                 NULL,
 568                 NULL,
 569         },
 570
 571         [VCS] = {
 572                 &decode_info_mi,
 573                 NULL,
 574                 NULL,
 575                 &decode_info_mfx_vc,
 576                 NULL,
 577                 NULL,
 578                 NULL,
 579                 NULL,
 580         },
 581
 582         [BCS] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 &decode_info_2d,
 586                 NULL,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VECS] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_vebox,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [VCS2] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 NULL,
 608                 &decode_info_mfx_vc,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614 };
 615
 616 static inline u32 get_opcode(u32 cmd, int ring_id)
 617 {
 618         struct decode_info *d_info;
 619
 620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 621         if (d_info == NULL)
 622                 return INVALID_OP;
 623
 624         return cmd >> (32 - d_info->op_len);
 625 }
 626
 627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 628                 unsigned int opcode, int ring_id)
 629 {
 630         struct cmd_entry *e;
 631
 632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 633                 if ((opcode == e->info->opcode) &&
 634                                 (e->info->rings & (1 << ring_id)))
 635                         return e->info;
 636         }
 637         return NULL;
 638 }
 639
 640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 641                 u32 cmd, int ring_id)
 642 {
 643         u32 opcode;
 644
 645         opcode = get_opcode(cmd, ring_id);
 646         if (opcode == INVALID_OP)
 647                 return NULL;
 648
 649         return find_cmd_entry(gvt, opcode, ring_id);
 650 }
 651
 652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 653 {
 654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 655 }
 656
 657 static inline void print_opcode(u32 cmd, int ring_id)
 658 {
 659         struct decode_info *d_info;
 660         int i;
 661
 662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 663         if (d_info == NULL)
 664                 return;
 665
 666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 667                         cmd >> (32 - d_info->op_len), d_info->name);
 668
 669         for (i = 0; i < d_info->nr_sub_op; i++)
 670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 671                                         d_info->sub_op[i].low));
 672
 673         pr_err("\n");
 674 }
 675
 676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 677 {
 678         return s->ip_va + (index << 2);
 679 }
 680
 681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 682 {
 683         return *cmd_ptr(s, index);
 684 }
 685
 686 static void parser_exec_state_dump(struct parser_exec_state *s)
 687 {
 688         int cnt = 0;
 689         int i;
 690
 691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 694                         s->ring_head, s->ring_tail);
 695
 696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 698                         "RING_BUFFER" : "BATCH_BUFFER",
 699                         s->buf_addr_type == GTT_BUFFER ?
 700                         "GTT" : "PPGTT", s->ip_gma);
 701
 702         if (s->ip_va == NULL) {
 703                 gvt_dbg_cmd(" ip_va(NULL)");
 704                 return;
 705         }
 706
 707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 709                         cmd_val(s, 2), cmd_val(s, 3));
 710
 711         print_opcode(cmd_val(s, 0), s->ring_id);
 712
 713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 714
 715         while (cnt < 1024) {
 716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 717                 for (i = 0; i < 8; i++)
 718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 719                 gvt_dbg_cmd("\n");
 720
 721                 s->ip_va += 8 * sizeof(u32);
 722                 cnt += 8;
 723         }
 724 }
 725
 726 static inline void update_ip_va(struct parser_exec_state *s)
 727 {
 728         unsigned long len = 0;
 729
 730         if (WARN_ON(s->ring_head == s->ring_tail))
 731                 return;
 732
 733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 734                 unsigned long ring_top = s->ring_start + s->ring_size;
 735
 736                 if (s->ring_head > s->ring_tail) {
 737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 738                                 len = (s->ip_gma - s->ring_head);
 739                         else if (s->ip_gma >= s->ring_start &&
 740                                         s->ip_gma <= s->ring_tail)
 741                                 len = (ring_top - s->ring_head) +
 742                                         (s->ip_gma - s->ring_start);
 743                 } else
 744                         len = (s->ip_gma - s->ring_head);
 745
 746                 s->ip_va = s->rb_va + len;
 747         } else {/* shadow batch buffer */
 748                 s->ip_va = s->ret_bb_va;
 749         }
 750 }
 751
 752 static inline int ip_gma_set(struct parser_exec_state *s,
 753                 unsigned long ip_gma)
 754 {
 755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 756
 757         s->ip_gma = ip_gma;
 758         update_ip_va(s);
 759         return 0;
 760 }
 761
 762 static inline int ip_gma_advance(struct parser_exec_state *s,
 763                 unsigned int dw_len)
 764 {
 765         s->ip_gma += (dw_len << 2);
 766
 767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 768                 if (s->ip_gma >= s->ring_start + s->ring_size)
 769                         s->ip_gma -= s->ring_size;
 770                 update_ip_va(s);
 771         } else {
 772                 s->ip_va += (dw_len << 2);
 773         }
 774
 775         return 0;
 776 }
 777
 778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
 779 {
 780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 781                 return info->len;
 782         else
 783                 return (cmd & ((1U << info->len) - 1)) + 2;
 784         return 0;
 785 }
 786
 787 static inline int cmd_length(struct parser_exec_state *s)
 788 {
 789         return get_cmd_length(s->info, cmd_val(s, 0));
 790 }
 791
 792 /* do not remove this, some platform may need clflush here */
 793 #define patch_value(s, addr, val) do { \
 794         *addr = val; \
 795 } while (0)
 796
 797 static bool is_shadowed_mmio(unsigned int offset)
 798 {
 799         bool ret = false;
 800
 801         if ((offset == 0x2168) || /*BB current head register UDW */
 802             (offset == 0x2140) || /*BB current header register */
 803             (offset == 0x211c) || /*second BB header register UDW */
 804             (offset == 0x2114)) { /*second BB header register UDW */
 805                 ret = true;
 806         }
 807         return ret;
 808 }
 809
 810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 811 {
 812         return (offset >= 0x24d0 && offset < 0x2500);
 813 }
 814
 815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 816                                      unsigned int offset, unsigned int index)
 817 {
 818         struct intel_gvt *gvt = s->vgpu->gvt;
 819         unsigned int data = cmd_val(s, index + 1);
 820
 821         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
 822                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 823                         offset, data);
 824                 return -EPERM;
 825         }
 826         return 0;
 827 }
 828
 829 static inline bool is_mocs_mmio(unsigned int offset)
 830 {
 831         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 832                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 833 }
 834
 835 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 836                                 unsigned int offset, unsigned int index)
 837 {
 838         if (!is_mocs_mmio(offset))
 839                 return -EINVAL;
 840         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 841         return 0;
 842 }
 843
 844 static int cmd_reg_handler(struct parser_exec_state *s,
 845         unsigned int offset, unsigned int index, char *cmd)
 846 {
 847         struct intel_vgpu *vgpu = s->vgpu;
 848         struct intel_gvt *gvt = vgpu->gvt;
 849
 850         if (offset + 4 > gvt->device_info.mmio_size) {
 851                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 852                                 cmd, offset);
 853                 return -EFAULT;
 854         }
 855
 856         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 857                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 858                                 cmd, offset);
 859                 return 0;
 860         }
 861
 862         if (is_shadowed_mmio(offset)) {
 863                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 864                 return 0;
 865         }
 866
 867         if (is_mocs_mmio(offset) &&
 868             mocs_cmd_reg_handler(s, offset, index))
 869                 return -EINVAL;
 870
 871         if (is_force_nonpriv_mmio(offset) &&
 872                 force_nonpriv_reg_handler(s, offset, index))
 873                 return -EPERM;
 874
 875         if (offset == i915_mmio_reg_offset(DERRMR) ||
 876                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 877                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 878                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 879         }
 880
 881         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 882         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 883         return 0;
 884 }
 885
 886 #define cmd_reg(s, i) \
 887         (cmd_val(s, i) & GENMASK(22, 2))
 888
 889 #define cmd_reg_inhibit(s, i) \
 890         (cmd_val(s, i) & GENMASK(22, 18))
 891
 892 #define cmd_gma(s, i) \
 893         (cmd_val(s, i) & GENMASK(31, 2))
 894
 895 #define cmd_gma_hi(s, i) \
 896         (cmd_val(s, i) & GENMASK(15, 0))
 897
 898 static int cmd_handler_lri(struct parser_exec_state *s)
 899 {
 900         int i, ret = 0;
 901         int cmd_len = cmd_length(s);
 902         struct intel_gvt *gvt = s->vgpu->gvt;
 903
 904         for (i = 1; i < cmd_len; i += 2) {
 905                 if (IS_BROADWELL(gvt->dev_priv) &&
 906                                 (s->ring_id != RCS)) {
 907                         if (s->ring_id == BCS &&
 908                                         cmd_reg(s, i) ==
 909                                         i915_mmio_reg_offset(DERRMR))
 910                                 ret |= 0;
 911                         else
 912                                 ret |= (cmd_reg_inhibit(s, i)) ?
 913                                         -EBADRQC : 0;
 914                 }
 915                 if (ret)
 916                         break;
 917                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 918                 if (ret)
 919                         break;
 920         }
 921         return ret;
 922 }
 923
 924 static int cmd_handler_lrr(struct parser_exec_state *s)
 925 {
 926         int i, ret = 0;
 927         int cmd_len = cmd_length(s);
 928
 929         for (i = 1; i < cmd_len; i += 2) {
 930                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
 931                         ret |= ((cmd_reg_inhibit(s, i) ||
 932                                         (cmd_reg_inhibit(s, i + 1)))) ?
 933                                 -EBADRQC : 0;
 934                 if (ret)
 935                         break;
 936                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
 937                 if (ret)
 938                         break;
 939                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
 940                 if (ret)
 941                         break;
 942         }
 943         return ret;
 944 }
 945
 946 static inline int cmd_address_audit(struct parser_exec_state *s,
 947                 unsigned long guest_gma, int op_size, bool index_mode);
 948
 949 static int cmd_handler_lrm(struct parser_exec_state *s)
 950 {
 951         struct intel_gvt *gvt = s->vgpu->gvt;
 952         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 953         unsigned long gma;
 954         int i, ret = 0;
 955         int cmd_len = cmd_length(s);
 956
 957         for (i = 1; i < cmd_len;) {
 958                 if (IS_BROADWELL(gvt->dev_priv))
 959                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
 960                 if (ret)
 961                         break;
 962                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
 963                 if (ret)
 964                         break;
 965                 if (cmd_val(s, 0) & (1 << 22)) {
 966                         gma = cmd_gma(s, i + 1);
 967                         if (gmadr_bytes == 8)
 968                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 969                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 970                         if (ret)
 971                                 break;
 972                 }
 973                 i += gmadr_dw_number(s) + 1;
 974         }
 975         return ret;
 976 }
 977
 978 static int cmd_handler_srm(struct parser_exec_state *s)
 979 {
 980         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
 981         unsigned long gma;
 982         int i, ret = 0;
 983         int cmd_len = cmd_length(s);
 984
 985         for (i = 1; i < cmd_len;) {
 986                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
 987                 if (ret)
 988                         break;
 989                 if (cmd_val(s, 0) & (1 << 22)) {
 990                         gma = cmd_gma(s, i + 1);
 991                         if (gmadr_bytes == 8)
 992                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 993                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 994                         if (ret)
 995                                 break;
 996                 }
 997                 i += gmadr_dw_number(s) + 1;
 998         }
 999         return ret;
1000 }
1001
1002 struct cmd_interrupt_event {
1003         int pipe_control_notify;
1004         int mi_flush_dw;
1005         int mi_user_interrupt;
1006 };
1007
1008 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1009         [RCS] = {
1010                 .pipe_control_notify = RCS_PIPE_CONTROL,
1011                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1012                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1013         },
1014         [BCS] = {
1015                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1016                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1017                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1018         },
1019         [VCS] = {
1020                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1021                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1022                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1023         },
1024         [VCS2] = {
1025                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1026                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1027                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1028         },
1029         [VECS] = {
1030                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1031                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1032                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1033         },
1034 };
1035
1036 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1037 {
1038         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1039         unsigned long gma;
1040         bool index_mode = false;
1041         unsigned int post_sync;
1042         int ret = 0;
1043
1044         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1045
1046         /* LRI post sync */
1047         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1048                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1049         /* post sync */
1050         else if (post_sync) {
1051                 if (post_sync == 2)
1052                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1053                 else if (post_sync == 3)
1054                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1055                 else if (post_sync == 1) {
1056                         /* check ggtt*/
1057                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1058                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1059                                 if (gmadr_bytes == 8)
1060                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1061                                 /* Store Data Index */
1062                                 if (cmd_val(s, 1) & (1 << 21))
1063                                         index_mode = true;
1064                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1065                                                 index_mode);
1066                         }
1067                 }
1068         }
1069
1070         if (ret)
1071                 return ret;
1072
1073         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1074                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1075                                 s->workload->pending_events);
1076         return 0;
1077 }
1078
1079 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1080 {
1081         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1082                         s->workload->pending_events);
1083         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1084         return 0;
1085 }
1086
1087 static int cmd_advance_default(struct parser_exec_state *s)
1088 {
1089         return ip_gma_advance(s, cmd_length(s));
1090 }
1091
1092 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1093 {
1094         int ret;
1095
1096         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1097                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1098                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1099                 s->buf_addr_type = s->saved_buf_addr_type;
1100         } else {
1101                 s->buf_type = RING_BUFFER_INSTRUCTION;
1102                 s->buf_addr_type = GTT_BUFFER;
1103                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1104                         s->ret_ip_gma_ring -= s->ring_size;
1105                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1106         }
1107         return ret;
1108 }
1109
1110 struct mi_display_flip_command_info {
1111         int pipe;
1112         int plane;
1113         int event;
1114         i915_reg_t stride_reg;
1115         i915_reg_t ctrl_reg;
1116         i915_reg_t surf_reg;
1117         u64 stride_val;
1118         u64 tile_val;
1119         u64 surf_val;
1120         bool async_flip;
1121 };
1122
1123 struct plane_code_mapping {
1124         int pipe;
1125         int plane;
1126         int event;
1127 };
1128
1129 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1130                 struct mi_display_flip_command_info *info)
1131 {
1132         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1133         struct plane_code_mapping gen8_plane_code[] = {
1134                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1135                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1136                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1137                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1138                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1139                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1140         };
1141         u32 dword0, dword1, dword2;
1142         u32 v;
1143
1144         dword0 = cmd_val(s, 0);
1145         dword1 = cmd_val(s, 1);
1146         dword2 = cmd_val(s, 2);
1147
1148         v = (dword0 & GENMASK(21, 19)) >> 19;
1149         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1150                 return -EBADRQC;
1151
1152         info->pipe = gen8_plane_code[v].pipe;
1153         info->plane = gen8_plane_code[v].plane;
1154         info->event = gen8_plane_code[v].event;
1155         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1156         info->tile_val = (dword1 & 0x1);
1157         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1158         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1159
1160         if (info->plane == PLANE_A) {
1161                 info->ctrl_reg = DSPCNTR(info->pipe);
1162                 info->stride_reg = DSPSTRIDE(info->pipe);
1163                 info->surf_reg = DSPSURF(info->pipe);
1164         } else if (info->plane == PLANE_B) {
1165                 info->ctrl_reg = SPRCTL(info->pipe);
1166                 info->stride_reg = SPRSTRIDE(info->pipe);
1167                 info->surf_reg = SPRSURF(info->pipe);
1168         } else {
1169                 WARN_ON(1);
1170                 return -EBADRQC;
1171         }
1172         return 0;
1173 }
1174
1175 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1176                 struct mi_display_flip_command_info *info)
1177 {
1178         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1179         struct intel_vgpu *vgpu = s->vgpu;
1180         u32 dword0 = cmd_val(s, 0);
1181         u32 dword1 = cmd_val(s, 1);
1182         u32 dword2 = cmd_val(s, 2);
1183         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1184
1185         info->plane = PRIMARY_PLANE;
1186
1187         switch (plane) {
1188         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1189                 info->pipe = PIPE_A;
1190                 info->event = PRIMARY_A_FLIP_DONE;
1191                 break;
1192         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1193                 info->pipe = PIPE_B;
1194                 info->event = PRIMARY_B_FLIP_DONE;
1195                 break;
1196         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1197                 info->pipe = PIPE_C;
1198                 info->event = PRIMARY_C_FLIP_DONE;
1199                 break;
1200
1201         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1202                 info->pipe = PIPE_A;
1203                 info->event = SPRITE_A_FLIP_DONE;
1204                 info->plane = SPRITE_PLANE;
1205                 break;
1206         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1207                 info->pipe = PIPE_B;
1208                 info->event = SPRITE_B_FLIP_DONE;
1209                 info->plane = SPRITE_PLANE;
1210                 break;
1211         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1212                 info->pipe = PIPE_C;
1213                 info->event = SPRITE_C_FLIP_DONE;
1214                 info->plane = SPRITE_PLANE;
1215                 break;
1216
1217         default:
1218                 gvt_vgpu_err("unknown plane code %d\n", plane);
1219                 return -EBADRQC;
1220         }
1221
1222         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1223         info->tile_val = (dword1 & GENMASK(2, 0));
1224         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1225         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1226
1227         info->ctrl_reg = DSPCNTR(info->pipe);
1228         info->stride_reg = DSPSTRIDE(info->pipe);
1229         info->surf_reg = DSPSURF(info->pipe);
1230
1231         return 0;
1232 }
1233
1234 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1235                 struct mi_display_flip_command_info *info)
1236 {
1237         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1238         u32 stride, tile;
1239
1240         if (!info->async_flip)
1241                 return 0;
1242
1243         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1244                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1245                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1246                                 GENMASK(12, 10)) >> 10;
1247         } else {
1248                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1249                                 GENMASK(15, 6)) >> 6;
1250                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1251         }
1252
1253         if (stride != info->stride_val)
1254                 gvt_dbg_cmd("cannot change stride during async flip\n");
1255
1256         if (tile != info->tile_val)
1257                 gvt_dbg_cmd("cannot change tile during async flip\n");
1258
1259         return 0;
1260 }
1261
1262 static int gen8_update_plane_mmio_from_mi_display_flip(
1263                 struct parser_exec_state *s,
1264                 struct mi_display_flip_command_info *info)
1265 {
1266         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1267         struct intel_vgpu *vgpu = s->vgpu;
1268
1269         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1270                       info->surf_val << 12);
1271         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1272                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1273                               info->stride_val);
1274                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1275                               info->tile_val << 10);
1276         } else {
1277                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1278                               info->stride_val << 6);
1279                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1280                               info->tile_val << 10);
1281         }
1282
1283         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1284         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1285         return 0;
1286 }
1287
1288 static int decode_mi_display_flip(struct parser_exec_state *s,
1289                 struct mi_display_flip_command_info *info)
1290 {
1291         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1292
1293         if (IS_BROADWELL(dev_priv))
1294                 return gen8_decode_mi_display_flip(s, info);
1295         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1296                 return skl_decode_mi_display_flip(s, info);
1297
1298         return -ENODEV;
1299 }
1300
1301 static int check_mi_display_flip(struct parser_exec_state *s,
1302                 struct mi_display_flip_command_info *info)
1303 {
1304         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1305
1306         if (IS_BROADWELL(dev_priv)
1307                 || IS_SKYLAKE(dev_priv)
1308                 || IS_KABYLAKE(dev_priv))
1309                 return gen8_check_mi_display_flip(s, info);
1310         return -ENODEV;
1311 }
1312
1313 static int update_plane_mmio_from_mi_display_flip(
1314                 struct parser_exec_state *s,
1315                 struct mi_display_flip_command_info *info)
1316 {
1317         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1318
1319         if (IS_BROADWELL(dev_priv)
1320                 || IS_SKYLAKE(dev_priv)
1321                 || IS_KABYLAKE(dev_priv))
1322                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1323         return -ENODEV;
1324 }
1325
1326 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1327 {
1328         struct mi_display_flip_command_info info;
1329         struct intel_vgpu *vgpu = s->vgpu;
1330         int ret;
1331         int i;
1332         int len = cmd_length(s);
1333
1334         ret = decode_mi_display_flip(s, &info);
1335         if (ret) {
1336                 gvt_vgpu_err("fail to decode MI display flip command\n");
1337                 return ret;
1338         }
1339
1340         ret = check_mi_display_flip(s, &info);
1341         if (ret) {
1342                 gvt_vgpu_err("invalid MI display flip command\n");
1343                 return ret;
1344         }
1345
1346         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1347         if (ret) {
1348                 gvt_vgpu_err("fail to update plane mmio\n");
1349                 return ret;
1350         }
1351
1352         for (i = 0; i < len; i++)
1353                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1354         return 0;
1355 }
1356
1357 static bool is_wait_for_flip_pending(u32 cmd)
1358 {
1359         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1360                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1361                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1362                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1363                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1364                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1365 }
1366
1367 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1368 {
1369         u32 cmd = cmd_val(s, 0);
1370
1371         if (!is_wait_for_flip_pending(cmd))
1372                 return 0;
1373
1374         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1375         return 0;
1376 }
1377
1378 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1379 {
1380         unsigned long addr;
1381         unsigned long gma_high, gma_low;
1382         struct intel_vgpu *vgpu = s->vgpu;
1383         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1384
1385         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1386                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1387                 return INTEL_GVT_INVALID_ADDR;
1388         }
1389
1390         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1391         if (gmadr_bytes == 4) {
1392                 addr = gma_low;
1393         } else {
1394                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1395                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1396         }
1397         return addr;
1398 }
1399
1400 static inline int cmd_address_audit(struct parser_exec_state *s,
1401                 unsigned long guest_gma, int op_size, bool index_mode)
1402 {
1403         struct intel_vgpu *vgpu = s->vgpu;
1404         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1405         int i;
1406         int ret;
1407
1408         if (op_size > max_surface_size) {
1409                 gvt_vgpu_err("command address audit fail name %s\n",
1410                         s->info->name);
1411                 return -EFAULT;
1412         }
1413
1414         if (index_mode) {
1415                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1416                         ret = -EFAULT;
1417                         goto err;
1418                 }
1419         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1420                 ret = -EFAULT;
1421                 goto err;
1422         }
1423
1424         return 0;
1425
1426 err:
1427         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1428                         s->info->name, guest_gma, op_size);
1429
1430         pr_err("cmd dump: ");
1431         for (i = 0; i < cmd_length(s); i++) {
1432                 if (!(i % 4))
1433                         pr_err("\n%08x ", cmd_val(s, i));
1434                 else
1435                         pr_err("%08x ", cmd_val(s, i));
1436         }
1437         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1438                         vgpu->id,
1439                         vgpu_aperture_gmadr_base(vgpu),
1440                         vgpu_aperture_gmadr_end(vgpu),
1441                         vgpu_hidden_gmadr_base(vgpu),
1442                         vgpu_hidden_gmadr_end(vgpu));
1443         return ret;
1444 }
1445
1446 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1447 {
1448         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1449         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1450         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1451         unsigned long gma, gma_low, gma_high;
1452         int ret = 0;
1453
1454         /* check ppggt */
1455         if (!(cmd_val(s, 0) & (1 << 22)))
1456                 return 0;
1457
1458         gma = cmd_val(s, 2) & GENMASK(31, 2);
1459
1460         if (gmadr_bytes == 8) {
1461                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1462                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1463                 gma = (gma_high << 32) | gma_low;
1464                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1465         }
1466         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1467         return ret;
1468 }
1469
1470 static inline int unexpected_cmd(struct parser_exec_state *s)
1471 {
1472         struct intel_vgpu *vgpu = s->vgpu;
1473
1474         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1475
1476         return -EBADRQC;
1477 }
1478
1479 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1480 {
1481         return unexpected_cmd(s);
1482 }
1483
1484 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1485 {
1486         return unexpected_cmd(s);
1487 }
1488
1489 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1490 {
1491         return unexpected_cmd(s);
1492 }
1493
1494 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1495 {
1496         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1497         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1498                         sizeof(u32);
1499         unsigned long gma, gma_high;
1500         int ret = 0;
1501
1502         if (!(cmd_val(s, 0) & (1 << 22)))
1503                 return ret;
1504
1505         gma = cmd_val(s, 1) & GENMASK(31, 2);
1506         if (gmadr_bytes == 8) {
1507                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1508                 gma = (gma_high << 32) | gma;
1509         }
1510         ret = cmd_address_audit(s, gma, op_size, false);
1511         return ret;
1512 }
1513
1514 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1515 {
1516         return unexpected_cmd(s);
1517 }
1518
1519 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1520 {
1521         return unexpected_cmd(s);
1522 }
1523
1524 static int cmd_handler_mi_conditional_batch_buffer_end(
1525                 struct parser_exec_state *s)
1526 {
1527         return unexpected_cmd(s);
1528 }
1529
1530 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1531 {
1532         return unexpected_cmd(s);
1533 }
1534
1535 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1536 {
1537         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1538         unsigned long gma;
1539         bool index_mode = false;
1540         int ret = 0;
1541
1542         /* Check post-sync and ppgtt bit */
1543         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1544                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1545                 if (gmadr_bytes == 8)
1546                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1547                 /* Store Data Index */
1548                 if (cmd_val(s, 0) & (1 << 21))
1549                         index_mode = true;
1550                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1551         }
1552         /* Check notify bit */
1553         if ((cmd_val(s, 0) & (1 << 8)))
1554                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1555                                 s->workload->pending_events);
1556         return ret;
1557 }
1558
1559 static void addr_type_update_snb(struct parser_exec_state *s)
1560 {
1561         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1562                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1563                 s->buf_addr_type = PPGTT_BUFFER;
1564         }
1565 }
1566
1567
1568 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1569                 unsigned long gma, unsigned long end_gma, void *va)
1570 {
1571         unsigned long copy_len, offset;
1572         unsigned long len = 0;
1573         unsigned long gpa;
1574
1575         while (gma != end_gma) {
1576                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1577                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1578                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1579                         return -EFAULT;
1580                 }
1581
1582                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1583
1584                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1585                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1586
1587                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1588
1589                 len += copy_len;
1590                 gma += copy_len;
1591         }
1592         return len;
1593 }
1594
1595
1596 /*
1597  * Check whether a batch buffer needs to be scanned. Currently
1598  * the only criteria is based on privilege.
1599  */
1600 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1601 {
1602         struct intel_gvt *gvt = s->vgpu->gvt;
1603
1604         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1605                 || IS_KABYLAKE(gvt->dev_priv)) {
1606                 /* BDW decides privilege based on address space */
1607                 if (cmd_val(s, 0) & (1 << 8))
1608                         return 0;
1609         }
1610         return 1;
1611 }
1612
1613 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1614 {
1615         unsigned long gma = 0;
1616         struct cmd_info *info;
1617         uint32_t cmd_len = 0;
1618         bool bb_end = false;
1619         struct intel_vgpu *vgpu = s->vgpu;
1620         u32 cmd;
1621
1622         *bb_size = 0;
1623
1624         /* get the start gm address of the batch buffer */
1625         gma = get_gma_bb_from_cmd(s, 1);
1626         if (gma == INTEL_GVT_INVALID_ADDR)
1627                 return -EFAULT;
1628
1629         cmd = cmd_val(s, 0);
1630         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1631         if (info == NULL) {
1632                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1633                                 cmd, get_opcode(cmd, s->ring_id));
1634                 return -EBADRQC;
1635         }
1636         do {
1637                 if (copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1638                                 gma, gma + 4, &cmd) < 0)
1639                         return -EFAULT;
1640                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1641                 if (info == NULL) {
1642                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1643                                 cmd, get_opcode(cmd, s->ring_id));
1644                         return -EBADRQC;
1645                 }
1646
1647                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1648                         bb_end = true;
1649                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1650                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1651                                 /* chained batch buffer */
1652                                 bb_end = true;
1653                 }
1654                 cmd_len = get_cmd_length(info, cmd) << 2;
1655                 *bb_size += cmd_len;
1656                 gma += cmd_len;
1657         } while (!bb_end);
1658
1659         return 0;
1660 }
1661
1662 static int perform_bb_shadow(struct parser_exec_state *s)
1663 {
1664         struct intel_vgpu *vgpu = s->vgpu;
1665         struct intel_vgpu_shadow_bb *bb;
1666         unsigned long gma = 0;
1667         unsigned long bb_size;
1668         int ret = 0;
1669
1670         /* get the start gm address of the batch buffer */
1671         gma = get_gma_bb_from_cmd(s, 1);
1672         if (gma == INTEL_GVT_INVALID_ADDR)
1673                 return -EFAULT;
1674
1675         ret = find_bb_size(s, &bb_size);
1676         if (ret)
1677                 return ret;
1678
1679         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1680         if (!bb)
1681                 return -ENOMEM;
1682
1683         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1684                                          roundup(bb_size, PAGE_SIZE));
1685         if (IS_ERR(bb->obj)) {
1686                 ret = PTR_ERR(bb->obj);
1687                 goto err_free_bb;
1688         }
1689
1690         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1691         if (ret)
1692                 goto err_free_obj;
1693
1694         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1695         if (IS_ERR(bb->va)) {
1696                 ret = PTR_ERR(bb->va);
1697                 goto err_finish_shmem_access;
1698         }
1699
1700         if (bb->clflush & CLFLUSH_BEFORE) {
1701                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1702                 bb->clflush &= ~CLFLUSH_BEFORE;
1703         }
1704
1705         ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1706                               gma, gma + bb_size,
1707                               bb->va);
1708         if (ret < 0) {
1709                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1710                 ret = -EFAULT;
1711                 goto err_unmap;
1712         }
1713
1714         INIT_LIST_HEAD(&bb->list);
1715         list_add(&bb->list, &s->workload->shadow_bb);
1716
1717         bb->accessing = true;
1718         bb->bb_start_cmd_va = s->ip_va;
1719
1720         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1721                 bb->bb_offset = s->ip_va - s->rb_va;
1722         else
1723                 bb->bb_offset = 0;
1724
1725         /*
1726          * ip_va saves the virtual address of the shadow batch buffer, while
1727          * ip_gma saves the graphics address of the original batch buffer.
1728          * As the shadow batch buffer is just a copy from the originial one,
1729          * it should be right to use shadow batch buffer'va and original batch
1730          * buffer's gma in pair. After all, we don't want to pin the shadow
1731          * buffer here (too early).
1732          */
1733         s->ip_va = bb->va;
1734         s->ip_gma = gma;
1735         return 0;
1736 err_unmap:
1737         i915_gem_object_unpin_map(bb->obj);
1738 err_finish_shmem_access:
1739         i915_gem_obj_finish_shmem_access(bb->obj);
1740 err_free_obj:
1741         i915_gem_object_put(bb->obj);
1742 err_free_bb:
1743         kfree(bb);
1744         return ret;
1745 }
1746
1747 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1748 {
1749         bool second_level;
1750         int ret = 0;
1751         struct intel_vgpu *vgpu = s->vgpu;
1752
1753         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1754                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1755                 return -EFAULT;
1756         }
1757
1758         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1759         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1760                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1761                 return -EFAULT;
1762         }
1763
1764         s->saved_buf_addr_type = s->buf_addr_type;
1765         addr_type_update_snb(s);
1766         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1767                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1768                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1769         } else if (second_level) {
1770                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1771                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1772                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1773         }
1774
1775         if (batch_buffer_needs_scan(s)) {
1776                 ret = perform_bb_shadow(s);
1777                 if (ret < 0)
1778                         gvt_vgpu_err("invalid shadow batch buffer\n");
1779         } else {
1780                 /* emulate a batch buffer end to do return right */
1781                 ret = cmd_handler_mi_batch_buffer_end(s);
1782                 if (ret < 0)
1783                         return ret;
1784         }
1785         return ret;
1786 }
1787
1788 static struct cmd_info cmd_info[] = {
1789         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1790
1791         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1792                 0, 1, NULL},
1793
1794         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1795                 0, 1, cmd_handler_mi_user_interrupt},
1796
1797         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1798                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1799
1800         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1801
1802         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1803                 NULL},
1804
1805         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1806                 NULL},
1807
1808         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1809                 NULL},
1810
1811         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1812                 NULL},
1813
1814         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1815                 D_ALL, 0, 1, NULL},
1816
1817         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1818                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1819                 cmd_handler_mi_batch_buffer_end},
1820
1821         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1822                 0, 1, NULL},
1823
1824         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1825                 NULL},
1826
1827         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1828                 D_ALL, 0, 1, NULL},
1829
1830         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1831                 NULL},
1832
1833         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1834                 NULL},
1835
1836         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1837                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1838
1839         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1840                 0, 8, NULL},
1841
1842         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1843
1844         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1845
1846         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1847                 D_BDW_PLUS, 0, 8, NULL},
1848
1849         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1850                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1851
1852         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1853                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1854
1855         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1856                 0, 8, cmd_handler_mi_store_data_index},
1857
1858         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1859                 D_ALL, 0, 8, cmd_handler_lri},
1860
1861         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1862                 cmd_handler_mi_update_gtt},
1863
1864         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1865                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1866
1867         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1868                 cmd_handler_mi_flush_dw},
1869
1870         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1871                 10, cmd_handler_mi_clflush},
1872
1873         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1874                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1875
1876         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1877                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1878
1879         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1880                 D_ALL, 0, 8, cmd_handler_lrr},
1881
1882         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1883                 D_ALL, 0, 8, NULL},
1884
1885         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1886                 ADDR_FIX_1(2), 8, NULL},
1887
1888         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1889                 ADDR_FIX_1(2), 8, NULL},
1890
1891         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1892                 8, cmd_handler_mi_op_2e},
1893
1894         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1895                 8, cmd_handler_mi_op_2f},
1896
1897         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1898                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1899                 cmd_handler_mi_batch_buffer_start},
1900
1901         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1902                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1903                 cmd_handler_mi_conditional_batch_buffer_end},
1904
1905         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1906                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1907
1908         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1909                 ADDR_FIX_2(4, 7), 8, NULL},
1910
1911         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1912                 0, 8, NULL},
1913
1914         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1915                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1916
1917         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1918
1919         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1920                 0, 8, NULL},
1921
1922         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1923                 ADDR_FIX_1(3), 8, NULL},
1924
1925         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1926                 D_ALL, 0, 8, NULL},
1927
1928         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1929                 ADDR_FIX_1(4), 8, NULL},
1930
1931         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1932                 ADDR_FIX_2(4, 5), 8, NULL},
1933
1934         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1935                 ADDR_FIX_1(4), 8, NULL},
1936
1937         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1938                 ADDR_FIX_2(4, 7), 8, NULL},
1939
1940         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1941                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1942
1943         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1944
1945         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1946                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1947
1948         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1949                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1950
1951         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1952                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1953                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1954
1955         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1956                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1957
1958         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1959                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1960
1961         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1962                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1963
1964         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1965                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1966
1967         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
1968                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1969
1970         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
1971                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
1972                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1973
1974         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
1975                 ADDR_FIX_2(4, 5), 8, NULL},
1976
1977         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
1978                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1979
1980         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
1981                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1982                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1983
1984         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
1985                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
1986                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1987
1988         {"3DSTATE_BLEND_STATE_POINTERS",
1989                 OP_3DSTATE_BLEND_STATE_POINTERS,
1990                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1991
1992         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
1993                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1994                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1995
1996         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
1997                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
1998                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1999
2000         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2001                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2002                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2003
2004         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2005                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2006                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2007
2008         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2009                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2010                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2011
2012         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2013                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2014                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2015
2016         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2017                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2018                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2019
2020         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2021                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2022                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2023
2024         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2025                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2026                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2027
2028         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2029                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2030                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2031
2032         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2033                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2034                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2035
2036         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2037                 0, 8, NULL},
2038
2039         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2040                 0, 8, NULL},
2041
2042         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2043                 0, 8, NULL},
2044
2045         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2046                 0, 8, NULL},
2047
2048         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2049                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2050
2051         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2052                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2053
2054         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2055                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2056
2057         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2058                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2059
2060         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2061                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2062
2063         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2064                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2065
2066         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2067                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2068
2069         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2070                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2071
2072         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2073                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2074
2075         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2076                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2077
2078         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2079                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2080
2081         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2082                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2083
2084         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2085                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2086
2087         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2088                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2089
2090         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2091                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2092
2093         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2094                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2095
2096         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2097                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2098
2099         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2100                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2101
2102         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2103                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2104
2105         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2106                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2107
2108         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2109                 D_BDW_PLUS, 0, 8, NULL},
2110
2111         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2112                 NULL},
2113
2114         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2115                 D_BDW_PLUS, 0, 8, NULL},
2116
2117         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2118                 D_BDW_PLUS, 0, 8, NULL},
2119
2120         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2121                 8, NULL},
2122
2123         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2124                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2125
2126         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2127                 8, NULL},
2128
2129         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2130                 NULL},
2131
2132         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2133                 NULL},
2134
2135         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2136                 NULL},
2137
2138         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2139                 D_BDW_PLUS, 0, 8, NULL},
2140
2141         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2142                 R_RCS, D_ALL, 0, 8, NULL},
2143
2144         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2145                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2146
2147         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2148                 R_RCS, D_ALL, 0, 1, NULL},
2149
2150         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2151
2152         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2153                 R_RCS, D_ALL, 0, 8, NULL},
2154
2155         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2156                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2157
2158         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2159
2160         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2161
2162         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2163
2164         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2165                 D_BDW_PLUS, 0, 8, NULL},
2166
2167         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2168                 D_BDW_PLUS, 0, 8, NULL},
2169
2170         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2171                 D_ALL, 0, 8, NULL},
2172
2173         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2174                 D_BDW_PLUS, 0, 8, NULL},
2175
2176         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2177                 D_BDW_PLUS, 0, 8, NULL},
2178
2179         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2180
2181         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2182
2183         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2184
2185         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2186                 D_ALL, 0, 8, NULL},
2187
2188         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2189
2190         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2191
2192         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2193                 R_RCS, D_ALL, 0, 8, NULL},
2194
2195         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2196                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2197
2198         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2199                 0, 8, NULL},
2200
2201         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2202                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2203
2204         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2205                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2206
2207         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2208                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2209
2210         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2211                 D_ALL, 0, 8, NULL},
2212
2213         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2214                 D_ALL, 0, 8, NULL},
2215
2216         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2217                 D_ALL, 0, 8, NULL},
2218
2219         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2220                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2221
2222         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2223                 D_BDW_PLUS, 0, 8, NULL},
2224
2225         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2226                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2227
2228         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2229                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2230
2231         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2232                 R_RCS, D_ALL, 0, 8, NULL},
2233
2234         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2235                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2236
2237         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2238                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2241                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2242
2243         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2244                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2247                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2248
2249         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2250                 R_RCS, D_ALL, 0, 8, NULL},
2251
2252         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2253                 D_ALL, 0, 9, NULL},
2254
2255         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2256                 ADDR_FIX_2(2, 4), 8, NULL},
2257
2258         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2259                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2260                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2261
2262         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2263                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2264
2265         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2266                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2267                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2268
2269         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2270                 D_BDW_PLUS, 0, 8, NULL},
2271
2272         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2273                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2274
2275         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2276
2277         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2278                 1, NULL},
2279
2280         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2281                 ADDR_FIX_1(1), 8, NULL},
2282
2283         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2284
2285         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2286                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2287
2288         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2289                 ADDR_FIX_1(1), 8, NULL},
2290
2291         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2292
2293         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2294
2295         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2296                 0, 8, NULL},
2297
2298         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2299                 D_SKL_PLUS, 0, 8, NULL},
2300
2301         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2302                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2303
2304         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2305                 0, 16, NULL},
2306
2307         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2308                 0, 16, NULL},
2309
2310         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2311
2312         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2313                 0, 16, NULL},
2314
2315         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2316                 0, 16, NULL},
2317
2318         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2319                 0, 16, NULL},
2320
2321         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2322                 0, 8, NULL},
2323
2324         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2325                 NULL},
2326
2327         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2328                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2329
2330         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2331                 R_VCS, D_ALL, 0, 12, NULL},
2332
2333         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2334                 R_VCS, D_ALL, 0, 12, NULL},
2335
2336         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2337                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2338
2339         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2340                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2341
2342         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2343                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2344
2345         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2346
2347         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2348                 R_VCS, D_ALL, 0, 12, NULL},
2349
2350         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2351                 R_VCS, D_ALL, 0, 12, NULL},
2352
2353         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2354                 R_VCS, D_ALL, 0, 12, NULL},
2355
2356         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2357                 R_VCS, D_ALL, 0, 12, NULL},
2358
2359         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2360                 R_VCS, D_ALL, 0, 12, NULL},
2361
2362         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2363                 R_VCS, D_ALL, 0, 12, NULL},
2364
2365         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2366                 R_VCS, D_ALL, 0, 6, NULL},
2367
2368         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2369                 R_VCS, D_ALL, 0, 12, NULL},
2370
2371         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2372                 R_VCS, D_ALL, 0, 12, NULL},
2373
2374         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2375                 R_VCS, D_ALL, 0, 12, NULL},
2376
2377         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2378                 R_VCS, D_ALL, 0, 12, NULL},
2379
2380         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2381                 R_VCS, D_ALL, 0, 12, NULL},
2382
2383         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2384                 R_VCS, D_ALL, 0, 12, NULL},
2385
2386         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2387                 R_VCS, D_ALL, 0, 12, NULL},
2388         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2389                 R_VCS, D_ALL, 0, 12, NULL},
2390
2391         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2392                 R_VCS, D_ALL, 0, 12, NULL},
2393
2394         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2395                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2396
2397         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2398                 R_VCS, D_ALL, 0, 12, NULL},
2399
2400         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2401                 R_VCS, D_ALL, 0, 12, NULL},
2402
2403         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2404                 R_VCS, D_ALL, 0, 12, NULL},
2405
2406         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2407                 R_VCS, D_ALL, 0, 12, NULL},
2408
2409         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2410                 R_VCS, D_ALL, 0, 12, NULL},
2411
2412         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2413                 R_VCS, D_ALL, 0, 12, NULL},
2414
2415         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2416                 R_VCS, D_ALL, 0, 12, NULL},
2417
2418         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2419                 R_VCS, D_ALL, 0, 12, NULL},
2420
2421         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2422                 R_VCS, D_ALL, 0, 12, NULL},
2423
2424         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2425                 R_VCS, D_ALL, 0, 12, NULL},
2426
2427         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2428                 R_VCS, D_ALL, 0, 12, NULL},
2429
2430         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2431                 0, 16, NULL},
2432
2433         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2434
2435         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2436
2437         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2438                 R_VCS, D_ALL, 0, 12, NULL},
2439
2440         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2441                 R_VCS, D_ALL, 0, 12, NULL},
2442
2443         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2444                 R_VCS, D_ALL, 0, 12, NULL},
2445
2446         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2447
2448         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2449                 0, 12, NULL},
2450
2451         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2452                 0, 20, NULL},
2453 };
2454
2455 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2456 {
2457         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2458 }
2459
2460 /* call the cmd handler, and advance ip */
2461 static int cmd_parser_exec(struct parser_exec_state *s)
2462 {
2463         struct intel_vgpu *vgpu = s->vgpu;
2464         struct cmd_info *info;
2465         u32 cmd;
2466         int ret = 0;
2467
2468         cmd = cmd_val(s, 0);
2469
2470         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2471         if (info == NULL) {
2472                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
2473                                 cmd, get_opcode(cmd, s->ring_id));
2474                 return -EBADRQC;
2475         }
2476
2477         s->info = info;
2478
2479         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2480                           cmd_length(s), s->buf_type);
2481
2482         if (info->handler) {
2483                 ret = info->handler(s);
2484                 if (ret < 0) {
2485                         gvt_vgpu_err("%s handler error\n", info->name);
2486                         return ret;
2487                 }
2488         }
2489
2490         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2491                 ret = cmd_advance_default(s);
2492                 if (ret) {
2493                         gvt_vgpu_err("%s IP advance error\n", info->name);
2494                         return ret;
2495                 }
2496         }
2497         return 0;
2498 }
2499
2500 static inline bool gma_out_of_range(unsigned long gma,
2501                 unsigned long gma_head, unsigned int gma_tail)
2502 {
2503         if (gma_tail >= gma_head)
2504                 return (gma < gma_head) || (gma > gma_tail);
2505         else
2506                 return (gma > gma_tail) && (gma < gma_head);
2507 }
2508
2509 /* Keep the consistent return type, e.g EBADRQC for unknown
2510  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2511  * works as the input of VM healthy status.
2512  */
2513 static int command_scan(struct parser_exec_state *s,
2514                 unsigned long rb_head, unsigned long rb_tail,
2515                 unsigned long rb_start, unsigned long rb_len)
2516 {
2517
2518         unsigned long gma_head, gma_tail, gma_bottom;
2519         int ret = 0;
2520         struct intel_vgpu *vgpu = s->vgpu;
2521
2522         gma_head = rb_start + rb_head;
2523         gma_tail = rb_start + rb_tail;
2524         gma_bottom = rb_start +  rb_len;
2525
2526         while (s->ip_gma != gma_tail) {
2527                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2528                         if (!(s->ip_gma >= rb_start) ||
2529                                 !(s->ip_gma < gma_bottom)) {
2530                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2531                                         "(base:0x%lx, bottom: 0x%lx)\n",
2532                                         s->ip_gma, rb_start,
2533                                         gma_bottom);
2534                                 parser_exec_state_dump(s);
2535                                 return -EFAULT;
2536                         }
2537                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2538                                 gvt_vgpu_err("ip_gma %lx out of range."
2539                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2540                                         s->ip_gma, rb_start,
2541                                         rb_head, rb_tail);
2542                                 parser_exec_state_dump(s);
2543                                 break;
2544                         }
2545                 }
2546                 ret = cmd_parser_exec(s);
2547                 if (ret) {
2548                         gvt_vgpu_err("cmd parser error\n");
2549                         parser_exec_state_dump(s);
2550                         break;
2551                 }
2552         }
2553
2554         return ret;
2555 }
2556
2557 static int scan_workload(struct intel_vgpu_workload *workload)
2558 {
2559         unsigned long gma_head, gma_tail, gma_bottom;
2560         struct parser_exec_state s;
2561         int ret = 0;
2562
2563         /* ring base is page aligned */
2564         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2565                 return -EINVAL;
2566
2567         gma_head = workload->rb_start + workload->rb_head;
2568         gma_tail = workload->rb_start + workload->rb_tail;
2569         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2570
2571         s.buf_type = RING_BUFFER_INSTRUCTION;
2572         s.buf_addr_type = GTT_BUFFER;
2573         s.vgpu = workload->vgpu;
2574         s.ring_id = workload->ring_id;
2575         s.ring_start = workload->rb_start;
2576         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2577         s.ring_head = gma_head;
2578         s.ring_tail = gma_tail;
2579         s.rb_va = workload->shadow_ring_buffer_va;
2580         s.workload = workload;
2581         s.is_ctx_wa = false;
2582
2583         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2584                 gma_head == gma_tail)
2585                 return 0;
2586
2587         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2588                 ret = -EINVAL;
2589                 goto out;
2590         }
2591
2592         ret = ip_gma_set(&s, gma_head);
2593         if (ret)
2594                 goto out;
2595
2596         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2597                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2598
2599 out:
2600         return ret;
2601 }
2602
2603 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2604 {
2605
2606         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2607         struct parser_exec_state s;
2608         int ret = 0;
2609         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2610                                 struct intel_vgpu_workload,
2611                                 wa_ctx);
2612
2613         /* ring base is page aligned */
2614         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2615                                         I915_GTT_PAGE_SIZE)))
2616                 return -EINVAL;
2617
2618         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2619         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2620                         PAGE_SIZE);
2621         gma_head = wa_ctx->indirect_ctx.guest_gma;
2622         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2623         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2624
2625         s.buf_type = RING_BUFFER_INSTRUCTION;
2626         s.buf_addr_type = GTT_BUFFER;
2627         s.vgpu = workload->vgpu;
2628         s.ring_id = workload->ring_id;
2629         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2630         s.ring_size = ring_size;
2631         s.ring_head = gma_head;
2632         s.ring_tail = gma_tail;
2633         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2634         s.workload = workload;
2635         s.is_ctx_wa = true;
2636
2637         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2638                 ret = -EINVAL;
2639                 goto out;
2640         }
2641
2642         ret = ip_gma_set(&s, gma_head);
2643         if (ret)
2644                 goto out;
2645
2646         ret = command_scan(&s, 0, ring_tail,
2647                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2648 out:
2649         return ret;
2650 }
2651
2652 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2653 {
2654         struct intel_vgpu *vgpu = workload->vgpu;
2655         struct intel_vgpu_submission *s = &vgpu->submission;
2656         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2657         void *shadow_ring_buffer_va;
2658         int ring_id = workload->ring_id;
2659         int ret;
2660
2661         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2662
2663         /* calculate workload ring buffer size */
2664         workload->rb_len = (workload->rb_tail + guest_rb_size -
2665                         workload->rb_head) % guest_rb_size;
2666
2667         gma_head = workload->rb_start + workload->rb_head;
2668         gma_tail = workload->rb_start + workload->rb_tail;
2669         gma_top = workload->rb_start + guest_rb_size;
2670
2671         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2672                 void *p;
2673
2674                 /* realloc the new ring buffer if needed */
2675                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2676                                 GFP_KERNEL);
2677                 if (!p) {
2678                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2679                         return -ENOMEM;
2680                 }
2681                 s->ring_scan_buffer[ring_id] = p;
2682                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2683         }
2684
2685         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2686
2687         /* get shadow ring buffer va */
2688         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2689
2690         /* head > tail --> copy head <-> top */
2691         if (gma_head > gma_tail) {
2692                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2693                                       gma_head, gma_top, shadow_ring_buffer_va);
2694                 if (ret < 0) {
2695                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2696                         return ret;
2697                 }
2698                 shadow_ring_buffer_va += ret;
2699                 gma_head = workload->rb_start;
2700         }
2701
2702         /* copy head or start <-> tail */
2703         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2704                                 shadow_ring_buffer_va);
2705         if (ret < 0) {
2706                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2707                 return ret;
2708         }
2709         return 0;
2710 }
2711
2712 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2713 {
2714         int ret;
2715         struct intel_vgpu *vgpu = workload->vgpu;
2716
2717         ret = shadow_workload_ring_buffer(workload);
2718         if (ret) {
2719                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2720                 return ret;
2721         }
2722
2723         ret = scan_workload(workload);
2724         if (ret) {
2725                 gvt_vgpu_err("scan workload error\n");
2726                 return ret;
2727         }
2728         return 0;
2729 }
2730
2731 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2732 {
2733         int ctx_size = wa_ctx->indirect_ctx.size;
2734         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2735         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2736                                         struct intel_vgpu_workload,
2737                                         wa_ctx);
2738         struct intel_vgpu *vgpu = workload->vgpu;
2739         struct drm_i915_gem_object *obj;
2740         int ret = 0;
2741         void *map;
2742
2743         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2744                                      roundup(ctx_size + CACHELINE_BYTES,
2745                                              PAGE_SIZE));
2746         if (IS_ERR(obj))
2747                 return PTR_ERR(obj);
2748
2749         /* get the va of the shadow batch buffer */
2750         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2751         if (IS_ERR(map)) {
2752                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2753                 ret = PTR_ERR(map);
2754                 goto put_obj;
2755         }
2756
2757         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2758         if (ret) {
2759                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2760                 goto unmap_src;
2761         }
2762
2763         ret = copy_gma_to_hva(workload->vgpu,
2764                                 workload->vgpu->gtt.ggtt_mm,
2765                                 guest_gma, guest_gma + ctx_size,
2766                                 map);
2767         if (ret < 0) {
2768                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2769                 goto unmap_src;
2770         }
2771
2772         wa_ctx->indirect_ctx.obj = obj;
2773         wa_ctx->indirect_ctx.shadow_va = map;
2774         return 0;
2775
2776 unmap_src:
2777         i915_gem_object_unpin_map(obj);
2778 put_obj:
2779         i915_gem_object_put(obj);
2780         return ret;
2781 }
2782
2783 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2784 {
2785         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2786         unsigned char *bb_start_sva;
2787
2788         if (!wa_ctx->per_ctx.valid)
2789                 return 0;
2790
2791         per_ctx_start[0] = 0x18800001;
2792         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2793
2794         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2795                                 wa_ctx->indirect_ctx.size;
2796
2797         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2798
2799         return 0;
2800 }
2801
2802 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2803 {
2804         int ret;
2805         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2806                                         struct intel_vgpu_workload,
2807                                         wa_ctx);
2808         struct intel_vgpu *vgpu = workload->vgpu;
2809
2810         if (wa_ctx->indirect_ctx.size == 0)
2811                 return 0;
2812
2813         ret = shadow_indirect_ctx(wa_ctx);
2814         if (ret) {
2815                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2816                 return ret;
2817         }
2818
2819         combine_wa_ctx(wa_ctx);
2820
2821         ret = scan_wa_ctx(wa_ctx);
2822         if (ret) {
2823                 gvt_vgpu_err("scan wa ctx error\n");
2824                 return ret;
2825         }
2826
2827         return 0;
2828 }
2829
2830 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2831                 unsigned int opcode, unsigned long rings)
2832 {
2833         struct cmd_info *info = NULL;
2834         unsigned int ring;
2835
2836         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2837                 info = find_cmd_entry(gvt, opcode, ring);
2838                 if (info)
2839                         break;
2840         }
2841         return info;
2842 }
2843
2844 static int init_cmd_table(struct intel_gvt *gvt)
2845 {
2846         int i;
2847         struct cmd_entry *e;
2848         struct cmd_info *info;
2849         unsigned int gen_type;
2850
2851         gen_type = intel_gvt_get_device_type(gvt);
2852
2853         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2854                 if (!(cmd_info[i].devices & gen_type))
2855                         continue;
2856
2857                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2858                 if (!e)
2859                         return -ENOMEM;
2860
2861                 e->info = &cmd_info[i];
2862                 info = find_cmd_entry_any_ring(gvt,
2863                                 e->info->opcode, e->info->rings);
2864                 if (info) {
2865                         gvt_err("%s %s duplicated\n", e->info->name,
2866                                         info->name);
2867                         return -EEXIST;
2868                 }
2869
2870                 INIT_HLIST_NODE(&e->hlist);
2871                 add_cmd_entry(gvt, e);
2872                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2873                                 e->info->name, e->info->opcode, e->info->flag,
2874                                 e->info->devices, e->info->rings);
2875         }
2876         return 0;
2877 }
2878
2879 static void clean_cmd_table(struct intel_gvt *gvt)
2880 {
2881         struct hlist_node *tmp;
2882         struct cmd_entry *e;
2883         int i;
2884
2885         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2886                 kfree(e);
2887
2888         hash_init(gvt->cmd_table);
2889 }
2890
2891 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2892 {
2893         clean_cmd_table(gvt);
2894 }
2895
2896 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2897 {
2898         int ret;
2899
2900         ret = init_cmd_table(gvt);
2901         if (ret) {
2902                 intel_gvt_clean_cmd_parser(gvt);
2903                 return ret;
2904         }
2905         return 0;
2906 }