drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40 #include "i915_pvinfo.h"
  41 #include "trace.h"
  42
  43 #define INVALID_OP    (~0U)
  44
  45 #define OP_LEN_MI           9
  46 #define OP_LEN_2D           10
  47 #define OP_LEN_3D_MEDIA     16
  48 #define OP_LEN_MFX_VC       16
  49 #define OP_LEN_VEBOX        16
  50
  51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  52
  53 struct sub_op_bits {
  54         int hi;
  55         int low;
  56 };
  57 struct decode_info {
  58         char *name;
  59         int op_len;
  60         int nr_sub_op;
  61         struct sub_op_bits *sub_op;
  62 };
  63
  64 #define   MAX_CMD_BUDGET                        0x7fffffff
  65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  68
  69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  72
  73 /* Render Command Map */
  74
  75 /* MI_* command Opcode (28:23) */
  76 #define OP_MI_NOOP                          0x0
  77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  78 #define OP_MI_USER_INTERRUPT                0x2
  79 #define OP_MI_WAIT_FOR_EVENT                0x3
  80 #define OP_MI_FLUSH                         0x4
  81 #define OP_MI_ARB_CHECK                     0x5
  82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  83 #define OP_MI_REPORT_HEAD                   0x7
  84 #define OP_MI_ARB_ON_OFF                    0x8
  85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  86 #define OP_MI_BATCH_BUFFER_END              0xA
  87 #define OP_MI_SUSPEND_FLUSH                 0xB
  88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  93 #define OP_MI_DISPLAY_FLIP                  0x14
  94 #define OP_MI_SEMAPHORE_MBOX                0x16
  95 #define OP_MI_SET_CONTEXT                   0x18
  96 #define OP_MI_MATH                          0x1A
  97 #define OP_MI_URB_CLEAR                     0x19
  98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
  99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 100
 101 #define OP_MI_STORE_DATA_IMM                0x20
 102 #define OP_MI_STORE_DATA_INDEX              0x21
 103 #define OP_MI_LOAD_REGISTER_IMM             0x22
 104 #define OP_MI_UPDATE_GTT                    0x23
 105 #define OP_MI_STORE_REGISTER_MEM            0x24
 106 #define OP_MI_FLUSH_DW                      0x26
 107 #define OP_MI_CLFLUSH                       0x27
 108 #define OP_MI_REPORT_PERF_COUNT             0x28
 109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 114 #define OP_MI_2E                            0x2E  /* BDW+ */
 115 #define OP_MI_2F                            0x2F  /* BDW+ */
 116 #define OP_MI_BATCH_BUFFER_START            0x31
 117
 118 /* Bit definition for dword 0 */
 119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 120
 121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 122
 123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 127
 128 /* 2D command: Opcode (28:22) */
 129 #define OP_2D(x)    ((2<<7) | x)
 130
 131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 155
 156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 159
 160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 161
 162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 165
 166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 167
 168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 169
 170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 175
 176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 180
 181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 247
 248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 259
 260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 288
 289 /* VCCP Command Parser */
 290
 291 /*
 292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 293  * git://anongit.freedesktop.org/vaapi/intel-driver
 294  * src/i965_defines.h
 295  *
 296  */
 297
 298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 299         (3 << 13 | \
 300          (pipeline) << 11 | \
 301          (op) << 8 | \
 302          (sub_opa) << 5 | \
 303          (sub_opb))
 304
 305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 316
 317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 318
 319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 331
 332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 337
 338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 343
 344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 347
 348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 351
 352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 353         (3 << 13 | \
 354          (pipeline) << 11 | \
 355          (op) << 8 | \
 356          (sub_opa) << 5 | \
 357          (sub_opb))
 358
 359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 362
 363 struct parser_exec_state;
 364
 365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 366
 367 #define GVT_CMD_HASH_BITS   7
 368
 369 /* which DWords need address fix */
 370 #define ADDR_FIX_1(x1)                  (1 << (x1))
 371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 375
 376 struct cmd_info {
 377         char *name;
 378         u32 opcode;
 379
 380 #define F_LEN_MASK      (1U<<0)
 381 #define F_LEN_CONST  1U
 382 #define F_LEN_VAR    0U
 383
 384 /*
 385  * command has its own ip advance logic
 386  * e.g. MI_BATCH_START, MI_BATCH_END
 387  */
 388 #define F_IP_ADVANCE_CUSTOM (1<<1)
 389
 390 #define F_POST_HANDLE   (1<<2)
 391         u32 flag;
 392
 393 #define R_RCS   (1 << RCS)
 394 #define R_VCS1  (1 << VCS)
 395 #define R_VCS2  (1 << VCS2)
 396 #define R_VCS   (R_VCS1 | R_VCS2)
 397 #define R_BCS   (1 << BCS)
 398 #define R_VECS  (1 << VECS)
 399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 401         uint16_t rings;
 402
 403         /* devices that support this cmd: SNB/IVB/HSW/... */
 404         uint16_t devices;
 405
 406         /* which DWords are address that need fix up.
 407          * bit 0 means a 32-bit non address operand in command
 408          * bit 1 means address operand, which could be 32-bit
 409          * or 64-bit depending on different architectures.(
 410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 411          * No matter the address length, each address only takes
 412          * one bit in the bitmap.
 413          */
 414         uint16_t addr_bitmap;
 415
 416         /* flag == F_LEN_CONST : command length
 417          * flag == F_LEN_VAR : length bias bits
 418          * Note: length is in DWord
 419          */
 420         uint8_t len;
 421
 422         parser_cmd_handler handler;
 423 };
 424
 425 struct cmd_entry {
 426         struct hlist_node hlist;
 427         struct cmd_info *info;
 428 };
 429
 430 enum {
 431         RING_BUFFER_INSTRUCTION,
 432         BATCH_BUFFER_INSTRUCTION,
 433         BATCH_BUFFER_2ND_LEVEL,
 434 };
 435
 436 enum {
 437         GTT_BUFFER,
 438         PPGTT_BUFFER
 439 };
 440
 441 struct parser_exec_state {
 442         struct intel_vgpu *vgpu;
 443         int ring_id;
 444
 445         int buf_type;
 446
 447         /* batch buffer address type */
 448         int buf_addr_type;
 449
 450         /* graphics memory address of ring buffer start */
 451         unsigned long ring_start;
 452         unsigned long ring_size;
 453         unsigned long ring_head;
 454         unsigned long ring_tail;
 455
 456         /* instruction graphics memory address */
 457         unsigned long ip_gma;
 458
 459         /* mapped va of the instr_gma */
 460         void *ip_va;
 461         void *rb_va;
 462
 463         void *ret_bb_va;
 464         /* next instruction when return from  batch buffer to ring buffer */
 465         unsigned long ret_ip_gma_ring;
 466
 467         /* next instruction when return from 2nd batch buffer to batch buffer */
 468         unsigned long ret_ip_gma_bb;
 469
 470         /* batch buffer address type (GTT or PPGTT)
 471          * used when ret from 2nd level batch buffer
 472          */
 473         int saved_buf_addr_type;
 474         bool is_ctx_wa;
 475
 476         struct cmd_info *info;
 477
 478         struct intel_vgpu_workload *workload;
 479 };
 480
 481 #define gmadr_dw_number(s)      \
 482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 483
 484 static unsigned long bypass_scan_mask = 0;
 485
 486 /* ring ALL, type = 0 */
 487 static struct sub_op_bits sub_op_mi[] = {
 488         {31, 29},
 489         {28, 23},
 490 };
 491
 492 static struct decode_info decode_info_mi = {
 493         "MI",
 494         OP_LEN_MI,
 495         ARRAY_SIZE(sub_op_mi),
 496         sub_op_mi,
 497 };
 498
 499 /* ring RCS, command type 2 */
 500 static struct sub_op_bits sub_op_2d[] = {
 501         {31, 29},
 502         {28, 22},
 503 };
 504
 505 static struct decode_info decode_info_2d = {
 506         "2D",
 507         OP_LEN_2D,
 508         ARRAY_SIZE(sub_op_2d),
 509         sub_op_2d,
 510 };
 511
 512 /* ring RCS, command type 3 */
 513 static struct sub_op_bits sub_op_3d_media[] = {
 514         {31, 29},
 515         {28, 27},
 516         {26, 24},
 517         {23, 16},
 518 };
 519
 520 static struct decode_info decode_info_3d_media = {
 521         "3D_Media",
 522         OP_LEN_3D_MEDIA,
 523         ARRAY_SIZE(sub_op_3d_media),
 524         sub_op_3d_media,
 525 };
 526
 527 /* ring VCS, command type 3 */
 528 static struct sub_op_bits sub_op_mfx_vc[] = {
 529         {31, 29},
 530         {28, 27},
 531         {26, 24},
 532         {23, 21},
 533         {20, 16},
 534 };
 535
 536 static struct decode_info decode_info_mfx_vc = {
 537         "MFX_VC",
 538         OP_LEN_MFX_VC,
 539         ARRAY_SIZE(sub_op_mfx_vc),
 540         sub_op_mfx_vc,
 541 };
 542
 543 /* ring VECS, command type 3 */
 544 static struct sub_op_bits sub_op_vebox[] = {
 545         {31, 29},
 546         {28, 27},
 547         {26, 24},
 548         {23, 21},
 549         {20, 16},
 550 };
 551
 552 static struct decode_info decode_info_vebox = {
 553         "VEBOX",
 554         OP_LEN_VEBOX,
 555         ARRAY_SIZE(sub_op_vebox),
 556         sub_op_vebox,
 557 };
 558
 559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 560         [RCS] = {
 561                 &decode_info_mi,
 562                 NULL,
 563                 NULL,
 564                 &decode_info_3d_media,
 565                 NULL,
 566                 NULL,
 567                 NULL,
 568                 NULL,
 569         },
 570
 571         [VCS] = {
 572                 &decode_info_mi,
 573                 NULL,
 574                 NULL,
 575                 &decode_info_mfx_vc,
 576                 NULL,
 577                 NULL,
 578                 NULL,
 579                 NULL,
 580         },
 581
 582         [BCS] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 &decode_info_2d,
 586                 NULL,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VECS] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_vebox,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [VCS2] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 NULL,
 608                 &decode_info_mfx_vc,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614 };
 615
 616 static inline u32 get_opcode(u32 cmd, int ring_id)
 617 {
 618         struct decode_info *d_info;
 619
 620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 621         if (d_info == NULL)
 622                 return INVALID_OP;
 623
 624         return cmd >> (32 - d_info->op_len);
 625 }
 626
 627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 628                 unsigned int opcode, int ring_id)
 629 {
 630         struct cmd_entry *e;
 631
 632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 633                 if ((opcode == e->info->opcode) &&
 634                                 (e->info->rings & (1 << ring_id)))
 635                         return e->info;
 636         }
 637         return NULL;
 638 }
 639
 640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 641                 u32 cmd, int ring_id)
 642 {
 643         u32 opcode;
 644
 645         opcode = get_opcode(cmd, ring_id);
 646         if (opcode == INVALID_OP)
 647                 return NULL;
 648
 649         return find_cmd_entry(gvt, opcode, ring_id);
 650 }
 651
 652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 653 {
 654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 655 }
 656
 657 static inline void print_opcode(u32 cmd, int ring_id)
 658 {
 659         struct decode_info *d_info;
 660         int i;
 661
 662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 663         if (d_info == NULL)
 664                 return;
 665
 666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 667                         cmd >> (32 - d_info->op_len), d_info->name);
 668
 669         for (i = 0; i < d_info->nr_sub_op; i++)
 670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 671                                         d_info->sub_op[i].low));
 672
 673         pr_err("\n");
 674 }
 675
 676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 677 {
 678         return s->ip_va + (index << 2);
 679 }
 680
 681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 682 {
 683         return *cmd_ptr(s, index);
 684 }
 685
 686 static void parser_exec_state_dump(struct parser_exec_state *s)
 687 {
 688         int cnt = 0;
 689         int i;
 690
 691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 694                         s->ring_head, s->ring_tail);
 695
 696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 698                         "RING_BUFFER" : "BATCH_BUFFER",
 699                         s->buf_addr_type == GTT_BUFFER ?
 700                         "GTT" : "PPGTT", s->ip_gma);
 701
 702         if (s->ip_va == NULL) {
 703                 gvt_dbg_cmd(" ip_va(NULL)");
 704                 return;
 705         }
 706
 707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 709                         cmd_val(s, 2), cmd_val(s, 3));
 710
 711         print_opcode(cmd_val(s, 0), s->ring_id);
 712
 713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 714
 715         while (cnt < 1024) {
 716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 717                 for (i = 0; i < 8; i++)
 718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 719                 gvt_dbg_cmd("\n");
 720
 721                 s->ip_va += 8 * sizeof(u32);
 722                 cnt += 8;
 723         }
 724 }
 725
 726 static inline void update_ip_va(struct parser_exec_state *s)
 727 {
 728         unsigned long len = 0;
 729
 730         if (WARN_ON(s->ring_head == s->ring_tail))
 731                 return;
 732
 733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 734                 unsigned long ring_top = s->ring_start + s->ring_size;
 735
 736                 if (s->ring_head > s->ring_tail) {
 737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 738                                 len = (s->ip_gma - s->ring_head);
 739                         else if (s->ip_gma >= s->ring_start &&
 740                                         s->ip_gma <= s->ring_tail)
 741                                 len = (ring_top - s->ring_head) +
 742                                         (s->ip_gma - s->ring_start);
 743                 } else
 744                         len = (s->ip_gma - s->ring_head);
 745
 746                 s->ip_va = s->rb_va + len;
 747         } else {/* shadow batch buffer */
 748                 s->ip_va = s->ret_bb_va;
 749         }
 750 }
 751
 752 static inline int ip_gma_set(struct parser_exec_state *s,
 753                 unsigned long ip_gma)
 754 {
 755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 756
 757         s->ip_gma = ip_gma;
 758         update_ip_va(s);
 759         return 0;
 760 }
 761
 762 static inline int ip_gma_advance(struct parser_exec_state *s,
 763                 unsigned int dw_len)
 764 {
 765         s->ip_gma += (dw_len << 2);
 766
 767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 768                 if (s->ip_gma >= s->ring_start + s->ring_size)
 769                         s->ip_gma -= s->ring_size;
 770                 update_ip_va(s);
 771         } else {
 772                 s->ip_va += (dw_len << 2);
 773         }
 774
 775         return 0;
 776 }
 777
 778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
 779 {
 780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 781                 return info->len;
 782         else
 783                 return (cmd & ((1U << info->len) - 1)) + 2;
 784         return 0;
 785 }
 786
 787 static inline int cmd_length(struct parser_exec_state *s)
 788 {
 789         return get_cmd_length(s->info, cmd_val(s, 0));
 790 }
 791
 792 /* do not remove this, some platform may need clflush here */
 793 #define patch_value(s, addr, val) do { \
 794         *addr = val; \
 795 } while (0)
 796
 797 static bool is_shadowed_mmio(unsigned int offset)
 798 {
 799         bool ret = false;
 800
 801         if ((offset == 0x2168) || /*BB current head register UDW */
 802             (offset == 0x2140) || /*BB current header register */
 803             (offset == 0x211c) || /*second BB header register UDW */
 804             (offset == 0x2114)) { /*second BB header register UDW */
 805                 ret = true;
 806         }
 807         return ret;
 808 }
 809
 810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 811 {
 812         return (offset >= 0x24d0 && offset < 0x2500);
 813 }
 814
 815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 816                                      unsigned int offset, unsigned int index)
 817 {
 818         struct intel_gvt *gvt = s->vgpu->gvt;
 819         unsigned int data = cmd_val(s, index + 1);
 820
 821         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
 822                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 823                         offset, data);
 824                 return -EPERM;
 825         }
 826         return 0;
 827 }
 828
 829 static inline bool is_mocs_mmio(unsigned int offset)
 830 {
 831         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 832                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 833 }
 834
 835 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 836                                 unsigned int offset, unsigned int index)
 837 {
 838         if (!is_mocs_mmio(offset))
 839                 return -EINVAL;
 840         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 841         return 0;
 842 }
 843
 844 static int cmd_reg_handler(struct parser_exec_state *s,
 845         unsigned int offset, unsigned int index, char *cmd)
 846 {
 847         struct intel_vgpu *vgpu = s->vgpu;
 848         struct intel_gvt *gvt = vgpu->gvt;
 849
 850         if (offset + 4 > gvt->device_info.mmio_size) {
 851                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 852                                 cmd, offset);
 853                 return -EFAULT;
 854         }
 855
 856         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 857                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 858                                 cmd, offset);
 859                 return 0;
 860         }
 861
 862         if (is_shadowed_mmio(offset)) {
 863                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 864                 return 0;
 865         }
 866
 867         if (is_mocs_mmio(offset) &&
 868             mocs_cmd_reg_handler(s, offset, index))
 869                 return -EINVAL;
 870
 871         if (is_force_nonpriv_mmio(offset) &&
 872                 force_nonpriv_reg_handler(s, offset, index))
 873                 return -EPERM;
 874
 875         if (offset == i915_mmio_reg_offset(DERRMR) ||
 876                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 877                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 878                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 879         }
 880
 881         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 882         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 883         return 0;
 884 }
 885
 886 #define cmd_reg(s, i) \
 887         (cmd_val(s, i) & GENMASK(22, 2))
 888
 889 #define cmd_reg_inhibit(s, i) \
 890         (cmd_val(s, i) & GENMASK(22, 18))
 891
 892 #define cmd_gma(s, i) \
 893         (cmd_val(s, i) & GENMASK(31, 2))
 894
 895 #define cmd_gma_hi(s, i) \
 896         (cmd_val(s, i) & GENMASK(15, 0))
 897
 898 static int cmd_handler_lri(struct parser_exec_state *s)
 899 {
 900         int i, ret = 0;
 901         int cmd_len = cmd_length(s);
 902         struct intel_gvt *gvt = s->vgpu->gvt;
 903
 904         for (i = 1; i < cmd_len; i += 2) {
 905                 if (IS_BROADWELL(gvt->dev_priv) &&
 906                                 (s->ring_id != RCS)) {
 907                         if (s->ring_id == BCS &&
 908                                         cmd_reg(s, i) ==
 909                                         i915_mmio_reg_offset(DERRMR))
 910                                 ret |= 0;
 911                         else
 912                                 ret |= (cmd_reg_inhibit(s, i)) ?
 913                                         -EBADRQC : 0;
 914                 }
 915                 if (ret)
 916                         break;
 917                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 918                 if (ret)
 919                         break;
 920         }
 921         return ret;
 922 }
 923
 924 static int cmd_handler_lrr(struct parser_exec_state *s)
 925 {
 926         int i, ret = 0;
 927         int cmd_len = cmd_length(s);
 928
 929         for (i = 1; i < cmd_len; i += 2) {
 930                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
 931                         ret |= ((cmd_reg_inhibit(s, i) ||
 932                                         (cmd_reg_inhibit(s, i + 1)))) ?
 933                                 -EBADRQC : 0;
 934                 if (ret)
 935                         break;
 936                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
 937                 if (ret)
 938                         break;
 939                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
 940                 if (ret)
 941                         break;
 942         }
 943         return ret;
 944 }
 945
 946 static inline int cmd_address_audit(struct parser_exec_state *s,
 947                 unsigned long guest_gma, int op_size, bool index_mode);
 948
 949 static int cmd_handler_lrm(struct parser_exec_state *s)
 950 {
 951         struct intel_gvt *gvt = s->vgpu->gvt;
 952         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 953         unsigned long gma;
 954         int i, ret = 0;
 955         int cmd_len = cmd_length(s);
 956
 957         for (i = 1; i < cmd_len;) {
 958                 if (IS_BROADWELL(gvt->dev_priv))
 959                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
 960                 if (ret)
 961                         break;
 962                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
 963                 if (ret)
 964                         break;
 965                 if (cmd_val(s, 0) & (1 << 22)) {
 966                         gma = cmd_gma(s, i + 1);
 967                         if (gmadr_bytes == 8)
 968                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 969                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 970                         if (ret)
 971                                 break;
 972                 }
 973                 i += gmadr_dw_number(s) + 1;
 974         }
 975         return ret;
 976 }
 977
 978 static int cmd_handler_srm(struct parser_exec_state *s)
 979 {
 980         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
 981         unsigned long gma;
 982         int i, ret = 0;
 983         int cmd_len = cmd_length(s);
 984
 985         for (i = 1; i < cmd_len;) {
 986                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
 987                 if (ret)
 988                         break;
 989                 if (cmd_val(s, 0) & (1 << 22)) {
 990                         gma = cmd_gma(s, i + 1);
 991                         if (gmadr_bytes == 8)
 992                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
 993                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
 994                         if (ret)
 995                                 break;
 996                 }
 997                 i += gmadr_dw_number(s) + 1;
 998         }
 999         return ret;
1000 }
1001
1002 struct cmd_interrupt_event {
1003         int pipe_control_notify;
1004         int mi_flush_dw;
1005         int mi_user_interrupt;
1006 };
1007
1008 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1009         [RCS] = {
1010                 .pipe_control_notify = RCS_PIPE_CONTROL,
1011                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1012                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1013         },
1014         [BCS] = {
1015                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1016                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1017                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1018         },
1019         [VCS] = {
1020                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1021                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1022                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1023         },
1024         [VCS2] = {
1025                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1026                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1027                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1028         },
1029         [VECS] = {
1030                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1031                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1032                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1033         },
1034 };
1035
1036 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1037 {
1038         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1039         unsigned long gma;
1040         bool index_mode = false;
1041         unsigned int post_sync;
1042         int ret = 0;
1043
1044         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1045
1046         /* LRI post sync */
1047         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1048                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1049         /* post sync */
1050         else if (post_sync) {
1051                 if (post_sync == 2)
1052                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1053                 else if (post_sync == 3)
1054                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1055                 else if (post_sync == 1) {
1056                         /* check ggtt*/
1057                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1058                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1059                                 if (gmadr_bytes == 8)
1060                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1061                                 /* Store Data Index */
1062                                 if (cmd_val(s, 1) & (1 << 21))
1063                                         index_mode = true;
1064                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1065                                                 index_mode);
1066                         }
1067                 }
1068         }
1069
1070         if (ret)
1071                 return ret;
1072
1073         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1074                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1075                                 s->workload->pending_events);
1076         return 0;
1077 }
1078
1079 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1080 {
1081         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1082                         s->workload->pending_events);
1083         return 0;
1084 }
1085
1086 static int cmd_advance_default(struct parser_exec_state *s)
1087 {
1088         return ip_gma_advance(s, cmd_length(s));
1089 }
1090
1091 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1092 {
1093         int ret;
1094
1095         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1096                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1097                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1098                 s->buf_addr_type = s->saved_buf_addr_type;
1099         } else {
1100                 s->buf_type = RING_BUFFER_INSTRUCTION;
1101                 s->buf_addr_type = GTT_BUFFER;
1102                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1103                         s->ret_ip_gma_ring -= s->ring_size;
1104                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1105         }
1106         return ret;
1107 }
1108
1109 struct mi_display_flip_command_info {
1110         int pipe;
1111         int plane;
1112         int event;
1113         i915_reg_t stride_reg;
1114         i915_reg_t ctrl_reg;
1115         i915_reg_t surf_reg;
1116         u64 stride_val;
1117         u64 tile_val;
1118         u64 surf_val;
1119         bool async_flip;
1120 };
1121
1122 struct plane_code_mapping {
1123         int pipe;
1124         int plane;
1125         int event;
1126 };
1127
1128 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1129                 struct mi_display_flip_command_info *info)
1130 {
1131         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1132         struct plane_code_mapping gen8_plane_code[] = {
1133                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1134                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1135                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1136                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1137                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1138                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1139         };
1140         u32 dword0, dword1, dword2;
1141         u32 v;
1142
1143         dword0 = cmd_val(s, 0);
1144         dword1 = cmd_val(s, 1);
1145         dword2 = cmd_val(s, 2);
1146
1147         v = (dword0 & GENMASK(21, 19)) >> 19;
1148         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1149                 return -EBADRQC;
1150
1151         info->pipe = gen8_plane_code[v].pipe;
1152         info->plane = gen8_plane_code[v].plane;
1153         info->event = gen8_plane_code[v].event;
1154         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1155         info->tile_val = (dword1 & 0x1);
1156         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1157         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1158
1159         if (info->plane == PLANE_A) {
1160                 info->ctrl_reg = DSPCNTR(info->pipe);
1161                 info->stride_reg = DSPSTRIDE(info->pipe);
1162                 info->surf_reg = DSPSURF(info->pipe);
1163         } else if (info->plane == PLANE_B) {
1164                 info->ctrl_reg = SPRCTL(info->pipe);
1165                 info->stride_reg = SPRSTRIDE(info->pipe);
1166                 info->surf_reg = SPRSURF(info->pipe);
1167         } else {
1168                 WARN_ON(1);
1169                 return -EBADRQC;
1170         }
1171         return 0;
1172 }
1173
1174 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1175                 struct mi_display_flip_command_info *info)
1176 {
1177         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1178         struct intel_vgpu *vgpu = s->vgpu;
1179         u32 dword0 = cmd_val(s, 0);
1180         u32 dword1 = cmd_val(s, 1);
1181         u32 dword2 = cmd_val(s, 2);
1182         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1183
1184         info->plane = PRIMARY_PLANE;
1185
1186         switch (plane) {
1187         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1188                 info->pipe = PIPE_A;
1189                 info->event = PRIMARY_A_FLIP_DONE;
1190                 break;
1191         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1192                 info->pipe = PIPE_B;
1193                 info->event = PRIMARY_B_FLIP_DONE;
1194                 break;
1195         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1196                 info->pipe = PIPE_C;
1197                 info->event = PRIMARY_C_FLIP_DONE;
1198                 break;
1199
1200         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1201                 info->pipe = PIPE_A;
1202                 info->event = SPRITE_A_FLIP_DONE;
1203                 info->plane = SPRITE_PLANE;
1204                 break;
1205         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1206                 info->pipe = PIPE_B;
1207                 info->event = SPRITE_B_FLIP_DONE;
1208                 info->plane = SPRITE_PLANE;
1209                 break;
1210         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1211                 info->pipe = PIPE_C;
1212                 info->event = SPRITE_C_FLIP_DONE;
1213                 info->plane = SPRITE_PLANE;
1214                 break;
1215
1216         default:
1217                 gvt_vgpu_err("unknown plane code %d\n", plane);
1218                 return -EBADRQC;
1219         }
1220
1221         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1222         info->tile_val = (dword1 & GENMASK(2, 0));
1223         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1224         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1225
1226         info->ctrl_reg = DSPCNTR(info->pipe);
1227         info->stride_reg = DSPSTRIDE(info->pipe);
1228         info->surf_reg = DSPSURF(info->pipe);
1229
1230         return 0;
1231 }
1232
1233 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1234                 struct mi_display_flip_command_info *info)
1235 {
1236         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1237         u32 stride, tile;
1238
1239         if (!info->async_flip)
1240                 return 0;
1241
1242         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1243                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1244                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1245                                 GENMASK(12, 10)) >> 10;
1246         } else {
1247                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1248                                 GENMASK(15, 6)) >> 6;
1249                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1250         }
1251
1252         if (stride != info->stride_val)
1253                 gvt_dbg_cmd("cannot change stride during async flip\n");
1254
1255         if (tile != info->tile_val)
1256                 gvt_dbg_cmd("cannot change tile during async flip\n");
1257
1258         return 0;
1259 }
1260
1261 static int gen8_update_plane_mmio_from_mi_display_flip(
1262                 struct parser_exec_state *s,
1263                 struct mi_display_flip_command_info *info)
1264 {
1265         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1266         struct intel_vgpu *vgpu = s->vgpu;
1267
1268         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1269                       info->surf_val << 12);
1270         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1271                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1272                               info->stride_val);
1273                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1274                               info->tile_val << 10);
1275         } else {
1276                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1277                               info->stride_val << 6);
1278                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1279                               info->tile_val << 10);
1280         }
1281
1282         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1283         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1284         return 0;
1285 }
1286
1287 static int decode_mi_display_flip(struct parser_exec_state *s,
1288                 struct mi_display_flip_command_info *info)
1289 {
1290         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1291
1292         if (IS_BROADWELL(dev_priv))
1293                 return gen8_decode_mi_display_flip(s, info);
1294         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1295                 return skl_decode_mi_display_flip(s, info);
1296
1297         return -ENODEV;
1298 }
1299
1300 static int check_mi_display_flip(struct parser_exec_state *s,
1301                 struct mi_display_flip_command_info *info)
1302 {
1303         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1304
1305         if (IS_BROADWELL(dev_priv)
1306                 || IS_SKYLAKE(dev_priv)
1307                 || IS_KABYLAKE(dev_priv))
1308                 return gen8_check_mi_display_flip(s, info);
1309         return -ENODEV;
1310 }
1311
1312 static int update_plane_mmio_from_mi_display_flip(
1313                 struct parser_exec_state *s,
1314                 struct mi_display_flip_command_info *info)
1315 {
1316         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1317
1318         if (IS_BROADWELL(dev_priv)
1319                 || IS_SKYLAKE(dev_priv)
1320                 || IS_KABYLAKE(dev_priv))
1321                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1322         return -ENODEV;
1323 }
1324
1325 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1326 {
1327         struct mi_display_flip_command_info info;
1328         struct intel_vgpu *vgpu = s->vgpu;
1329         int ret;
1330         int i;
1331         int len = cmd_length(s);
1332
1333         ret = decode_mi_display_flip(s, &info);
1334         if (ret) {
1335                 gvt_vgpu_err("fail to decode MI display flip command\n");
1336                 return ret;
1337         }
1338
1339         ret = check_mi_display_flip(s, &info);
1340         if (ret) {
1341                 gvt_vgpu_err("invalid MI display flip command\n");
1342                 return ret;
1343         }
1344
1345         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1346         if (ret) {
1347                 gvt_vgpu_err("fail to update plane mmio\n");
1348                 return ret;
1349         }
1350
1351         for (i = 0; i < len; i++)
1352                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1353         return 0;
1354 }
1355
1356 static bool is_wait_for_flip_pending(u32 cmd)
1357 {
1358         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1359                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1360                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1361                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1362                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1363                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1364 }
1365
1366 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1367 {
1368         u32 cmd = cmd_val(s, 0);
1369
1370         if (!is_wait_for_flip_pending(cmd))
1371                 return 0;
1372
1373         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1374         return 0;
1375 }
1376
1377 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1378 {
1379         unsigned long addr;
1380         unsigned long gma_high, gma_low;
1381         struct intel_vgpu *vgpu = s->vgpu;
1382         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1383
1384         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1385                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1386                 return INTEL_GVT_INVALID_ADDR;
1387         }
1388
1389         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1390         if (gmadr_bytes == 4) {
1391                 addr = gma_low;
1392         } else {
1393                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1394                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1395         }
1396         return addr;
1397 }
1398
1399 static inline int cmd_address_audit(struct parser_exec_state *s,
1400                 unsigned long guest_gma, int op_size, bool index_mode)
1401 {
1402         struct intel_vgpu *vgpu = s->vgpu;
1403         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1404         int i;
1405         int ret;
1406
1407         if (op_size > max_surface_size) {
1408                 gvt_vgpu_err("command address audit fail name %s\n",
1409                         s->info->name);
1410                 return -EFAULT;
1411         }
1412
1413         if (index_mode) {
1414                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1415                         ret = -EFAULT;
1416                         goto err;
1417                 }
1418         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1419                 ret = -EFAULT;
1420                 goto err;
1421         }
1422
1423         return 0;
1424
1425 err:
1426         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1427                         s->info->name, guest_gma, op_size);
1428
1429         pr_err("cmd dump: ");
1430         for (i = 0; i < cmd_length(s); i++) {
1431                 if (!(i % 4))
1432                         pr_err("\n%08x ", cmd_val(s, i));
1433                 else
1434                         pr_err("%08x ", cmd_val(s, i));
1435         }
1436         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1437                         vgpu->id,
1438                         vgpu_aperture_gmadr_base(vgpu),
1439                         vgpu_aperture_gmadr_end(vgpu),
1440                         vgpu_hidden_gmadr_base(vgpu),
1441                         vgpu_hidden_gmadr_end(vgpu));
1442         return ret;
1443 }
1444
1445 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1446 {
1447         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1448         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1449         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1450         unsigned long gma, gma_low, gma_high;
1451         int ret = 0;
1452
1453         /* check ppggt */
1454         if (!(cmd_val(s, 0) & (1 << 22)))
1455                 return 0;
1456
1457         gma = cmd_val(s, 2) & GENMASK(31, 2);
1458
1459         if (gmadr_bytes == 8) {
1460                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1461                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1462                 gma = (gma_high << 32) | gma_low;
1463                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1464         }
1465         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1466         return ret;
1467 }
1468
1469 static inline int unexpected_cmd(struct parser_exec_state *s)
1470 {
1471         struct intel_vgpu *vgpu = s->vgpu;
1472
1473         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1474
1475         return -EBADRQC;
1476 }
1477
1478 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1479 {
1480         return unexpected_cmd(s);
1481 }
1482
1483 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1484 {
1485         return unexpected_cmd(s);
1486 }
1487
1488 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1489 {
1490         return unexpected_cmd(s);
1491 }
1492
1493 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1494 {
1495         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1496         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1497                         sizeof(u32);
1498         unsigned long gma, gma_high;
1499         int ret = 0;
1500
1501         if (!(cmd_val(s, 0) & (1 << 22)))
1502                 return ret;
1503
1504         gma = cmd_val(s, 1) & GENMASK(31, 2);
1505         if (gmadr_bytes == 8) {
1506                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1507                 gma = (gma_high << 32) | gma;
1508         }
1509         ret = cmd_address_audit(s, gma, op_size, false);
1510         return ret;
1511 }
1512
1513 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1514 {
1515         return unexpected_cmd(s);
1516 }
1517
1518 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1519 {
1520         return unexpected_cmd(s);
1521 }
1522
1523 static int cmd_handler_mi_conditional_batch_buffer_end(
1524                 struct parser_exec_state *s)
1525 {
1526         return unexpected_cmd(s);
1527 }
1528
1529 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1530 {
1531         return unexpected_cmd(s);
1532 }
1533
1534 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1535 {
1536         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1537         unsigned long gma;
1538         bool index_mode = false;
1539         int ret = 0;
1540
1541         /* Check post-sync and ppgtt bit */
1542         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1543                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1544                 if (gmadr_bytes == 8)
1545                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1546                 /* Store Data Index */
1547                 if (cmd_val(s, 0) & (1 << 21))
1548                         index_mode = true;
1549                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1550         }
1551         /* Check notify bit */
1552         if ((cmd_val(s, 0) & (1 << 8)))
1553                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1554                                 s->workload->pending_events);
1555         return ret;
1556 }
1557
1558 static void addr_type_update_snb(struct parser_exec_state *s)
1559 {
1560         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1561                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1562                 s->buf_addr_type = PPGTT_BUFFER;
1563         }
1564 }
1565
1566
1567 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1568                 unsigned long gma, unsigned long end_gma, void *va)
1569 {
1570         unsigned long copy_len, offset;
1571         unsigned long len = 0;
1572         unsigned long gpa;
1573
1574         while (gma != end_gma) {
1575                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1576                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1577                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1578                         return -EFAULT;
1579                 }
1580
1581                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1582
1583                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1584                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1585
1586                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1587
1588                 len += copy_len;
1589                 gma += copy_len;
1590         }
1591         return len;
1592 }
1593
1594
1595 /*
1596  * Check whether a batch buffer needs to be scanned. Currently
1597  * the only criteria is based on privilege.
1598  */
1599 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1600 {
1601         struct intel_gvt *gvt = s->vgpu->gvt;
1602
1603         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1604                 || IS_KABYLAKE(gvt->dev_priv)) {
1605                 /* BDW decides privilege based on address space */
1606                 if (cmd_val(s, 0) & (1 << 8))
1607                         return 0;
1608         }
1609         return 1;
1610 }
1611
1612 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1613 {
1614         unsigned long gma = 0;
1615         struct cmd_info *info;
1616         uint32_t cmd_len = 0;
1617         bool bb_end = false;
1618         struct intel_vgpu *vgpu = s->vgpu;
1619         u32 cmd;
1620
1621         *bb_size = 0;
1622
1623         /* get the start gm address of the batch buffer */
1624         gma = get_gma_bb_from_cmd(s, 1);
1625         if (gma == INTEL_GVT_INVALID_ADDR)
1626                 return -EFAULT;
1627
1628         cmd = cmd_val(s, 0);
1629         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1630         if (info == NULL) {
1631                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1632                                 cmd, get_opcode(cmd, s->ring_id));
1633                 return -EBADRQC;
1634         }
1635         do {
1636                 if (copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1637                                 gma, gma + 4, &cmd) < 0)
1638                         return -EFAULT;
1639                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1640                 if (info == NULL) {
1641                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
1642                                 cmd, get_opcode(cmd, s->ring_id));
1643                         return -EBADRQC;
1644                 }
1645
1646                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1647                         bb_end = true;
1648                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1649                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1650                                 /* chained batch buffer */
1651                                 bb_end = true;
1652                 }
1653                 cmd_len = get_cmd_length(info, cmd) << 2;
1654                 *bb_size += cmd_len;
1655                 gma += cmd_len;
1656         } while (!bb_end);
1657
1658         return 0;
1659 }
1660
1661 static int perform_bb_shadow(struct parser_exec_state *s)
1662 {
1663         struct intel_vgpu *vgpu = s->vgpu;
1664         struct intel_vgpu_shadow_bb *bb;
1665         unsigned long gma = 0;
1666         unsigned long bb_size;
1667         int ret = 0;
1668
1669         /* get the start gm address of the batch buffer */
1670         gma = get_gma_bb_from_cmd(s, 1);
1671         if (gma == INTEL_GVT_INVALID_ADDR)
1672                 return -EFAULT;
1673
1674         ret = find_bb_size(s, &bb_size);
1675         if (ret)
1676                 return ret;
1677
1678         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1679         if (!bb)
1680                 return -ENOMEM;
1681
1682         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1683                                          roundup(bb_size, PAGE_SIZE));
1684         if (IS_ERR(bb->obj)) {
1685                 ret = PTR_ERR(bb->obj);
1686                 goto err_free_bb;
1687         }
1688
1689         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1690         if (ret)
1691                 goto err_free_obj;
1692
1693         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1694         if (IS_ERR(bb->va)) {
1695                 ret = PTR_ERR(bb->va);
1696                 goto err_finish_shmem_access;
1697         }
1698
1699         if (bb->clflush & CLFLUSH_BEFORE) {
1700                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1701                 bb->clflush &= ~CLFLUSH_BEFORE;
1702         }
1703
1704         ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1705                               gma, gma + bb_size,
1706                               bb->va);
1707         if (ret < 0) {
1708                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1709                 ret = -EFAULT;
1710                 goto err_unmap;
1711         }
1712
1713         INIT_LIST_HEAD(&bb->list);
1714         list_add(&bb->list, &s->workload->shadow_bb);
1715
1716         bb->accessing = true;
1717         bb->bb_start_cmd_va = s->ip_va;
1718
1719         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1720                 bb->bb_offset = s->ip_va - s->rb_va;
1721         else
1722                 bb->bb_offset = 0;
1723
1724         /*
1725          * ip_va saves the virtual address of the shadow batch buffer, while
1726          * ip_gma saves the graphics address of the original batch buffer.
1727          * As the shadow batch buffer is just a copy from the originial one,
1728          * it should be right to use shadow batch buffer'va and original batch
1729          * buffer's gma in pair. After all, we don't want to pin the shadow
1730          * buffer here (too early).
1731          */
1732         s->ip_va = bb->va;
1733         s->ip_gma = gma;
1734         return 0;
1735 err_unmap:
1736         i915_gem_object_unpin_map(bb->obj);
1737 err_finish_shmem_access:
1738         i915_gem_obj_finish_shmem_access(bb->obj);
1739 err_free_obj:
1740         i915_gem_object_put(bb->obj);
1741 err_free_bb:
1742         kfree(bb);
1743         return ret;
1744 }
1745
1746 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1747 {
1748         bool second_level;
1749         int ret = 0;
1750         struct intel_vgpu *vgpu = s->vgpu;
1751
1752         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1753                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1754                 return -EFAULT;
1755         }
1756
1757         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1758         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1759                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1760                 return -EFAULT;
1761         }
1762
1763         s->saved_buf_addr_type = s->buf_addr_type;
1764         addr_type_update_snb(s);
1765         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1766                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1767                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1768         } else if (second_level) {
1769                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1770                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1771                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1772         }
1773
1774         if (batch_buffer_needs_scan(s)) {
1775                 ret = perform_bb_shadow(s);
1776                 if (ret < 0)
1777                         gvt_vgpu_err("invalid shadow batch buffer\n");
1778         } else {
1779                 /* emulate a batch buffer end to do return right */
1780                 ret = cmd_handler_mi_batch_buffer_end(s);
1781                 if (ret < 0)
1782                         return ret;
1783         }
1784         return ret;
1785 }
1786
1787 static struct cmd_info cmd_info[] = {
1788         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1789
1790         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1791                 0, 1, NULL},
1792
1793         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1794                 0, 1, cmd_handler_mi_user_interrupt},
1795
1796         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1797                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1798
1799         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1800
1801         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1802                 NULL},
1803
1804         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1805                 NULL},
1806
1807         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1808                 NULL},
1809
1810         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1811                 NULL},
1812
1813         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1814                 D_ALL, 0, 1, NULL},
1815
1816         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1817                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1818                 cmd_handler_mi_batch_buffer_end},
1819
1820         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1821                 0, 1, NULL},
1822
1823         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1824                 NULL},
1825
1826         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1827                 D_ALL, 0, 1, NULL},
1828
1829         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1830                 NULL},
1831
1832         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1833                 NULL},
1834
1835         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1836                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1837
1838         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1839                 0, 8, NULL},
1840
1841         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1842
1843         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1844
1845         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1846                 D_BDW_PLUS, 0, 8, NULL},
1847
1848         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1849                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1850
1851         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1852                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1853
1854         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1855                 0, 8, cmd_handler_mi_store_data_index},
1856
1857         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1858                 D_ALL, 0, 8, cmd_handler_lri},
1859
1860         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1861                 cmd_handler_mi_update_gtt},
1862
1863         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1864                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1865
1866         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1867                 cmd_handler_mi_flush_dw},
1868
1869         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1870                 10, cmd_handler_mi_clflush},
1871
1872         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1873                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1874
1875         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1876                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1877
1878         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1879                 D_ALL, 0, 8, cmd_handler_lrr},
1880
1881         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1882                 D_ALL, 0, 8, NULL},
1883
1884         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1885                 ADDR_FIX_1(2), 8, NULL},
1886
1887         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1888                 ADDR_FIX_1(2), 8, NULL},
1889
1890         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1891                 8, cmd_handler_mi_op_2e},
1892
1893         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1894                 8, cmd_handler_mi_op_2f},
1895
1896         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1897                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1898                 cmd_handler_mi_batch_buffer_start},
1899
1900         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1901                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1902                 cmd_handler_mi_conditional_batch_buffer_end},
1903
1904         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1905                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1906
1907         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1908                 ADDR_FIX_2(4, 7), 8, NULL},
1909
1910         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1911                 0, 8, NULL},
1912
1913         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1914                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1915
1916         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1917
1918         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1919                 0, 8, NULL},
1920
1921         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1922                 ADDR_FIX_1(3), 8, NULL},
1923
1924         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1925                 D_ALL, 0, 8, NULL},
1926
1927         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1928                 ADDR_FIX_1(4), 8, NULL},
1929
1930         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1931                 ADDR_FIX_2(4, 5), 8, NULL},
1932
1933         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1934                 ADDR_FIX_1(4), 8, NULL},
1935
1936         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1937                 ADDR_FIX_2(4, 7), 8, NULL},
1938
1939         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1940                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1941
1942         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1943
1944         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1945                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1946
1947         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1948                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1949
1950         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1951                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1952                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1953
1954         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1955                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1956
1957         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1958                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1959
1960         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1961                 D_ALL, ADDR_FIX_1(4), 8, NULL},
1962
1963         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1964                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1965
1966         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
1967                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1968
1969         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
1970                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
1971                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1972
1973         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
1974                 ADDR_FIX_2(4, 5), 8, NULL},
1975
1976         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
1977                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1978
1979         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
1980                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1981                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1982
1983         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
1984                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
1985                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1986
1987         {"3DSTATE_BLEND_STATE_POINTERS",
1988                 OP_3DSTATE_BLEND_STATE_POINTERS,
1989                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1990
1991         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
1992                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1993                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1994
1995         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
1996                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
1997                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1998
1999         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2000                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2001                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2002
2003         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2004                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2005                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2006
2007         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2008                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2009                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2010
2011         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2012                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2013                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2014
2015         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2016                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2017                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2018
2019         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2020                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2021                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2022
2023         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2024                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2025                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2026
2027         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2028                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2029                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2030
2031         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2032                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2033                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2034
2035         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2036                 0, 8, NULL},
2037
2038         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2039                 0, 8, NULL},
2040
2041         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2042                 0, 8, NULL},
2043
2044         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2045                 0, 8, NULL},
2046
2047         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2048                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2049
2050         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2051                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2052
2053         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2054                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2055
2056         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2057                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2058
2059         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2060                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2061
2062         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2063                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2064
2065         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2066                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2067
2068         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2069                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2070
2071         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2072                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2073
2074         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2075                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2076
2077         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2078                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2079
2080         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2081                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2082
2083         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2084                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2085
2086         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2087                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2088
2089         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2090                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2091
2092         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2093                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2094
2095         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2096                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2097
2098         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2099                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2100
2101         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2102                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2103
2104         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2105                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2106
2107         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2108                 D_BDW_PLUS, 0, 8, NULL},
2109
2110         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2111                 NULL},
2112
2113         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2114                 D_BDW_PLUS, 0, 8, NULL},
2115
2116         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2117                 D_BDW_PLUS, 0, 8, NULL},
2118
2119         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2120                 8, NULL},
2121
2122         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2123                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2124
2125         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2126                 8, NULL},
2127
2128         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2129                 NULL},
2130
2131         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2132                 NULL},
2133
2134         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2135                 NULL},
2136
2137         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2138                 D_BDW_PLUS, 0, 8, NULL},
2139
2140         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2141                 R_RCS, D_ALL, 0, 8, NULL},
2142
2143         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2144                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2145
2146         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2147                 R_RCS, D_ALL, 0, 1, NULL},
2148
2149         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2150
2151         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2152                 R_RCS, D_ALL, 0, 8, NULL},
2153
2154         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2155                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2156
2157         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2158
2159         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2160
2161         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2162
2163         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2164                 D_BDW_PLUS, 0, 8, NULL},
2165
2166         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2167                 D_BDW_PLUS, 0, 8, NULL},
2168
2169         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2170                 D_ALL, 0, 8, NULL},
2171
2172         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2173                 D_BDW_PLUS, 0, 8, NULL},
2174
2175         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2176                 D_BDW_PLUS, 0, 8, NULL},
2177
2178         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2179
2180         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2181
2182         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2183
2184         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2185                 D_ALL, 0, 8, NULL},
2186
2187         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2188
2189         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2190
2191         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2192                 R_RCS, D_ALL, 0, 8, NULL},
2193
2194         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2195                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2196
2197         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2198                 0, 8, NULL},
2199
2200         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2201                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2202
2203         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2204                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2205
2206         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2207                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2208
2209         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2210                 D_ALL, 0, 8, NULL},
2211
2212         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2213                 D_ALL, 0, 8, NULL},
2214
2215         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2216                 D_ALL, 0, 8, NULL},
2217
2218         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2219                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2220
2221         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2222                 D_BDW_PLUS, 0, 8, NULL},
2223
2224         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2225                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2226
2227         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2228                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2229
2230         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2231                 R_RCS, D_ALL, 0, 8, NULL},
2232
2233         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2234                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2235
2236         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2237                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2238
2239         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2240                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2241
2242         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2243                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2244
2245         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2246                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2249                 R_RCS, D_ALL, 0, 8, NULL},
2250
2251         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2252                 D_ALL, 0, 9, NULL},
2253
2254         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2255                 ADDR_FIX_2(2, 4), 8, NULL},
2256
2257         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2258                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2259                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2260
2261         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2262                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2263
2264         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2265                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2266                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2267
2268         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2269                 D_BDW_PLUS, 0, 8, NULL},
2270
2271         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2272                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2273
2274         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2275
2276         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2277                 1, NULL},
2278
2279         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2280                 ADDR_FIX_1(1), 8, NULL},
2281
2282         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2283
2284         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2285                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2286
2287         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2288                 ADDR_FIX_1(1), 8, NULL},
2289
2290         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2291
2292         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2293
2294         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2295                 0, 8, NULL},
2296
2297         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2298                 D_SKL_PLUS, 0, 8, NULL},
2299
2300         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2301                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2302
2303         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2304                 0, 16, NULL},
2305
2306         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2307                 0, 16, NULL},
2308
2309         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2310
2311         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2312                 0, 16, NULL},
2313
2314         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2315                 0, 16, NULL},
2316
2317         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2318                 0, 16, NULL},
2319
2320         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2321                 0, 8, NULL},
2322
2323         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2324                 NULL},
2325
2326         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2327                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2328
2329         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2330                 R_VCS, D_ALL, 0, 12, NULL},
2331
2332         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2333                 R_VCS, D_ALL, 0, 12, NULL},
2334
2335         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2336                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2337
2338         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2339                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2340
2341         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2342                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2343
2344         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2345
2346         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2347                 R_VCS, D_ALL, 0, 12, NULL},
2348
2349         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2350                 R_VCS, D_ALL, 0, 12, NULL},
2351
2352         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2353                 R_VCS, D_ALL, 0, 12, NULL},
2354
2355         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2356                 R_VCS, D_ALL, 0, 12, NULL},
2357
2358         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2359                 R_VCS, D_ALL, 0, 12, NULL},
2360
2361         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2362                 R_VCS, D_ALL, 0, 12, NULL},
2363
2364         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2365                 R_VCS, D_ALL, 0, 6, NULL},
2366
2367         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2368                 R_VCS, D_ALL, 0, 12, NULL},
2369
2370         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2371                 R_VCS, D_ALL, 0, 12, NULL},
2372
2373         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2374                 R_VCS, D_ALL, 0, 12, NULL},
2375
2376         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2377                 R_VCS, D_ALL, 0, 12, NULL},
2378
2379         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2380                 R_VCS, D_ALL, 0, 12, NULL},
2381
2382         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2383                 R_VCS, D_ALL, 0, 12, NULL},
2384
2385         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2386                 R_VCS, D_ALL, 0, 12, NULL},
2387         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2388                 R_VCS, D_ALL, 0, 12, NULL},
2389
2390         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2391                 R_VCS, D_ALL, 0, 12, NULL},
2392
2393         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2394                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2395
2396         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2397                 R_VCS, D_ALL, 0, 12, NULL},
2398
2399         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2400                 R_VCS, D_ALL, 0, 12, NULL},
2401
2402         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2403                 R_VCS, D_ALL, 0, 12, NULL},
2404
2405         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2406                 R_VCS, D_ALL, 0, 12, NULL},
2407
2408         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2409                 R_VCS, D_ALL, 0, 12, NULL},
2410
2411         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2412                 R_VCS, D_ALL, 0, 12, NULL},
2413
2414         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2415                 R_VCS, D_ALL, 0, 12, NULL},
2416
2417         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2418                 R_VCS, D_ALL, 0, 12, NULL},
2419
2420         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2421                 R_VCS, D_ALL, 0, 12, NULL},
2422
2423         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2424                 R_VCS, D_ALL, 0, 12, NULL},
2425
2426         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2427                 R_VCS, D_ALL, 0, 12, NULL},
2428
2429         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2430                 0, 16, NULL},
2431
2432         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2433
2434         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2435
2436         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2437                 R_VCS, D_ALL, 0, 12, NULL},
2438
2439         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2440                 R_VCS, D_ALL, 0, 12, NULL},
2441
2442         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2443                 R_VCS, D_ALL, 0, 12, NULL},
2444
2445         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2446
2447         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2448                 0, 12, NULL},
2449
2450         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2451                 0, 20, NULL},
2452 };
2453
2454 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2455 {
2456         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2457 }
2458
2459 /* call the cmd handler, and advance ip */
2460 static int cmd_parser_exec(struct parser_exec_state *s)
2461 {
2462         struct intel_vgpu *vgpu = s->vgpu;
2463         struct cmd_info *info;
2464         u32 cmd;
2465         int ret = 0;
2466
2467         cmd = cmd_val(s, 0);
2468
2469         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2470         if (info == NULL) {
2471                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x\n",
2472                                 cmd, get_opcode(cmd, s->ring_id));
2473                 return -EBADRQC;
2474         }
2475
2476         s->info = info;
2477
2478         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2479                           cmd_length(s), s->buf_type);
2480
2481         if (info->handler) {
2482                 ret = info->handler(s);
2483                 if (ret < 0) {
2484                         gvt_vgpu_err("%s handler error\n", info->name);
2485                         return ret;
2486                 }
2487         }
2488
2489         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2490                 ret = cmd_advance_default(s);
2491                 if (ret) {
2492                         gvt_vgpu_err("%s IP advance error\n", info->name);
2493                         return ret;
2494                 }
2495         }
2496         return 0;
2497 }
2498
2499 static inline bool gma_out_of_range(unsigned long gma,
2500                 unsigned long gma_head, unsigned int gma_tail)
2501 {
2502         if (gma_tail >= gma_head)
2503                 return (gma < gma_head) || (gma > gma_tail);
2504         else
2505                 return (gma > gma_tail) && (gma < gma_head);
2506 }
2507
2508 /* Keep the consistent return type, e.g EBADRQC for unknown
2509  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2510  * works as the input of VM healthy status.
2511  */
2512 static int command_scan(struct parser_exec_state *s,
2513                 unsigned long rb_head, unsigned long rb_tail,
2514                 unsigned long rb_start, unsigned long rb_len)
2515 {
2516
2517         unsigned long gma_head, gma_tail, gma_bottom;
2518         int ret = 0;
2519         struct intel_vgpu *vgpu = s->vgpu;
2520
2521         gma_head = rb_start + rb_head;
2522         gma_tail = rb_start + rb_tail;
2523         gma_bottom = rb_start +  rb_len;
2524
2525         while (s->ip_gma != gma_tail) {
2526                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2527                         if (!(s->ip_gma >= rb_start) ||
2528                                 !(s->ip_gma < gma_bottom)) {
2529                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2530                                         "(base:0x%lx, bottom: 0x%lx)\n",
2531                                         s->ip_gma, rb_start,
2532                                         gma_bottom);
2533                                 parser_exec_state_dump(s);
2534                                 return -EFAULT;
2535                         }
2536                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2537                                 gvt_vgpu_err("ip_gma %lx out of range."
2538                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2539                                         s->ip_gma, rb_start,
2540                                         rb_head, rb_tail);
2541                                 parser_exec_state_dump(s);
2542                                 break;
2543                         }
2544                 }
2545                 ret = cmd_parser_exec(s);
2546                 if (ret) {
2547                         gvt_vgpu_err("cmd parser error\n");
2548                         parser_exec_state_dump(s);
2549                         break;
2550                 }
2551         }
2552
2553         return ret;
2554 }
2555
2556 static int scan_workload(struct intel_vgpu_workload *workload)
2557 {
2558         unsigned long gma_head, gma_tail, gma_bottom;
2559         struct parser_exec_state s;
2560         int ret = 0;
2561
2562         /* ring base is page aligned */
2563         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2564                 return -EINVAL;
2565
2566         gma_head = workload->rb_start + workload->rb_head;
2567         gma_tail = workload->rb_start + workload->rb_tail;
2568         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2569
2570         s.buf_type = RING_BUFFER_INSTRUCTION;
2571         s.buf_addr_type = GTT_BUFFER;
2572         s.vgpu = workload->vgpu;
2573         s.ring_id = workload->ring_id;
2574         s.ring_start = workload->rb_start;
2575         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2576         s.ring_head = gma_head;
2577         s.ring_tail = gma_tail;
2578         s.rb_va = workload->shadow_ring_buffer_va;
2579         s.workload = workload;
2580         s.is_ctx_wa = false;
2581
2582         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2583                 gma_head == gma_tail)
2584                 return 0;
2585
2586         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2587                 ret = -EINVAL;
2588                 goto out;
2589         }
2590
2591         ret = ip_gma_set(&s, gma_head);
2592         if (ret)
2593                 goto out;
2594
2595         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2596                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2597
2598 out:
2599         return ret;
2600 }
2601
2602 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2603 {
2604
2605         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2606         struct parser_exec_state s;
2607         int ret = 0;
2608         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2609                                 struct intel_vgpu_workload,
2610                                 wa_ctx);
2611
2612         /* ring base is page aligned */
2613         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2614                                         I915_GTT_PAGE_SIZE)))
2615                 return -EINVAL;
2616
2617         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2618         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2619                         PAGE_SIZE);
2620         gma_head = wa_ctx->indirect_ctx.guest_gma;
2621         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2622         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2623
2624         s.buf_type = RING_BUFFER_INSTRUCTION;
2625         s.buf_addr_type = GTT_BUFFER;
2626         s.vgpu = workload->vgpu;
2627         s.ring_id = workload->ring_id;
2628         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2629         s.ring_size = ring_size;
2630         s.ring_head = gma_head;
2631         s.ring_tail = gma_tail;
2632         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2633         s.workload = workload;
2634         s.is_ctx_wa = true;
2635
2636         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2637                 ret = -EINVAL;
2638                 goto out;
2639         }
2640
2641         ret = ip_gma_set(&s, gma_head);
2642         if (ret)
2643                 goto out;
2644
2645         ret = command_scan(&s, 0, ring_tail,
2646                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2647 out:
2648         return ret;
2649 }
2650
2651 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2652 {
2653         struct intel_vgpu *vgpu = workload->vgpu;
2654         struct intel_vgpu_submission *s = &vgpu->submission;
2655         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2656         void *shadow_ring_buffer_va;
2657         int ring_id = workload->ring_id;
2658         int ret;
2659
2660         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2661
2662         /* calculate workload ring buffer size */
2663         workload->rb_len = (workload->rb_tail + guest_rb_size -
2664                         workload->rb_head) % guest_rb_size;
2665
2666         gma_head = workload->rb_start + workload->rb_head;
2667         gma_tail = workload->rb_start + workload->rb_tail;
2668         gma_top = workload->rb_start + guest_rb_size;
2669
2670         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2671                 void *p;
2672
2673                 /* realloc the new ring buffer if needed */
2674                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2675                                 GFP_KERNEL);
2676                 if (!p) {
2677                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2678                         return -ENOMEM;
2679                 }
2680                 s->ring_scan_buffer[ring_id] = p;
2681                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2682         }
2683
2684         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2685
2686         /* get shadow ring buffer va */
2687         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2688
2689         /* head > tail --> copy head <-> top */
2690         if (gma_head > gma_tail) {
2691                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2692                                       gma_head, gma_top, shadow_ring_buffer_va);
2693                 if (ret < 0) {
2694                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2695                         return ret;
2696                 }
2697                 shadow_ring_buffer_va += ret;
2698                 gma_head = workload->rb_start;
2699         }
2700
2701         /* copy head or start <-> tail */
2702         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2703                                 shadow_ring_buffer_va);
2704         if (ret < 0) {
2705                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2706                 return ret;
2707         }
2708         return 0;
2709 }
2710
2711 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2712 {
2713         int ret;
2714         struct intel_vgpu *vgpu = workload->vgpu;
2715
2716         ret = shadow_workload_ring_buffer(workload);
2717         if (ret) {
2718                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2719                 return ret;
2720         }
2721
2722         ret = scan_workload(workload);
2723         if (ret) {
2724                 gvt_vgpu_err("scan workload error\n");
2725                 return ret;
2726         }
2727         return 0;
2728 }
2729
2730 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2731 {
2732         int ctx_size = wa_ctx->indirect_ctx.size;
2733         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2734         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2735                                         struct intel_vgpu_workload,
2736                                         wa_ctx);
2737         struct intel_vgpu *vgpu = workload->vgpu;
2738         struct drm_i915_gem_object *obj;
2739         int ret = 0;
2740         void *map;
2741
2742         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2743                                      roundup(ctx_size + CACHELINE_BYTES,
2744                                              PAGE_SIZE));
2745         if (IS_ERR(obj))
2746                 return PTR_ERR(obj);
2747
2748         /* get the va of the shadow batch buffer */
2749         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2750         if (IS_ERR(map)) {
2751                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2752                 ret = PTR_ERR(map);
2753                 goto put_obj;
2754         }
2755
2756         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2757         if (ret) {
2758                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2759                 goto unmap_src;
2760         }
2761
2762         ret = copy_gma_to_hva(workload->vgpu,
2763                                 workload->vgpu->gtt.ggtt_mm,
2764                                 guest_gma, guest_gma + ctx_size,
2765                                 map);
2766         if (ret < 0) {
2767                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2768                 goto unmap_src;
2769         }
2770
2771         wa_ctx->indirect_ctx.obj = obj;
2772         wa_ctx->indirect_ctx.shadow_va = map;
2773         return 0;
2774
2775 unmap_src:
2776         i915_gem_object_unpin_map(obj);
2777 put_obj:
2778         i915_gem_object_put(obj);
2779         return ret;
2780 }
2781
2782 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2783 {
2784         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2785         unsigned char *bb_start_sva;
2786
2787         if (!wa_ctx->per_ctx.valid)
2788                 return 0;
2789
2790         per_ctx_start[0] = 0x18800001;
2791         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2792
2793         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2794                                 wa_ctx->indirect_ctx.size;
2795
2796         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2797
2798         return 0;
2799 }
2800
2801 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2802 {
2803         int ret;
2804         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2805                                         struct intel_vgpu_workload,
2806                                         wa_ctx);
2807         struct intel_vgpu *vgpu = workload->vgpu;
2808
2809         if (wa_ctx->indirect_ctx.size == 0)
2810                 return 0;
2811
2812         ret = shadow_indirect_ctx(wa_ctx);
2813         if (ret) {
2814                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2815                 return ret;
2816         }
2817
2818         combine_wa_ctx(wa_ctx);
2819
2820         ret = scan_wa_ctx(wa_ctx);
2821         if (ret) {
2822                 gvt_vgpu_err("scan wa ctx error\n");
2823                 return ret;
2824         }
2825
2826         return 0;
2827 }
2828
2829 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2830                 unsigned int opcode, unsigned long rings)
2831 {
2832         struct cmd_info *info = NULL;
2833         unsigned int ring;
2834
2835         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2836                 info = find_cmd_entry(gvt, opcode, ring);
2837                 if (info)
2838                         break;
2839         }
2840         return info;
2841 }
2842
2843 static int init_cmd_table(struct intel_gvt *gvt)
2844 {
2845         int i;
2846         struct cmd_entry *e;
2847         struct cmd_info *info;
2848         unsigned int gen_type;
2849
2850         gen_type = intel_gvt_get_device_type(gvt);
2851
2852         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2853                 if (!(cmd_info[i].devices & gen_type))
2854                         continue;
2855
2856                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2857                 if (!e)
2858                         return -ENOMEM;
2859
2860                 e->info = &cmd_info[i];
2861                 info = find_cmd_entry_any_ring(gvt,
2862                                 e->info->opcode, e->info->rings);
2863                 if (info) {
2864                         gvt_err("%s %s duplicated\n", e->info->name,
2865                                         info->name);
2866                         return -EEXIST;
2867                 }
2868
2869                 INIT_HLIST_NODE(&e->hlist);
2870                 add_cmd_entry(gvt, e);
2871                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2872                                 e->info->name, e->info->opcode, e->info->flag,
2873                                 e->info->devices, e->info->rings);
2874         }
2875         return 0;
2876 }
2877
2878 static void clean_cmd_table(struct intel_gvt *gvt)
2879 {
2880         struct hlist_node *tmp;
2881         struct cmd_entry *e;
2882         int i;
2883
2884         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2885                 kfree(e);
2886
2887         hash_init(gvt->cmd_table);
2888 }
2889
2890 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2891 {
2892         clean_cmd_table(gvt);
2893 }
2894
2895 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2896 {
2897         int ret;
2898
2899         ret = init_cmd_table(gvt);
2900         if (ret) {
2901                 intel_gvt_clean_cmd_parser(gvt);
2902                 return ret;
2903         }
2904         return 0;
2905 }