drivers/gpu/drm/i915/gvt/cmd_parser.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27  *
  28  * Contributors:
  29  *    Min He <min.he@intel.com>
  30  *    Ping Gao <ping.a.gao@intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Yulei Zhang <yulei.zhang@intel.com>
  33  *    Zhi Wang <zhi.a.wang@intel.com>
  34  *
  35  */
  36
  37 #include <linux/slab.h>
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40 #include "i915_pvinfo.h"
  41 #include "trace.h"
  42
  43 #define INVALID_OP    (~0U)
  44
  45 #define OP_LEN_MI           9
  46 #define OP_LEN_2D           10
  47 #define OP_LEN_3D_MEDIA     16
  48 #define OP_LEN_MFX_VC       16
  49 #define OP_LEN_VEBOX        16
  50
  51 #define CMD_TYPE(cmd)   (((cmd) >> 29) & 7)
  52
  53 struct sub_op_bits {
  54         int hi;
  55         int low;
  56 };
  57 struct decode_info {
  58         char *name;
  59         int op_len;
  60         int nr_sub_op;
  61         struct sub_op_bits *sub_op;
  62 };
  63
  64 #define   MAX_CMD_BUDGET                        0x7fffffff
  65 #define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  66 #define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  67 #define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  68
  69 #define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  70 #define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  71 #define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  72
  73 /* Render Command Map */
  74
  75 /* MI_* command Opcode (28:23) */
  76 #define OP_MI_NOOP                          0x0
  77 #define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  78 #define OP_MI_USER_INTERRUPT                0x2
  79 #define OP_MI_WAIT_FOR_EVENT                0x3
  80 #define OP_MI_FLUSH                         0x4
  81 #define OP_MI_ARB_CHECK                     0x5
  82 #define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  83 #define OP_MI_REPORT_HEAD                   0x7
  84 #define OP_MI_ARB_ON_OFF                    0x8
  85 #define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  86 #define OP_MI_BATCH_BUFFER_END              0xA
  87 #define OP_MI_SUSPEND_FLUSH                 0xB
  88 #define OP_MI_PREDICATE                     0xC  /* IVB+ */
  89 #define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
  90 #define OP_MI_SET_APPID                     0xE  /* IVB+ */
  91 #define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
  92 #define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
  93 #define OP_MI_DISPLAY_FLIP                  0x14
  94 #define OP_MI_SEMAPHORE_MBOX                0x16
  95 #define OP_MI_SET_CONTEXT                   0x18
  96 #define OP_MI_MATH                          0x1A
  97 #define OP_MI_URB_CLEAR                     0x19
  98 #define OP_MI_SEMAPHORE_SIGNAL              0x1B  /* BDW+ */
  99 #define OP_MI_SEMAPHORE_WAIT                0x1C  /* BDW+ */
 100
 101 #define OP_MI_STORE_DATA_IMM                0x20
 102 #define OP_MI_STORE_DATA_INDEX              0x21
 103 #define OP_MI_LOAD_REGISTER_IMM             0x22
 104 #define OP_MI_UPDATE_GTT                    0x23
 105 #define OP_MI_STORE_REGISTER_MEM            0x24
 106 #define OP_MI_FLUSH_DW                      0x26
 107 #define OP_MI_CLFLUSH                       0x27
 108 #define OP_MI_REPORT_PERF_COUNT             0x28
 109 #define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 110 #define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 111 #define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 112 #define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 113 #define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 114 #define OP_MI_2E                            0x2E  /* BDW+ */
 115 #define OP_MI_2F                            0x2F  /* BDW+ */
 116 #define OP_MI_BATCH_BUFFER_START            0x31
 117
 118 /* Bit definition for dword 0 */
 119 #define _CMDBIT_BB_START_IN_PPGTT       (1UL << 8)
 120
 121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 122
 123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 125 #define BATCH_BUFFER_ADR_SPACE_BIT(x)   (((x) >> 8) & 1U)
 126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 127
 128 /* 2D command: Opcode (28:22) */
 129 #define OP_2D(x)    ((2<<7) | x)
 130
 131 #define OP_XY_SETUP_BLT                             OP_2D(0x1)
 132 #define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 134 #define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 135 #define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 136 #define OP_XY_TEXT_BLT                              OP_2D(0x26)
 137 #define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 138 #define OP_XY_COLOR_BLT                             OP_2D(0x50)
 139 #define OP_XY_PAT_BLT                               OP_2D(0x51)
 140 #define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 141 #define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 142 #define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 143 #define OP_XY_FULL_BLT                              OP_2D(0x55)
 144 #define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 145 #define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 147 #define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 149 #define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 150 #define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 153 #define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 155
 156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 158         ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 159
 160 #define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 161
 162 #define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 163 #define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 164 #define OP_3D_MEDIA_0_1_4                       OP_3D_MEDIA(0x0, 0x1, 0x04)
 165
 166 #define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 167
 168 #define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 169
 170 #define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 171 #define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 173 #define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 174 #define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 175
 176 #define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 177 #define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 178 #define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 179 #define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 180
 181 #define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 182 #define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 183 #define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 184 #define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 185 #define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 186 #define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 187 #define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 188 #define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 189 #define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 190 #define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 192 #define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 193 #define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 194 #define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 195 #define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 196 #define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 197 #define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 198 #define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 199 #define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 200 #define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 201 #define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 202 #define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 203 #define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 204 #define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 205 #define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 206 #define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 207 #define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 208 #define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 211 #define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 223 #define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 224 #define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 225 #define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 226 #define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 227 #define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 228 #define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 229 #define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 230 #define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 231 #define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 232 #define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 233 #define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 234 #define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 235 #define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 236 #define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 237 #define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 247
 248 #define OP_3DSTATE_VF_INSTANCING                OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 249 #define OP_3DSTATE_VF_SGVS                      OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 250 #define OP_3DSTATE_VF_TOPOLOGY                  OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 251 #define OP_3DSTATE_WM_CHROMAKEY                 OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 252 #define OP_3DSTATE_PS_BLEND                     OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 253 #define OP_3DSTATE_WM_DEPTH_STENCIL             OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 254 #define OP_3DSTATE_PS_EXTRA                     OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 255 #define OP_3DSTATE_RASTER                       OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 256 #define OP_3DSTATE_SBE_SWIZ                     OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 257 #define OP_3DSTATE_WM_HZ_OP                     OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 258 #define OP_3DSTATE_COMPONENT_PACKING            OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 259
 260 #define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 262 #define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 263 #define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 266 #define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 267 #define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 268 #define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 270 #define OP_3DSTATE_MULTISAMPLE_BDW              OP_3D_MEDIA(0x3, 0x0, 0x0D)
 271 #define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 273 #define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 274 #define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 280 #define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 281 #define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 283 #define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 285 #define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 286 #define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 287 #define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 288
 289 /* VCCP Command Parser */
 290
 291 /*
 292  * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 293  * git://anongit.freedesktop.org/vaapi/intel-driver
 294  * src/i965_defines.h
 295  *
 296  */
 297
 298 #define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 299         (3 << 13 | \
 300          (pipeline) << 11 | \
 301          (op) << 8 | \
 302          (sub_opa) << 5 | \
 303          (sub_opb))
 304
 305 #define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 306 #define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 307 #define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 310 #define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 311 #define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 312 #define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 313 #define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 314 #define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 315 #define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 316
 317 #define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 318
 319 #define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 320 #define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 321 #define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 322 #define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 323 #define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 324 #define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 326 #define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 327 #define OP_MFD_AVC_DPB_STATE                       OP_MFX(2, 1, 1, 6) /* IVB+ */
 328 #define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 329 #define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 330 #define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 331
 332 #define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 333 #define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 334 #define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 335 #define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 336 #define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 337
 338 #define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 339 #define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 340 #define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 341 #define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 342 #define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 343
 344 #define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 345 #define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 346 #define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 347
 348 #define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 349 #define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 350 #define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 351
 352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 353         (3 << 13 | \
 354          (pipeline) << 11 | \
 355          (op) << 8 | \
 356          (sub_opa) << 5 | \
 357          (sub_opb))
 358
 359 #define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 360 #define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 361 #define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 362
 363 struct parser_exec_state;
 364
 365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 366
 367 #define GVT_CMD_HASH_BITS   7
 368
 369 /* which DWords need address fix */
 370 #define ADDR_FIX_1(x1)                  (1 << (x1))
 371 #define ADDR_FIX_2(x1, x2)              (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 372 #define ADDR_FIX_3(x1, x2, x3)          (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 373 #define ADDR_FIX_4(x1, x2, x3, x4)      (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 374 #define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 375
 376 struct cmd_info {
 377         char *name;
 378         u32 opcode;
 379
 380 #define F_LEN_MASK      (1U<<0)
 381 #define F_LEN_CONST  1U
 382 #define F_LEN_VAR    0U
 383
 384 /*
 385  * command has its own ip advance logic
 386  * e.g. MI_BATCH_START, MI_BATCH_END
 387  */
 388 #define F_IP_ADVANCE_CUSTOM (1<<1)
 389
 390 #define F_POST_HANDLE   (1<<2)
 391         u32 flag;
 392
 393 #define R_RCS   (1 << RCS)
 394 #define R_VCS1  (1 << VCS)
 395 #define R_VCS2  (1 << VCS2)
 396 #define R_VCS   (R_VCS1 | R_VCS2)
 397 #define R_BCS   (1 << BCS)
 398 #define R_VECS  (1 << VECS)
 399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 400         /* rings that support this cmd: BLT/RCS/VCS/VECS */
 401         uint16_t rings;
 402
 403         /* devices that support this cmd: SNB/IVB/HSW/... */
 404         uint16_t devices;
 405
 406         /* which DWords are address that need fix up.
 407          * bit 0 means a 32-bit non address operand in command
 408          * bit 1 means address operand, which could be 32-bit
 409          * or 64-bit depending on different architectures.(
 410          * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 411          * No matter the address length, each address only takes
 412          * one bit in the bitmap.
 413          */
 414         uint16_t addr_bitmap;
 415
 416         /* flag == F_LEN_CONST : command length
 417          * flag == F_LEN_VAR : length bias bits
 418          * Note: length is in DWord
 419          */
 420         uint8_t len;
 421
 422         parser_cmd_handler handler;
 423 };
 424
 425 struct cmd_entry {
 426         struct hlist_node hlist;
 427         struct cmd_info *info;
 428 };
 429
 430 enum {
 431         RING_BUFFER_INSTRUCTION,
 432         BATCH_BUFFER_INSTRUCTION,
 433         BATCH_BUFFER_2ND_LEVEL,
 434 };
 435
 436 enum {
 437         GTT_BUFFER,
 438         PPGTT_BUFFER
 439 };
 440
 441 struct parser_exec_state {
 442         struct intel_vgpu *vgpu;
 443         int ring_id;
 444
 445         int buf_type;
 446
 447         /* batch buffer address type */
 448         int buf_addr_type;
 449
 450         /* graphics memory address of ring buffer start */
 451         unsigned long ring_start;
 452         unsigned long ring_size;
 453         unsigned long ring_head;
 454         unsigned long ring_tail;
 455
 456         /* instruction graphics memory address */
 457         unsigned long ip_gma;
 458
 459         /* mapped va of the instr_gma */
 460         void *ip_va;
 461         void *rb_va;
 462
 463         void *ret_bb_va;
 464         /* next instruction when return from  batch buffer to ring buffer */
 465         unsigned long ret_ip_gma_ring;
 466
 467         /* next instruction when return from 2nd batch buffer to batch buffer */
 468         unsigned long ret_ip_gma_bb;
 469
 470         /* batch buffer address type (GTT or PPGTT)
 471          * used when ret from 2nd level batch buffer
 472          */
 473         int saved_buf_addr_type;
 474         bool is_ctx_wa;
 475
 476         struct cmd_info *info;
 477
 478         struct intel_vgpu_workload *workload;
 479 };
 480
 481 #define gmadr_dw_number(s)      \
 482         (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 483
 484 static unsigned long bypass_scan_mask = 0;
 485
 486 /* ring ALL, type = 0 */
 487 static struct sub_op_bits sub_op_mi[] = {
 488         {31, 29},
 489         {28, 23},
 490 };
 491
 492 static struct decode_info decode_info_mi = {
 493         "MI",
 494         OP_LEN_MI,
 495         ARRAY_SIZE(sub_op_mi),
 496         sub_op_mi,
 497 };
 498
 499 /* ring RCS, command type 2 */
 500 static struct sub_op_bits sub_op_2d[] = {
 501         {31, 29},
 502         {28, 22},
 503 };
 504
 505 static struct decode_info decode_info_2d = {
 506         "2D",
 507         OP_LEN_2D,
 508         ARRAY_SIZE(sub_op_2d),
 509         sub_op_2d,
 510 };
 511
 512 /* ring RCS, command type 3 */
 513 static struct sub_op_bits sub_op_3d_media[] = {
 514         {31, 29},
 515         {28, 27},
 516         {26, 24},
 517         {23, 16},
 518 };
 519
 520 static struct decode_info decode_info_3d_media = {
 521         "3D_Media",
 522         OP_LEN_3D_MEDIA,
 523         ARRAY_SIZE(sub_op_3d_media),
 524         sub_op_3d_media,
 525 };
 526
 527 /* ring VCS, command type 3 */
 528 static struct sub_op_bits sub_op_mfx_vc[] = {
 529         {31, 29},
 530         {28, 27},
 531         {26, 24},
 532         {23, 21},
 533         {20, 16},
 534 };
 535
 536 static struct decode_info decode_info_mfx_vc = {
 537         "MFX_VC",
 538         OP_LEN_MFX_VC,
 539         ARRAY_SIZE(sub_op_mfx_vc),
 540         sub_op_mfx_vc,
 541 };
 542
 543 /* ring VECS, command type 3 */
 544 static struct sub_op_bits sub_op_vebox[] = {
 545         {31, 29},
 546         {28, 27},
 547         {26, 24},
 548         {23, 21},
 549         {20, 16},
 550 };
 551
 552 static struct decode_info decode_info_vebox = {
 553         "VEBOX",
 554         OP_LEN_VEBOX,
 555         ARRAY_SIZE(sub_op_vebox),
 556         sub_op_vebox,
 557 };
 558
 559 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 560         [RCS] = {
 561                 &decode_info_mi,
 562                 NULL,
 563                 NULL,
 564                 &decode_info_3d_media,
 565                 NULL,
 566                 NULL,
 567                 NULL,
 568                 NULL,
 569         },
 570
 571         [VCS] = {
 572                 &decode_info_mi,
 573                 NULL,
 574                 NULL,
 575                 &decode_info_mfx_vc,
 576                 NULL,
 577                 NULL,
 578                 NULL,
 579                 NULL,
 580         },
 581
 582         [BCS] = {
 583                 &decode_info_mi,
 584                 NULL,
 585                 &decode_info_2d,
 586                 NULL,
 587                 NULL,
 588                 NULL,
 589                 NULL,
 590                 NULL,
 591         },
 592
 593         [VECS] = {
 594                 &decode_info_mi,
 595                 NULL,
 596                 NULL,
 597                 &decode_info_vebox,
 598                 NULL,
 599                 NULL,
 600                 NULL,
 601                 NULL,
 602         },
 603
 604         [VCS2] = {
 605                 &decode_info_mi,
 606                 NULL,
 607                 NULL,
 608                 &decode_info_mfx_vc,
 609                 NULL,
 610                 NULL,
 611                 NULL,
 612                 NULL,
 613         },
 614 };
 615
 616 static inline u32 get_opcode(u32 cmd, int ring_id)
 617 {
 618         struct decode_info *d_info;
 619
 620         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 621         if (d_info == NULL)
 622                 return INVALID_OP;
 623
 624         return cmd >> (32 - d_info->op_len);
 625 }
 626
 627 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
 628                 unsigned int opcode, int ring_id)
 629 {
 630         struct cmd_entry *e;
 631
 632         hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 633                 if ((opcode == e->info->opcode) &&
 634                                 (e->info->rings & (1 << ring_id)))
 635                         return e->info;
 636         }
 637         return NULL;
 638 }
 639
 640 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
 641                 u32 cmd, int ring_id)
 642 {
 643         u32 opcode;
 644
 645         opcode = get_opcode(cmd, ring_id);
 646         if (opcode == INVALID_OP)
 647                 return NULL;
 648
 649         return find_cmd_entry(gvt, opcode, ring_id);
 650 }
 651
 652 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 653 {
 654         return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 655 }
 656
 657 static inline void print_opcode(u32 cmd, int ring_id)
 658 {
 659         struct decode_info *d_info;
 660         int i;
 661
 662         d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
 663         if (d_info == NULL)
 664                 return;
 665
 666         gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 667                         cmd >> (32 - d_info->op_len), d_info->name);
 668
 669         for (i = 0; i < d_info->nr_sub_op; i++)
 670                 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 671                                         d_info->sub_op[i].low));
 672
 673         pr_err("\n");
 674 }
 675
 676 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 677 {
 678         return s->ip_va + (index << 2);
 679 }
 680
 681 static inline u32 cmd_val(struct parser_exec_state *s, int index)
 682 {
 683         return *cmd_ptr(s, index);
 684 }
 685
 686 static void parser_exec_state_dump(struct parser_exec_state *s)
 687 {
 688         int cnt = 0;
 689         int i;
 690
 691         gvt_dbg_cmd("  vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
 692                         " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
 693                         s->ring_id, s->ring_start, s->ring_start + s->ring_size,
 694                         s->ring_head, s->ring_tail);
 695
 696         gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 697                         s->buf_type == RING_BUFFER_INSTRUCTION ?
 698                         "RING_BUFFER" : "BATCH_BUFFER",
 699                         s->buf_addr_type == GTT_BUFFER ?
 700                         "GTT" : "PPGTT", s->ip_gma);
 701
 702         if (s->ip_va == NULL) {
 703                 gvt_dbg_cmd(" ip_va(NULL)");
 704                 return;
 705         }
 706
 707         gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 708                         s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 709                         cmd_val(s, 2), cmd_val(s, 3));
 710
 711         print_opcode(cmd_val(s, 0), s->ring_id);
 712
 713         s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 714
 715         while (cnt < 1024) {
 716                 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 717                 for (i = 0; i < 8; i++)
 718                         gvt_dbg_cmd("%08x ", cmd_val(s, i));
 719                 gvt_dbg_cmd("\n");
 720
 721                 s->ip_va += 8 * sizeof(u32);
 722                 cnt += 8;
 723         }
 724 }
 725
 726 static inline void update_ip_va(struct parser_exec_state *s)
 727 {
 728         unsigned long len = 0;
 729
 730         if (WARN_ON(s->ring_head == s->ring_tail))
 731                 return;
 732
 733         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 734                 unsigned long ring_top = s->ring_start + s->ring_size;
 735
 736                 if (s->ring_head > s->ring_tail) {
 737                         if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 738                                 len = (s->ip_gma - s->ring_head);
 739                         else if (s->ip_gma >= s->ring_start &&
 740                                         s->ip_gma <= s->ring_tail)
 741                                 len = (ring_top - s->ring_head) +
 742                                         (s->ip_gma - s->ring_start);
 743                 } else
 744                         len = (s->ip_gma - s->ring_head);
 745
 746                 s->ip_va = s->rb_va + len;
 747         } else {/* shadow batch buffer */
 748                 s->ip_va = s->ret_bb_va;
 749         }
 750 }
 751
 752 static inline int ip_gma_set(struct parser_exec_state *s,
 753                 unsigned long ip_gma)
 754 {
 755         WARN_ON(!IS_ALIGNED(ip_gma, 4));
 756
 757         s->ip_gma = ip_gma;
 758         update_ip_va(s);
 759         return 0;
 760 }
 761
 762 static inline int ip_gma_advance(struct parser_exec_state *s,
 763                 unsigned int dw_len)
 764 {
 765         s->ip_gma += (dw_len << 2);
 766
 767         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 768                 if (s->ip_gma >= s->ring_start + s->ring_size)
 769                         s->ip_gma -= s->ring_size;
 770                 update_ip_va(s);
 771         } else {
 772                 s->ip_va += (dw_len << 2);
 773         }
 774
 775         return 0;
 776 }
 777
 778 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
 779 {
 780         if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 781                 return info->len;
 782         else
 783                 return (cmd & ((1U << info->len) - 1)) + 2;
 784         return 0;
 785 }
 786
 787 static inline int cmd_length(struct parser_exec_state *s)
 788 {
 789         return get_cmd_length(s->info, cmd_val(s, 0));
 790 }
 791
 792 /* do not remove this, some platform may need clflush here */
 793 #define patch_value(s, addr, val) do { \
 794         *addr = val; \
 795 } while (0)
 796
 797 static bool is_shadowed_mmio(unsigned int offset)
 798 {
 799         bool ret = false;
 800
 801         if ((offset == 0x2168) || /*BB current head register UDW */
 802             (offset == 0x2140) || /*BB current header register */
 803             (offset == 0x211c) || /*second BB header register UDW */
 804             (offset == 0x2114)) { /*second BB header register UDW */
 805                 ret = true;
 806         }
 807         return ret;
 808 }
 809
 810 static inline bool is_force_nonpriv_mmio(unsigned int offset)
 811 {
 812         return (offset >= 0x24d0 && offset < 0x2500);
 813 }
 814
 815 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 816                 unsigned int offset, unsigned int index, char *cmd)
 817 {
 818         struct intel_gvt *gvt = s->vgpu->gvt;
 819         unsigned int data;
 820         u32 ring_base;
 821         u32 nopid;
 822         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
 823
 824         if (!strcmp(cmd, "lri"))
 825                 data = cmd_val(s, index + 1);
 826         else {
 827                 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
 828                         offset, cmd);
 829                 return -EINVAL;
 830         }
 831
 832         ring_base = dev_priv->engine[s->ring_id]->mmio_base;
 833         nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 834
 835         if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
 836                         data != nopid) {
 837                 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 838                         offset, data);
 839                 patch_value(s, cmd_ptr(s, index), nopid);
 840                 return 0;
 841         }
 842         return 0;
 843 }
 844
 845 static inline bool is_mocs_mmio(unsigned int offset)
 846 {
 847         return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 848                 ((offset >= 0xb020) && (offset <= 0xb0a0));
 849 }
 850
 851 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
 852                                 unsigned int offset, unsigned int index)
 853 {
 854         if (!is_mocs_mmio(offset))
 855                 return -EINVAL;
 856         vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
 857         return 0;
 858 }
 859
 860 static int cmd_reg_handler(struct parser_exec_state *s,
 861         unsigned int offset, unsigned int index, char *cmd)
 862 {
 863         struct intel_vgpu *vgpu = s->vgpu;
 864         struct intel_gvt *gvt = vgpu->gvt;
 865         u32 ctx_sr_ctl;
 866
 867         if (offset + 4 > gvt->device_info.mmio_size) {
 868                 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 869                                 cmd, offset);
 870                 return -EFAULT;
 871         }
 872
 873         if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
 874                 gvt_vgpu_err("%s access to non-render register (%x)\n",
 875                                 cmd, offset);
 876                 return 0;
 877         }
 878
 879         if (is_shadowed_mmio(offset)) {
 880                 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
 881                 return 0;
 882         }
 883
 884         if (is_mocs_mmio(offset) &&
 885             mocs_cmd_reg_handler(s, offset, index))
 886                 return -EINVAL;
 887
 888         if (is_force_nonpriv_mmio(offset) &&
 889                 force_nonpriv_reg_handler(s, offset, index, cmd))
 890                 return -EPERM;
 891
 892         if (offset == i915_mmio_reg_offset(DERRMR) ||
 893                 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 894                 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 895                 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 896         }
 897
 898         /* TODO
 899          * Right now only scan LRI command on KBL and in inhibit context.
 900          * It's good enough to support initializing mmio by lri command in
 901          * vgpu inhibit context on KBL.
 902          */
 903         if (IS_KABYLAKE(s->vgpu->gvt->dev_priv) &&
 904                         intel_gvt_mmio_is_in_ctx(gvt, offset) &&
 905                         !strncmp(cmd, "lri", 3)) {
 906                 intel_gvt_hypervisor_read_gpa(s->vgpu,
 907                         s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
 908                 /* check inhibit context */
 909                 if (ctx_sr_ctl & 1) {
 910                         u32 data = cmd_val(s, index + 1);
 911
 912                         if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
 913                                 intel_vgpu_mask_mmio_write(vgpu,
 914                                                         offset, &data, 4);
 915                         else
 916                                 vgpu_vreg(vgpu, offset) = data;
 917                 }
 918         }
 919
 920         /* TODO: Update the global mask if this MMIO is a masked-MMIO */
 921         intel_gvt_mmio_set_cmd_accessed(gvt, offset);
 922         return 0;
 923 }
 924
 925 #define cmd_reg(s, i) \
 926         (cmd_val(s, i) & GENMASK(22, 2))
 927
 928 #define cmd_reg_inhibit(s, i) \
 929         (cmd_val(s, i) & GENMASK(22, 18))
 930
 931 #define cmd_gma(s, i) \
 932         (cmd_val(s, i) & GENMASK(31, 2))
 933
 934 #define cmd_gma_hi(s, i) \
 935         (cmd_val(s, i) & GENMASK(15, 0))
 936
 937 static int cmd_handler_lri(struct parser_exec_state *s)
 938 {
 939         int i, ret = 0;
 940         int cmd_len = cmd_length(s);
 941         struct intel_gvt *gvt = s->vgpu->gvt;
 942
 943         for (i = 1; i < cmd_len; i += 2) {
 944                 if (IS_BROADWELL(gvt->dev_priv) &&
 945                                 (s->ring_id != RCS)) {
 946                         if (s->ring_id == BCS &&
 947                                         cmd_reg(s, i) ==
 948                                         i915_mmio_reg_offset(DERRMR))
 949                                 ret |= 0;
 950                         else
 951                                 ret |= (cmd_reg_inhibit(s, i)) ?
 952                                         -EBADRQC : 0;
 953                 }
 954                 if (ret)
 955                         break;
 956                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
 957                 if (ret)
 958                         break;
 959         }
 960         return ret;
 961 }
 962
 963 static int cmd_handler_lrr(struct parser_exec_state *s)
 964 {
 965         int i, ret = 0;
 966         int cmd_len = cmd_length(s);
 967
 968         for (i = 1; i < cmd_len; i += 2) {
 969                 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
 970                         ret |= ((cmd_reg_inhibit(s, i) ||
 971                                         (cmd_reg_inhibit(s, i + 1)))) ?
 972                                 -EBADRQC : 0;
 973                 if (ret)
 974                         break;
 975                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
 976                 if (ret)
 977                         break;
 978                 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
 979                 if (ret)
 980                         break;
 981         }
 982         return ret;
 983 }
 984
 985 static inline int cmd_address_audit(struct parser_exec_state *s,
 986                 unsigned long guest_gma, int op_size, bool index_mode);
 987
 988 static int cmd_handler_lrm(struct parser_exec_state *s)
 989 {
 990         struct intel_gvt *gvt = s->vgpu->gvt;
 991         int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 992         unsigned long gma;
 993         int i, ret = 0;
 994         int cmd_len = cmd_length(s);
 995
 996         for (i = 1; i < cmd_len;) {
 997                 if (IS_BROADWELL(gvt->dev_priv))
 998                         ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
 999                 if (ret)
1000                         break;
1001                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1002                 if (ret)
1003                         break;
1004                 if (cmd_val(s, 0) & (1 << 22)) {
1005                         gma = cmd_gma(s, i + 1);
1006                         if (gmadr_bytes == 8)
1007                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1008                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1009                         if (ret)
1010                                 break;
1011                 }
1012                 i += gmadr_dw_number(s) + 1;
1013         }
1014         return ret;
1015 }
1016
1017 static int cmd_handler_srm(struct parser_exec_state *s)
1018 {
1019         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1020         unsigned long gma;
1021         int i, ret = 0;
1022         int cmd_len = cmd_length(s);
1023
1024         for (i = 1; i < cmd_len;) {
1025                 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1026                 if (ret)
1027                         break;
1028                 if (cmd_val(s, 0) & (1 << 22)) {
1029                         gma = cmd_gma(s, i + 1);
1030                         if (gmadr_bytes == 8)
1031                                 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1032                         ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1033                         if (ret)
1034                                 break;
1035                 }
1036                 i += gmadr_dw_number(s) + 1;
1037         }
1038         return ret;
1039 }
1040
1041 struct cmd_interrupt_event {
1042         int pipe_control_notify;
1043         int mi_flush_dw;
1044         int mi_user_interrupt;
1045 };
1046
1047 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1048         [RCS] = {
1049                 .pipe_control_notify = RCS_PIPE_CONTROL,
1050                 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1051                 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1052         },
1053         [BCS] = {
1054                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1055                 .mi_flush_dw = BCS_MI_FLUSH_DW,
1056                 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1057         },
1058         [VCS] = {
1059                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1060                 .mi_flush_dw = VCS_MI_FLUSH_DW,
1061                 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1062         },
1063         [VCS2] = {
1064                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1065                 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1066                 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1067         },
1068         [VECS] = {
1069                 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1070                 .mi_flush_dw = VECS_MI_FLUSH_DW,
1071                 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1072         },
1073 };
1074
1075 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1076 {
1077         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1078         unsigned long gma;
1079         bool index_mode = false;
1080         unsigned int post_sync;
1081         int ret = 0;
1082
1083         post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1084
1085         /* LRI post sync */
1086         if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1087                 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1088         /* post sync */
1089         else if (post_sync) {
1090                 if (post_sync == 2)
1091                         ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1092                 else if (post_sync == 3)
1093                         ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1094                 else if (post_sync == 1) {
1095                         /* check ggtt*/
1096                         if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1097                                 gma = cmd_val(s, 2) & GENMASK(31, 3);
1098                                 if (gmadr_bytes == 8)
1099                                         gma |= (cmd_gma_hi(s, 3)) << 32;
1100                                 /* Store Data Index */
1101                                 if (cmd_val(s, 1) & (1 << 21))
1102                                         index_mode = true;
1103                                 ret |= cmd_address_audit(s, gma, sizeof(u64),
1104                                                 index_mode);
1105                         }
1106                 }
1107         }
1108
1109         if (ret)
1110                 return ret;
1111
1112         if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1113                 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1114                                 s->workload->pending_events);
1115         return 0;
1116 }
1117
1118 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1119 {
1120         set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1121                         s->workload->pending_events);
1122         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1123         return 0;
1124 }
1125
1126 static int cmd_advance_default(struct parser_exec_state *s)
1127 {
1128         return ip_gma_advance(s, cmd_length(s));
1129 }
1130
1131 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1132 {
1133         int ret;
1134
1135         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1136                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1137                 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1138                 s->buf_addr_type = s->saved_buf_addr_type;
1139         } else {
1140                 s->buf_type = RING_BUFFER_INSTRUCTION;
1141                 s->buf_addr_type = GTT_BUFFER;
1142                 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1143                         s->ret_ip_gma_ring -= s->ring_size;
1144                 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1145         }
1146         return ret;
1147 }
1148
1149 struct mi_display_flip_command_info {
1150         int pipe;
1151         int plane;
1152         int event;
1153         i915_reg_t stride_reg;
1154         i915_reg_t ctrl_reg;
1155         i915_reg_t surf_reg;
1156         u64 stride_val;
1157         u64 tile_val;
1158         u64 surf_val;
1159         bool async_flip;
1160 };
1161
1162 struct plane_code_mapping {
1163         int pipe;
1164         int plane;
1165         int event;
1166 };
1167
1168 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1169                 struct mi_display_flip_command_info *info)
1170 {
1171         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1172         struct plane_code_mapping gen8_plane_code[] = {
1173                 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1174                 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1175                 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1176                 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1177                 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1178                 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1179         };
1180         u32 dword0, dword1, dword2;
1181         u32 v;
1182
1183         dword0 = cmd_val(s, 0);
1184         dword1 = cmd_val(s, 1);
1185         dword2 = cmd_val(s, 2);
1186
1187         v = (dword0 & GENMASK(21, 19)) >> 19;
1188         if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1189                 return -EBADRQC;
1190
1191         info->pipe = gen8_plane_code[v].pipe;
1192         info->plane = gen8_plane_code[v].plane;
1193         info->event = gen8_plane_code[v].event;
1194         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1195         info->tile_val = (dword1 & 0x1);
1196         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1197         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1198
1199         if (info->plane == PLANE_A) {
1200                 info->ctrl_reg = DSPCNTR(info->pipe);
1201                 info->stride_reg = DSPSTRIDE(info->pipe);
1202                 info->surf_reg = DSPSURF(info->pipe);
1203         } else if (info->plane == PLANE_B) {
1204                 info->ctrl_reg = SPRCTL(info->pipe);
1205                 info->stride_reg = SPRSTRIDE(info->pipe);
1206                 info->surf_reg = SPRSURF(info->pipe);
1207         } else {
1208                 WARN_ON(1);
1209                 return -EBADRQC;
1210         }
1211         return 0;
1212 }
1213
1214 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1215                 struct mi_display_flip_command_info *info)
1216 {
1217         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1218         struct intel_vgpu *vgpu = s->vgpu;
1219         u32 dword0 = cmd_val(s, 0);
1220         u32 dword1 = cmd_val(s, 1);
1221         u32 dword2 = cmd_val(s, 2);
1222         u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1223
1224         info->plane = PRIMARY_PLANE;
1225
1226         switch (plane) {
1227         case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1228                 info->pipe = PIPE_A;
1229                 info->event = PRIMARY_A_FLIP_DONE;
1230                 break;
1231         case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1232                 info->pipe = PIPE_B;
1233                 info->event = PRIMARY_B_FLIP_DONE;
1234                 break;
1235         case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1236                 info->pipe = PIPE_C;
1237                 info->event = PRIMARY_C_FLIP_DONE;
1238                 break;
1239
1240         case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1241                 info->pipe = PIPE_A;
1242                 info->event = SPRITE_A_FLIP_DONE;
1243                 info->plane = SPRITE_PLANE;
1244                 break;
1245         case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1246                 info->pipe = PIPE_B;
1247                 info->event = SPRITE_B_FLIP_DONE;
1248                 info->plane = SPRITE_PLANE;
1249                 break;
1250         case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1251                 info->pipe = PIPE_C;
1252                 info->event = SPRITE_C_FLIP_DONE;
1253                 info->plane = SPRITE_PLANE;
1254                 break;
1255
1256         default:
1257                 gvt_vgpu_err("unknown plane code %d\n", plane);
1258                 return -EBADRQC;
1259         }
1260
1261         info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1262         info->tile_val = (dword1 & GENMASK(2, 0));
1263         info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1264         info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1265
1266         info->ctrl_reg = DSPCNTR(info->pipe);
1267         info->stride_reg = DSPSTRIDE(info->pipe);
1268         info->surf_reg = DSPSURF(info->pipe);
1269
1270         return 0;
1271 }
1272
1273 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1274                 struct mi_display_flip_command_info *info)
1275 {
1276         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1277         u32 stride, tile;
1278
1279         if (!info->async_flip)
1280                 return 0;
1281
1282         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1283                 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1284                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1285                                 GENMASK(12, 10)) >> 10;
1286         } else {
1287                 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1288                                 GENMASK(15, 6)) >> 6;
1289                 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1290         }
1291
1292         if (stride != info->stride_val)
1293                 gvt_dbg_cmd("cannot change stride during async flip\n");
1294
1295         if (tile != info->tile_val)
1296                 gvt_dbg_cmd("cannot change tile during async flip\n");
1297
1298         return 0;
1299 }
1300
1301 static int gen8_update_plane_mmio_from_mi_display_flip(
1302                 struct parser_exec_state *s,
1303                 struct mi_display_flip_command_info *info)
1304 {
1305         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1306         struct intel_vgpu *vgpu = s->vgpu;
1307
1308         set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1309                       info->surf_val << 12);
1310         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1311                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1312                               info->stride_val);
1313                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1314                               info->tile_val << 10);
1315         } else {
1316                 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1317                               info->stride_val << 6);
1318                 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1319                               info->tile_val << 10);
1320         }
1321
1322         vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1323         intel_vgpu_trigger_virtual_event(vgpu, info->event);
1324         return 0;
1325 }
1326
1327 static int decode_mi_display_flip(struct parser_exec_state *s,
1328                 struct mi_display_flip_command_info *info)
1329 {
1330         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1331
1332         if (IS_BROADWELL(dev_priv))
1333                 return gen8_decode_mi_display_flip(s, info);
1334         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1335                 return skl_decode_mi_display_flip(s, info);
1336
1337         return -ENODEV;
1338 }
1339
1340 static int check_mi_display_flip(struct parser_exec_state *s,
1341                 struct mi_display_flip_command_info *info)
1342 {
1343         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1344
1345         if (IS_BROADWELL(dev_priv)
1346                 || IS_SKYLAKE(dev_priv)
1347                 || IS_KABYLAKE(dev_priv))
1348                 return gen8_check_mi_display_flip(s, info);
1349         return -ENODEV;
1350 }
1351
1352 static int update_plane_mmio_from_mi_display_flip(
1353                 struct parser_exec_state *s,
1354                 struct mi_display_flip_command_info *info)
1355 {
1356         struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1357
1358         if (IS_BROADWELL(dev_priv)
1359                 || IS_SKYLAKE(dev_priv)
1360                 || IS_KABYLAKE(dev_priv))
1361                 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1362         return -ENODEV;
1363 }
1364
1365 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1366 {
1367         struct mi_display_flip_command_info info;
1368         struct intel_vgpu *vgpu = s->vgpu;
1369         int ret;
1370         int i;
1371         int len = cmd_length(s);
1372
1373         ret = decode_mi_display_flip(s, &info);
1374         if (ret) {
1375                 gvt_vgpu_err("fail to decode MI display flip command\n");
1376                 return ret;
1377         }
1378
1379         ret = check_mi_display_flip(s, &info);
1380         if (ret) {
1381                 gvt_vgpu_err("invalid MI display flip command\n");
1382                 return ret;
1383         }
1384
1385         ret = update_plane_mmio_from_mi_display_flip(s, &info);
1386         if (ret) {
1387                 gvt_vgpu_err("fail to update plane mmio\n");
1388                 return ret;
1389         }
1390
1391         for (i = 0; i < len; i++)
1392                 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1393         return 0;
1394 }
1395
1396 static bool is_wait_for_flip_pending(u32 cmd)
1397 {
1398         return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1399                         MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1400                         MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1401                         MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1402                         MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1403                         MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1404 }
1405
1406 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1407 {
1408         u32 cmd = cmd_val(s, 0);
1409
1410         if (!is_wait_for_flip_pending(cmd))
1411                 return 0;
1412
1413         patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1414         return 0;
1415 }
1416
1417 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1418 {
1419         unsigned long addr;
1420         unsigned long gma_high, gma_low;
1421         struct intel_vgpu *vgpu = s->vgpu;
1422         int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1423
1424         if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1425                 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1426                 return INTEL_GVT_INVALID_ADDR;
1427         }
1428
1429         gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1430         if (gmadr_bytes == 4) {
1431                 addr = gma_low;
1432         } else {
1433                 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1434                 addr = (((unsigned long)gma_high) << 32) | gma_low;
1435         }
1436         return addr;
1437 }
1438
1439 static inline int cmd_address_audit(struct parser_exec_state *s,
1440                 unsigned long guest_gma, int op_size, bool index_mode)
1441 {
1442         struct intel_vgpu *vgpu = s->vgpu;
1443         u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1444         int i;
1445         int ret;
1446
1447         if (op_size > max_surface_size) {
1448                 gvt_vgpu_err("command address audit fail name %s\n",
1449                         s->info->name);
1450                 return -EFAULT;
1451         }
1452
1453         if (index_mode) {
1454                 if (guest_gma >= I915_GTT_PAGE_SIZE / sizeof(u64)) {
1455                         ret = -EFAULT;
1456                         goto err;
1457                 }
1458         } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1459                 ret = -EFAULT;
1460                 goto err;
1461         }
1462
1463         return 0;
1464
1465 err:
1466         gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1467                         s->info->name, guest_gma, op_size);
1468
1469         pr_err("cmd dump: ");
1470         for (i = 0; i < cmd_length(s); i++) {
1471                 if (!(i % 4))
1472                         pr_err("\n%08x ", cmd_val(s, i));
1473                 else
1474                         pr_err("%08x ", cmd_val(s, i));
1475         }
1476         pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1477                         vgpu->id,
1478                         vgpu_aperture_gmadr_base(vgpu),
1479                         vgpu_aperture_gmadr_end(vgpu),
1480                         vgpu_hidden_gmadr_base(vgpu),
1481                         vgpu_hidden_gmadr_end(vgpu));
1482         return ret;
1483 }
1484
1485 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1486 {
1487         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1488         int op_size = (cmd_length(s) - 3) * sizeof(u32);
1489         int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1490         unsigned long gma, gma_low, gma_high;
1491         int ret = 0;
1492
1493         /* check ppggt */
1494         if (!(cmd_val(s, 0) & (1 << 22)))
1495                 return 0;
1496
1497         gma = cmd_val(s, 2) & GENMASK(31, 2);
1498
1499         if (gmadr_bytes == 8) {
1500                 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1501                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1502                 gma = (gma_high << 32) | gma_low;
1503                 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1504         }
1505         ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1506         return ret;
1507 }
1508
1509 static inline int unexpected_cmd(struct parser_exec_state *s)
1510 {
1511         struct intel_vgpu *vgpu = s->vgpu;
1512
1513         gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1514
1515         return -EBADRQC;
1516 }
1517
1518 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1519 {
1520         return unexpected_cmd(s);
1521 }
1522
1523 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1524 {
1525         return unexpected_cmd(s);
1526 }
1527
1528 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1529 {
1530         return unexpected_cmd(s);
1531 }
1532
1533 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1534 {
1535         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1536         int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1537                         sizeof(u32);
1538         unsigned long gma, gma_high;
1539         int ret = 0;
1540
1541         if (!(cmd_val(s, 0) & (1 << 22)))
1542                 return ret;
1543
1544         gma = cmd_val(s, 1) & GENMASK(31, 2);
1545         if (gmadr_bytes == 8) {
1546                 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1547                 gma = (gma_high << 32) | gma;
1548         }
1549         ret = cmd_address_audit(s, gma, op_size, false);
1550         return ret;
1551 }
1552
1553 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1554 {
1555         return unexpected_cmd(s);
1556 }
1557
1558 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1559 {
1560         return unexpected_cmd(s);
1561 }
1562
1563 static int cmd_handler_mi_conditional_batch_buffer_end(
1564                 struct parser_exec_state *s)
1565 {
1566         return unexpected_cmd(s);
1567 }
1568
1569 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1570 {
1571         return unexpected_cmd(s);
1572 }
1573
1574 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1575 {
1576         int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1577         unsigned long gma;
1578         bool index_mode = false;
1579         int ret = 0;
1580
1581         /* Check post-sync and ppgtt bit */
1582         if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1583                 gma = cmd_val(s, 1) & GENMASK(31, 3);
1584                 if (gmadr_bytes == 8)
1585                         gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1586                 /* Store Data Index */
1587                 if (cmd_val(s, 0) & (1 << 21))
1588                         index_mode = true;
1589                 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1590         }
1591         /* Check notify bit */
1592         if ((cmd_val(s, 0) & (1 << 8)))
1593                 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1594                                 s->workload->pending_events);
1595         return ret;
1596 }
1597
1598 static void addr_type_update_snb(struct parser_exec_state *s)
1599 {
1600         if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1601                         (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1602                 s->buf_addr_type = PPGTT_BUFFER;
1603         }
1604 }
1605
1606
1607 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1608                 unsigned long gma, unsigned long end_gma, void *va)
1609 {
1610         unsigned long copy_len, offset;
1611         unsigned long len = 0;
1612         unsigned long gpa;
1613
1614         while (gma != end_gma) {
1615                 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1616                 if (gpa == INTEL_GVT_INVALID_ADDR) {
1617                         gvt_vgpu_err("invalid gma address: %lx\n", gma);
1618                         return -EFAULT;
1619                 }
1620
1621                 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1622
1623                 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1624                         I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1625
1626                 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1627
1628                 len += copy_len;
1629                 gma += copy_len;
1630         }
1631         return len;
1632 }
1633
1634
1635 /*
1636  * Check whether a batch buffer needs to be scanned. Currently
1637  * the only criteria is based on privilege.
1638  */
1639 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1640 {
1641         struct intel_gvt *gvt = s->vgpu->gvt;
1642
1643         if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
1644                 || IS_KABYLAKE(gvt->dev_priv)) {
1645                 /* BDW decides privilege based on address space */
1646                 if (cmd_val(s, 0) & (1 << 8) &&
1647                         !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1648                         return 0;
1649         }
1650         return 1;
1651 }
1652
1653 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1654 {
1655         unsigned long gma = 0;
1656         struct cmd_info *info;
1657         uint32_t cmd_len = 0;
1658         bool bb_end = false;
1659         struct intel_vgpu *vgpu = s->vgpu;
1660         u32 cmd;
1661         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1662                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1663
1664         *bb_size = 0;
1665
1666         /* get the start gm address of the batch buffer */
1667         gma = get_gma_bb_from_cmd(s, 1);
1668         if (gma == INTEL_GVT_INVALID_ADDR)
1669                 return -EFAULT;
1670
1671         cmd = cmd_val(s, 0);
1672         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1673         if (info == NULL) {
1674                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1675                                 cmd, get_opcode(cmd, s->ring_id),
1676                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1677                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1678                 return -EBADRQC;
1679         }
1680         do {
1681                 if (copy_gma_to_hva(s->vgpu, mm,
1682                                 gma, gma + 4, &cmd) < 0)
1683                         return -EFAULT;
1684                 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1685                 if (info == NULL) {
1686                         gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1687                                 cmd, get_opcode(cmd, s->ring_id),
1688                                 (s->buf_addr_type == PPGTT_BUFFER) ?
1689                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
1690                         return -EBADRQC;
1691                 }
1692
1693                 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1694                         bb_end = true;
1695                 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1696                         if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1697                                 /* chained batch buffer */
1698                                 bb_end = true;
1699                 }
1700                 cmd_len = get_cmd_length(info, cmd) << 2;
1701                 *bb_size += cmd_len;
1702                 gma += cmd_len;
1703         } while (!bb_end);
1704
1705         return 0;
1706 }
1707
1708 static int perform_bb_shadow(struct parser_exec_state *s)
1709 {
1710         struct intel_vgpu *vgpu = s->vgpu;
1711         struct intel_vgpu_shadow_bb *bb;
1712         unsigned long gma = 0;
1713         unsigned long bb_size;
1714         int ret = 0;
1715         struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1716                 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1717         unsigned long gma_start_offset = 0;
1718
1719         /* get the start gm address of the batch buffer */
1720         gma = get_gma_bb_from_cmd(s, 1);
1721         if (gma == INTEL_GVT_INVALID_ADDR)
1722                 return -EFAULT;
1723
1724         ret = find_bb_size(s, &bb_size);
1725         if (ret)
1726                 return ret;
1727
1728         bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1729         if (!bb)
1730                 return -ENOMEM;
1731
1732         bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1733
1734         /* the gma_start_offset stores the batch buffer's start gma's
1735          * offset relative to page boundary. so for non-privileged batch
1736          * buffer, the shadowed gem object holds exactly the same page
1737          * layout as original gem object. This is for the convience of
1738          * replacing the whole non-privilged batch buffer page to this
1739          * shadowed one in PPGTT at the same gma address. (this replacing
1740          * action is not implemented yet now, but may be necessary in
1741          * future).
1742          * for prileged batch buffer, we just change start gma address to
1743          * that of shadowed page.
1744          */
1745         if (bb->ppgtt)
1746                 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1747
1748         bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1749                          roundup(bb_size + gma_start_offset, PAGE_SIZE));
1750         if (IS_ERR(bb->obj)) {
1751                 ret = PTR_ERR(bb->obj);
1752                 goto err_free_bb;
1753         }
1754
1755         ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1756         if (ret)
1757                 goto err_free_obj;
1758
1759         bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1760         if (IS_ERR(bb->va)) {
1761                 ret = PTR_ERR(bb->va);
1762                 goto err_finish_shmem_access;
1763         }
1764
1765         if (bb->clflush & CLFLUSH_BEFORE) {
1766                 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1767                 bb->clflush &= ~CLFLUSH_BEFORE;
1768         }
1769
1770         ret = copy_gma_to_hva(s->vgpu, mm,
1771                               gma, gma + bb_size,
1772                               bb->va + gma_start_offset);
1773         if (ret < 0) {
1774                 gvt_vgpu_err("fail to copy guest ring buffer\n");
1775                 ret = -EFAULT;
1776                 goto err_unmap;
1777         }
1778
1779         INIT_LIST_HEAD(&bb->list);
1780         list_add(&bb->list, &s->workload->shadow_bb);
1781
1782         bb->accessing = true;
1783         bb->bb_start_cmd_va = s->ip_va;
1784
1785         if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1786                 bb->bb_offset = s->ip_va - s->rb_va;
1787         else
1788                 bb->bb_offset = 0;
1789
1790         /*
1791          * ip_va saves the virtual address of the shadow batch buffer, while
1792          * ip_gma saves the graphics address of the original batch buffer.
1793          * As the shadow batch buffer is just a copy from the originial one,
1794          * it should be right to use shadow batch buffer'va and original batch
1795          * buffer's gma in pair. After all, we don't want to pin the shadow
1796          * buffer here (too early).
1797          */
1798         s->ip_va = bb->va + gma_start_offset;
1799         s->ip_gma = gma;
1800         return 0;
1801 err_unmap:
1802         i915_gem_object_unpin_map(bb->obj);
1803 err_finish_shmem_access:
1804         i915_gem_obj_finish_shmem_access(bb->obj);
1805 err_free_obj:
1806         i915_gem_object_put(bb->obj);
1807 err_free_bb:
1808         kfree(bb);
1809         return ret;
1810 }
1811
1812 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1813 {
1814         bool second_level;
1815         int ret = 0;
1816         struct intel_vgpu *vgpu = s->vgpu;
1817
1818         if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1819                 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1820                 return -EFAULT;
1821         }
1822
1823         second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1824         if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1825                 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1826                 return -EFAULT;
1827         }
1828
1829         s->saved_buf_addr_type = s->buf_addr_type;
1830         addr_type_update_snb(s);
1831         if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1832                 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1833                 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1834         } else if (second_level) {
1835                 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1836                 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1837                 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1838         }
1839
1840         if (batch_buffer_needs_scan(s)) {
1841                 ret = perform_bb_shadow(s);
1842                 if (ret < 0)
1843                         gvt_vgpu_err("invalid shadow batch buffer\n");
1844         } else {
1845                 /* emulate a batch buffer end to do return right */
1846                 ret = cmd_handler_mi_batch_buffer_end(s);
1847                 if (ret < 0)
1848                         return ret;
1849         }
1850         return ret;
1851 }
1852
1853 static struct cmd_info cmd_info[] = {
1854         {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1855
1856         {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1857                 0, 1, NULL},
1858
1859         {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1860                 0, 1, cmd_handler_mi_user_interrupt},
1861
1862         {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1863                 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1864
1865         {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1866
1867         {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1868                 NULL},
1869
1870         {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1871                 NULL},
1872
1873         {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1874                 NULL},
1875
1876         {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1877                 NULL},
1878
1879         {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1880                 D_ALL, 0, 1, NULL},
1881
1882         {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1883                 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1884                 cmd_handler_mi_batch_buffer_end},
1885
1886         {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1887                 0, 1, NULL},
1888
1889         {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1890                 NULL},
1891
1892         {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1893                 D_ALL, 0, 1, NULL},
1894
1895         {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1896                 NULL},
1897
1898         {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1899                 NULL},
1900
1901         {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1902                 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1903
1904         {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1905                 0, 8, NULL},
1906
1907         {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1908
1909         {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1910
1911         {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1912                 D_BDW_PLUS, 0, 8, NULL},
1913
1914         {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1915                 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1916
1917         {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1918                 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1919
1920         {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1921                 0, 8, cmd_handler_mi_store_data_index},
1922
1923         {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1924                 D_ALL, 0, 8, cmd_handler_lri},
1925
1926         {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1927                 cmd_handler_mi_update_gtt},
1928
1929         {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1930                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1931
1932         {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1933                 cmd_handler_mi_flush_dw},
1934
1935         {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1936                 10, cmd_handler_mi_clflush},
1937
1938         {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1939                 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1940
1941         {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1942                 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1943
1944         {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1945                 D_ALL, 0, 8, cmd_handler_lrr},
1946
1947         {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1948                 D_ALL, 0, 8, NULL},
1949
1950         {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1951                 ADDR_FIX_1(2), 8, NULL},
1952
1953         {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1954                 ADDR_FIX_1(2), 8, NULL},
1955
1956         {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1957                 8, cmd_handler_mi_op_2e},
1958
1959         {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1960                 8, cmd_handler_mi_op_2f},
1961
1962         {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1963                 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1964                 cmd_handler_mi_batch_buffer_start},
1965
1966         {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1967                 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1968                 cmd_handler_mi_conditional_batch_buffer_end},
1969
1970         {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1971                 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1972
1973         {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1974                 ADDR_FIX_2(4, 7), 8, NULL},
1975
1976         {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1977                 0, 8, NULL},
1978
1979         {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1980                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1981
1982         {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1983
1984         {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1985                 0, 8, NULL},
1986
1987         {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1988                 ADDR_FIX_1(3), 8, NULL},
1989
1990         {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1991                 D_ALL, 0, 8, NULL},
1992
1993         {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1994                 ADDR_FIX_1(4), 8, NULL},
1995
1996         {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1997                 ADDR_FIX_2(4, 5), 8, NULL},
1998
1999         {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2000                 ADDR_FIX_1(4), 8, NULL},
2001
2002         {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2003                 ADDR_FIX_2(4, 7), 8, NULL},
2004
2005         {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2006                 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2007
2008         {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2009
2010         {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2011                 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2012
2013         {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2014                 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2015
2016         {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2017                 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2018                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2019
2020         {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2021                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2022
2023         {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2024                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2025
2026         {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2027                 D_ALL, ADDR_FIX_1(4), 8, NULL},
2028
2029         {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2030                 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2031
2032         {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2033                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2034
2035         {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2036                 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2037                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2038
2039         {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2040                 ADDR_FIX_2(4, 5), 8, NULL},
2041
2042         {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2043                 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2044
2045         {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2046                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2047                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2048
2049         {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2050                 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2051                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2052
2053         {"3DSTATE_BLEND_STATE_POINTERS",
2054                 OP_3DSTATE_BLEND_STATE_POINTERS,
2055                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2056
2057         {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2058                 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2059                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2060
2061         {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2062                 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2063                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2064
2065         {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2066                 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2067                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2068
2069         {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2070                 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2071                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2072
2073         {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2074                 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2075                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2076
2077         {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2078                 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2079                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2080
2081         {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2082                 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2083                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2084
2085         {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2086                 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2087                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2088
2089         {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2090                 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2091                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2092
2093         {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2094                 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2095                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2096
2097         {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2098                 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2099                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2100
2101         {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2102                 0, 8, NULL},
2103
2104         {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2105                 0, 8, NULL},
2106
2107         {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2108                 0, 8, NULL},
2109
2110         {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2111                 0, 8, NULL},
2112
2113         {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2114                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2115
2116         {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2117                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2118
2119         {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2120                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2121
2122         {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2123                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2124
2125         {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2126                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2127
2128         {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2129                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2130
2131         {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2132                 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2133
2134         {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2135                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2136
2137         {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2138                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2139
2140         {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2141                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2142
2143         {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2144                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2145
2146         {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2147                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2148
2149         {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2150                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2151
2152         {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2153                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2154
2155         {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2156                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2157
2158         {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2159                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2160
2161         {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2162                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2163
2164         {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2165                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2166
2167         {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2168                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2169
2170         {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2171                 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2172
2173         {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2174                 D_BDW_PLUS, 0, 8, NULL},
2175
2176         {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2177                 NULL},
2178
2179         {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2180                 D_BDW_PLUS, 0, 8, NULL},
2181
2182         {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2183                 D_BDW_PLUS, 0, 8, NULL},
2184
2185         {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2186                 8, NULL},
2187
2188         {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2189                 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2190
2191         {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2192                 8, NULL},
2193
2194         {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2195                 NULL},
2196
2197         {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2198                 NULL},
2199
2200         {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2201                 NULL},
2202
2203         {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2204                 D_BDW_PLUS, 0, 8, NULL},
2205
2206         {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2207                 R_RCS, D_ALL, 0, 8, NULL},
2208
2209         {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2210                 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2211
2212         {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2213                 R_RCS, D_ALL, 0, 1, NULL},
2214
2215         {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2216
2217         {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2218                 R_RCS, D_ALL, 0, 8, NULL},
2219
2220         {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2221                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2222
2223         {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2224
2225         {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2226
2227         {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2228
2229         {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2230                 D_BDW_PLUS, 0, 8, NULL},
2231
2232         {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2233                 D_BDW_PLUS, 0, 8, NULL},
2234
2235         {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2236                 D_ALL, 0, 8, NULL},
2237
2238         {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2239                 D_BDW_PLUS, 0, 8, NULL},
2240
2241         {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2242                 D_BDW_PLUS, 0, 8, NULL},
2243
2244         {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246         {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2247
2248         {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2249
2250         {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2251                 D_ALL, 0, 8, NULL},
2252
2253         {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2254
2255         {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2256
2257         {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2258                 R_RCS, D_ALL, 0, 8, NULL},
2259
2260         {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2261                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2262
2263         {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2264                 0, 8, NULL},
2265
2266         {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2267                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2268
2269         {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2270                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2271
2272         {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2273                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2274
2275         {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2276                 D_ALL, 0, 8, NULL},
2277
2278         {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2279                 D_ALL, 0, 8, NULL},
2280
2281         {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2282                 D_ALL, 0, 8, NULL},
2283
2284         {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2285                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2286
2287         {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2288                 D_BDW_PLUS, 0, 8, NULL},
2289
2290         {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2291                 D_ALL, ADDR_FIX_1(2), 8, NULL},
2292
2293         {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2294                 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2295
2296         {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2297                 R_RCS, D_ALL, 0, 8, NULL},
2298
2299         {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2300                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2301
2302         {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2303                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2304
2305         {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2306                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2307
2308         {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2309                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2310
2311         {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2312                 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2313
2314         {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2315                 R_RCS, D_ALL, 0, 8, NULL},
2316
2317         {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2318                 D_ALL, 0, 9, NULL},
2319
2320         {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2321                 ADDR_FIX_2(2, 4), 8, NULL},
2322
2323         {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2324                 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2325                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2326
2327         {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2328                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2329
2330         {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2331                 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2332                 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2333
2334         {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2335                 D_BDW_PLUS, 0, 8, NULL},
2336
2337         {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2338                 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2339
2340         {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2341
2342         {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2343                 1, NULL},
2344
2345         {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2346                 ADDR_FIX_1(1), 8, NULL},
2347
2348         {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349
2350         {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2351                 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2352
2353         {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2354                 ADDR_FIX_1(1), 8, NULL},
2355
2356         {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2357
2358         {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2359
2360         {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2361                 0, 8, NULL},
2362
2363         {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2364                 D_SKL_PLUS, 0, 8, NULL},
2365
2366         {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2367                 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2368
2369         {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2370                 0, 16, NULL},
2371
2372         {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2373                 0, 16, NULL},
2374
2375         {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2376
2377         {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2378                 0, 16, NULL},
2379
2380         {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2381                 0, 16, NULL},
2382
2383         {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2384                 0, 16, NULL},
2385
2386         {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2387                 0, 8, NULL},
2388
2389         {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2390                 NULL},
2391
2392         {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2393                 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2394
2395         {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2396                 R_VCS, D_ALL, 0, 12, NULL},
2397
2398         {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2399                 R_VCS, D_ALL, 0, 12, NULL},
2400
2401         {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2402                 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2403
2404         {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2405                 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2406
2407         {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2408                 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2409
2410         {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2411
2412         {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2413                 R_VCS, D_ALL, 0, 12, NULL},
2414
2415         {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2416                 R_VCS, D_ALL, 0, 12, NULL},
2417
2418         {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2419                 R_VCS, D_ALL, 0, 12, NULL},
2420
2421         {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2422                 R_VCS, D_ALL, 0, 12, NULL},
2423
2424         {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2425                 R_VCS, D_ALL, 0, 12, NULL},
2426
2427         {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2428                 R_VCS, D_ALL, 0, 12, NULL},
2429
2430         {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2431                 R_VCS, D_ALL, 0, 6, NULL},
2432
2433         {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2434                 R_VCS, D_ALL, 0, 12, NULL},
2435
2436         {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2437                 R_VCS, D_ALL, 0, 12, NULL},
2438
2439         {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2440                 R_VCS, D_ALL, 0, 12, NULL},
2441
2442         {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2443                 R_VCS, D_ALL, 0, 12, NULL},
2444
2445         {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2446                 R_VCS, D_ALL, 0, 12, NULL},
2447
2448         {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2449                 R_VCS, D_ALL, 0, 12, NULL},
2450
2451         {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2452                 R_VCS, D_ALL, 0, 12, NULL},
2453         {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2454                 R_VCS, D_ALL, 0, 12, NULL},
2455
2456         {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2457                 R_VCS, D_ALL, 0, 12, NULL},
2458
2459         {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2460                 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2461
2462         {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2463                 R_VCS, D_ALL, 0, 12, NULL},
2464
2465         {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2466                 R_VCS, D_ALL, 0, 12, NULL},
2467
2468         {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2469                 R_VCS, D_ALL, 0, 12, NULL},
2470
2471         {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2472                 R_VCS, D_ALL, 0, 12, NULL},
2473
2474         {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2475                 R_VCS, D_ALL, 0, 12, NULL},
2476
2477         {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2478                 R_VCS, D_ALL, 0, 12, NULL},
2479
2480         {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2481                 R_VCS, D_ALL, 0, 12, NULL},
2482
2483         {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2484                 R_VCS, D_ALL, 0, 12, NULL},
2485
2486         {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2487                 R_VCS, D_ALL, 0, 12, NULL},
2488
2489         {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2490                 R_VCS, D_ALL, 0, 12, NULL},
2491
2492         {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2493                 R_VCS, D_ALL, 0, 12, NULL},
2494
2495         {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2496                 0, 16, NULL},
2497
2498         {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2499
2500         {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2501
2502         {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2503                 R_VCS, D_ALL, 0, 12, NULL},
2504
2505         {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2506                 R_VCS, D_ALL, 0, 12, NULL},
2507
2508         {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2509                 R_VCS, D_ALL, 0, 12, NULL},
2510
2511         {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2512
2513         {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2514                 0, 12, NULL},
2515
2516         {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2517                 0, 20, NULL},
2518 };
2519
2520 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2521 {
2522         hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2523 }
2524
2525 /* call the cmd handler, and advance ip */
2526 static int cmd_parser_exec(struct parser_exec_state *s)
2527 {
2528         struct intel_vgpu *vgpu = s->vgpu;
2529         struct cmd_info *info;
2530         u32 cmd;
2531         int ret = 0;
2532
2533         cmd = cmd_val(s, 0);
2534
2535         info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2536         if (info == NULL) {
2537                 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2538                                 cmd, get_opcode(cmd, s->ring_id),
2539                                 (s->buf_addr_type == PPGTT_BUFFER) ?
2540                                 "ppgtt" : "ggtt", s->ring_id, s->workload);
2541                 return -EBADRQC;
2542         }
2543
2544         s->info = info;
2545
2546         trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2547                           cmd_length(s), s->buf_type, s->buf_addr_type,
2548                           s->workload, info->name);
2549
2550         if (info->handler) {
2551                 ret = info->handler(s);
2552                 if (ret < 0) {
2553                         gvt_vgpu_err("%s handler error\n", info->name);
2554                         return ret;
2555                 }
2556         }
2557
2558         if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2559                 ret = cmd_advance_default(s);
2560                 if (ret) {
2561                         gvt_vgpu_err("%s IP advance error\n", info->name);
2562                         return ret;
2563                 }
2564         }
2565         return 0;
2566 }
2567
2568 static inline bool gma_out_of_range(unsigned long gma,
2569                 unsigned long gma_head, unsigned int gma_tail)
2570 {
2571         if (gma_tail >= gma_head)
2572                 return (gma < gma_head) || (gma > gma_tail);
2573         else
2574                 return (gma > gma_tail) && (gma < gma_head);
2575 }
2576
2577 /* Keep the consistent return type, e.g EBADRQC for unknown
2578  * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2579  * works as the input of VM healthy status.
2580  */
2581 static int command_scan(struct parser_exec_state *s,
2582                 unsigned long rb_head, unsigned long rb_tail,
2583                 unsigned long rb_start, unsigned long rb_len)
2584 {
2585
2586         unsigned long gma_head, gma_tail, gma_bottom;
2587         int ret = 0;
2588         struct intel_vgpu *vgpu = s->vgpu;
2589
2590         gma_head = rb_start + rb_head;
2591         gma_tail = rb_start + rb_tail;
2592         gma_bottom = rb_start +  rb_len;
2593
2594         while (s->ip_gma != gma_tail) {
2595                 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2596                         if (!(s->ip_gma >= rb_start) ||
2597                                 !(s->ip_gma < gma_bottom)) {
2598                                 gvt_vgpu_err("ip_gma %lx out of ring scope."
2599                                         "(base:0x%lx, bottom: 0x%lx)\n",
2600                                         s->ip_gma, rb_start,
2601                                         gma_bottom);
2602                                 parser_exec_state_dump(s);
2603                                 return -EFAULT;
2604                         }
2605                         if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2606                                 gvt_vgpu_err("ip_gma %lx out of range."
2607                                         "base 0x%lx head 0x%lx tail 0x%lx\n",
2608                                         s->ip_gma, rb_start,
2609                                         rb_head, rb_tail);
2610                                 parser_exec_state_dump(s);
2611                                 break;
2612                         }
2613                 }
2614                 ret = cmd_parser_exec(s);
2615                 if (ret) {
2616                         gvt_vgpu_err("cmd parser error\n");
2617                         parser_exec_state_dump(s);
2618                         break;
2619                 }
2620         }
2621
2622         return ret;
2623 }
2624
2625 static int scan_workload(struct intel_vgpu_workload *workload)
2626 {
2627         unsigned long gma_head, gma_tail, gma_bottom;
2628         struct parser_exec_state s;
2629         int ret = 0;
2630
2631         /* ring base is page aligned */
2632         if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2633                 return -EINVAL;
2634
2635         gma_head = workload->rb_start + workload->rb_head;
2636         gma_tail = workload->rb_start + workload->rb_tail;
2637         gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2638
2639         s.buf_type = RING_BUFFER_INSTRUCTION;
2640         s.buf_addr_type = GTT_BUFFER;
2641         s.vgpu = workload->vgpu;
2642         s.ring_id = workload->ring_id;
2643         s.ring_start = workload->rb_start;
2644         s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2645         s.ring_head = gma_head;
2646         s.ring_tail = gma_tail;
2647         s.rb_va = workload->shadow_ring_buffer_va;
2648         s.workload = workload;
2649         s.is_ctx_wa = false;
2650
2651         if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2652                 gma_head == gma_tail)
2653                 return 0;
2654
2655         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2656                 ret = -EINVAL;
2657                 goto out;
2658         }
2659
2660         ret = ip_gma_set(&s, gma_head);
2661         if (ret)
2662                 goto out;
2663
2664         ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2665                 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2666
2667 out:
2668         return ret;
2669 }
2670
2671 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2672 {
2673
2674         unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2675         struct parser_exec_state s;
2676         int ret = 0;
2677         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2678                                 struct intel_vgpu_workload,
2679                                 wa_ctx);
2680
2681         /* ring base is page aligned */
2682         if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2683                                         I915_GTT_PAGE_SIZE)))
2684                 return -EINVAL;
2685
2686         ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2687         ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2688                         PAGE_SIZE);
2689         gma_head = wa_ctx->indirect_ctx.guest_gma;
2690         gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2691         gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2692
2693         s.buf_type = RING_BUFFER_INSTRUCTION;
2694         s.buf_addr_type = GTT_BUFFER;
2695         s.vgpu = workload->vgpu;
2696         s.ring_id = workload->ring_id;
2697         s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2698         s.ring_size = ring_size;
2699         s.ring_head = gma_head;
2700         s.ring_tail = gma_tail;
2701         s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2702         s.workload = workload;
2703         s.is_ctx_wa = true;
2704
2705         if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2706                 ret = -EINVAL;
2707                 goto out;
2708         }
2709
2710         ret = ip_gma_set(&s, gma_head);
2711         if (ret)
2712                 goto out;
2713
2714         ret = command_scan(&s, 0, ring_tail,
2715                 wa_ctx->indirect_ctx.guest_gma, ring_size);
2716 out:
2717         return ret;
2718 }
2719
2720 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2721 {
2722         struct intel_vgpu *vgpu = workload->vgpu;
2723         struct intel_vgpu_submission *s = &vgpu->submission;
2724         unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2725         void *shadow_ring_buffer_va;
2726         int ring_id = workload->ring_id;
2727         int ret;
2728
2729         guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2730
2731         /* calculate workload ring buffer size */
2732         workload->rb_len = (workload->rb_tail + guest_rb_size -
2733                         workload->rb_head) % guest_rb_size;
2734
2735         gma_head = workload->rb_start + workload->rb_head;
2736         gma_tail = workload->rb_start + workload->rb_tail;
2737         gma_top = workload->rb_start + guest_rb_size;
2738
2739         if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2740                 void *p;
2741
2742                 /* realloc the new ring buffer if needed */
2743                 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2744                                 GFP_KERNEL);
2745                 if (!p) {
2746                         gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2747                         return -ENOMEM;
2748                 }
2749                 s->ring_scan_buffer[ring_id] = p;
2750                 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2751         }
2752
2753         shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2754
2755         /* get shadow ring buffer va */
2756         workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2757
2758         /* head > tail --> copy head <-> top */
2759         if (gma_head > gma_tail) {
2760                 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2761                                       gma_head, gma_top, shadow_ring_buffer_va);
2762                 if (ret < 0) {
2763                         gvt_vgpu_err("fail to copy guest ring buffer\n");
2764                         return ret;
2765                 }
2766                 shadow_ring_buffer_va += ret;
2767                 gma_head = workload->rb_start;
2768         }
2769
2770         /* copy head or start <-> tail */
2771         ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2772                                 shadow_ring_buffer_va);
2773         if (ret < 0) {
2774                 gvt_vgpu_err("fail to copy guest ring buffer\n");
2775                 return ret;
2776         }
2777         return 0;
2778 }
2779
2780 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2781 {
2782         int ret;
2783         struct intel_vgpu *vgpu = workload->vgpu;
2784
2785         ret = shadow_workload_ring_buffer(workload);
2786         if (ret) {
2787                 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2788                 return ret;
2789         }
2790
2791         ret = scan_workload(workload);
2792         if (ret) {
2793                 gvt_vgpu_err("scan workload error\n");
2794                 return ret;
2795         }
2796         return 0;
2797 }
2798
2799 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2800 {
2801         int ctx_size = wa_ctx->indirect_ctx.size;
2802         unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2803         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2804                                         struct intel_vgpu_workload,
2805                                         wa_ctx);
2806         struct intel_vgpu *vgpu = workload->vgpu;
2807         struct drm_i915_gem_object *obj;
2808         int ret = 0;
2809         void *map;
2810
2811         obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2812                                      roundup(ctx_size + CACHELINE_BYTES,
2813                                              PAGE_SIZE));
2814         if (IS_ERR(obj))
2815                 return PTR_ERR(obj);
2816
2817         /* get the va of the shadow batch buffer */
2818         map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2819         if (IS_ERR(map)) {
2820                 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2821                 ret = PTR_ERR(map);
2822                 goto put_obj;
2823         }
2824
2825         ret = i915_gem_object_set_to_cpu_domain(obj, false);
2826         if (ret) {
2827                 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2828                 goto unmap_src;
2829         }
2830
2831         ret = copy_gma_to_hva(workload->vgpu,
2832                                 workload->vgpu->gtt.ggtt_mm,
2833                                 guest_gma, guest_gma + ctx_size,
2834                                 map);
2835         if (ret < 0) {
2836                 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2837                 goto unmap_src;
2838         }
2839
2840         wa_ctx->indirect_ctx.obj = obj;
2841         wa_ctx->indirect_ctx.shadow_va = map;
2842         return 0;
2843
2844 unmap_src:
2845         i915_gem_object_unpin_map(obj);
2846 put_obj:
2847         i915_gem_object_put(obj);
2848         return ret;
2849 }
2850
2851 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2852 {
2853         uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2854         unsigned char *bb_start_sva;
2855
2856         if (!wa_ctx->per_ctx.valid)
2857                 return 0;
2858
2859         per_ctx_start[0] = 0x18800001;
2860         per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2861
2862         bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2863                                 wa_ctx->indirect_ctx.size;
2864
2865         memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2866
2867         return 0;
2868 }
2869
2870 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2871 {
2872         int ret;
2873         struct intel_vgpu_workload *workload = container_of(wa_ctx,
2874                                         struct intel_vgpu_workload,
2875                                         wa_ctx);
2876         struct intel_vgpu *vgpu = workload->vgpu;
2877
2878         if (wa_ctx->indirect_ctx.size == 0)
2879                 return 0;
2880
2881         ret = shadow_indirect_ctx(wa_ctx);
2882         if (ret) {
2883                 gvt_vgpu_err("fail to shadow indirect ctx\n");
2884                 return ret;
2885         }
2886
2887         combine_wa_ctx(wa_ctx);
2888
2889         ret = scan_wa_ctx(wa_ctx);
2890         if (ret) {
2891                 gvt_vgpu_err("scan wa ctx error\n");
2892                 return ret;
2893         }
2894
2895         return 0;
2896 }
2897
2898 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2899                 unsigned int opcode, unsigned long rings)
2900 {
2901         struct cmd_info *info = NULL;
2902         unsigned int ring;
2903
2904         for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2905                 info = find_cmd_entry(gvt, opcode, ring);
2906                 if (info)
2907                         break;
2908         }
2909         return info;
2910 }
2911
2912 static int init_cmd_table(struct intel_gvt *gvt)
2913 {
2914         int i;
2915         struct cmd_entry *e;
2916         struct cmd_info *info;
2917         unsigned int gen_type;
2918
2919         gen_type = intel_gvt_get_device_type(gvt);
2920
2921         for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2922                 if (!(cmd_info[i].devices & gen_type))
2923                         continue;
2924
2925                 e = kzalloc(sizeof(*e), GFP_KERNEL);
2926                 if (!e)
2927                         return -ENOMEM;
2928
2929                 e->info = &cmd_info[i];
2930                 info = find_cmd_entry_any_ring(gvt,
2931                                 e->info->opcode, e->info->rings);
2932                 if (info) {
2933                         gvt_err("%s %s duplicated\n", e->info->name,
2934                                         info->name);
2935                         kfree(e);
2936                         return -EEXIST;
2937                 }
2938
2939                 INIT_HLIST_NODE(&e->hlist);
2940                 add_cmd_entry(gvt, e);
2941                 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2942                                 e->info->name, e->info->opcode, e->info->flag,
2943                                 e->info->devices, e->info->rings);
2944         }
2945         return 0;
2946 }
2947
2948 static void clean_cmd_table(struct intel_gvt *gvt)
2949 {
2950         struct hlist_node *tmp;
2951         struct cmd_entry *e;
2952         int i;
2953
2954         hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2955                 kfree(e);
2956
2957         hash_init(gvt->cmd_table);
2958 }
2959
2960 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2961 {
2962         clean_cmd_table(gvt);
2963 }
2964
2965 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2966 {
2967         int ret;
2968
2969         ret = init_cmd_table(gvt);
2970         if (ret) {
2971                 intel_gvt_clean_cmd_parser(gvt);
2972                 return ret;
2973         }
2974         return 0;
2975 }