drm/i915/gvt: remove duplicated definition
[sfrench/cifs-2.6.git] / drivers / gpu / drm / i915 / gvt / aperture_gm.c
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *    Dexuan Cui
26  *
27  * Contributors:
28  *    Pei Zhang <pei.zhang@intel.com>
29  *    Min He <min.he@intel.com>
30  *    Niu Bing <bing.niu@intel.com>
31  *    Yulei Zhang <yulei.zhang@intel.com>
32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
33  *    Zhi Wang <zhi.a.wang@intel.com>
34  *
35  */
36
37 #include "i915_drv.h"
38 #include "gvt.h"
39
40 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
41 {
42         struct intel_gvt *gvt = vgpu->gvt;
43         struct drm_i915_private *dev_priv = gvt->dev_priv;
44         u32 alloc_flag, search_flag;
45         u64 start, end, size;
46         struct drm_mm_node *node;
47         int retried = 0;
48         int ret;
49
50         if (high_gm) {
51                 search_flag = DRM_MM_SEARCH_BELOW;
52                 alloc_flag = DRM_MM_CREATE_TOP;
53                 node = &vgpu->gm.high_gm_node;
54                 size = vgpu_hidden_sz(vgpu);
55                 start = gvt_hidden_gmadr_base(gvt);
56                 end = gvt_hidden_gmadr_end(gvt);
57         } else {
58                 search_flag = DRM_MM_SEARCH_DEFAULT;
59                 alloc_flag = DRM_MM_CREATE_DEFAULT;
60                 node = &vgpu->gm.low_gm_node;
61                 size = vgpu_aperture_sz(vgpu);
62                 start = gvt_aperture_gmadr_base(gvt);
63                 end = gvt_aperture_gmadr_end(gvt);
64         }
65
66         mutex_lock(&dev_priv->drm.struct_mutex);
67 search_again:
68         ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,
69                                                   node, size, 4096, 0,
70                                                   start, end, search_flag,
71                                                   alloc_flag);
72         if (ret) {
73                 ret = i915_gem_evict_something(&dev_priv->ggtt.base,
74                                                size, 4096, 0, start, end, 0);
75                 if (ret == 0 && ++retried < 3)
76                         goto search_again;
77
78                 gvt_err("fail to alloc %s gm space from host, retried %d\n",
79                                 high_gm ? "high" : "low", retried);
80         }
81         mutex_unlock(&dev_priv->drm.struct_mutex);
82         return ret;
83 }
84
85 static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
86 {
87         struct intel_gvt *gvt = vgpu->gvt;
88         struct drm_i915_private *dev_priv = gvt->dev_priv;
89         int ret;
90
91         ret = alloc_gm(vgpu, false);
92         if (ret)
93                 return ret;
94
95         ret = alloc_gm(vgpu, true);
96         if (ret)
97                 goto out_free_aperture;
98
99         gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
100                      vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
101
102         gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
103                      vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
104
105         return 0;
106 out_free_aperture:
107         mutex_lock(&dev_priv->drm.struct_mutex);
108         drm_mm_remove_node(&vgpu->gm.low_gm_node);
109         mutex_unlock(&dev_priv->drm.struct_mutex);
110         return ret;
111 }
112
113 static void free_vgpu_gm(struct intel_vgpu *vgpu)
114 {
115         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
116
117         mutex_lock(&dev_priv->drm.struct_mutex);
118         drm_mm_remove_node(&vgpu->gm.low_gm_node);
119         drm_mm_remove_node(&vgpu->gm.high_gm_node);
120         mutex_unlock(&dev_priv->drm.struct_mutex);
121 }
122
123 /**
124  * intel_vgpu_write_fence - write fence registers owned by a vGPU
125  * @vgpu: vGPU instance
126  * @fence: vGPU fence register number
127  * @value: Fence register value to be written
128  *
129  * This function is used to write fence registers owned by a vGPU. The vGPU
130  * fence register number will be translated into HW fence register number.
131  *
132  */
133 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
134                 u32 fence, u64 value)
135 {
136         struct intel_gvt *gvt = vgpu->gvt;
137         struct drm_i915_private *dev_priv = gvt->dev_priv;
138         struct drm_i915_fence_reg *reg;
139         i915_reg_t fence_reg_lo, fence_reg_hi;
140
141         assert_rpm_wakelock_held(dev_priv);
142
143         if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
144                 return;
145
146         reg = vgpu->fence.regs[fence];
147         if (WARN_ON(!reg))
148                 return;
149
150         fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
151         fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
152
153         I915_WRITE(fence_reg_lo, 0);
154         POSTING_READ(fence_reg_lo);
155
156         I915_WRITE(fence_reg_hi, upper_32_bits(value));
157         I915_WRITE(fence_reg_lo, lower_32_bits(value));
158         POSTING_READ(fence_reg_lo);
159 }
160
161 static void free_vgpu_fence(struct intel_vgpu *vgpu)
162 {
163         struct intel_gvt *gvt = vgpu->gvt;
164         struct drm_i915_private *dev_priv = gvt->dev_priv;
165         struct drm_i915_fence_reg *reg;
166         u32 i;
167
168         if (WARN_ON(!vgpu_fence_sz(vgpu)))
169                 return;
170
171         intel_runtime_pm_get(dev_priv);
172
173         mutex_lock(&dev_priv->drm.struct_mutex);
174         for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
175                 reg = vgpu->fence.regs[i];
176                 intel_vgpu_write_fence(vgpu, i, 0);
177                 list_add_tail(&reg->link,
178                               &dev_priv->mm.fence_list);
179         }
180         mutex_unlock(&dev_priv->drm.struct_mutex);
181
182         intel_runtime_pm_put(dev_priv);
183 }
184
185 static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
186 {
187         struct intel_gvt *gvt = vgpu->gvt;
188         struct drm_i915_private *dev_priv = gvt->dev_priv;
189         struct drm_i915_fence_reg *reg;
190         int i;
191         struct list_head *pos, *q;
192
193         intel_runtime_pm_get(dev_priv);
194
195         /* Request fences from host */
196         mutex_lock(&dev_priv->drm.struct_mutex);
197         i = 0;
198         list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
199                 reg = list_entry(pos, struct drm_i915_fence_reg, link);
200                 if (reg->pin_count || reg->vma)
201                         continue;
202                 list_del(pos);
203                 vgpu->fence.regs[i] = reg;
204                 intel_vgpu_write_fence(vgpu, i, 0);
205                 if (++i == vgpu_fence_sz(vgpu))
206                         break;
207         }
208         if (i != vgpu_fence_sz(vgpu))
209                 goto out_free_fence;
210
211         mutex_unlock(&dev_priv->drm.struct_mutex);
212         intel_runtime_pm_put(dev_priv);
213         return 0;
214 out_free_fence:
215         /* Return fences to host, if fail */
216         for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
217                 reg = vgpu->fence.regs[i];
218                 if (!reg)
219                         continue;
220                 list_add_tail(&reg->link,
221                               &dev_priv->mm.fence_list);
222         }
223         mutex_unlock(&dev_priv->drm.struct_mutex);
224         intel_runtime_pm_put(dev_priv);
225         return -ENOSPC;
226 }
227
228 static void free_resource(struct intel_vgpu *vgpu)
229 {
230         struct intel_gvt *gvt = vgpu->gvt;
231
232         gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
233         gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
234         gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
235 }
236
237 static int alloc_resource(struct intel_vgpu *vgpu,
238                 struct intel_vgpu_creation_params *param)
239 {
240         struct intel_gvt *gvt = vgpu->gvt;
241         unsigned long request, avail, max, taken;
242         const char *item;
243
244         if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
245                 gvt_err("Invalid vGPU creation params\n");
246                 return -EINVAL;
247         }
248
249         item = "low GM space";
250         max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
251         taken = gvt->gm.vgpu_allocated_low_gm_size;
252         avail = max - taken;
253         request = MB_TO_BYTES(param->low_gm_sz);
254
255         if (request > avail)
256                 goto no_enough_resource;
257
258         vgpu_aperture_sz(vgpu) = request;
259
260         item = "high GM space";
261         max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
262         taken = gvt->gm.vgpu_allocated_high_gm_size;
263         avail = max - taken;
264         request = MB_TO_BYTES(param->high_gm_sz);
265
266         if (request > avail)
267                 goto no_enough_resource;
268
269         vgpu_hidden_sz(vgpu) = request;
270
271         item = "fence";
272         max = gvt_fence_sz(gvt) - HOST_FENCE;
273         taken = gvt->fence.vgpu_allocated_fence_num;
274         avail = max - taken;
275         request = param->fence_sz;
276
277         if (request > avail)
278                 goto no_enough_resource;
279
280         vgpu_fence_sz(vgpu) = request;
281
282         gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
283         gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
284         gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
285         return 0;
286
287 no_enough_resource:
288         gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);
289         gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",
290                 vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),
291                 BYTES_TO_MB(max), BYTES_TO_MB(taken));
292         return -ENOSPC;
293 }
294
295 /**
296  * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
297  * @vgpu: a vGPU
298  *
299  * This function is used to free the HW resource owned by a vGPU.
300  *
301  */
302 void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
303 {
304         free_vgpu_gm(vgpu);
305         free_vgpu_fence(vgpu);
306         free_resource(vgpu);
307 }
308
309 /**
310  * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
311  * @vgpu: vGPU
312  * @param: vGPU creation params
313  *
314  * This function is used to allocate HW resource for a vGPU. User specifies
315  * the resource configuration through the creation params.
316  *
317  * Returns:
318  * zero on success, negative error code if failed.
319  *
320  */
321 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
322                 struct intel_vgpu_creation_params *param)
323 {
324         int ret;
325
326         ret = alloc_resource(vgpu, param);
327         if (ret)
328                 return ret;
329
330         ret = alloc_vgpu_gm(vgpu);
331         if (ret)
332                 goto out_free_resource;
333
334         ret = alloc_vgpu_fence(vgpu);
335         if (ret)
336                 goto out_free_vgpu_gm;
337
338         return 0;
339
340 out_free_vgpu_gm:
341         free_vgpu_gm(vgpu);
342 out_free_resource:
343         free_resource(vgpu);
344         return ret;
345 }