2 * SPDX-License-Identifier: MIT
4 * Copyright © 2014-2018 Intel Corporation
8 #include "intel_context.h"
10 #include "intel_workarounds.h"
13 * DOC: Hardware workarounds
15 * This file is intended as a central place to implement most [1]_ of the
16 * required workarounds for hardware to work as originally intended. They fall
17 * in five basic categories depending on how/when they are applied:
19 * - Workarounds that touch registers that are saved/restored to/from the HW
20 * context image. The list is emitted (via Load Register Immediate commands)
21 * everytime a new context is created.
22 * - GT workarounds. The list of these WAs is applied whenever these registers
23 * revert to default values (on GPU reset, suspend/resume [2]_, etc..).
24 * - Display workarounds. The list is applied during display clock-gating
26 * - Workarounds that whitelist a privileged register, so that UMDs can manage
27 * them directly. This is just a special case of a MMMIO workaround (as we
28 * write the list of these to/be-whitelisted registers to some special HW
30 * - Workaround batchbuffers, that get executed automatically by the hardware
31 * on every HW context restore.
33 * .. [1] Please notice that there are other WAs that, due to their nature,
34 * cannot be applied from a central place. Those are peppered around the rest
35 * of the code, as needed.
37 * .. [2] Technically, some registers are powercontext saved & restored, so they
38 * survive a suspend/resume. In practice, writing them again is not too
39 * costly and simplifies things. We can revisit this in the future.
44 * Keep things in this file ordered by WA type, as per the above (context, GT,
45 * display, register whitelist, batchbuffer). Then, inside each type, keep the
48 * - Infrastructure functions and macros
49 * - WAs per platform in standard gen/chrono order
50 * - Public functions to init or apply the given workaround type.
53 static void wa_init_start(struct i915_wa_list *wal, const char *name)
58 #define WA_LIST_CHUNK (1 << 4)
60 static void wa_init_finish(struct i915_wa_list *wal)
62 /* Trim unused entries. */
63 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
64 struct i915_wa *list = kmemdup(wal->list,
65 wal->count * sizeof(*list),
77 DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
78 wal->wa_count, wal->name);
81 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
83 unsigned int addr = i915_mmio_reg_offset(wa->reg);
84 unsigned int start = 0, end = wal->count;
85 const unsigned int grow = WA_LIST_CHUNK;
88 GEM_BUG_ON(!is_power_of_2(grow));
90 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
93 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
96 DRM_ERROR("No space for workaround init!\n");
101 memcpy(list, wal->list, sizeof(*wa) * wal->count);
106 while (start < end) {
107 unsigned int mid = start + (end - start) / 2;
109 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
111 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
114 wa_ = &wal->list[mid];
116 if ((wa->mask & ~wa_->mask) == 0) {
117 DRM_ERROR("Discarding overwritten w/a for reg %04x (mask: %08x, value: %08x)\n",
118 i915_mmio_reg_offset(wa_->reg),
119 wa_->mask, wa_->val);
121 wa_->val &= ~wa->mask;
126 wa_->mask |= wa->mask;
127 wa_->read |= wa->read;
133 wa_ = &wal->list[wal->count++];
136 while (wa_-- > wal->list) {
137 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
138 i915_mmio_reg_offset(wa_[1].reg));
139 if (i915_mmio_reg_offset(wa_[1].reg) >
140 i915_mmio_reg_offset(wa_[0].reg))
143 swap(wa_[1], wa_[0]);
148 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
151 struct i915_wa wa = {
162 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
164 wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
168 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
170 wa_write_masked_or(wal, reg, ~0, val);
174 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
176 wa_write_masked_or(wal, reg, val, val);
180 ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
182 struct i915_wa wa = {
186 /* Bonkers HW, skip verifying */
192 #define WA_SET_BIT_MASKED(addr, mask) \
193 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
195 #define WA_CLR_BIT_MASKED(addr, mask) \
196 wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
198 #define WA_SET_FIELD_MASKED(addr, mask, value) \
199 wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
201 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
202 struct i915_wa_list *wal)
204 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
206 /* WaDisableAsyncFlipPerfMode:bdw,chv */
207 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
209 /* WaDisablePartialInstShootdown:bdw,chv */
210 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
211 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
213 /* Use Force Non-Coherent whenever executing a 3D context. This is a
214 * workaround for for a possible hang in the unlikely event a TLB
215 * invalidation occurs during a PSD flush.
217 /* WaForceEnableNonCoherent:bdw,chv */
218 /* WaHdcDisableFetchWhenMasked:bdw,chv */
219 WA_SET_BIT_MASKED(HDC_CHICKEN0,
220 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
221 HDC_FORCE_NON_COHERENT);
223 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
224 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
225 * polygons in the same 8x4 pixel/sample area to be processed without
226 * stalling waiting for the earlier ones to write to Hierarchical Z
229 * This optimization is off by default for BDW and CHV; turn it on.
231 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
233 /* Wa4x4STCOptimizationDisable:bdw,chv */
234 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
237 * BSpec recommends 8x4 when MSAA is used,
238 * however in practice 16x4 seems fastest.
240 * Note that PS/WM thread counts depend on the WIZ hashing
241 * disable bit, which we don't touch here, but it's good
242 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
244 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
245 GEN6_WIZ_HASHING_MASK,
246 GEN6_WIZ_HASHING_16x4);
249 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
250 struct i915_wa_list *wal)
252 struct drm_i915_private *i915 = engine->i915;
254 gen8_ctx_workarounds_init(engine, wal);
256 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
257 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
259 /* WaDisableDopClockGating:bdw
261 * Also see the related UCGTCL1 write in broadwell_init_clock_gating()
262 * to disable EUTC clock gating.
264 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
265 DOP_CLOCK_GATING_DISABLE);
267 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
268 GEN8_SAMPLER_POWER_BYPASS_DIS);
270 WA_SET_BIT_MASKED(HDC_CHICKEN0,
271 /* WaForceContextSaveRestoreNonCoherent:bdw */
272 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
273 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
274 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
277 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
278 struct i915_wa_list *wal)
280 gen8_ctx_workarounds_init(engine, wal);
282 /* WaDisableThreadStallDopClockGating:chv */
283 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
285 /* Improve HiZ throughput on CHV. */
286 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
289 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
290 struct i915_wa_list *wal)
292 struct drm_i915_private *i915 = engine->i915;
295 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
297 * Must match Display Engine. See
298 * WaCompressedResourceDisplayNewHashMode.
300 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
301 GEN9_PBE_COMPRESSED_HASH_SELECTION);
302 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
303 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
306 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
307 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
308 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
309 FLOW_CONTROL_ENABLE |
310 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
312 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
313 if (!IS_COFFEELAKE(i915))
314 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
315 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
317 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
318 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
319 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
320 GEN9_ENABLE_YV12_BUGFIX |
321 GEN9_ENABLE_GPGPU_PREEMPTION);
323 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
324 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
325 WA_SET_BIT_MASKED(CACHE_MODE_1,
326 GEN8_4x4_STC_OPTIMIZATION_DISABLE |
327 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
329 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
330 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
331 GEN9_CCS_TLB_PREFETCH_ENABLE);
333 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
334 WA_SET_BIT_MASKED(HDC_CHICKEN0,
335 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
336 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
338 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
339 * both tied to WaForceContextSaveRestoreNonCoherent
340 * in some hsds for skl. We keep the tie for all gen9. The
341 * documentation is a bit hazy and so we want to get common behaviour,
342 * even though there is no clear evidence we would need both on kbl/bxt.
343 * This area has been source of system hangs so we play it safe
344 * and mimic the skl regardless of what bspec says.
346 * Use Force Non-Coherent whenever executing a 3D context. This
347 * is a workaround for a possible hang in the unlikely event
348 * a TLB invalidation occurs during a PSD flush.
351 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
352 WA_SET_BIT_MASKED(HDC_CHICKEN0,
353 HDC_FORCE_NON_COHERENT);
355 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
356 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915))
357 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
358 GEN8_SAMPLER_POWER_BYPASS_DIS);
360 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
361 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
364 * Supporting preemption with fine-granularity requires changes in the
365 * batch buffer programming. Since we can't break old userspace, we
366 * need to set our default preemption level to safe value. Userspace is
367 * still able to use more fine-grained preemption levels, since in
368 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
369 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
370 * not real HW workarounds, but merely a way to start using preemption
371 * while maintaining old contract with userspace.
374 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
375 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
377 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
378 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
379 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
380 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
382 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
383 if (IS_GEN9_LP(i915))
384 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
387 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
388 struct i915_wa_list *wal)
390 struct drm_i915_private *i915 = engine->i915;
391 u8 vals[3] = { 0, 0, 0 };
394 for (i = 0; i < 3; i++) {
398 * Only consider slices where one, and only one, subslice has 7
401 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
405 * subslice_7eu[i] != 0 (because of the check above) and
406 * ss_max == 4 (maximum number of subslices possible per slice)
410 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
414 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
417 /* Tune IZ hashing. See intel_device_info_runtime_init() */
418 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
419 GEN9_IZ_HASHING_MASK(2) |
420 GEN9_IZ_HASHING_MASK(1) |
421 GEN9_IZ_HASHING_MASK(0),
422 GEN9_IZ_HASHING(2, vals[2]) |
423 GEN9_IZ_HASHING(1, vals[1]) |
424 GEN9_IZ_HASHING(0, vals[0]));
427 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
428 struct i915_wa_list *wal)
430 gen9_ctx_workarounds_init(engine, wal);
431 skl_tune_iz_hashing(engine, wal);
434 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
435 struct i915_wa_list *wal)
437 gen9_ctx_workarounds_init(engine, wal);
439 /* WaDisableThreadStallDopClockGating:bxt */
440 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
441 STALL_DOP_GATING_DISABLE);
443 /* WaToEnableHwFixForPushConstHWBug:bxt */
444 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
445 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
448 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
449 struct i915_wa_list *wal)
451 struct drm_i915_private *i915 = engine->i915;
453 gen9_ctx_workarounds_init(engine, wal);
455 /* WaToEnableHwFixForPushConstHWBug:kbl */
456 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER))
457 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
458 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
460 /* WaDisableSbeCacheDispatchPortSharing:kbl */
461 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
462 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
465 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
466 struct i915_wa_list *wal)
468 gen9_ctx_workarounds_init(engine, wal);
470 /* WaToEnableHwFixForPushConstHWBug:glk */
471 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
472 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
475 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
476 struct i915_wa_list *wal)
478 gen9_ctx_workarounds_init(engine, wal);
480 /* WaToEnableHwFixForPushConstHWBug:cfl */
481 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
482 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
484 /* WaDisableSbeCacheDispatchPortSharing:cfl */
485 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
486 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
489 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
490 struct i915_wa_list *wal)
492 struct drm_i915_private *i915 = engine->i915;
494 /* WaForceContextSaveRestoreNonCoherent:cnl */
495 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
496 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
498 /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
499 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
500 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5);
502 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
503 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
504 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
506 /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */
507 if (IS_CNL_REVID(i915, 0, CNL_REVID_B0))
508 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
509 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
511 /* WaPushConstantDereferenceHoldDisable:cnl */
512 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
514 /* FtrEnableFastAnisoL1BankingFix:cnl */
515 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
517 /* WaDisable3DMidCmdPreemption:cnl */
518 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
520 /* WaDisableGPGPUMidCmdPreemption:cnl */
521 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
522 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
523 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
525 /* WaDisableEarlyEOT:cnl */
526 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
529 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
530 struct i915_wa_list *wal)
532 struct drm_i915_private *i915 = engine->i915;
534 /* WaDisableBankHangMode:icl */
537 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
540 /* Wa_1604370585:icl (pre-prod)
541 * Formerly known as WaPushConstantDereferenceHoldDisable
543 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
544 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
545 PUSH_CONSTANT_DEREF_DISABLE);
547 /* WaForceEnableNonCoherent:icl
548 * This is not the same workaround as in early Gen9 platforms, where
549 * lacking this could cause system hangs, but coherency performance
550 * overhead is high and only a few compute workloads really need it
551 * (the register is whitelisted in hardware now, so UMDs can opt in
552 * for coherency if they have a good reason).
554 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
556 /* Wa_2006611047:icl (pre-prod)
557 * Formerly known as WaDisableImprovedTdlClkGating
559 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
560 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
561 GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
563 /* Wa_2006665173:icl (pre-prod) */
564 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
565 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
566 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
568 /* WaEnableFloatBlendOptimization:icl */
569 wa_write_masked_or(wal,
571 0, /* write-only, so skip validation */
572 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
574 /* WaDisableGPGPUMidThreadPreemption:icl */
575 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
576 GEN9_PREEMPT_GPGPU_LEVEL_MASK,
577 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
579 /* allow headerless messages for preemptible GPGPU context */
580 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
581 GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
585 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
586 struct i915_wa_list *wal,
589 struct drm_i915_private *i915 = engine->i915;
591 if (engine->class != RENDER_CLASS)
594 wa_init_start(wal, name);
596 if (IS_GEN(i915, 11))
597 icl_ctx_workarounds_init(engine, wal);
598 else if (IS_CANNONLAKE(i915))
599 cnl_ctx_workarounds_init(engine, wal);
600 else if (IS_COFFEELAKE(i915))
601 cfl_ctx_workarounds_init(engine, wal);
602 else if (IS_GEMINILAKE(i915))
603 glk_ctx_workarounds_init(engine, wal);
604 else if (IS_KABYLAKE(i915))
605 kbl_ctx_workarounds_init(engine, wal);
606 else if (IS_BROXTON(i915))
607 bxt_ctx_workarounds_init(engine, wal);
608 else if (IS_SKYLAKE(i915))
609 skl_ctx_workarounds_init(engine, wal);
610 else if (IS_CHERRYVIEW(i915))
611 chv_ctx_workarounds_init(engine, wal);
612 else if (IS_BROADWELL(i915))
613 bdw_ctx_workarounds_init(engine, wal);
614 else if (INTEL_GEN(i915) < 8)
617 MISSING_CASE(INTEL_GEN(i915));
622 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
624 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
627 int intel_engine_emit_ctx_wa(struct i915_request *rq)
629 struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
638 ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
642 cs = intel_ring_begin(rq, (wal->count * 2 + 2));
646 *cs++ = MI_LOAD_REGISTER_IMM(wal->count);
647 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
648 *cs++ = i915_mmio_reg_offset(wa->reg);
653 intel_ring_advance(rq, cs);
655 ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
663 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
665 /* WaDisableKillLogic:bxt,skl,kbl */
666 if (!IS_COFFEELAKE(i915))
672 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
674 * Must match Display Engine. See
675 * WaCompressedResourceDisplayNewHashMode.
679 MMCD_PCLA | MMCD_HOTSPOT_EN);
682 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
685 BDW_DISABLE_HDC_INVALIDATION);
689 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
691 gen9_gt_workarounds_init(i915, wal);
693 /* WaDisableGafsUnitClkGating:skl */
696 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
698 /* WaInPlaceDecompressionHang:skl */
699 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
701 GEN9_GAMT_ECO_REG_RW_IA,
702 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
706 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
708 gen9_gt_workarounds_init(i915, wal);
710 /* WaInPlaceDecompressionHang:bxt */
712 GEN9_GAMT_ECO_REG_RW_IA,
713 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
717 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
719 gen9_gt_workarounds_init(i915, wal);
721 /* WaDisableDynamicCreditSharing:kbl */
722 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0))
725 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
727 /* WaDisableGafsUnitClkGating:kbl */
730 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
732 /* WaInPlaceDecompressionHang:kbl */
734 GEN9_GAMT_ECO_REG_RW_IA,
735 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
739 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
741 gen9_gt_workarounds_init(i915, wal);
745 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
747 gen9_gt_workarounds_init(i915, wal);
749 /* WaDisableGafsUnitClkGating:cfl */
752 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
754 /* WaInPlaceDecompressionHang:cfl */
756 GEN9_GAMT_ECO_REG_RW_IA,
757 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
761 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
763 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
764 u32 mcr_slice_subslice_mask;
767 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
768 * L3Banks could be fused off in single slice scenario. If that is
769 * the case, we might need to program MCR select to a valid L3Bank
770 * by default, to make sure we correctly read certain registers
771 * later on (in the range 0xB100 - 0xB3FF).
772 * This might be incompatible with
773 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
774 * Fortunately, this should not happen in production hardware, so
775 * we only assert that this is the case (instead of implementing
776 * something more complex that requires checking the range of every
779 if (INTEL_GEN(i915) >= 10 &&
780 is_power_of_2(sseu->slice_mask)) {
782 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
783 * enabled subslice, no need to redirect MCR packet
785 u32 slice = fls(sseu->slice_mask);
787 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
788 u8 ss_mask = sseu->subslice_mask[slice];
790 u8 enabled_mask = (ss_mask | ss_mask >>
791 GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
792 u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
795 * Production silicon should have matched L3Bank and
798 WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
801 if (INTEL_GEN(i915) >= 11)
802 mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
803 GEN11_MCR_SUBSLICE_MASK;
805 mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
806 GEN8_MCR_SUBSLICE_MASK;
808 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
809 * Before any MMIO read into slice/subslice specific registers, MCR
810 * packet control register needs to be programmed to point to any
811 * enabled s/ss pair. Otherwise, incorrect values will be returned.
812 * This means each subsequent MMIO read will be forwarded to an
813 * specific s/ss combination, but this is OK since these registers
814 * are consistent across s/ss in almost all cases. In the rare
815 * occasions, such as INSTDONE, where this value is dependent
816 * on s/ss combo, the read should be done with read_subslice_reg.
818 wa_write_masked_or(wal,
820 mcr_slice_subslice_mask,
821 intel_calculate_mcr_s_ss_select(i915));
825 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
827 wa_init_mcr(i915, wal);
829 /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */
830 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0))
833 GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT);
835 /* WaInPlaceDecompressionHang:cnl */
837 GEN9_GAMT_ECO_REG_RW_IA,
838 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
842 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
844 wa_init_mcr(i915, wal);
846 /* WaInPlaceDecompressionHang:icl */
848 GEN9_GAMT_ECO_REG_RW_IA,
849 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
851 /* WaModifyGamTlbPartitioning:icl */
852 wa_write_masked_or(wal,
853 GEN11_GACB_PERF_CTRL,
854 GEN11_HASH_CTRL_MASK,
855 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
858 * Formerly known as WaCL2SFHalfMaxAlloc
862 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
863 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
866 * Formerly known as WaDisCtxReload
869 GEN8_GAMW_ECO_DEV_RW_IA,
870 GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
872 /* Wa_1405779004:icl (pre-prod) */
873 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
875 SLICE_UNIT_LEVEL_CLKGATE,
876 MSCUNIT_CLKGATE_DIS);
878 /* Wa_1406680159:icl */
880 SUBSLICE_UNIT_LEVEL_CLKGATE,
883 /* Wa_1406838659:icl (pre-prod) */
884 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
886 INF_UNIT_LEVEL_CLKGATE,
890 * Formerly known as WaGamTlbPendError
894 GAMT_CHKN_DISABLE_L3_COH_PIPE);
898 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
900 if (IS_GEN(i915, 11))
901 icl_gt_workarounds_init(i915, wal);
902 else if (IS_CANNONLAKE(i915))
903 cnl_gt_workarounds_init(i915, wal);
904 else if (IS_COFFEELAKE(i915))
905 cfl_gt_workarounds_init(i915, wal);
906 else if (IS_GEMINILAKE(i915))
907 glk_gt_workarounds_init(i915, wal);
908 else if (IS_KABYLAKE(i915))
909 kbl_gt_workarounds_init(i915, wal);
910 else if (IS_BROXTON(i915))
911 bxt_gt_workarounds_init(i915, wal);
912 else if (IS_SKYLAKE(i915))
913 skl_gt_workarounds_init(i915, wal);
914 else if (INTEL_GEN(i915) <= 8)
917 MISSING_CASE(INTEL_GEN(i915));
920 void intel_gt_init_workarounds(struct drm_i915_private *i915)
922 struct i915_wa_list *wal = &i915->gt_wa_list;
924 wa_init_start(wal, "GT");
925 gt_init_workarounds(i915, wal);
929 static enum forcewake_domains
930 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
932 enum forcewake_domains fw = 0;
936 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
937 fw |= intel_uncore_forcewake_for_reg(uncore,
946 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
948 if ((cur ^ wa->val) & wa->read) {
949 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
950 name, from, i915_mmio_reg_offset(wa->reg),
961 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
963 enum forcewake_domains fw;
971 fw = wal_get_fw_for_rmw(uncore, wal);
973 spin_lock_irqsave(&uncore->lock, flags);
974 intel_uncore_forcewake_get__locked(uncore, fw);
976 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
977 intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
978 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
980 intel_uncore_read_fw(uncore, wa->reg),
981 wal->name, "application");
984 intel_uncore_forcewake_put__locked(uncore, fw);
985 spin_unlock_irqrestore(&uncore->lock, flags);
988 void intel_gt_apply_workarounds(struct intel_gt *gt)
990 wa_list_apply(gt->uncore, >->i915->gt_wa_list);
993 static bool wa_list_verify(struct intel_uncore *uncore,
994 const struct i915_wa_list *wal,
1001 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1003 intel_uncore_read(uncore, wa->reg),
1009 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1011 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from);
1015 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1017 struct i915_wa wa = {
1021 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1024 wa.reg.reg |= flags;
1029 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1031 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
1034 static void gen9_whitelist_build(struct i915_wa_list *w)
1036 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1037 whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1039 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1040 whitelist_reg(w, GEN8_CS_CHICKEN1);
1042 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1043 whitelist_reg(w, GEN8_HDC_CHICKEN1);
1046 static void skl_whitelist_build(struct intel_engine_cs *engine)
1048 struct i915_wa_list *w = &engine->whitelist;
1050 if (engine->class != RENDER_CLASS)
1053 gen9_whitelist_build(w);
1055 /* WaDisableLSQCROPERFforOCL:skl */
1056 whitelist_reg(w, GEN8_L3SQCREG4);
1059 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1061 if (engine->class != RENDER_CLASS)
1064 gen9_whitelist_build(&engine->whitelist);
1067 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1069 struct i915_wa_list *w = &engine->whitelist;
1071 if (engine->class != RENDER_CLASS)
1074 gen9_whitelist_build(w);
1076 /* WaDisableLSQCROPERFforOCL:kbl */
1077 whitelist_reg(w, GEN8_L3SQCREG4);
1080 static void glk_whitelist_build(struct intel_engine_cs *engine)
1082 struct i915_wa_list *w = &engine->whitelist;
1084 if (engine->class != RENDER_CLASS)
1087 gen9_whitelist_build(w);
1089 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1090 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1093 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1095 struct i915_wa_list *w = &engine->whitelist;
1097 if (engine->class != RENDER_CLASS)
1100 gen9_whitelist_build(w);
1103 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1105 * This covers 4 register which are next to one another :
1106 * - PS_INVOCATION_COUNT
1107 * - PS_INVOCATION_COUNT_UDW
1109 * - PS_DEPTH_COUNT_UDW
1111 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1112 RING_FORCE_TO_NONPRIV_RD |
1113 RING_FORCE_TO_NONPRIV_RANGE_4);
1116 static void cnl_whitelist_build(struct intel_engine_cs *engine)
1118 struct i915_wa_list *w = &engine->whitelist;
1120 if (engine->class != RENDER_CLASS)
1123 /* WaEnablePreemptionGranularityControlByUMD:cnl */
1124 whitelist_reg(w, GEN8_CS_CHICKEN1);
1127 static void icl_whitelist_build(struct intel_engine_cs *engine)
1129 struct i915_wa_list *w = &engine->whitelist;
1131 switch (engine->class) {
1133 /* WaAllowUMDToModifyHalfSliceChicken7:icl */
1134 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1136 /* WaAllowUMDToModifySamplerMode:icl */
1137 whitelist_reg(w, GEN10_SAMPLER_MODE);
1139 /* WaEnableStateCacheRedirectToCS:icl */
1140 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1143 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1145 * This covers 4 register which are next to one another :
1146 * - PS_INVOCATION_COUNT
1147 * - PS_INVOCATION_COUNT_UDW
1149 * - PS_DEPTH_COUNT_UDW
1151 whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1152 RING_FORCE_TO_NONPRIV_RD |
1153 RING_FORCE_TO_NONPRIV_RANGE_4);
1156 case VIDEO_DECODE_CLASS:
1157 /* hucStatusRegOffset */
1158 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1159 RING_FORCE_TO_NONPRIV_RD);
1160 /* hucUKernelHdrInfoRegOffset */
1161 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1162 RING_FORCE_TO_NONPRIV_RD);
1163 /* hucStatus2RegOffset */
1164 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1165 RING_FORCE_TO_NONPRIV_RD);
1173 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
1175 struct drm_i915_private *i915 = engine->i915;
1176 struct i915_wa_list *w = &engine->whitelist;
1178 wa_init_start(w, "whitelist");
1180 if (IS_GEN(i915, 11))
1181 icl_whitelist_build(engine);
1182 else if (IS_CANNONLAKE(i915))
1183 cnl_whitelist_build(engine);
1184 else if (IS_COFFEELAKE(i915))
1185 cfl_whitelist_build(engine);
1186 else if (IS_GEMINILAKE(i915))
1187 glk_whitelist_build(engine);
1188 else if (IS_KABYLAKE(i915))
1189 kbl_whitelist_build(engine);
1190 else if (IS_BROXTON(i915))
1191 bxt_whitelist_build(engine);
1192 else if (IS_SKYLAKE(i915))
1193 skl_whitelist_build(engine);
1194 else if (INTEL_GEN(i915) <= 8)
1197 MISSING_CASE(INTEL_GEN(i915));
1202 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
1204 const struct i915_wa_list *wal = &engine->whitelist;
1205 struct intel_uncore *uncore = engine->uncore;
1206 const u32 base = engine->mmio_base;
1213 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1214 intel_uncore_write(uncore,
1215 RING_FORCE_TO_NONPRIV(base, i),
1216 i915_mmio_reg_offset(wa->reg));
1218 /* And clear the rest just in case of garbage */
1219 for (; i < RING_MAX_NONPRIV_SLOTS; i++)
1220 intel_uncore_write(uncore,
1221 RING_FORCE_TO_NONPRIV(base, i),
1222 i915_mmio_reg_offset(RING_NOPID(base)));
1226 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1228 struct drm_i915_private *i915 = engine->i915;
1230 if (IS_GEN(i915, 11)) {
1231 /* This is not an Wa. Enable for better image quality */
1234 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1236 /* WaPipelineFlushCoherentLines:icl */
1237 ignore_wa_write_or(wal,
1239 GEN8_LQSC_FLUSH_COHERENT_LINES,
1240 GEN8_LQSC_FLUSH_COHERENT_LINES);
1244 * Formerly known as WaGAPZPriorityScheme
1248 GEN11_ARBITRATION_PRIO_ORDER_MASK);
1252 * Formerly known as WaL3BankAddressHashing
1254 wa_write_masked_or(wal,
1256 GEN11_HASH_CTRL_EXCL_MASK,
1257 GEN11_HASH_CTRL_EXCL_BIT0);
1258 wa_write_masked_or(wal,
1260 GEN11_BANK_HASH_ADDR_EXCL_MASK,
1261 GEN11_BANK_HASH_ADDR_EXCL_BIT0);
1265 * Formerly known as WaDisableCleanEvicts
1267 ignore_wa_write_or(wal,
1269 GEN11_LQSC_CLEAN_EVICT_DISABLE,
1270 GEN11_LQSC_CLEAN_EVICT_DISABLE);
1272 /* WaForwardProgressSoftReset:icl */
1274 GEN10_SCRATCH_LNCF2,
1275 PMFLUSHDONE_LNICRSDROP |
1276 PMFLUSH_GAPL3UNBLOCK |
1277 PMFLUSHDONE_LNEBLK);
1279 /* Wa_1406609255:icl (pre-prod) */
1280 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1283 GEN7_DISABLE_DEMAND_PREFETCH);
1285 /* Wa_1606682166:icl */
1288 GEN7_DISABLE_SAMPLER_PREFETCH);
1291 if (IS_GEN_RANGE(i915, 9, 11)) {
1292 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */
1294 GEN7_FF_SLICE_CS_CHICKEN1,
1295 GEN9_FFSC_PERCTX_PREEMPT_CTRL);
1298 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
1299 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
1302 GEN9_GAPS_TSV_CREDIT_DISABLE);
1305 if (IS_BROXTON(i915)) {
1306 /* WaDisablePooledEuLoadBalancingFix:bxt */
1308 FF_SLICE_CS_CHICKEN2,
1309 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1312 if (IS_GEN(i915, 9)) {
1313 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
1315 GEN9_CSFE_CHICKEN1_RCS,
1316 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
1318 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
1321 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
1323 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
1324 if (IS_GEN9_LP(i915))
1325 wa_write_masked_or(wal,
1327 L3_PRIO_CREDITS_MASK,
1328 L3_GENERAL_PRIO_CREDITS(62) |
1329 L3_HIGH_PRIO_CREDITS(2));
1331 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
1334 GEN8_LQSC_FLUSH_COHERENT_LINES);
1339 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1341 struct drm_i915_private *i915 = engine->i915;
1343 /* WaKBLVECSSemaphoreWaitPoll:kbl */
1344 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) {
1346 RING_SEMA_WAIT_POLL(engine->mmio_base),
1352 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
1354 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
1357 if (engine->id == RCS0)
1358 rcs_engine_wa_init(engine, wal);
1360 xcs_engine_wa_init(engine, wal);
1363 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
1365 struct i915_wa_list *wal = &engine->wa_list;
1367 if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
1370 wa_init_start(wal, engine->name);
1371 engine_init_workarounds(engine, wal);
1372 wa_init_finish(wal);
1375 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
1377 wa_list_apply(engine->uncore, &engine->wa_list);
1380 static struct i915_vma *
1381 create_scratch(struct i915_address_space *vm, int count)
1383 struct drm_i915_gem_object *obj;
1384 struct i915_vma *vma;
1388 size = round_up(count * sizeof(u32), PAGE_SIZE);
1389 obj = i915_gem_object_create_internal(vm->i915, size);
1391 return ERR_CAST(obj);
1393 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1395 vma = i915_vma_instance(obj, vm, NULL);
1401 err = i915_vma_pin(vma, 0, 0,
1402 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
1409 i915_gem_object_put(obj);
1410 return ERR_PTR(err);
1414 wa_list_srm(struct i915_request *rq,
1415 const struct i915_wa_list *wal,
1416 struct i915_vma *vma)
1418 const struct i915_wa *wa;
1422 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1423 if (INTEL_GEN(rq->i915) >= 8)
1426 cs = intel_ring_begin(rq, 4 * wal->count);
1430 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1432 *cs++ = i915_mmio_reg_offset(wa->reg);
1433 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
1436 intel_ring_advance(rq, cs);
1441 static int engine_wa_list_verify(struct intel_context *ce,
1442 const struct i915_wa_list * const wal,
1445 const struct i915_wa *wa;
1446 struct i915_request *rq;
1447 struct i915_vma *vma;
1455 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1457 return PTR_ERR(vma);
1459 rq = intel_context_create_request(ce);
1465 err = wa_list_srm(rq, wal, vma);
1469 i915_request_add(rq);
1470 if (i915_request_wait(rq, 0, HZ / 5) < 0) {
1475 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1476 if (IS_ERR(results)) {
1477 err = PTR_ERR(results);
1482 for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1483 if (!wa_verify(wa, results[i], wal->name, from))
1486 i915_gem_object_unpin_map(vma->obj);
1489 i915_vma_unpin(vma);
1494 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
1497 return engine_wa_list_verify(engine->kernel_context,
1502 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1503 #include "selftest_workarounds.c"