drivers/gpu/drm/i915/display/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
   6  *         Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 #include <drm/i915_drm.h>
  10
  11 #include "i915_drv.h"
  12 #include "intel_drv.h"
  13 #include "intel_vdsc.h"
  14
  15 enum ROW_INDEX_BPP {
  16         ROW_INDEX_6BPP = 0,
  17         ROW_INDEX_8BPP,
  18         ROW_INDEX_10BPP,
  19         ROW_INDEX_12BPP,
  20         ROW_INDEX_15BPP,
  21         MAX_ROW_INDEX
  22 };
  23
  24 enum COLUMN_INDEX_BPC {
  25         COLUMN_INDEX_8BPC = 0,
  26         COLUMN_INDEX_10BPC,
  27         COLUMN_INDEX_12BPC,
  28         COLUMN_INDEX_14BPC,
  29         COLUMN_INDEX_16BPC,
  30         MAX_COLUMN_INDEX
  31 };
  32
  33 #define DSC_SUPPORTED_VERSION_MIN               1
  34
  35 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  36 static u16 rc_buf_thresh[] = {
  37         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  38         7744, 7872, 8000, 8064
  39 };
  40
  41 struct rc_parameters {
  42         u16 initial_xmit_delay;
  43         u8 first_line_bpg_offset;
  44         u16 initial_offset;
  45         u8 flatness_min_qp;
  46         u8 flatness_max_qp;
  47         u8 rc_quant_incr_limit0;
  48         u8 rc_quant_incr_limit1;
  49         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  50 };
  51
  52 /*
  53  * Selected Rate Control Related Parameter Recommended Values
  54  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  55  */
  56 static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
  57 {
  58         /* 6BPP/8BPC */
  59         { 768, 15, 6144, 3, 13, 11, 11, {
  60                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  61                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  62                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  63                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  64                 }
  65         },
  66         /* 6BPP/10BPC */
  67         { 768, 15, 6144, 7, 17, 15, 15, {
  68                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  69                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  70                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  71                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  72                 { 17, 18, -12 }
  73                 }
  74         },
  75         /* 6BPP/12BPC */
  76         { 768, 15, 6144, 11, 21, 19, 19, {
  77                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  78                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  79                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  80                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  81                 { 21, 22, -12 }
  82                 }
  83         },
  84         /* 6BPP/14BPC */
  85         { 768, 15, 6144, 15, 25, 23, 27, {
  86                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  87                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  88                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  89                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  90                 { 25, 26, -12 }
  91                 }
  92         },
  93         /* 6BPP/16BPC */
  94         { 768, 15, 6144, 19, 29, 27, 27, {
  95                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  96                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  97                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  98                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  99                 { 29, 30, -12 }
 100                 }
 101         },
 102 },
 103 {
 104         /* 8BPP/8BPC */
 105         { 512, 12, 6144, 3, 12, 11, 11, {
 106                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 107                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 108                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 109                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 110                 }
 111         },
 112         /* 8BPP/10BPC */
 113         { 512, 12, 6144, 7, 16, 15, 15, {
 114                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 115                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 116                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 117                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 118                 }
 119         },
 120         /* 8BPP/12BPC */
 121         { 512, 12, 6144, 11, 20, 19, 19, {
 122                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 123                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 124                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 125                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 126                 { 21, 23, -12 }
 127                 }
 128         },
 129         /* 8BPP/14BPC */
 130         { 512, 12, 6144, 15, 24, 23, 23, {
 131                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 132                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 133                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 134                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 135                 { 24, 25, -12 }
 136                 }
 137         },
 138         /* 8BPP/16BPC */
 139         { 512, 12, 6144, 19, 28, 27, 27, {
 140                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 141                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 142                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 143                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 144                 { 28, 29, -12 }
 145                 }
 146         },
 147 },
 148 {
 149         /* 10BPP/8BPC */
 150         { 410, 15, 5632, 3, 12, 11, 11, {
 151                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 152                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 153                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 154                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 155                 }
 156         },
 157         /* 10BPP/10BPC */
 158         { 410, 15, 5632, 7, 16, 15, 15, {
 159                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 160                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 161                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 162                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 163                 }
 164         },
 165         /* 10BPP/12BPC */
 166         { 410, 15, 5632, 11, 20, 19, 19, {
 167                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 168                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 169                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 170                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 171                 { 19, 20, -12 }
 172                 }
 173         },
 174         /* 10BPP/14BPC */
 175         { 410, 15, 5632, 15, 24, 23, 23, {
 176                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 177                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 178                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 179                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 180                 { 23, 24, -12 }
 181                 }
 182         },
 183         /* 10BPP/16BPC */
 184         { 410, 15, 5632, 19, 28, 27, 27, {
 185                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 186                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 187                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 188                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 189                 { 27, 28, -12 }
 190                 }
 191         },
 192 },
 193 {
 194         /* 12BPP/8BPC */
 195         { 341, 15, 2048, 3, 12, 11, 11, {
 196                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 197                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 198                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 199                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 200                 }
 201         },
 202         /* 12BPP/10BPC */
 203         { 341, 15, 2048, 7, 16, 15, 15, {
 204                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 205                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 206                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 207                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 208                 }
 209         },
 210         /* 12BPP/12BPC */
 211         { 341, 15, 2048, 11, 20, 19, 19, {
 212                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 213                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 214                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 215                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 216                 { 21, 23, -12 }
 217                 }
 218         },
 219         /* 12BPP/14BPC */
 220         { 341, 15, 2048, 15, 24, 23, 23, {
 221                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 222                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 223                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 224                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 225                 { 22, 23, -12 }
 226                 }
 227         },
 228         /* 12BPP/16BPC */
 229         { 341, 15, 2048, 19, 28, 27, 27, {
 230                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 231                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 232                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 233                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 234                 { 26, 27, -12 }
 235                 }
 236         },
 237 },
 238 {
 239         /* 15BPP/8BPC */
 240         { 273, 15, 2048, 3, 12, 11, 11, {
 241                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 242                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 243                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 244                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 245                 }
 246         },
 247         /* 15BPP/10BPC */
 248         { 273, 15, 2048, 7, 16, 15, 15, {
 249                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 250                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 251                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 252                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 253                 }
 254         },
 255         /* 15BPP/12BPC */
 256         { 273, 15, 2048, 11, 20, 19, 19, {
 257                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 258                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 259                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 260                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 261                 { 16, 17, -12 }
 262                 }
 263         },
 264         /* 15BPP/14BPC */
 265         { 273, 15, 2048, 15, 24, 23, 23, {
 266                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 267                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 268                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 269                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 270                 { 20, 21, -12 }
 271                 }
 272         },
 273         /* 15BPP/16BPC */
 274         { 273, 15, 2048, 19, 28, 27, 27, {
 275                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 276                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 277                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 278                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 279                 { 24, 25, -12 }
 280                 }
 281         }
 282 }
 283
 284 };
 285
 286 static int get_row_index_for_rc_params(u16 compressed_bpp)
 287 {
 288         switch (compressed_bpp) {
 289         case 6:
 290                 return ROW_INDEX_6BPP;
 291         case 8:
 292                 return ROW_INDEX_8BPP;
 293         case 10:
 294                 return ROW_INDEX_10BPP;
 295         case 12:
 296                 return ROW_INDEX_12BPP;
 297         case 15:
 298                 return ROW_INDEX_15BPP;
 299         default:
 300                 return -EINVAL;
 301         }
 302 }
 303
 304 static int get_column_index_for_rc_params(u8 bits_per_component)
 305 {
 306         switch (bits_per_component) {
 307         case 8:
 308                 return COLUMN_INDEX_8BPC;
 309         case 10:
 310                 return COLUMN_INDEX_10BPC;
 311         case 12:
 312                 return COLUMN_INDEX_12BPC;
 313         case 14:
 314                 return COLUMN_INDEX_14BPC;
 315         case 16:
 316                 return COLUMN_INDEX_16BPC;
 317         default:
 318                 return -EINVAL;
 319         }
 320 }
 321
 322 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 323                                 struct intel_crtc_state *pipe_config)
 324 {
 325         struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
 326         u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
 327         u8 i = 0;
 328         int row_index = 0;
 329         int column_index = 0;
 330         u8 line_buf_depth = 0;
 331
 332         vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
 333         vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
 334         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 335                                              pipe_config->dsc_params.slice_count);
 336         /*
 337          * Slice Height of 8 works for all currently available panels. So start
 338          * with that if pic_height is an integral multiple of 8.
 339          * Eventually add logic to try multiple slice heights.
 340          */
 341         if (vdsc_cfg->pic_height % 8 == 0)
 342                 vdsc_cfg->slice_height = 8;
 343         else if (vdsc_cfg->pic_height % 4 == 0)
 344                 vdsc_cfg->slice_height = 4;
 345         else
 346                 vdsc_cfg->slice_height = 2;
 347
 348         /* Values filled from DSC Sink DPCD */
 349         vdsc_cfg->dsc_version_major =
 350                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 351                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
 352         vdsc_cfg->dsc_version_minor =
 353                 min(DSC_SUPPORTED_VERSION_MIN,
 354                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 355                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
 356
 357         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
 358                 DP_DSC_RGB;
 359
 360         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 361         if (!line_buf_depth) {
 362                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
 363                 return -EINVAL;
 364         }
 365         if (vdsc_cfg->dsc_version_minor == 2)
 366                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
 367                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
 368         else
 369                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
 370                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 371
 372         /* Gen 11 does not support YCbCr */
 373         vdsc_cfg->simple_422 = false;
 374         /* Gen 11 does not support VBR */
 375         vdsc_cfg->vbr_enable = false;
 376         vdsc_cfg->block_pred_enable =
 377                         intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
 378                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 379
 380         /* Gen 11 only supports integral values of bpp */
 381         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 382         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 383
 384         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 385                 /*
 386                  * six 0s are appended to the lsb of each threshold value
 387                  * internally in h/w.
 388                  * Only 8 bits are allowed for programming RcBufThreshold
 389                  */
 390                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 391         }
 392
 393         /*
 394          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 395          * as per C Model
 396          */
 397         if (compressed_bpp == 6) {
 398                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 399                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 400         }
 401
 402         row_index = get_row_index_for_rc_params(compressed_bpp);
 403         column_index =
 404                 get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
 405
 406         if (row_index < 0 || column_index < 0)
 407                 return -EINVAL;
 408
 409         vdsc_cfg->first_line_bpg_offset =
 410                 rc_params[row_index][column_index].first_line_bpg_offset;
 411         vdsc_cfg->initial_xmit_delay =
 412                 rc_params[row_index][column_index].initial_xmit_delay;
 413         vdsc_cfg->initial_offset =
 414                 rc_params[row_index][column_index].initial_offset;
 415         vdsc_cfg->flatness_min_qp =
 416                 rc_params[row_index][column_index].flatness_min_qp;
 417         vdsc_cfg->flatness_max_qp =
 418                 rc_params[row_index][column_index].flatness_max_qp;
 419         vdsc_cfg->rc_quant_incr_limit0 =
 420                 rc_params[row_index][column_index].rc_quant_incr_limit0;
 421         vdsc_cfg->rc_quant_incr_limit1 =
 422                 rc_params[row_index][column_index].rc_quant_incr_limit1;
 423
 424         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 425                 vdsc_cfg->rc_range_params[i].range_min_qp =
 426                         rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
 427                 vdsc_cfg->rc_range_params[i].range_max_qp =
 428                         rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
 429                 /*
 430                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 431                  * mask it to get only 6 bits.
 432                  */
 433                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 434                         rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
 435                         DSC_RANGE_BPG_OFFSET_MASK;
 436         }
 437
 438         /*
 439          * BitsPerComponent value determines mux_word_size:
 440          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 441          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 442          * 48 bits
 443          */
 444         if (vdsc_cfg->bits_per_component == 8 ||
 445             vdsc_cfg->bits_per_component == 10)
 446                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 447         else if (vdsc_cfg->bits_per_component == 12)
 448                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 449
 450         /* RC_MODEL_SIZE is a constant across all configurations */
 451         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 452         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 453         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 454                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 455
 456         return drm_dsc_compute_rc_parameters(vdsc_cfg);
 457 }
 458
 459 enum intel_display_power_domain
 460 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 461 {
 462         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 463
 464         /*
 465          * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
 466          * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
 467          * For any other transcoder, VDSC/joining uses the power well associated
 468          * with the pipe/transcoder in use. Hence another reference on the
 469          * transcoder power domain will suffice.
 470          */
 471         if (cpu_transcoder == TRANSCODER_EDP)
 472                 return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
 473         else
 474                 return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 475 }
 476
 477 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 478                                                 const struct intel_crtc_state *crtc_state)
 479 {
 480         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 482         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 483         enum pipe pipe = crtc->pipe;
 484         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 485         u32 pps_val = 0;
 486         u32 rc_buf_thresh_dword[4];
 487         u32 rc_range_params_dword[8];
 488         u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
 489         int i = 0;
 490
 491         /* Populate PICTURE_PARAMETER_SET_0 registers */
 492         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 493                 DSC_VER_MIN_SHIFT |
 494                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 495                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 496         if (vdsc_cfg->block_pred_enable)
 497                 pps_val |= DSC_BLOCK_PREDICTION;
 498         if (vdsc_cfg->convert_rgb)
 499                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 500         if (vdsc_cfg->simple_422)
 501                 pps_val |= DSC_422_ENABLE;
 502         if (vdsc_cfg->vbr_enable)
 503                 pps_val |= DSC_VBR_ENABLE;
 504         DRM_INFO("PPS0 = 0x%08x\n", pps_val);
 505         if (cpu_transcoder == TRANSCODER_EDP) {
 506                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
 507                 /*
 508                  * If 2 VDSC instances are needed, configure PPS for second
 509                  * VDSC
 510                  */
 511                 if (crtc_state->dsc_params.dsc_split)
 512                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
 513         } else {
 514                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
 515                 if (crtc_state->dsc_params.dsc_split)
 516                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 517                                    pps_val);
 518         }
 519
 520         /* Populate PICTURE_PARAMETER_SET_1 registers */
 521         pps_val = 0;
 522         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 523         DRM_INFO("PPS1 = 0x%08x\n", pps_val);
 524         if (cpu_transcoder == TRANSCODER_EDP) {
 525                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
 526                 /*
 527                  * If 2 VDSC instances are needed, configure PPS for second
 528                  * VDSC
 529                  */
 530                 if (crtc_state->dsc_params.dsc_split)
 531                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
 532         } else {
 533                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
 534                 if (crtc_state->dsc_params.dsc_split)
 535                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 536                                    pps_val);
 537         }
 538
 539         /* Populate PICTURE_PARAMETER_SET_2 registers */
 540         pps_val = 0;
 541         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 542                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 543         DRM_INFO("PPS2 = 0x%08x\n", pps_val);
 544         if (encoder->type == INTEL_OUTPUT_EDP) {
 545                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
 546                 /*
 547                  * If 2 VDSC instances are needed, configure PPS for second
 548                  * VDSC
 549                  */
 550                 if (crtc_state->dsc_params.dsc_split)
 551                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
 552         } else {
 553                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
 554                 if (crtc_state->dsc_params.dsc_split)
 555                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 556                                    pps_val);
 557         }
 558
 559         /* Populate PICTURE_PARAMETER_SET_3 registers */
 560         pps_val = 0;
 561         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 562                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 563         DRM_INFO("PPS3 = 0x%08x\n", pps_val);
 564         if (cpu_transcoder == TRANSCODER_EDP) {
 565                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
 566                 /*
 567                  * If 2 VDSC instances are needed, configure PPS for second
 568                  * VDSC
 569                  */
 570                 if (crtc_state->dsc_params.dsc_split)
 571                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
 572         } else {
 573                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
 574                 if (crtc_state->dsc_params.dsc_split)
 575                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 576                                    pps_val);
 577         }
 578
 579         /* Populate PICTURE_PARAMETER_SET_4 registers */
 580         pps_val = 0;
 581         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 582                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 583         DRM_INFO("PPS4 = 0x%08x\n", pps_val);
 584         if (cpu_transcoder == TRANSCODER_EDP) {
 585                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
 586                 /*
 587                  * If 2 VDSC instances are needed, configure PPS for second
 588                  * VDSC
 589                  */
 590                 if (crtc_state->dsc_params.dsc_split)
 591                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
 592         } else {
 593                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
 594                 if (crtc_state->dsc_params.dsc_split)
 595                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 596                                    pps_val);
 597         }
 598
 599         /* Populate PICTURE_PARAMETER_SET_5 registers */
 600         pps_val = 0;
 601         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 602                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 603         DRM_INFO("PPS5 = 0x%08x\n", pps_val);
 604         if (cpu_transcoder == TRANSCODER_EDP) {
 605                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
 606                 /*
 607                  * If 2 VDSC instances are needed, configure PPS for second
 608                  * VDSC
 609                  */
 610                 if (crtc_state->dsc_params.dsc_split)
 611                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
 612         } else {
 613                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
 614                 if (crtc_state->dsc_params.dsc_split)
 615                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 616                                    pps_val);
 617         }
 618
 619         /* Populate PICTURE_PARAMETER_SET_6 registers */
 620         pps_val = 0;
 621         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 622                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 623                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 624                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 625         DRM_INFO("PPS6 = 0x%08x\n", pps_val);
 626         if (cpu_transcoder == TRANSCODER_EDP) {
 627                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
 628                 /*
 629                  * If 2 VDSC instances are needed, configure PPS for second
 630                  * VDSC
 631                  */
 632                 if (crtc_state->dsc_params.dsc_split)
 633                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
 634         } else {
 635                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
 636                 if (crtc_state->dsc_params.dsc_split)
 637                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 638                                    pps_val);
 639         }
 640
 641         /* Populate PICTURE_PARAMETER_SET_7 registers */
 642         pps_val = 0;
 643         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 644                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 645         DRM_INFO("PPS7 = 0x%08x\n", pps_val);
 646         if (cpu_transcoder == TRANSCODER_EDP) {
 647                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
 648                 /*
 649                  * If 2 VDSC instances are needed, configure PPS for second
 650                  * VDSC
 651                  */
 652                 if (crtc_state->dsc_params.dsc_split)
 653                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
 654         } else {
 655                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
 656                 if (crtc_state->dsc_params.dsc_split)
 657                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 658                                    pps_val);
 659         }
 660
 661         /* Populate PICTURE_PARAMETER_SET_8 registers */
 662         pps_val = 0;
 663         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 664                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 665         DRM_INFO("PPS8 = 0x%08x\n", pps_val);
 666         if (cpu_transcoder == TRANSCODER_EDP) {
 667                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
 668                 /*
 669                  * If 2 VDSC instances are needed, configure PPS for second
 670                  * VDSC
 671                  */
 672                 if (crtc_state->dsc_params.dsc_split)
 673                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
 674         } else {
 675                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
 676                 if (crtc_state->dsc_params.dsc_split)
 677                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 678                                    pps_val);
 679         }
 680
 681         /* Populate PICTURE_PARAMETER_SET_9 registers */
 682         pps_val = 0;
 683         pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
 684                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 685         DRM_INFO("PPS9 = 0x%08x\n", pps_val);
 686         if (cpu_transcoder == TRANSCODER_EDP) {
 687                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
 688                 /*
 689                  * If 2 VDSC instances are needed, configure PPS for second
 690                  * VDSC
 691                  */
 692                 if (crtc_state->dsc_params.dsc_split)
 693                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
 694         } else {
 695                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
 696                 if (crtc_state->dsc_params.dsc_split)
 697                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 698                                    pps_val);
 699         }
 700
 701         /* Populate PICTURE_PARAMETER_SET_10 registers */
 702         pps_val = 0;
 703         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 704                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 705                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 706                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 707         DRM_INFO("PPS10 = 0x%08x\n", pps_val);
 708         if (cpu_transcoder == TRANSCODER_EDP) {
 709                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
 710                 /*
 711                  * If 2 VDSC instances are needed, configure PPS for second
 712                  * VDSC
 713                  */
 714                 if (crtc_state->dsc_params.dsc_split)
 715                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 716         } else {
 717                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
 718                 if (crtc_state->dsc_params.dsc_split)
 719                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 720                                    pps_val);
 721         }
 722
 723         /* Populate Picture parameter set 16 */
 724         pps_val = 0;
 725         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 726                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 727                                    vdsc_cfg->slice_width) |
 728                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 729                                         vdsc_cfg->slice_height);
 730         DRM_INFO("PPS16 = 0x%08x\n", pps_val);
 731         if (cpu_transcoder == TRANSCODER_EDP) {
 732                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
 733                 /*
 734                  * If 2 VDSC instances are needed, configure PPS for second
 735                  * VDSC
 736                  */
 737                 if (crtc_state->dsc_params.dsc_split)
 738                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 739         } else {
 740                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
 741                 if (crtc_state->dsc_params.dsc_split)
 742                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 743                                    pps_val);
 744         }
 745
 746         /* Populate the RC_BUF_THRESH registers */
 747         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 748         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 749                 rc_buf_thresh_dword[i / 4] |=
 750                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 751                               BITS_PER_BYTE * (i % 4));
 752                 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
 753                          rc_buf_thresh_dword[i / 4]);
 754         }
 755         if (cpu_transcoder == TRANSCODER_EDP) {
 756                 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
 757                 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
 758                 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
 759                 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
 760                 if (crtc_state->dsc_params.dsc_split) {
 761                         I915_WRITE(DSCC_RC_BUF_THRESH_0,
 762                                    rc_buf_thresh_dword[0]);
 763                         I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
 764                                    rc_buf_thresh_dword[1]);
 765                         I915_WRITE(DSCC_RC_BUF_THRESH_1,
 766                                    rc_buf_thresh_dword[2]);
 767                         I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
 768                                    rc_buf_thresh_dword[3]);
 769                 }
 770         } else {
 771                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
 772                            rc_buf_thresh_dword[0]);
 773                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 774                            rc_buf_thresh_dword[1]);
 775                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
 776                            rc_buf_thresh_dword[2]);
 777                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 778                            rc_buf_thresh_dword[3]);
 779                 if (crtc_state->dsc_params.dsc_split) {
 780                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
 781                                    rc_buf_thresh_dword[0]);
 782                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 783                                    rc_buf_thresh_dword[1]);
 784                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
 785                                    rc_buf_thresh_dword[2]);
 786                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 787                                    rc_buf_thresh_dword[3]);
 788                 }
 789         }
 790
 791         /* Populate the RC_RANGE_PARAMETERS registers */
 792         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 793         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 794                 rc_range_params_dword[i / 2] |=
 795                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 796                                 RC_BPG_OFFSET_SHIFT) |
 797                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 798                                 RC_MAX_QP_SHIFT) |
 799                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 800                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 801                 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
 802                          rc_range_params_dword[i / 2]);
 803         }
 804         if (cpu_transcoder == TRANSCODER_EDP) {
 805                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
 806                            rc_range_params_dword[0]);
 807                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
 808                            rc_range_params_dword[1]);
 809                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
 810                            rc_range_params_dword[2]);
 811                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
 812                            rc_range_params_dword[3]);
 813                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
 814                            rc_range_params_dword[4]);
 815                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
 816                            rc_range_params_dword[5]);
 817                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
 818                            rc_range_params_dword[6]);
 819                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
 820                            rc_range_params_dword[7]);
 821                 if (crtc_state->dsc_params.dsc_split) {
 822                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
 823                                    rc_range_params_dword[0]);
 824                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
 825                                    rc_range_params_dword[1]);
 826                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
 827                                    rc_range_params_dword[2]);
 828                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
 829                                    rc_range_params_dword[3]);
 830                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
 831                                    rc_range_params_dword[4]);
 832                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
 833                                    rc_range_params_dword[5]);
 834                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
 835                                    rc_range_params_dword[6]);
 836                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
 837                                    rc_range_params_dword[7]);
 838                 }
 839         } else {
 840                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 841                            rc_range_params_dword[0]);
 842                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 843                            rc_range_params_dword[1]);
 844                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 845                            rc_range_params_dword[2]);
 846                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 847                            rc_range_params_dword[3]);
 848                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 849                            rc_range_params_dword[4]);
 850                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 851                            rc_range_params_dword[5]);
 852                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 853                            rc_range_params_dword[6]);
 854                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 855                            rc_range_params_dword[7]);
 856                 if (crtc_state->dsc_params.dsc_split) {
 857                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 858                                    rc_range_params_dword[0]);
 859                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 860                                    rc_range_params_dword[1]);
 861                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 862                                    rc_range_params_dword[2]);
 863                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 864                                    rc_range_params_dword[3]);
 865                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 866                                    rc_range_params_dword[4]);
 867                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 868                                    rc_range_params_dword[5]);
 869                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 870                                    rc_range_params_dword[6]);
 871                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 872                                    rc_range_params_dword[7]);
 873                 }
 874         }
 875 }
 876
 877 static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 878                                        const struct intel_crtc_state *crtc_state)
 879 {
 880         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 881         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 882         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 883         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
 884
 885         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
 886         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
 887
 888         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
 889         drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
 890
 891         intel_dig_port->write_infoframe(encoder, crtc_state,
 892                                         DP_SDP_PPS, &dp_dsc_pps_sdp,
 893                                         sizeof(dp_dsc_pps_sdp));
 894 }
 895
 896 void intel_dsc_enable(struct intel_encoder *encoder,
 897                       const struct intel_crtc_state *crtc_state)
 898 {
 899         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 900         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 901         enum pipe pipe = crtc->pipe;
 902         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 903         u32 dss_ctl1_val = 0;
 904         u32 dss_ctl2_val = 0;
 905
 906         if (!crtc_state->dsc_params.compression_enable)
 907                 return;
 908
 909         /* Enable Power wells for VDSC/joining */
 910         intel_display_power_get(dev_priv,
 911                                 intel_dsc_power_domain(crtc_state));
 912
 913         intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 914
 915         intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
 916
 917         if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 918                 dss_ctl1_reg = DSS_CTL1;
 919                 dss_ctl2_reg = DSS_CTL2;
 920         } else {
 921                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 922                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 923         }
 924         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
 925         if (crtc_state->dsc_params.dsc_split) {
 926                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
 927                 dss_ctl1_val |= JOINER_ENABLE;
 928         }
 929         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 930         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 931 }
 932
 933 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 934 {
 935         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 936         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 937         enum pipe pipe = crtc->pipe;
 938         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 939         u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
 940
 941         if (!old_crtc_state->dsc_params.compression_enable)
 942                 return;
 943
 944         if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 945                 dss_ctl1_reg = DSS_CTL1;
 946                 dss_ctl2_reg = DSS_CTL2;
 947         } else {
 948                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 949                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 950         }
 951         dss_ctl1_val = I915_READ(dss_ctl1_reg);
 952         if (dss_ctl1_val & JOINER_ENABLE)
 953                 dss_ctl1_val &= ~JOINER_ENABLE;
 954         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 955
 956         dss_ctl2_val = I915_READ(dss_ctl2_reg);
 957         if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
 958             dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
 959                 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
 960                                   RIGHT_BRANCH_VDSC_ENABLE);
 961         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 962
 963         /* Disable Power wells for VDSC/joining */
 964         intel_display_power_put_unchecked(dev_priv,
 965                                           intel_dsc_power_domain(old_crtc_state));
 966 }