drivers/gpu/drm/i915/display/intel_dpll_mgr.c

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_dpio_phy.h"
  25 #include "intel_dpll_mgr.h"
  26 #include "intel_drv.h"
  27
  28 /**
  29  * DOC: Display PLLs
  30  *
  31  * Display PLLs used for driving outputs vary by platform. While some have
  32  * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
  33  * from a pool. In the latter scenario, it is possible that multiple pipes
  34  * share a PLL if their configurations match.
  35  *
  36  * This file provides an abstraction over display PLLs. The function
  37  * intel_shared_dpll_init() initializes the PLLs for the given platform.  The
  38  * users of a PLL are tracked and that tracking is integrated with the atomic
  39  * modset interface. During an atomic operation, required PLLs can be reserved
  40  * for a given CRTC and encoder configuration by calling
  41  * intel_reserve_shared_dplls() and previously reserved PLLs can be released
  42  * with intel_release_shared_dplls().
  43  * Changes to the users are first staged in the atomic state, and then made
  44  * effective by calling intel_shared_dpll_swap_state() during the atomic
  45  * commit phase.
  46  */
  47
  48 static void
  49 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
  50                                   struct intel_shared_dpll_state *shared_dpll)
  51 {
  52         enum intel_dpll_id i;
  53
  54         /* Copy shared dpll state */
  55         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  56                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  57
  58                 shared_dpll[i] = pll->state;
  59         }
  60 }
  61
  62 static struct intel_shared_dpll_state *
  63 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
  64 {
  65         struct intel_atomic_state *state = to_intel_atomic_state(s);
  66
  67         WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
  68
  69         if (!state->dpll_set) {
  70                 state->dpll_set = true;
  71
  72                 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
  73                                                   state->shared_dpll);
  74         }
  75
  76         return state->shared_dpll;
  77 }
  78
  79 /**
  80  * intel_get_shared_dpll_by_id - get a DPLL given its id
  81  * @dev_priv: i915 device instance
  82  * @id: pll id
  83  *
  84  * Returns:
  85  * A pointer to the DPLL with @id
  86  */
  87 struct intel_shared_dpll *
  88 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
  89                             enum intel_dpll_id id)
  90 {
  91         return &dev_priv->shared_dplls[id];
  92 }
  93
  94 /**
  95  * intel_get_shared_dpll_id - get the id of a DPLL
  96  * @dev_priv: i915 device instance
  97  * @pll: the DPLL
  98  *
  99  * Returns:
 100  * The id of @pll
 101  */
 102 enum intel_dpll_id
 103 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 104                          struct intel_shared_dpll *pll)
 105 {
 106         if (WARN_ON(pll < dev_priv->shared_dplls||
 107                     pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
 108                 return -1;
 109
 110         return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
 111 }
 112
 113 /* For ILK+ */
 114 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 115                         struct intel_shared_dpll *pll,
 116                         bool state)
 117 {
 118         bool cur_state;
 119         struct intel_dpll_hw_state hw_state;
 120
 121         if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
 122                 return;
 123
 124         cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
 125         I915_STATE_WARN(cur_state != state,
 126              "%s assertion failure (expected %s, current %s)\n",
 127                         pll->info->name, onoff(state), onoff(cur_state));
 128 }
 129
 130 /**
 131  * intel_prepare_shared_dpll - call a dpll's prepare hook
 132  * @crtc_state: CRTC, and its state, which has a shared dpll
 133  *
 134  * This calls the PLL's prepare hook if it has one and if the PLL is not
 135  * already enabled. The prepare hook is platform specific.
 136  */
 137 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
 138 {
 139         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 140         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 141         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 142
 143         if (WARN_ON(pll == NULL))
 144                 return;
 145
 146         mutex_lock(&dev_priv->dpll_lock);
 147         WARN_ON(!pll->state.crtc_mask);
 148         if (!pll->active_mask) {
 149                 DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
 150                 WARN_ON(pll->on);
 151                 assert_shared_dpll_disabled(dev_priv, pll);
 152
 153                 pll->info->funcs->prepare(dev_priv, pll);
 154         }
 155         mutex_unlock(&dev_priv->dpll_lock);
 156 }
 157
 158 /**
 159  * intel_enable_shared_dpll - enable a CRTC's shared DPLL
 160  * @crtc_state: CRTC, and its state, which has a shared DPLL
 161  *
 162  * Enable the shared DPLL used by @crtc.
 163  */
 164 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 165 {
 166         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 167         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 168         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 169         unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
 170         unsigned int old_mask;
 171
 172         if (WARN_ON(pll == NULL))
 173                 return;
 174
 175         mutex_lock(&dev_priv->dpll_lock);
 176         old_mask = pll->active_mask;
 177
 178         if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
 179             WARN_ON(pll->active_mask & crtc_mask))
 180                 goto out;
 181
 182         pll->active_mask |= crtc_mask;
 183
 184         DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
 185                       pll->info->name, pll->active_mask, pll->on,
 186                       crtc->base.base.id);
 187
 188         if (old_mask) {
 189                 WARN_ON(!pll->on);
 190                 assert_shared_dpll_enabled(dev_priv, pll);
 191                 goto out;
 192         }
 193         WARN_ON(pll->on);
 194
 195         DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
 196         pll->info->funcs->enable(dev_priv, pll);
 197         pll->on = true;
 198
 199 out:
 200         mutex_unlock(&dev_priv->dpll_lock);
 201 }
 202
 203 /**
 204  * intel_disable_shared_dpll - disable a CRTC's shared DPLL
 205  * @crtc_state: CRTC, and its state, which has a shared DPLL
 206  *
 207  * Disable the shared DPLL used by @crtc.
 208  */
 209 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 210 {
 211         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 212         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 213         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 214         unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
 215
 216         /* PCH only available on ILK+ */
 217         if (INTEL_GEN(dev_priv) < 5)
 218                 return;
 219
 220         if (pll == NULL)
 221                 return;
 222
 223         mutex_lock(&dev_priv->dpll_lock);
 224         if (WARN_ON(!(pll->active_mask & crtc_mask)))
 225                 goto out;
 226
 227         DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
 228                       pll->info->name, pll->active_mask, pll->on,
 229                       crtc->base.base.id);
 230
 231         assert_shared_dpll_enabled(dev_priv, pll);
 232         WARN_ON(!pll->on);
 233
 234         pll->active_mask &= ~crtc_mask;
 235         if (pll->active_mask)
 236                 goto out;
 237
 238         DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
 239         pll->info->funcs->disable(dev_priv, pll);
 240         pll->on = false;
 241
 242 out:
 243         mutex_unlock(&dev_priv->dpll_lock);
 244 }
 245
 246 static struct intel_shared_dpll *
 247 intel_find_shared_dpll(struct intel_atomic_state *state,
 248                        const struct intel_crtc *crtc,
 249                        const struct intel_dpll_hw_state *pll_state,
 250                        enum intel_dpll_id range_min,
 251                        enum intel_dpll_id range_max)
 252 {
 253         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 254         struct intel_shared_dpll *pll, *unused_pll = NULL;
 255         struct intel_shared_dpll_state *shared_dpll;
 256         enum intel_dpll_id i;
 257
 258         shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
 259
 260         for (i = range_min; i <= range_max; i++) {
 261                 pll = &dev_priv->shared_dplls[i];
 262
 263                 /* Only want to check enabled timings first */
 264                 if (shared_dpll[i].crtc_mask == 0) {
 265                         if (!unused_pll)
 266                                 unused_pll = pll;
 267                         continue;
 268                 }
 269
 270                 if (memcmp(pll_state,
 271                            &shared_dpll[i].hw_state,
 272                            sizeof(*pll_state)) == 0) {
 273                         DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
 274                                       crtc->base.base.id, crtc->base.name,
 275                                       pll->info->name,
 276                                       shared_dpll[i].crtc_mask,
 277                                       pll->active_mask);
 278                         return pll;
 279                 }
 280         }
 281
 282         /* Ok no matching timings, maybe there's a free one? */
 283         if (unused_pll) {
 284                 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
 285                               crtc->base.base.id, crtc->base.name,
 286                               unused_pll->info->name);
 287                 return unused_pll;
 288         }
 289
 290         return NULL;
 291 }
 292
 293 static void
 294 intel_reference_shared_dpll(struct intel_atomic_state *state,
 295                             const struct intel_crtc *crtc,
 296                             const struct intel_shared_dpll *pll,
 297                             const struct intel_dpll_hw_state *pll_state)
 298 {
 299         struct intel_shared_dpll_state *shared_dpll;
 300         const enum intel_dpll_id id = pll->info->id;
 301
 302         shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
 303
 304         if (shared_dpll[id].crtc_mask == 0)
 305                 shared_dpll[id].hw_state = *pll_state;
 306
 307         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
 308                          pipe_name(crtc->pipe));
 309
 310         shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
 311 }
 312
 313 static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
 314                                           const struct intel_crtc *crtc,
 315                                           const struct intel_shared_dpll *pll)
 316 {
 317         struct intel_shared_dpll_state *shared_dpll;
 318
 319         shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
 320         shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
 321 }
 322
 323 static void intel_put_dpll(struct intel_atomic_state *state,
 324                            struct intel_crtc *crtc)
 325 {
 326         const struct intel_crtc_state *old_crtc_state =
 327                 intel_atomic_get_old_crtc_state(state, crtc);
 328         struct intel_crtc_state *new_crtc_state =
 329                 intel_atomic_get_new_crtc_state(state, crtc);
 330
 331         new_crtc_state->shared_dpll = NULL;
 332
 333         if (!old_crtc_state->shared_dpll)
 334                 return;
 335
 336         intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
 337 }
 338
 339 /**
 340  * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
 341  * @state: atomic state
 342  *
 343  * This is the dpll version of drm_atomic_helper_swap_state() since the
 344  * helper does not handle driver-specific global state.
 345  *
 346  * For consistency with atomic helpers this function does a complete swap,
 347  * i.e. it also puts the current state into @state, even though there is no
 348  * need for that at this moment.
 349  */
 350 void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
 351 {
 352         struct drm_i915_private *dev_priv = to_i915(state->dev);
 353         struct intel_shared_dpll_state *shared_dpll;
 354         struct intel_shared_dpll *pll;
 355         enum intel_dpll_id i;
 356
 357         if (!to_intel_atomic_state(state)->dpll_set)
 358                 return;
 359
 360         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
 361         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 362                 struct intel_shared_dpll_state tmp;
 363
 364                 pll = &dev_priv->shared_dplls[i];
 365
 366                 tmp = pll->state;
 367                 pll->state = shared_dpll[i];
 368                 shared_dpll[i] = tmp;
 369         }
 370 }
 371
 372 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 373                                       struct intel_shared_dpll *pll,
 374                                       struct intel_dpll_hw_state *hw_state)
 375 {
 376         const enum intel_dpll_id id = pll->info->id;
 377         intel_wakeref_t wakeref;
 378         u32 val;
 379
 380         wakeref = intel_display_power_get_if_enabled(dev_priv,
 381                                                      POWER_DOMAIN_DISPLAY_CORE);
 382         if (!wakeref)
 383                 return false;
 384
 385         val = I915_READ(PCH_DPLL(id));
 386         hw_state->dpll = val;
 387         hw_state->fp0 = I915_READ(PCH_FP0(id));
 388         hw_state->fp1 = I915_READ(PCH_FP1(id));
 389
 390         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 391
 392         return val & DPLL_VCO_ENABLE;
 393 }
 394
 395 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
 396                                  struct intel_shared_dpll *pll)
 397 {
 398         const enum intel_dpll_id id = pll->info->id;
 399
 400         I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
 401         I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
 402 }
 403
 404 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 405 {
 406         u32 val;
 407         bool enabled;
 408
 409         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
 410
 411         val = I915_READ(PCH_DREF_CONTROL);
 412         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 413                             DREF_SUPERSPREAD_SOURCE_MASK));
 414         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 415 }
 416
 417 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 418                                 struct intel_shared_dpll *pll)
 419 {
 420         const enum intel_dpll_id id = pll->info->id;
 421
 422         /* PCH refclock must be enabled first */
 423         ibx_assert_pch_refclk_enabled(dev_priv);
 424
 425         I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
 426
 427         /* Wait for the clocks to stabilize. */
 428         POSTING_READ(PCH_DPLL(id));
 429         udelay(150);
 430
 431         /* The pixel multiplier can only be updated once the
 432          * DPLL is enabled and the clocks are stable.
 433          *
 434          * So write it again.
 435          */
 436         I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
 437         POSTING_READ(PCH_DPLL(id));
 438         udelay(200);
 439 }
 440
 441 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 442                                  struct intel_shared_dpll *pll)
 443 {
 444         const enum intel_dpll_id id = pll->info->id;
 445
 446         I915_WRITE(PCH_DPLL(id), 0);
 447         POSTING_READ(PCH_DPLL(id));
 448         udelay(200);
 449 }
 450
 451 static bool ibx_get_dpll(struct intel_atomic_state *state,
 452                          struct intel_crtc *crtc,
 453                          struct intel_encoder *encoder)
 454 {
 455         struct intel_crtc_state *crtc_state =
 456                 intel_atomic_get_new_crtc_state(state, crtc);
 457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 458         struct intel_shared_dpll *pll;
 459         enum intel_dpll_id i;
 460
 461         if (HAS_PCH_IBX(dev_priv)) {
 462                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
 463                 i = (enum intel_dpll_id) crtc->pipe;
 464                 pll = &dev_priv->shared_dplls[i];
 465
 466                 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
 467                               crtc->base.base.id, crtc->base.name,
 468                               pll->info->name);
 469         } else {
 470                 pll = intel_find_shared_dpll(state, crtc,
 471                                              &crtc_state->dpll_hw_state,
 472                                              DPLL_ID_PCH_PLL_A,
 473                                              DPLL_ID_PCH_PLL_B);
 474         }
 475
 476         if (!pll)
 477                 return false;
 478
 479         /* reference the pll */
 480         intel_reference_shared_dpll(state, crtc,
 481                                     pll, &crtc_state->dpll_hw_state);
 482
 483         crtc_state->shared_dpll = pll;
 484
 485         return true;
 486 }
 487
 488 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
 489                               const struct intel_dpll_hw_state *hw_state)
 490 {
 491         DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 492                       "fp0: 0x%x, fp1: 0x%x\n",
 493                       hw_state->dpll,
 494                       hw_state->dpll_md,
 495                       hw_state->fp0,
 496                       hw_state->fp1);
 497 }
 498
 499 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
 500         .prepare = ibx_pch_dpll_prepare,
 501         .enable = ibx_pch_dpll_enable,
 502         .disable = ibx_pch_dpll_disable,
 503         .get_hw_state = ibx_pch_dpll_get_hw_state,
 504 };
 505
 506 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
 507                                struct intel_shared_dpll *pll)
 508 {
 509         const enum intel_dpll_id id = pll->info->id;
 510
 511         I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
 512         POSTING_READ(WRPLL_CTL(id));
 513         udelay(20);
 514 }
 515
 516 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
 517                                 struct intel_shared_dpll *pll)
 518 {
 519         I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
 520         POSTING_READ(SPLL_CTL);
 521         udelay(20);
 522 }
 523
 524 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
 525                                   struct intel_shared_dpll *pll)
 526 {
 527         const enum intel_dpll_id id = pll->info->id;
 528         u32 val;
 529
 530         val = I915_READ(WRPLL_CTL(id));
 531         I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
 532         POSTING_READ(WRPLL_CTL(id));
 533 }
 534
 535 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
 536                                  struct intel_shared_dpll *pll)
 537 {
 538         u32 val;
 539
 540         val = I915_READ(SPLL_CTL);
 541         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 542         POSTING_READ(SPLL_CTL);
 543 }
 544
 545 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 546                                        struct intel_shared_dpll *pll,
 547                                        struct intel_dpll_hw_state *hw_state)
 548 {
 549         const enum intel_dpll_id id = pll->info->id;
 550         intel_wakeref_t wakeref;
 551         u32 val;
 552
 553         wakeref = intel_display_power_get_if_enabled(dev_priv,
 554                                                      POWER_DOMAIN_DISPLAY_CORE);
 555         if (!wakeref)
 556                 return false;
 557
 558         val = I915_READ(WRPLL_CTL(id));
 559         hw_state->wrpll = val;
 560
 561         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 562
 563         return val & WRPLL_PLL_ENABLE;
 564 }
 565
 566 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
 567                                       struct intel_shared_dpll *pll,
 568                                       struct intel_dpll_hw_state *hw_state)
 569 {
 570         intel_wakeref_t wakeref;
 571         u32 val;
 572
 573         wakeref = intel_display_power_get_if_enabled(dev_priv,
 574                                                      POWER_DOMAIN_DISPLAY_CORE);
 575         if (!wakeref)
 576                 return false;
 577
 578         val = I915_READ(SPLL_CTL);
 579         hw_state->spll = val;
 580
 581         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 582
 583         return val & SPLL_PLL_ENABLE;
 584 }
 585
 586 #define LC_FREQ 2700
 587 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 588
 589 #define P_MIN 2
 590 #define P_MAX 64
 591 #define P_INC 2
 592
 593 /* Constraints for PLL good behavior */
 594 #define REF_MIN 48
 595 #define REF_MAX 400
 596 #define VCO_MIN 2400
 597 #define VCO_MAX 4800
 598
 599 struct hsw_wrpll_rnp {
 600         unsigned p, n2, r2;
 601 };
 602
 603 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
 604 {
 605         unsigned budget;
 606
 607         switch (clock) {
 608         case 25175000:
 609         case 25200000:
 610         case 27000000:
 611         case 27027000:
 612         case 37762500:
 613         case 37800000:
 614         case 40500000:
 615         case 40541000:
 616         case 54000000:
 617         case 54054000:
 618         case 59341000:
 619         case 59400000:
 620         case 72000000:
 621         case 74176000:
 622         case 74250000:
 623         case 81000000:
 624         case 81081000:
 625         case 89012000:
 626         case 89100000:
 627         case 108000000:
 628         case 108108000:
 629         case 111264000:
 630         case 111375000:
 631         case 148352000:
 632         case 148500000:
 633         case 162000000:
 634         case 162162000:
 635         case 222525000:
 636         case 222750000:
 637         case 296703000:
 638         case 297000000:
 639                 budget = 0;
 640                 break;
 641         case 233500000:
 642         case 245250000:
 643         case 247750000:
 644         case 253250000:
 645         case 298000000:
 646                 budget = 1500;
 647                 break;
 648         case 169128000:
 649         case 169500000:
 650         case 179500000:
 651         case 202000000:
 652                 budget = 2000;
 653                 break;
 654         case 256250000:
 655         case 262500000:
 656         case 270000000:
 657         case 272500000:
 658         case 273750000:
 659         case 280750000:
 660         case 281250000:
 661         case 286000000:
 662         case 291750000:
 663                 budget = 4000;
 664                 break;
 665         case 267250000:
 666         case 268500000:
 667                 budget = 5000;
 668                 break;
 669         default:
 670                 budget = 1000;
 671                 break;
 672         }
 673
 674         return budget;
 675 }
 676
 677 static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
 678                                  unsigned int r2, unsigned int n2,
 679                                  unsigned int p,
 680                                  struct hsw_wrpll_rnp *best)
 681 {
 682         u64 a, b, c, d, diff, diff_best;
 683
 684         /* No best (r,n,p) yet */
 685         if (best->p == 0) {
 686                 best->p = p;
 687                 best->n2 = n2;
 688                 best->r2 = r2;
 689                 return;
 690         }
 691
 692         /*
 693          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 694          * freq2k.
 695          *
 696          * delta = 1e6 *
 697          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 698          *         freq2k;
 699          *
 700          * and we would like delta <= budget.
 701          *
 702          * If the discrepancy is above the PPM-based budget, always prefer to
 703          * improve upon the previous solution.  However, if you're within the
 704          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 705          */
 706         a = freq2k * budget * p * r2;
 707         b = freq2k * budget * best->p * best->r2;
 708         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 709         diff_best = abs_diff(freq2k * best->p * best->r2,
 710                              LC_FREQ_2K * best->n2);
 711         c = 1000000 * diff;
 712         d = 1000000 * diff_best;
 713
 714         if (a < c && b < d) {
 715                 /* If both are above the budget, pick the closer */
 716                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 717                         best->p = p;
 718                         best->n2 = n2;
 719                         best->r2 = r2;
 720                 }
 721         } else if (a >= c && b < d) {
 722                 /* If A is below the threshold but B is above it?  Update. */
 723                 best->p = p;
 724                 best->n2 = n2;
 725                 best->r2 = r2;
 726         } else if (a >= c && b >= d) {
 727                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 728                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 729                         best->p = p;
 730                         best->n2 = n2;
 731                         best->r2 = r2;
 732                 }
 733         }
 734         /* Otherwise a < c && b >= d, do nothing */
 735 }
 736
 737 static void
 738 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 739                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 740 {
 741         u64 freq2k;
 742         unsigned p, n2, r2;
 743         struct hsw_wrpll_rnp best = { 0, 0, 0 };
 744         unsigned budget;
 745
 746         freq2k = clock / 100;
 747
 748         budget = hsw_wrpll_get_budget_for_freq(clock);
 749
 750         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 751          * and directly pass the LC PLL to it. */
 752         if (freq2k == 5400000) {
 753                 *n2_out = 2;
 754                 *p_out = 1;
 755                 *r2_out = 2;
 756                 return;
 757         }
 758
 759         /*
 760          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 761          * the WR PLL.
 762          *
 763          * We want R so that REF_MIN <= Ref <= REF_MAX.
 764          * Injecting R2 = 2 * R gives:
 765          *   REF_MAX * r2 > LC_FREQ * 2 and
 766          *   REF_MIN * r2 < LC_FREQ * 2
 767          *
 768          * Which means the desired boundaries for r2 are:
 769          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 770          *
 771          */
 772         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 773              r2 <= LC_FREQ * 2 / REF_MIN;
 774              r2++) {
 775
 776                 /*
 777                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 778                  *
 779                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 780                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 781                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 782                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 783                  *
 784                  * Which means the desired boundaries for n2 are:
 785                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 786                  */
 787                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 788                      n2 <= VCO_MAX * r2 / LC_FREQ;
 789                      n2++) {
 790
 791                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 792                                 hsw_wrpll_update_rnp(freq2k, budget,
 793                                                      r2, n2, p, &best);
 794                 }
 795         }
 796
 797         *n2_out = best.n2;
 798         *p_out = best.p;
 799         *r2_out = best.r2;
 800 }
 801
 802 static struct intel_shared_dpll *
 803 hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
 804                       struct intel_crtc *crtc)
 805 {
 806         struct intel_crtc_state *crtc_state =
 807                 intel_atomic_get_new_crtc_state(state, crtc);
 808         struct intel_shared_dpll *pll;
 809         u32 val;
 810         unsigned int p, n2, r2;
 811
 812         hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
 813
 814         val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
 815               WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 816               WRPLL_DIVIDER_POST(p);
 817
 818         crtc_state->dpll_hw_state.wrpll = val;
 819
 820         pll = intel_find_shared_dpll(state, crtc,
 821                                      &crtc_state->dpll_hw_state,
 822                                      DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
 823
 824         if (!pll)
 825                 return NULL;
 826
 827         return pll;
 828 }
 829
 830 static struct intel_shared_dpll *
 831 hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 834         struct intel_shared_dpll *pll;
 835         enum intel_dpll_id pll_id;
 836         int clock = crtc_state->port_clock;
 837
 838         switch (clock / 2) {
 839         case 81000:
 840                 pll_id = DPLL_ID_LCPLL_810;
 841                 break;
 842         case 135000:
 843                 pll_id = DPLL_ID_LCPLL_1350;
 844                 break;
 845         case 270000:
 846                 pll_id = DPLL_ID_LCPLL_2700;
 847                 break;
 848         default:
 849                 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
 850                 return NULL;
 851         }
 852
 853         pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
 854
 855         if (!pll)
 856                 return NULL;
 857
 858         return pll;
 859 }
 860
 861 static bool hsw_get_dpll(struct intel_atomic_state *state,
 862                          struct intel_crtc *crtc,
 863                          struct intel_encoder *encoder)
 864 {
 865         struct intel_crtc_state *crtc_state =
 866                 intel_atomic_get_new_crtc_state(state, crtc);
 867         struct intel_shared_dpll *pll;
 868
 869         memset(&crtc_state->dpll_hw_state, 0,
 870                sizeof(crtc_state->dpll_hw_state));
 871
 872         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 873                 pll = hsw_ddi_hdmi_get_dpll(state, crtc);
 874         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
 875                 pll = hsw_ddi_dp_get_dpll(crtc_state);
 876         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 877                 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
 878                         return false;
 879
 880                 crtc_state->dpll_hw_state.spll =
 881                         SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
 882
 883                 pll = intel_find_shared_dpll(state, crtc,
 884                                              &crtc_state->dpll_hw_state,
 885                                              DPLL_ID_SPLL, DPLL_ID_SPLL);
 886         } else {
 887                 return false;
 888         }
 889
 890         if (!pll)
 891                 return false;
 892
 893         intel_reference_shared_dpll(state, crtc,
 894                                     pll, &crtc_state->dpll_hw_state);
 895
 896         crtc_state->shared_dpll = pll;
 897
 898         return true;
 899 }
 900
 901 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
 902                               const struct intel_dpll_hw_state *hw_state)
 903 {
 904         DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
 905                       hw_state->wrpll, hw_state->spll);
 906 }
 907
 908 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
 909         .enable = hsw_ddi_wrpll_enable,
 910         .disable = hsw_ddi_wrpll_disable,
 911         .get_hw_state = hsw_ddi_wrpll_get_hw_state,
 912 };
 913
 914 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
 915         .enable = hsw_ddi_spll_enable,
 916         .disable = hsw_ddi_spll_disable,
 917         .get_hw_state = hsw_ddi_spll_get_hw_state,
 918 };
 919
 920 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
 921                                  struct intel_shared_dpll *pll)
 922 {
 923 }
 924
 925 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
 926                                   struct intel_shared_dpll *pll)
 927 {
 928 }
 929
 930 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
 931                                        struct intel_shared_dpll *pll,
 932                                        struct intel_dpll_hw_state *hw_state)
 933 {
 934         return true;
 935 }
 936
 937 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
 938         .enable = hsw_ddi_lcpll_enable,
 939         .disable = hsw_ddi_lcpll_disable,
 940         .get_hw_state = hsw_ddi_lcpll_get_hw_state,
 941 };
 942
 943 struct skl_dpll_regs {
 944         i915_reg_t ctl, cfgcr1, cfgcr2;
 945 };
 946
 947 /* this array is indexed by the *shared* pll id */
 948 static const struct skl_dpll_regs skl_dpll_regs[4] = {
 949         {
 950                 /* DPLL 0 */
 951                 .ctl = LCPLL1_CTL,
 952                 /* DPLL 0 doesn't support HDMI mode */
 953         },
 954         {
 955                 /* DPLL 1 */
 956                 .ctl = LCPLL2_CTL,
 957                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
 958                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
 959         },
 960         {
 961                 /* DPLL 2 */
 962                 .ctl = WRPLL_CTL(0),
 963                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
 964                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
 965         },
 966         {
 967                 /* DPLL 3 */
 968                 .ctl = WRPLL_CTL(1),
 969                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
 970                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
 971         },
 972 };
 973
 974 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
 975                                     struct intel_shared_dpll *pll)
 976 {
 977         const enum intel_dpll_id id = pll->info->id;
 978         u32 val;
 979
 980         val = I915_READ(DPLL_CTRL1);
 981
 982         val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
 983                  DPLL_CTRL1_SSC(id) |
 984                  DPLL_CTRL1_LINK_RATE_MASK(id));
 985         val |= pll->state.hw_state.ctrl1 << (id * 6);
 986
 987         I915_WRITE(DPLL_CTRL1, val);
 988         POSTING_READ(DPLL_CTRL1);
 989 }
 990
 991 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 992                                struct intel_shared_dpll *pll)
 993 {
 994         const struct skl_dpll_regs *regs = skl_dpll_regs;
 995         const enum intel_dpll_id id = pll->info->id;
 996
 997         skl_ddi_pll_write_ctrl1(dev_priv, pll);
 998
 999         I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
1000         I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
1001         POSTING_READ(regs[id].cfgcr1);
1002         POSTING_READ(regs[id].cfgcr2);
1003
1004         /* the enable bit is always bit 31 */
1005         I915_WRITE(regs[id].ctl,
1006                    I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
1007
1008         if (intel_wait_for_register(&dev_priv->uncore,
1009                                     DPLL_STATUS,
1010                                     DPLL_LOCK(id),
1011                                     DPLL_LOCK(id),
1012                                     5))
1013                 DRM_ERROR("DPLL %d not locked\n", id);
1014 }
1015
1016 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
1017                                  struct intel_shared_dpll *pll)
1018 {
1019         skl_ddi_pll_write_ctrl1(dev_priv, pll);
1020 }
1021
1022 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1023                                 struct intel_shared_dpll *pll)
1024 {
1025         const struct skl_dpll_regs *regs = skl_dpll_regs;
1026         const enum intel_dpll_id id = pll->info->id;
1027
1028         /* the enable bit is always bit 31 */
1029         I915_WRITE(regs[id].ctl,
1030                    I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
1031         POSTING_READ(regs[id].ctl);
1032 }
1033
1034 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
1035                                   struct intel_shared_dpll *pll)
1036 {
1037 }
1038
1039 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1040                                      struct intel_shared_dpll *pll,
1041                                      struct intel_dpll_hw_state *hw_state)
1042 {
1043         u32 val;
1044         const struct skl_dpll_regs *regs = skl_dpll_regs;
1045         const enum intel_dpll_id id = pll->info->id;
1046         intel_wakeref_t wakeref;
1047         bool ret;
1048
1049         wakeref = intel_display_power_get_if_enabled(dev_priv,
1050                                                      POWER_DOMAIN_DISPLAY_CORE);
1051         if (!wakeref)
1052                 return false;
1053
1054         ret = false;
1055
1056         val = I915_READ(regs[id].ctl);
1057         if (!(val & LCPLL_PLL_ENABLE))
1058                 goto out;
1059
1060         val = I915_READ(DPLL_CTRL1);
1061         hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1062
1063         /* avoid reading back stale values if HDMI mode is not enabled */
1064         if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1065                 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1066                 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
1067         }
1068         ret = true;
1069
1070 out:
1071         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1072
1073         return ret;
1074 }
1075
1076 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1077                                        struct intel_shared_dpll *pll,
1078                                        struct intel_dpll_hw_state *hw_state)
1079 {
1080         const struct skl_dpll_regs *regs = skl_dpll_regs;
1081         const enum intel_dpll_id id = pll->info->id;
1082         intel_wakeref_t wakeref;
1083         u32 val;
1084         bool ret;
1085
1086         wakeref = intel_display_power_get_if_enabled(dev_priv,
1087                                                      POWER_DOMAIN_DISPLAY_CORE);
1088         if (!wakeref)
1089                 return false;
1090
1091         ret = false;
1092
1093         /* DPLL0 is always enabled since it drives CDCLK */
1094         val = I915_READ(regs[id].ctl);
1095         if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
1096                 goto out;
1097
1098         val = I915_READ(DPLL_CTRL1);
1099         hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1100
1101         ret = true;
1102
1103 out:
1104         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1105
1106         return ret;
1107 }
1108
1109 struct skl_wrpll_context {
1110         u64 min_deviation;              /* current minimal deviation */
1111         u64 central_freq;               /* chosen central freq */
1112         u64 dco_freq;                   /* chosen dco freq */
1113         unsigned int p;                 /* chosen divider */
1114 };
1115
1116 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1117 {
1118         memset(ctx, 0, sizeof(*ctx));
1119
1120         ctx->min_deviation = U64_MAX;
1121 }
1122
1123 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1124 #define SKL_DCO_MAX_PDEVIATION  100
1125 #define SKL_DCO_MAX_NDEVIATION  600
1126
1127 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1128                                   u64 central_freq,
1129                                   u64 dco_freq,
1130                                   unsigned int divider)
1131 {
1132         u64 deviation;
1133
1134         deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1135                               central_freq);
1136
1137         /* positive deviation */
1138         if (dco_freq >= central_freq) {
1139                 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1140                     deviation < ctx->min_deviation) {
1141                         ctx->min_deviation = deviation;
1142                         ctx->central_freq = central_freq;
1143                         ctx->dco_freq = dco_freq;
1144                         ctx->p = divider;
1145                 }
1146         /* negative deviation */
1147         } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1148                    deviation < ctx->min_deviation) {
1149                 ctx->min_deviation = deviation;
1150                 ctx->central_freq = central_freq;
1151                 ctx->dco_freq = dco_freq;
1152                 ctx->p = divider;
1153         }
1154 }
1155
1156 static void skl_wrpll_get_multipliers(unsigned int p,
1157                                       unsigned int *p0 /* out */,
1158                                       unsigned int *p1 /* out */,
1159                                       unsigned int *p2 /* out */)
1160 {
1161         /* even dividers */
1162         if (p % 2 == 0) {
1163                 unsigned int half = p / 2;
1164
1165                 if (half == 1 || half == 2 || half == 3 || half == 5) {
1166                         *p0 = 2;
1167                         *p1 = 1;
1168                         *p2 = half;
1169                 } else if (half % 2 == 0) {
1170                         *p0 = 2;
1171                         *p1 = half / 2;
1172                         *p2 = 2;
1173                 } else if (half % 3 == 0) {
1174                         *p0 = 3;
1175                         *p1 = half / 3;
1176                         *p2 = 2;
1177                 } else if (half % 7 == 0) {
1178                         *p0 = 7;
1179                         *p1 = half / 7;
1180                         *p2 = 2;
1181                 }
1182         } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1183                 *p0 = 3;
1184                 *p1 = 1;
1185                 *p2 = p / 3;
1186         } else if (p == 5 || p == 7) {
1187                 *p0 = p;
1188                 *p1 = 1;
1189                 *p2 = 1;
1190         } else if (p == 15) {
1191                 *p0 = 3;
1192                 *p1 = 1;
1193                 *p2 = 5;
1194         } else if (p == 21) {
1195                 *p0 = 7;
1196                 *p1 = 1;
1197                 *p2 = 3;
1198         } else if (p == 35) {
1199                 *p0 = 7;
1200                 *p1 = 1;
1201                 *p2 = 5;
1202         }
1203 }
1204
1205 struct skl_wrpll_params {
1206         u32 dco_fraction;
1207         u32 dco_integer;
1208         u32 qdiv_ratio;
1209         u32 qdiv_mode;
1210         u32 kdiv;
1211         u32 pdiv;
1212         u32 central_freq;
1213 };
1214
1215 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1216                                       u64 afe_clock,
1217                                       u64 central_freq,
1218                                       u32 p0, u32 p1, u32 p2)
1219 {
1220         u64 dco_freq;
1221
1222         switch (central_freq) {
1223         case 9600000000ULL:
1224                 params->central_freq = 0;
1225                 break;
1226         case 9000000000ULL:
1227                 params->central_freq = 1;
1228                 break;
1229         case 8400000000ULL:
1230                 params->central_freq = 3;
1231         }
1232
1233         switch (p0) {
1234         case 1:
1235                 params->pdiv = 0;
1236                 break;
1237         case 2:
1238                 params->pdiv = 1;
1239                 break;
1240         case 3:
1241                 params->pdiv = 2;
1242                 break;
1243         case 7:
1244                 params->pdiv = 4;
1245                 break;
1246         default:
1247                 WARN(1, "Incorrect PDiv\n");
1248         }
1249
1250         switch (p2) {
1251         case 5:
1252                 params->kdiv = 0;
1253                 break;
1254         case 2:
1255                 params->kdiv = 1;
1256                 break;
1257         case 3:
1258                 params->kdiv = 2;
1259                 break;
1260         case 1:
1261                 params->kdiv = 3;
1262                 break;
1263         default:
1264                 WARN(1, "Incorrect KDiv\n");
1265         }
1266
1267         params->qdiv_ratio = p1;
1268         params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1269
1270         dco_freq = p0 * p1 * p2 * afe_clock;
1271
1272         /*
1273          * Intermediate values are in Hz.
1274          * Divide by MHz to match bsepc
1275          */
1276         params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1277         params->dco_fraction =
1278                 div_u64((div_u64(dco_freq, 24) -
1279                          params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1280 }
1281
1282 static bool
1283 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1284                         struct skl_wrpll_params *wrpll_params)
1285 {
1286         u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1287         u64 dco_central_freq[3] = { 8400000000ULL,
1288                                     9000000000ULL,
1289                                     9600000000ULL };
1290         static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1291                                              24, 28, 30, 32, 36, 40, 42, 44,
1292                                              48, 52, 54, 56, 60, 64, 66, 68,
1293                                              70, 72, 76, 78, 80, 84, 88, 90,
1294                                              92, 96, 98 };
1295         static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1296         static const struct {
1297                 const int *list;
1298                 int n_dividers;
1299         } dividers[] = {
1300                 { even_dividers, ARRAY_SIZE(even_dividers) },
1301                 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1302         };
1303         struct skl_wrpll_context ctx;
1304         unsigned int dco, d, i;
1305         unsigned int p0, p1, p2;
1306
1307         skl_wrpll_context_init(&ctx);
1308
1309         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1310                 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1311                         for (i = 0; i < dividers[d].n_dividers; i++) {
1312                                 unsigned int p = dividers[d].list[i];
1313                                 u64 dco_freq = p * afe_clock;
1314
1315                                 skl_wrpll_try_divider(&ctx,
1316                                                       dco_central_freq[dco],
1317                                                       dco_freq,
1318                                                       p);
1319                                 /*
1320                                  * Skip the remaining dividers if we're sure to
1321                                  * have found the definitive divider, we can't
1322                                  * improve a 0 deviation.
1323                                  */
1324                                 if (ctx.min_deviation == 0)
1325                                         goto skip_remaining_dividers;
1326                         }
1327                 }
1328
1329 skip_remaining_dividers:
1330                 /*
1331                  * If a solution is found with an even divider, prefer
1332                  * this one.
1333                  */
1334                 if (d == 0 && ctx.p)
1335                         break;
1336         }
1337
1338         if (!ctx.p) {
1339                 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1340                 return false;
1341         }
1342
1343         /*
1344          * gcc incorrectly analyses that these can be used without being
1345          * initialized. To be fair, it's hard to guess.
1346          */
1347         p0 = p1 = p2 = 0;
1348         skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1349         skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1350                                   p0, p1, p2);
1351
1352         return true;
1353 }
1354
1355 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1356 {
1357         u32 ctrl1, cfgcr1, cfgcr2;
1358         struct skl_wrpll_params wrpll_params = { 0, };
1359
1360         /*
1361          * See comment in intel_dpll_hw_state to understand why we always use 0
1362          * as the DPLL id in this function.
1363          */
1364         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1365
1366         ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1367
1368         if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
1369                                      &wrpll_params))
1370                 return false;
1371
1372         cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1373                 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1374                 wrpll_params.dco_integer;
1375
1376         cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1377                 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1378                 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1379                 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1380                 wrpll_params.central_freq;
1381
1382         memset(&crtc_state->dpll_hw_state, 0,
1383                sizeof(crtc_state->dpll_hw_state));
1384
1385         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1386         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1387         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1388         return true;
1389 }
1390
1391 static bool
1392 skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1393 {
1394         u32 ctrl1;
1395
1396         /*
1397          * See comment in intel_dpll_hw_state to understand why we always use 0
1398          * as the DPLL id in this function.
1399          */
1400         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1401         switch (crtc_state->port_clock / 2) {
1402         case 81000:
1403                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1404                 break;
1405         case 135000:
1406                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1407                 break;
1408         case 270000:
1409                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1410                 break;
1411                 /* eDP 1.4 rates */
1412         case 162000:
1413                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1414                 break;
1415         case 108000:
1416                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1417                 break;
1418         case 216000:
1419                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1420                 break;
1421         }
1422
1423         memset(&crtc_state->dpll_hw_state, 0,
1424                sizeof(crtc_state->dpll_hw_state));
1425
1426         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1427
1428         return true;
1429 }
1430
1431 static bool skl_get_dpll(struct intel_atomic_state *state,
1432                          struct intel_crtc *crtc,
1433                          struct intel_encoder *encoder)
1434 {
1435         struct intel_crtc_state *crtc_state =
1436                 intel_atomic_get_new_crtc_state(state, crtc);
1437         struct intel_shared_dpll *pll;
1438         bool bret;
1439
1440         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1441                 bret = skl_ddi_hdmi_pll_dividers(crtc_state);
1442                 if (!bret) {
1443                         DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1444                         return false;
1445                 }
1446         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1447                 bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
1448                 if (!bret) {
1449                         DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1450                         return false;
1451                 }
1452         } else {
1453                 return false;
1454         }
1455
1456         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1457                 pll = intel_find_shared_dpll(state, crtc,
1458                                              &crtc_state->dpll_hw_state,
1459                                              DPLL_ID_SKL_DPLL0,
1460                                              DPLL_ID_SKL_DPLL0);
1461         else
1462                 pll = intel_find_shared_dpll(state, crtc,
1463                                              &crtc_state->dpll_hw_state,
1464                                              DPLL_ID_SKL_DPLL1,
1465                                              DPLL_ID_SKL_DPLL3);
1466         if (!pll)
1467                 return false;
1468
1469         intel_reference_shared_dpll(state, crtc,
1470                                     pll, &crtc_state->dpll_hw_state);
1471
1472         crtc_state->shared_dpll = pll;
1473
1474         return true;
1475 }
1476
1477 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1478                               const struct intel_dpll_hw_state *hw_state)
1479 {
1480         DRM_DEBUG_KMS("dpll_hw_state: "
1481                       "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1482                       hw_state->ctrl1,
1483                       hw_state->cfgcr1,
1484                       hw_state->cfgcr2);
1485 }
1486
1487 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1488         .enable = skl_ddi_pll_enable,
1489         .disable = skl_ddi_pll_disable,
1490         .get_hw_state = skl_ddi_pll_get_hw_state,
1491 };
1492
1493 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1494         .enable = skl_ddi_dpll0_enable,
1495         .disable = skl_ddi_dpll0_disable,
1496         .get_hw_state = skl_ddi_dpll0_get_hw_state,
1497 };
1498
1499 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1500                                 struct intel_shared_dpll *pll)
1501 {
1502         u32 temp;
1503         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1504         enum dpio_phy phy;
1505         enum dpio_channel ch;
1506
1507         bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1508
1509         /* Non-SSC reference */
1510         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1511         temp |= PORT_PLL_REF_SEL;
1512         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1513
1514         if (IS_GEMINILAKE(dev_priv)) {
1515                 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1516                 temp |= PORT_PLL_POWER_ENABLE;
1517                 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1518
1519                 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1520                                  PORT_PLL_POWER_STATE), 200))
1521                         DRM_ERROR("Power state not set for PLL:%d\n", port);
1522         }
1523
1524         /* Disable 10 bit clock */
1525         temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1526         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1527         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1528
1529         /* Write P1 & P2 */
1530         temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1531         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1532         temp |= pll->state.hw_state.ebb0;
1533         I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
1534
1535         /* Write M2 integer */
1536         temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1537         temp &= ~PORT_PLL_M2_MASK;
1538         temp |= pll->state.hw_state.pll0;
1539         I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
1540
1541         /* Write N */
1542         temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1543         temp &= ~PORT_PLL_N_MASK;
1544         temp |= pll->state.hw_state.pll1;
1545         I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
1546
1547         /* Write M2 fraction */
1548         temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1549         temp &= ~PORT_PLL_M2_FRAC_MASK;
1550         temp |= pll->state.hw_state.pll2;
1551         I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
1552
1553         /* Write M2 fraction enable */
1554         temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1555         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1556         temp |= pll->state.hw_state.pll3;
1557         I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
1558
1559         /* Write coeff */
1560         temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1561         temp &= ~PORT_PLL_PROP_COEFF_MASK;
1562         temp &= ~PORT_PLL_INT_COEFF_MASK;
1563         temp &= ~PORT_PLL_GAIN_CTL_MASK;
1564         temp |= pll->state.hw_state.pll6;
1565         I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
1566
1567         /* Write calibration val */
1568         temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1569         temp &= ~PORT_PLL_TARGET_CNT_MASK;
1570         temp |= pll->state.hw_state.pll8;
1571         I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
1572
1573         temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1574         temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1575         temp |= pll->state.hw_state.pll9;
1576         I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
1577
1578         temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1579         temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1580         temp &= ~PORT_PLL_DCO_AMP_MASK;
1581         temp |= pll->state.hw_state.pll10;
1582         I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
1583
1584         /* Recalibrate with new settings */
1585         temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1586         temp |= PORT_PLL_RECALIBRATE;
1587         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1588         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1589         temp |= pll->state.hw_state.ebb4;
1590         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1591
1592         /* Enable PLL */
1593         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1594         temp |= PORT_PLL_ENABLE;
1595         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1596         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1597
1598         if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1599                         200))
1600                 DRM_ERROR("PLL %d not locked\n", port);
1601
1602         if (IS_GEMINILAKE(dev_priv)) {
1603                 temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
1604                 temp |= DCC_DELAY_RANGE_2;
1605                 I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1606         }
1607
1608         /*
1609          * While we write to the group register to program all lanes at once we
1610          * can read only lane registers and we pick lanes 0/1 for that.
1611          */
1612         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1613         temp &= ~LANE_STAGGER_MASK;
1614         temp &= ~LANESTAGGER_STRAP_OVRD;
1615         temp |= pll->state.hw_state.pcsdw12;
1616         I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1617 }
1618
1619 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1620                                         struct intel_shared_dpll *pll)
1621 {
1622         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1623         u32 temp;
1624
1625         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1626         temp &= ~PORT_PLL_ENABLE;
1627         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1628         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1629
1630         if (IS_GEMINILAKE(dev_priv)) {
1631                 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1632                 temp &= ~PORT_PLL_POWER_ENABLE;
1633                 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1634
1635                 if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1636                                 PORT_PLL_POWER_STATE), 200))
1637                         DRM_ERROR("Power state not reset for PLL:%d\n", port);
1638         }
1639 }
1640
1641 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1642                                         struct intel_shared_dpll *pll,
1643                                         struct intel_dpll_hw_state *hw_state)
1644 {
1645         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1646         intel_wakeref_t wakeref;
1647         enum dpio_phy phy;
1648         enum dpio_channel ch;
1649         u32 val;
1650         bool ret;
1651
1652         bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1653
1654         wakeref = intel_display_power_get_if_enabled(dev_priv,
1655                                                      POWER_DOMAIN_DISPLAY_CORE);
1656         if (!wakeref)
1657                 return false;
1658
1659         ret = false;
1660
1661         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1662         if (!(val & PORT_PLL_ENABLE))
1663                 goto out;
1664
1665         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1666         hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1667
1668         hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1669         hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1670
1671         hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1672         hw_state->pll0 &= PORT_PLL_M2_MASK;
1673
1674         hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1675         hw_state->pll1 &= PORT_PLL_N_MASK;
1676
1677         hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1678         hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1679
1680         hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1681         hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1682
1683         hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1684         hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1685                           PORT_PLL_INT_COEFF_MASK |
1686                           PORT_PLL_GAIN_CTL_MASK;
1687
1688         hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1689         hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1690
1691         hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1692         hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1693
1694         hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1695         hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1696                            PORT_PLL_DCO_AMP_MASK;
1697
1698         /*
1699          * While we write to the group register to program all lanes at once we
1700          * can read only lane registers. We configure all lanes the same way, so
1701          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1702          */
1703         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1704         if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
1705                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1706                                  hw_state->pcsdw12,
1707                                  I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
1708         hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1709
1710         ret = true;
1711
1712 out:
1713         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1714
1715         return ret;
1716 }
1717
1718 /* bxt clock parameters */
1719 struct bxt_clk_div {
1720         int clock;
1721         u32 p1;
1722         u32 p2;
1723         u32 m2_int;
1724         u32 m2_frac;
1725         bool m2_frac_en;
1726         u32 n;
1727
1728         int vco;
1729 };
1730
1731 /* pre-calculated values for DP linkrates */
1732 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1733         {162000, 4, 2, 32, 1677722, 1, 1},
1734         {270000, 4, 1, 27,       0, 0, 1},
1735         {540000, 2, 1, 27,       0, 0, 1},
1736         {216000, 3, 2, 32, 1677722, 1, 1},
1737         {243000, 4, 1, 24, 1258291, 1, 1},
1738         {324000, 4, 1, 32, 1677722, 1, 1},
1739         {432000, 3, 1, 32, 1677722, 1, 1}
1740 };
1741
1742 static bool
1743 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
1744                           struct bxt_clk_div *clk_div)
1745 {
1746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1747         struct dpll best_clock;
1748
1749         /* Calculate HDMI div */
1750         /*
1751          * FIXME: tie the following calculation into
1752          * i9xx_crtc_compute_clock
1753          */
1754         if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
1755                 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1756                                  crtc_state->port_clock,
1757                                  pipe_name(crtc->pipe));
1758                 return false;
1759         }
1760
1761         clk_div->p1 = best_clock.p1;
1762         clk_div->p2 = best_clock.p2;
1763         WARN_ON(best_clock.m1 != 2);
1764         clk_div->n = best_clock.n;
1765         clk_div->m2_int = best_clock.m2 >> 22;
1766         clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1767         clk_div->m2_frac_en = clk_div->m2_frac != 0;
1768
1769         clk_div->vco = best_clock.vco;
1770
1771         return true;
1772 }
1773
1774 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
1775                                     struct bxt_clk_div *clk_div)
1776 {
1777         int clock = crtc_state->port_clock;
1778         int i;
1779
1780         *clk_div = bxt_dp_clk_val[0];
1781         for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1782                 if (bxt_dp_clk_val[i].clock == clock) {
1783                         *clk_div = bxt_dp_clk_val[i];
1784                         break;
1785                 }
1786         }
1787
1788         clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1789 }
1790
1791 static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
1792                                       const struct bxt_clk_div *clk_div)
1793 {
1794         struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
1795         int clock = crtc_state->port_clock;
1796         int vco = clk_div->vco;
1797         u32 prop_coef, int_coef, gain_ctl, targ_cnt;
1798         u32 lanestagger;
1799
1800         memset(dpll_hw_state, 0, sizeof(*dpll_hw_state));
1801
1802         if (vco >= 6200000 && vco <= 6700000) {
1803                 prop_coef = 4;
1804                 int_coef = 9;
1805                 gain_ctl = 3;
1806                 targ_cnt = 8;
1807         } else if ((vco > 5400000 && vco < 6200000) ||
1808                         (vco >= 4800000 && vco < 5400000)) {
1809                 prop_coef = 5;
1810                 int_coef = 11;
1811                 gain_ctl = 3;
1812                 targ_cnt = 9;
1813         } else if (vco == 5400000) {
1814                 prop_coef = 3;
1815                 int_coef = 8;
1816                 gain_ctl = 1;
1817                 targ_cnt = 9;
1818         } else {
1819                 DRM_ERROR("Invalid VCO\n");
1820                 return false;
1821         }
1822
1823         if (clock > 270000)
1824                 lanestagger = 0x18;
1825         else if (clock > 135000)
1826                 lanestagger = 0x0d;
1827         else if (clock > 67000)
1828                 lanestagger = 0x07;
1829         else if (clock > 33000)
1830                 lanestagger = 0x04;
1831         else
1832                 lanestagger = 0x02;
1833
1834         dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1835         dpll_hw_state->pll0 = clk_div->m2_int;
1836         dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1837         dpll_hw_state->pll2 = clk_div->m2_frac;
1838
1839         if (clk_div->m2_frac_en)
1840                 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1841
1842         dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1843         dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
1844
1845         dpll_hw_state->pll8 = targ_cnt;
1846
1847         dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1848
1849         dpll_hw_state->pll10 =
1850                 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1851                 | PORT_PLL_DCO_AMP_OVR_EN_H;
1852
1853         dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1854
1855         dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1856
1857         return true;
1858 }
1859
1860 static bool
1861 bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1862 {
1863         struct bxt_clk_div clk_div = {};
1864
1865         bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
1866
1867         return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
1868 }
1869
1870 static bool
1871 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1872 {
1873         struct bxt_clk_div clk_div = {};
1874
1875         bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
1876
1877         return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
1878 }
1879
1880 static bool bxt_get_dpll(struct intel_atomic_state *state,
1881                          struct intel_crtc *crtc,
1882                          struct intel_encoder *encoder)
1883 {
1884         struct intel_crtc_state *crtc_state =
1885                 intel_atomic_get_new_crtc_state(state, crtc);
1886         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1887         struct intel_shared_dpll *pll;
1888         enum intel_dpll_id id;
1889
1890         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1891             !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
1892                 return false;
1893
1894         if (intel_crtc_has_dp_encoder(crtc_state) &&
1895             !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
1896                 return false;
1897
1898         /* 1:1 mapping between ports and PLLs */
1899         id = (enum intel_dpll_id) encoder->port;
1900         pll = intel_get_shared_dpll_by_id(dev_priv, id);
1901
1902         DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1903                       crtc->base.base.id, crtc->base.name, pll->info->name);
1904
1905         intel_reference_shared_dpll(state, crtc,
1906                                     pll, &crtc_state->dpll_hw_state);
1907
1908         crtc_state->shared_dpll = pll;
1909
1910         return true;
1911 }
1912
1913 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
1914                               const struct intel_dpll_hw_state *hw_state)
1915 {
1916         DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
1917                       "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1918                       "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1919                       hw_state->ebb0,
1920                       hw_state->ebb4,
1921                       hw_state->pll0,
1922                       hw_state->pll1,
1923                       hw_state->pll2,
1924                       hw_state->pll3,
1925                       hw_state->pll6,
1926                       hw_state->pll8,
1927                       hw_state->pll9,
1928                       hw_state->pll10,
1929                       hw_state->pcsdw12);
1930 }
1931
1932 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1933         .enable = bxt_ddi_pll_enable,
1934         .disable = bxt_ddi_pll_disable,
1935         .get_hw_state = bxt_ddi_pll_get_hw_state,
1936 };
1937
1938 struct intel_dpll_mgr {
1939         const struct dpll_info *dpll_info;
1940
1941         bool (*get_dplls)(struct intel_atomic_state *state,
1942                           struct intel_crtc *crtc,
1943                           struct intel_encoder *encoder);
1944         void (*put_dplls)(struct intel_atomic_state *state,
1945                           struct intel_crtc *crtc);
1946         void (*update_active_dpll)(struct intel_atomic_state *state,
1947                                    struct intel_crtc *crtc,
1948                                    struct intel_encoder *encoder);
1949         void (*dump_hw_state)(struct drm_i915_private *dev_priv,
1950                               const struct intel_dpll_hw_state *hw_state);
1951 };
1952
1953 static const struct dpll_info pch_plls[] = {
1954         { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
1955         { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
1956         { },
1957 };
1958
1959 static const struct intel_dpll_mgr pch_pll_mgr = {
1960         .dpll_info = pch_plls,
1961         .get_dplls = ibx_get_dpll,
1962         .put_dplls = intel_put_dpll,
1963         .dump_hw_state = ibx_dump_hw_state,
1964 };
1965
1966 static const struct dpll_info hsw_plls[] = {
1967         { "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
1968         { "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
1969         { "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
1970         { "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
1971         { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1972         { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1973         { },
1974 };
1975
1976 static const struct intel_dpll_mgr hsw_pll_mgr = {
1977         .dpll_info = hsw_plls,
1978         .get_dplls = hsw_get_dpll,
1979         .put_dplls = intel_put_dpll,
1980         .dump_hw_state = hsw_dump_hw_state,
1981 };
1982
1983 static const struct dpll_info skl_plls[] = {
1984         { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1985         { "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
1986         { "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
1987         { "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
1988         { },
1989 };
1990
1991 static const struct intel_dpll_mgr skl_pll_mgr = {
1992         .dpll_info = skl_plls,
1993         .get_dplls = skl_get_dpll,
1994         .put_dplls = intel_put_dpll,
1995         .dump_hw_state = skl_dump_hw_state,
1996 };
1997
1998 static const struct dpll_info bxt_plls[] = {
1999         { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2000         { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2001         { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2002         { },
2003 };
2004
2005 static const struct intel_dpll_mgr bxt_pll_mgr = {
2006         .dpll_info = bxt_plls,
2007         .get_dplls = bxt_get_dpll,
2008         .put_dplls = intel_put_dpll,
2009         .dump_hw_state = bxt_dump_hw_state,
2010 };
2011
2012 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2013                                struct intel_shared_dpll *pll)
2014 {
2015         const enum intel_dpll_id id = pll->info->id;
2016         u32 val;
2017
2018         /* 1. Enable DPLL power in DPLL_ENABLE. */
2019         val = I915_READ(CNL_DPLL_ENABLE(id));
2020         val |= PLL_POWER_ENABLE;
2021         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2022
2023         /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
2024         if (intel_wait_for_register(&dev_priv->uncore,
2025                                     CNL_DPLL_ENABLE(id),
2026                                     PLL_POWER_STATE,
2027                                     PLL_POWER_STATE,
2028                                     5))
2029                 DRM_ERROR("PLL %d Power not enabled\n", id);
2030
2031         /*
2032          * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
2033          * select DP mode, and set DP link rate.
2034          */
2035         val = pll->state.hw_state.cfgcr0;
2036         I915_WRITE(CNL_DPLL_CFGCR0(id), val);
2037
2038         /* 4. Reab back to ensure writes completed */
2039         POSTING_READ(CNL_DPLL_CFGCR0(id));
2040
2041         /* 3. Configure DPLL_CFGCR0 */
2042         /* Avoid touch CFGCR1 if HDMI mode is not enabled */
2043         if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
2044                 val = pll->state.hw_state.cfgcr1;
2045                 I915_WRITE(CNL_DPLL_CFGCR1(id), val);
2046                 /* 4. Reab back to ensure writes completed */
2047                 POSTING_READ(CNL_DPLL_CFGCR1(id));
2048         }
2049
2050         /*
2051          * 5. If the frequency will result in a change to the voltage
2052          * requirement, follow the Display Voltage Frequency Switching
2053          * Sequence Before Frequency Change
2054          *
2055          * Note: DVFS is actually handled via the cdclk code paths,
2056          * hence we do nothing here.
2057          */
2058
2059         /* 6. Enable DPLL in DPLL_ENABLE. */
2060         val = I915_READ(CNL_DPLL_ENABLE(id));
2061         val |= PLL_ENABLE;
2062         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2063
2064         /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2065         if (intel_wait_for_register(&dev_priv->uncore,
2066                                     CNL_DPLL_ENABLE(id),
2067                                     PLL_LOCK,
2068                                     PLL_LOCK,
2069                                     5))
2070                 DRM_ERROR("PLL %d not locked\n", id);
2071
2072         /*
2073          * 8. If the frequency will result in a change to the voltage
2074          * requirement, follow the Display Voltage Frequency Switching
2075          * Sequence After Frequency Change
2076          *
2077          * Note: DVFS is actually handled via the cdclk code paths,
2078          * hence we do nothing here.
2079          */
2080
2081         /*
2082          * 9. turn on the clock for the DDI and map the DPLL to the DDI
2083          * Done at intel_ddi_clk_select
2084          */
2085 }
2086
2087 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2088                                 struct intel_shared_dpll *pll)
2089 {
2090         const enum intel_dpll_id id = pll->info->id;
2091         u32 val;
2092
2093         /*
2094          * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2095          * Done at intel_ddi_post_disable
2096          */
2097
2098         /*
2099          * 2. If the frequency will result in a change to the voltage
2100          * requirement, follow the Display Voltage Frequency Switching
2101          * Sequence Before Frequency Change
2102          *
2103          * Note: DVFS is actually handled via the cdclk code paths,
2104          * hence we do nothing here.
2105          */
2106
2107         /* 3. Disable DPLL through DPLL_ENABLE. */
2108         val = I915_READ(CNL_DPLL_ENABLE(id));
2109         val &= ~PLL_ENABLE;
2110         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2111
2112         /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2113         if (intel_wait_for_register(&dev_priv->uncore,
2114                                     CNL_DPLL_ENABLE(id),
2115                                     PLL_LOCK,
2116                                     0,
2117                                     5))
2118                 DRM_ERROR("PLL %d locked\n", id);
2119
2120         /*
2121          * 5. If the frequency will result in a change to the voltage
2122          * requirement, follow the Display Voltage Frequency Switching
2123          * Sequence After Frequency Change
2124          *
2125          * Note: DVFS is actually handled via the cdclk code paths,
2126          * hence we do nothing here.
2127          */
2128
2129         /* 6. Disable DPLL power in DPLL_ENABLE. */
2130         val = I915_READ(CNL_DPLL_ENABLE(id));
2131         val &= ~PLL_POWER_ENABLE;
2132         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2133
2134         /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2135         if (intel_wait_for_register(&dev_priv->uncore,
2136                                     CNL_DPLL_ENABLE(id),
2137                                     PLL_POWER_STATE,
2138                                     0,
2139                                     5))
2140                 DRM_ERROR("PLL %d Power not disabled\n", id);
2141 }
2142
2143 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2144                                      struct intel_shared_dpll *pll,
2145                                      struct intel_dpll_hw_state *hw_state)
2146 {
2147         const enum intel_dpll_id id = pll->info->id;
2148         intel_wakeref_t wakeref;
2149         u32 val;
2150         bool ret;
2151
2152         wakeref = intel_display_power_get_if_enabled(dev_priv,
2153                                                      POWER_DOMAIN_DISPLAY_CORE);
2154         if (!wakeref)
2155                 return false;
2156
2157         ret = false;
2158
2159         val = I915_READ(CNL_DPLL_ENABLE(id));
2160         if (!(val & PLL_ENABLE))
2161                 goto out;
2162
2163         val = I915_READ(CNL_DPLL_CFGCR0(id));
2164         hw_state->cfgcr0 = val;
2165
2166         /* avoid reading back stale values if HDMI mode is not enabled */
2167         if (val & DPLL_CFGCR0_HDMI_MODE) {
2168                 hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
2169         }
2170         ret = true;
2171
2172 out:
2173         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2174
2175         return ret;
2176 }
2177
2178 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2179                                       int *qdiv, int *kdiv)
2180 {
2181         /* even dividers */
2182         if (bestdiv % 2 == 0) {
2183                 if (bestdiv == 2) {
2184                         *pdiv = 2;
2185                         *qdiv = 1;
2186                         *kdiv = 1;
2187                 } else if (bestdiv % 4 == 0) {
2188                         *pdiv = 2;
2189                         *qdiv = bestdiv / 4;
2190                         *kdiv = 2;
2191                 } else if (bestdiv % 6 == 0) {
2192                         *pdiv = 3;
2193                         *qdiv = bestdiv / 6;
2194                         *kdiv = 2;
2195                 } else if (bestdiv % 5 == 0) {
2196                         *pdiv = 5;
2197                         *qdiv = bestdiv / 10;
2198                         *kdiv = 2;
2199                 } else if (bestdiv % 14 == 0) {
2200                         *pdiv = 7;
2201                         *qdiv = bestdiv / 14;
2202                         *kdiv = 2;
2203                 }
2204         } else {
2205                 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2206                         *pdiv = bestdiv;
2207                         *qdiv = 1;
2208                         *kdiv = 1;
2209                 } else { /* 9, 15, 21 */
2210                         *pdiv = bestdiv / 3;
2211                         *qdiv = 1;
2212                         *kdiv = 3;
2213                 }
2214         }
2215 }
2216
2217 static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
2218                                       u32 dco_freq, u32 ref_freq,
2219                                       int pdiv, int qdiv, int kdiv)
2220 {
2221         u32 dco;
2222
2223         switch (kdiv) {
2224         case 1:
2225                 params->kdiv = 1;
2226                 break;
2227         case 2:
2228                 params->kdiv = 2;
2229                 break;
2230         case 3:
2231                 params->kdiv = 4;
2232                 break;
2233         default:
2234                 WARN(1, "Incorrect KDiv\n");
2235         }
2236
2237         switch (pdiv) {
2238         case 2:
2239                 params->pdiv = 1;
2240                 break;
2241         case 3:
2242                 params->pdiv = 2;
2243                 break;
2244         case 5:
2245                 params->pdiv = 4;
2246                 break;
2247         case 7:
2248                 params->pdiv = 8;
2249                 break;
2250         default:
2251                 WARN(1, "Incorrect PDiv\n");
2252         }
2253
2254         WARN_ON(kdiv != 2 && qdiv != 1);
2255
2256         params->qdiv_ratio = qdiv;
2257         params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2258
2259         dco = div_u64((u64)dco_freq << 15, ref_freq);
2260
2261         params->dco_integer = dco >> 15;
2262         params->dco_fraction = dco & 0x7fff;
2263 }
2264
2265 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
2266 {
2267         int ref_clock = dev_priv->cdclk.hw.ref;
2268
2269         /*
2270          * For ICL+, the spec states: if reference frequency is 38.4,
2271          * use 19.2 because the DPLL automatically divides that by 2.
2272          */
2273         if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
2274                 ref_clock = 19200;
2275
2276         return ref_clock;
2277 }
2278
2279 static bool
2280 cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state,
2281                         struct skl_wrpll_params *wrpll_params)
2282 {
2283         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2284         u32 afe_clock = crtc_state->port_clock * 5;
2285         u32 ref_clock;
2286         u32 dco_min = 7998000;
2287         u32 dco_max = 10000000;
2288         u32 dco_mid = (dco_min + dco_max) / 2;
2289         static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
2290                                          18, 20, 24, 28, 30, 32,  36,  40,
2291                                          42, 44, 48, 50, 52, 54,  56,  60,
2292                                          64, 66, 68, 70, 72, 76,  78,  80,
2293                                          84, 88, 90, 92, 96, 98, 100, 102,
2294                                           3,  5,  7,  9, 15, 21 };
2295         u32 dco, best_dco = 0, dco_centrality = 0;
2296         u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2297         int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2298
2299         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2300                 dco = afe_clock * dividers[d];
2301
2302                 if ((dco <= dco_max) && (dco >= dco_min)) {
2303                         dco_centrality = abs(dco - dco_mid);
2304
2305                         if (dco_centrality < best_dco_centrality) {
2306                                 best_dco_centrality = dco_centrality;
2307                                 best_div = dividers[d];
2308                                 best_dco = dco;
2309                         }
2310                 }
2311         }
2312
2313         if (best_div == 0)
2314                 return false;
2315
2316         cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2317
2318         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
2319
2320         cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
2321                                   pdiv, qdiv, kdiv);
2322
2323         return true;
2324 }
2325
2326 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
2327 {
2328         u32 cfgcr0, cfgcr1;
2329         struct skl_wrpll_params wrpll_params = { 0, };
2330
2331         cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2332
2333         if (!cnl_ddi_calculate_wrpll(crtc_state, &wrpll_params))
2334                 return false;
2335
2336         cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2337                 wrpll_params.dco_integer;
2338
2339         cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2340                 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2341                 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2342                 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2343                 DPLL_CFGCR1_CENTRAL_FREQ;
2344
2345         memset(&crtc_state->dpll_hw_state, 0,
2346                sizeof(crtc_state->dpll_hw_state));
2347
2348         crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2349         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2350         return true;
2351 }
2352
2353 static bool
2354 cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2355 {
2356         u32 cfgcr0;
2357
2358         cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2359
2360         switch (crtc_state->port_clock / 2) {
2361         case 81000:
2362                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2363                 break;
2364         case 135000:
2365                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2366                 break;
2367         case 270000:
2368                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2369                 break;
2370                 /* eDP 1.4 rates */
2371         case 162000:
2372                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2373                 break;
2374         case 108000:
2375                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2376                 break;
2377         case 216000:
2378                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2379                 break;
2380         case 324000:
2381                 /* Some SKUs may require elevated I/O voltage to support this */
2382                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2383                 break;
2384         case 405000:
2385                 /* Some SKUs may require elevated I/O voltage to support this */
2386                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2387                 break;
2388         }
2389
2390         memset(&crtc_state->dpll_hw_state, 0,
2391                sizeof(crtc_state->dpll_hw_state));
2392
2393         crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2394
2395         return true;
2396 }
2397
2398 static bool cnl_get_dpll(struct intel_atomic_state *state,
2399                          struct intel_crtc *crtc,
2400                          struct intel_encoder *encoder)
2401 {
2402         struct intel_crtc_state *crtc_state =
2403                 intel_atomic_get_new_crtc_state(state, crtc);
2404         struct intel_shared_dpll *pll;
2405         bool bret;
2406
2407         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2408                 bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
2409                 if (!bret) {
2410                         DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2411                         return false;
2412                 }
2413         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2414                 bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
2415                 if (!bret) {
2416                         DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2417                         return false;
2418                 }
2419         } else {
2420                 DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
2421                               crtc_state->output_types);
2422                 return false;
2423         }
2424
2425         pll = intel_find_shared_dpll(state, crtc,
2426                                      &crtc_state->dpll_hw_state,
2427                                      DPLL_ID_SKL_DPLL0,
2428                                      DPLL_ID_SKL_DPLL2);
2429         if (!pll) {
2430                 DRM_DEBUG_KMS("No PLL selected\n");
2431                 return false;
2432         }
2433
2434         intel_reference_shared_dpll(state, crtc,
2435                                     pll, &crtc_state->dpll_hw_state);
2436
2437         crtc_state->shared_dpll = pll;
2438
2439         return true;
2440 }
2441
2442 static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
2443                               const struct intel_dpll_hw_state *hw_state)
2444 {
2445         DRM_DEBUG_KMS("dpll_hw_state: "
2446                       "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
2447                       hw_state->cfgcr0,
2448                       hw_state->cfgcr1);
2449 }
2450
2451 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2452         .enable = cnl_ddi_pll_enable,
2453         .disable = cnl_ddi_pll_disable,
2454         .get_hw_state = cnl_ddi_pll_get_hw_state,
2455 };
2456
2457 static const struct dpll_info cnl_plls[] = {
2458         { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2459         { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2460         { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2461         { },
2462 };
2463
2464 static const struct intel_dpll_mgr cnl_pll_mgr = {
2465         .dpll_info = cnl_plls,
2466         .get_dplls = cnl_get_dpll,
2467         .put_dplls = intel_put_dpll,
2468         .dump_hw_state = cnl_dump_hw_state,
2469 };
2470
2471 struct icl_combo_pll_params {
2472         int clock;
2473         struct skl_wrpll_params wrpll;
2474 };
2475
2476 /*
2477  * These values alrea already adjusted: they're the bits we write to the
2478  * registers, not the logical values.
2479  */
2480 static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
2481         { 540000,
2482           { .dco_integer = 0x151, .dco_fraction = 0x4000,               /* [0]: 5.4 */
2483             .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2484         { 270000,
2485           { .dco_integer = 0x151, .dco_fraction = 0x4000,               /* [1]: 2.7 */
2486             .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2487         { 162000,
2488           { .dco_integer = 0x151, .dco_fraction = 0x4000,               /* [2]: 1.62 */
2489             .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2490         { 324000,
2491           { .dco_integer = 0x151, .dco_fraction = 0x4000,               /* [3]: 3.24 */
2492             .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2493         { 216000,
2494           { .dco_integer = 0x168, .dco_fraction = 0x0000,               /* [4]: 2.16 */
2495             .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2496         { 432000,
2497           { .dco_integer = 0x168, .dco_fraction = 0x0000,               /* [5]: 4.32 */
2498             .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2499         { 648000,
2500           { .dco_integer = 0x195, .dco_fraction = 0x0000,               /* [6]: 6.48 */
2501             .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2502         { 810000,
2503           { .dco_integer = 0x151, .dco_fraction = 0x4000,               /* [7]: 8.1 */
2504             .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2505 };
2506
2507
2508 /* Also used for 38.4 MHz values. */
2509 static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
2510         { 540000,
2511           { .dco_integer = 0x1A5, .dco_fraction = 0x7000,               /* [0]: 5.4 */
2512             .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2513         { 270000,
2514           { .dco_integer = 0x1A5, .dco_fraction = 0x7000,               /* [1]: 2.7 */
2515             .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2516         { 162000,
2517           { .dco_integer = 0x1A5, .dco_fraction = 0x7000,               /* [2]: 1.62 */
2518             .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2519         { 324000,
2520           { .dco_integer = 0x1A5, .dco_fraction = 0x7000,               /* [3]: 3.24 */
2521             .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2522         { 216000,
2523           { .dco_integer = 0x1C2, .dco_fraction = 0x0000,               /* [4]: 2.16 */
2524             .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2525         { 432000,
2526           { .dco_integer = 0x1C2, .dco_fraction = 0x0000,               /* [5]: 4.32 */
2527             .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2528         { 648000,
2529           { .dco_integer = 0x1FA, .dco_fraction = 0x2000,               /* [6]: 6.48 */
2530             .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2531         { 810000,
2532           { .dco_integer = 0x1A5, .dco_fraction = 0x7000,               /* [7]: 8.1 */
2533             .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2534 };
2535
2536 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2537         .dco_integer = 0x151, .dco_fraction = 0x4000,
2538         .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2539 };
2540
2541 static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2542         .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2543         .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2544 };
2545
2546 static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
2547                                   struct skl_wrpll_params *pll_params)
2548 {
2549         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2550         const struct icl_combo_pll_params *params =
2551                 dev_priv->cdclk.hw.ref == 24000 ?
2552                 icl_dp_combo_pll_24MHz_values :
2553                 icl_dp_combo_pll_19_2MHz_values;
2554         int clock = crtc_state->port_clock;
2555         int i;
2556
2557         for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
2558                 if (clock == params[i].clock) {
2559                         *pll_params = params[i].wrpll;
2560                         return true;
2561                 }
2562         }
2563
2564         MISSING_CASE(clock);
2565         return false;
2566 }
2567
2568 static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
2569                              struct skl_wrpll_params *pll_params)
2570 {
2571         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2572
2573         *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
2574                         icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
2575         return true;
2576 }
2577
2578 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
2579                                 struct intel_encoder *encoder,
2580                                 struct intel_dpll_hw_state *pll_state)
2581 {
2582         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2583         u32 cfgcr0, cfgcr1;
2584         struct skl_wrpll_params pll_params = { 0 };
2585         bool ret;
2586
2587         if (intel_port_is_tc(dev_priv, encoder->port))
2588                 ret = icl_calc_tbt_pll(crtc_state, &pll_params);
2589         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
2590                  intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
2591                 ret = cnl_ddi_calculate_wrpll(crtc_state, &pll_params);
2592         else
2593                 ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
2594
2595         if (!ret)
2596                 return false;
2597
2598         cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
2599                  pll_params.dco_integer;
2600
2601         cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
2602                  DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
2603                  DPLL_CFGCR1_KDIV(pll_params.kdiv) |
2604                  DPLL_CFGCR1_PDIV(pll_params.pdiv) |
2605                  DPLL_CFGCR1_CENTRAL_FREQ_8400;
2606
2607         memset(pll_state, 0, sizeof(*pll_state));
2608
2609         pll_state->cfgcr0 = cfgcr0;
2610         pll_state->cfgcr1 = cfgcr1;
2611
2612         return true;
2613 }
2614
2615
2616 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
2617 {
2618         return id - DPLL_ID_ICL_MGPLL1;
2619 }
2620
2621 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
2622 {
2623         return tc_port + DPLL_ID_ICL_MGPLL1;
2624 }
2625
2626 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2627                                      u32 *target_dco_khz,
2628                                      struct intel_dpll_hw_state *state)
2629 {
2630         u32 dco_min_freq, dco_max_freq;
2631         int div1_vals[] = {7, 5, 3, 2};
2632         unsigned int i;
2633         int div2;
2634
2635         dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2636         dco_max_freq = is_dp ? 8100000 : 10000000;
2637
2638         for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2639                 int div1 = div1_vals[i];
2640
2641                 for (div2 = 10; div2 > 0; div2--) {
2642                         int dco = div1 * div2 * clock_khz * 5;
2643                         int a_divratio, tlinedrv, inputsel;
2644                         u32 hsdiv;
2645
2646                         if (dco < dco_min_freq || dco > dco_max_freq)
2647                                 continue;
2648
2649                         if (div2 >= 2) {
2650                                 a_divratio = is_dp ? 10 : 5;
2651                                 tlinedrv = 2;
2652                         } else {
2653                                 a_divratio = 5;
2654                                 tlinedrv = 0;
2655                         }
2656                         inputsel = is_dp ? 0 : 1;
2657
2658                         switch (div1) {
2659                         default:
2660                                 MISSING_CASE(div1);
2661                                 /* fall through */
2662                         case 2:
2663                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2664                                 break;
2665                         case 3:
2666                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2667                                 break;
2668                         case 5:
2669                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2670                                 break;
2671                         case 7:
2672                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2673                                 break;
2674                         }
2675
2676                         *target_dco_khz = dco;
2677
2678                         state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2679
2680                         state->mg_clktop2_coreclkctl1 =
2681                                 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2682
2683                         state->mg_clktop2_hsclkctl =
2684                                 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2685                                 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2686                                 hsdiv |
2687                                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2688
2689                         return true;
2690                 }
2691         }
2692
2693         return false;
2694 }
2695
2696 /*
2697  * The specification for this function uses real numbers, so the math had to be
2698  * adapted to integer-only calculation, that's why it looks so different.
2699  */
2700 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2701                                   struct intel_dpll_hw_state *pll_state)
2702 {
2703         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2704         int refclk_khz = dev_priv->cdclk.hw.ref;
2705         int clock = crtc_state->port_clock;
2706         u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2707         u32 iref_ndiv, iref_trim, iref_pulse_w;
2708         u32 prop_coeff, int_coeff;
2709         u32 tdc_targetcnt, feedfwgain;
2710         u64 ssc_stepsize, ssc_steplen, ssc_steplog;
2711         u64 tmp;
2712         bool use_ssc = false;
2713         bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2714
2715         memset(pll_state, 0, sizeof(*pll_state));
2716
2717         if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2718                                       pll_state)) {
2719                 DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
2720                 return false;
2721         }
2722
2723         m1div = 2;
2724         m2div_int = dco_khz / (refclk_khz * m1div);
2725         if (m2div_int > 255) {
2726                 m1div = 4;
2727                 m2div_int = dco_khz / (refclk_khz * m1div);
2728                 if (m2div_int > 255) {
2729                         DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
2730                                       clock);
2731                         return false;
2732                 }
2733         }
2734         m2div_rem = dco_khz % (refclk_khz * m1div);
2735
2736         tmp = (u64)m2div_rem * (1 << 22);
2737         do_div(tmp, refclk_khz * m1div);
2738         m2div_frac = tmp;
2739
2740         switch (refclk_khz) {
2741         case 19200:
2742                 iref_ndiv = 1;
2743                 iref_trim = 28;
2744                 iref_pulse_w = 1;
2745                 break;
2746         case 24000:
2747                 iref_ndiv = 1;
2748                 iref_trim = 25;
2749                 iref_pulse_w = 2;
2750                 break;
2751         case 38400:
2752                 iref_ndiv = 2;
2753                 iref_trim = 28;
2754                 iref_pulse_w = 1;
2755                 break;
2756         default:
2757                 MISSING_CASE(refclk_khz);
2758                 return false;
2759         }
2760
2761         /*
2762          * tdc_res = 0.000003
2763          * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
2764          *
2765          * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
2766          * was supposed to be a division, but we rearranged the operations of
2767          * the formula to avoid early divisions so we don't multiply the
2768          * rounding errors.
2769          *
2770          * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
2771          * we also rearrange to work with integers.
2772          *
2773          * The 0.5 transformed to 5 results in a multiplication by 10 and the
2774          * last division by 10.
2775          */
2776         tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
2777
2778         /*
2779          * Here we divide dco_khz by 10 in order to allow the dividend to fit in
2780          * 32 bits. That's not a problem since we round the division down
2781          * anyway.
2782          */
2783         feedfwgain = (use_ssc || m2div_rem > 0) ?
2784                 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
2785
2786         if (dco_khz >= 9000000) {
2787                 prop_coeff = 5;
2788                 int_coeff = 10;
2789         } else {
2790                 prop_coeff = 4;
2791                 int_coeff = 8;
2792         }
2793
2794         if (use_ssc) {
2795                 tmp = mul_u32_u32(dco_khz, 47 * 32);
2796                 do_div(tmp, refclk_khz * m1div * 10000);
2797                 ssc_stepsize = tmp;
2798
2799                 tmp = mul_u32_u32(dco_khz, 1000);
2800                 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
2801         } else {
2802                 ssc_stepsize = 0;
2803                 ssc_steplen = 0;
2804         }
2805         ssc_steplog = 4;
2806
2807         pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
2808                                   MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
2809                                   MG_PLL_DIV0_FBDIV_INT(m2div_int);
2810
2811         pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
2812                                  MG_PLL_DIV1_DITHER_DIV_2 |
2813                                  MG_PLL_DIV1_NDIVRATIO(1) |
2814                                  MG_PLL_DIV1_FBPREDIV(m1div);
2815
2816         pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
2817                                MG_PLL_LF_AFCCNTSEL_512 |
2818                                MG_PLL_LF_GAINCTRL(1) |
2819                                MG_PLL_LF_INT_COEFF(int_coeff) |
2820                                MG_PLL_LF_PROP_COEFF(prop_coeff);
2821
2822         pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
2823                                       MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
2824                                       MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
2825                                       MG_PLL_FRAC_LOCK_DCODITHEREN |
2826                                       MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
2827         if (use_ssc || m2div_rem > 0)
2828                 pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
2829
2830         pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
2831                                 MG_PLL_SSC_TYPE(2) |
2832                                 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
2833                                 MG_PLL_SSC_STEPNUM(ssc_steplog) |
2834                                 MG_PLL_SSC_FLLEN |
2835                                 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
2836
2837         pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
2838                                             MG_PLL_TDC_COLDST_IREFINT_EN |
2839                                             MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
2840                                             MG_PLL_TDC_TDCOVCCORR_EN |
2841                                             MG_PLL_TDC_TDCSEL(3);
2842
2843         pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
2844                                  MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
2845                                  MG_PLL_BIAS_BIAS_BONUS(10) |
2846                                  MG_PLL_BIAS_BIASCAL_EN |
2847                                  MG_PLL_BIAS_CTRIM(12) |
2848                                  MG_PLL_BIAS_VREF_RDAC(4) |
2849                                  MG_PLL_BIAS_IREFTRIM(iref_trim);
2850
2851         if (refclk_khz == 38400) {
2852                 pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
2853                 pll_state->mg_pll_bias_mask = 0;
2854         } else {
2855                 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
2856                 pll_state->mg_pll_bias_mask = -1U;
2857         }
2858
2859         pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
2860         pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
2861
2862         return true;
2863 }
2864
2865 /**
2866  * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
2867  * @crtc_state: state for the CRTC to select the DPLL for
2868  * @port_dpll_id: the active @port_dpll_id to select
2869  *
2870  * Select the given @port_dpll_id instance from the DPLLs reserved for the
2871  * CRTC.
2872  */
2873 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
2874                               enum icl_port_dpll_id port_dpll_id)
2875 {
2876         struct icl_port_dpll *port_dpll =
2877                 &crtc_state->icl_port_dplls[port_dpll_id];
2878
2879         crtc_state->shared_dpll = port_dpll->pll;
2880         crtc_state->dpll_hw_state = port_dpll->hw_state;
2881 }
2882
2883 static void icl_update_active_dpll(struct intel_atomic_state *state,
2884                                    struct intel_crtc *crtc,
2885                                    struct intel_encoder *encoder)
2886 {
2887         struct intel_crtc_state *crtc_state =
2888                 intel_atomic_get_new_crtc_state(state, crtc);
2889         struct intel_digital_port *primary_port;
2890         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
2891
2892         primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
2893                 enc_to_mst(&encoder->base)->primary :
2894                 enc_to_dig_port(&encoder->base);
2895
2896         if (primary_port &&
2897             (primary_port->tc_mode == TC_PORT_DP_ALT ||
2898              primary_port->tc_mode == TC_PORT_LEGACY))
2899                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
2900
2901         icl_set_active_port_dpll(crtc_state, port_dpll_id);
2902 }
2903
2904 static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
2905                                    struct intel_crtc *crtc,
2906                                    struct intel_encoder *encoder)
2907 {
2908         struct intel_crtc_state *crtc_state =
2909                 intel_atomic_get_new_crtc_state(state, crtc);
2910         struct icl_port_dpll *port_dpll =
2911                 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
2912         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2913         enum port port = encoder->port;
2914         bool has_dpll4 = false;
2915
2916         if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
2917                 DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
2918
2919                 return false;
2920         }
2921
2922         if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
2923                 has_dpll4 = true;
2924
2925         port_dpll->pll = intel_find_shared_dpll(state, crtc,
2926                                                 &port_dpll->hw_state,
2927                                                 DPLL_ID_ICL_DPLL0,
2928                                                 has_dpll4 ? DPLL_ID_EHL_DPLL4
2929                                                           : DPLL_ID_ICL_DPLL1);
2930         if (!port_dpll->pll) {
2931                 DRM_DEBUG_KMS("No combo PHY PLL found for port %c\n",
2932                               port_name(encoder->port));
2933                 return false;
2934         }
2935
2936         intel_reference_shared_dpll(state, crtc,
2937                                     port_dpll->pll, &port_dpll->hw_state);
2938
2939         icl_update_active_dpll(state, crtc, encoder);
2940
2941         return true;
2942 }
2943
2944 static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
2945                                  struct intel_crtc *crtc,
2946                                  struct intel_encoder *encoder)
2947 {
2948         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2949         struct intel_crtc_state *crtc_state =
2950                 intel_atomic_get_new_crtc_state(state, crtc);
2951         struct icl_port_dpll *port_dpll;
2952         enum intel_dpll_id dpll_id;
2953
2954         port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
2955         if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
2956                 DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n");
2957                 return false;
2958         }
2959
2960         port_dpll->pll = intel_find_shared_dpll(state, crtc,
2961                                                 &port_dpll->hw_state,
2962                                                 DPLL_ID_ICL_TBTPLL,
2963                                                 DPLL_ID_ICL_TBTPLL);
2964         if (!port_dpll->pll) {
2965                 DRM_DEBUG_KMS("No TBT-ALT PLL found\n");
2966                 return false;
2967         }
2968         intel_reference_shared_dpll(state, crtc,
2969                                     port_dpll->pll, &port_dpll->hw_state);
2970
2971
2972         port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
2973         if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
2974                 DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");
2975                 goto err_unreference_tbt_pll;
2976         }
2977
2978         dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
2979                                                          encoder->port));
2980         port_dpll->pll = intel_find_shared_dpll(state, crtc,
2981                                                 &port_dpll->hw_state,
2982                                                 dpll_id,
2983                                                 dpll_id);
2984         if (!port_dpll->pll) {
2985                 DRM_DEBUG_KMS("No MG PHY PLL found\n");
2986                 goto err_unreference_tbt_pll;
2987         }
2988         intel_reference_shared_dpll(state, crtc,
2989                                     port_dpll->pll, &port_dpll->hw_state);
2990
2991         icl_update_active_dpll(state, crtc, encoder);
2992
2993         return true;
2994
2995 err_unreference_tbt_pll:
2996         port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
2997         intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
2998
2999         return false;
3000 }
3001
3002 static bool icl_get_dplls(struct intel_atomic_state *state,
3003                           struct intel_crtc *crtc,
3004                           struct intel_encoder *encoder)
3005 {
3006         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3007         enum port port = encoder->port;
3008
3009         if (intel_port_is_combophy(dev_priv, port))
3010                 return icl_get_combo_phy_dpll(state, crtc, encoder);
3011         else if (intel_port_is_tc(dev_priv, port))
3012                 return icl_get_tc_phy_dplls(state, crtc, encoder);
3013
3014         MISSING_CASE(port);
3015
3016         return false;
3017 }
3018
3019 static void icl_put_dplls(struct intel_atomic_state *state,
3020                           struct intel_crtc *crtc)
3021 {
3022         const struct intel_crtc_state *old_crtc_state =
3023                 intel_atomic_get_old_crtc_state(state, crtc);
3024         struct intel_crtc_state *new_crtc_state =
3025                 intel_atomic_get_new_crtc_state(state, crtc);
3026         enum icl_port_dpll_id id;
3027
3028         new_crtc_state->shared_dpll = NULL;
3029
3030         for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
3031                 const struct icl_port_dpll *old_port_dpll =
3032                         &old_crtc_state->icl_port_dplls[id];
3033                 struct icl_port_dpll *new_port_dpll =
3034                         &new_crtc_state->icl_port_dplls[id];
3035
3036                 new_port_dpll->pll = NULL;
3037
3038                 if (!old_port_dpll->pll)
3039                         continue;
3040
3041                 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
3042         }
3043 }
3044
3045 static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
3046                                 struct intel_shared_dpll *pll,
3047                                 struct intel_dpll_hw_state *hw_state)
3048 {
3049         const enum intel_dpll_id id = pll->info->id;
3050         enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3051         intel_wakeref_t wakeref;
3052         bool ret = false;
3053         u32 val;
3054
3055         wakeref = intel_display_power_get_if_enabled(dev_priv,
3056                                                      POWER_DOMAIN_DISPLAY_CORE);
3057         if (!wakeref)
3058                 return false;
3059
3060         val = I915_READ(MG_PLL_ENABLE(tc_port));
3061         if (!(val & PLL_ENABLE))
3062                 goto out;
3063
3064         hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));
3065         hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3066
3067         hw_state->mg_clktop2_coreclkctl1 =
3068                 I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
3069         hw_state->mg_clktop2_coreclkctl1 &=
3070                 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3071
3072         hw_state->mg_clktop2_hsclkctl =
3073                 I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3074         hw_state->mg_clktop2_hsclkctl &=
3075                 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3076                 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3077                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3078                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3079
3080         hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
3081         hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
3082         hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port));
3083         hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));
3084         hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port));
3085
3086         hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port));
3087         hw_state->mg_pll_tdc_coldst_bias =
3088                 I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3089
3090         if (dev_priv->cdclk.hw.ref == 38400) {
3091                 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3092                 hw_state->mg_pll_bias_mask = 0;
3093         } else {
3094                 hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3095                 hw_state->mg_pll_bias_mask = -1U;
3096         }
3097
3098         hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3099         hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3100
3101         ret = true;
3102 out:
3103         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3104         return ret;
3105 }
3106
3107 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
3108                                  struct intel_shared_dpll *pll,
3109                                  struct intel_dpll_hw_state *hw_state,
3110                                  i915_reg_t enable_reg)
3111 {
3112         const enum intel_dpll_id id = pll->info->id;
3113         intel_wakeref_t wakeref;
3114         bool ret = false;
3115         u32 val;
3116
3117         wakeref = intel_display_power_get_if_enabled(dev_priv,
3118                                                      POWER_DOMAIN_DISPLAY_CORE);
3119         if (!wakeref)
3120                 return false;
3121
3122         val = I915_READ(enable_reg);
3123         if (!(val & PLL_ENABLE))
3124                 goto out;
3125
3126         hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
3127         hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
3128
3129         ret = true;
3130 out:
3131         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3132         return ret;
3133 }
3134
3135 static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
3136                                    struct intel_shared_dpll *pll,
3137                                    struct intel_dpll_hw_state *hw_state)
3138 {
3139         i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
3140
3141         if (IS_ELKHARTLAKE(dev_priv) &&
3142             pll->info->id == DPLL_ID_EHL_DPLL4) {
3143                 enable_reg = MG_PLL_ENABLE(0);
3144         }
3145
3146         return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
3147 }
3148
3149 static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
3150                                  struct intel_shared_dpll *pll,
3151                                  struct intel_dpll_hw_state *hw_state)
3152 {
3153         return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
3154 }
3155
3156 static void icl_dpll_write(struct drm_i915_private *dev_priv,
3157                            struct intel_shared_dpll *pll)
3158 {
3159         struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3160         const enum intel_dpll_id id = pll->info->id;
3161
3162         I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
3163         I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
3164         POSTING_READ(ICL_DPLL_CFGCR1(id));
3165 }
3166
3167 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3168                              struct intel_shared_dpll *pll)
3169 {
3170         struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3171         enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3172         u32 val;
3173
3174         /*
3175          * Some of the following registers have reserved fields, so program
3176          * these with RMW based on a mask. The mask can be fixed or generated
3177          * during the calc/readout phase if the mask depends on some other HW
3178          * state like refclk, see icl_calc_mg_pll_state().
3179          */
3180         val = I915_READ(MG_REFCLKIN_CTL(tc_port));
3181         val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3182         val |= hw_state->mg_refclkin_ctl;
3183         I915_WRITE(MG_REFCLKIN_CTL(tc_port), val);
3184
3185         val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
3186         val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3187         val |= hw_state->mg_clktop2_coreclkctl1;
3188         I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val);
3189
3190         val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3191         val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3192                  MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3193                  MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3194                  MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3195         val |= hw_state->mg_clktop2_hsclkctl;
3196         I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val);
3197
3198         I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3199         I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3200         I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3201         I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);
3202         I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3203
3204         val = I915_READ(MG_PLL_BIAS(tc_port));
3205         val &= ~hw_state->mg_pll_bias_mask;
3206         val |= hw_state->mg_pll_bias;
3207         I915_WRITE(MG_PLL_BIAS(tc_port), val);
3208
3209         val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3210         val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
3211         val |= hw_state->mg_pll_tdc_coldst_bias;
3212         I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val);
3213
3214         POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3215 }
3216
3217 static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
3218                                  struct intel_shared_dpll *pll,
3219                                  i915_reg_t enable_reg)
3220 {
3221         u32 val;
3222
3223         val = I915_READ(enable_reg);
3224         val |= PLL_POWER_ENABLE;
3225         I915_WRITE(enable_reg, val);
3226
3227         /*
3228          * The spec says we need to "wait" but it also says it should be
3229          * immediate.
3230          */
3231         if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
3232                                     PLL_POWER_STATE, PLL_POWER_STATE, 1))
3233                 DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
3234 }
3235
3236 static void icl_pll_enable(struct drm_i915_private *dev_priv,
3237                            struct intel_shared_dpll *pll,
3238                            i915_reg_t enable_reg)
3239 {
3240         u32 val;
3241
3242         val = I915_READ(enable_reg);
3243         val |= PLL_ENABLE;
3244         I915_WRITE(enable_reg, val);
3245
3246         /* Timeout is actually 600us. */
3247         if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
3248                                     PLL_LOCK, PLL_LOCK, 1))
3249                 DRM_ERROR("PLL %d not locked\n", pll->info->id);
3250 }
3251
3252 static void combo_pll_enable(struct drm_i915_private *dev_priv,
3253                              struct intel_shared_dpll *pll)
3254 {
3255         i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
3256
3257         if (IS_ELKHARTLAKE(dev_priv) &&
3258             pll->info->id == DPLL_ID_EHL_DPLL4) {
3259                 enable_reg = MG_PLL_ENABLE(0);
3260
3261                 /*
3262                  * We need to disable DC states when this DPLL is enabled.
3263                  * This can be done by taking a reference on DPLL4 power
3264                  * domain.
3265                  */
3266                 pll->wakeref = intel_display_power_get(dev_priv,
3267                                                        POWER_DOMAIN_DPLL_DC_OFF);
3268         }
3269
3270         icl_pll_power_enable(dev_priv, pll, enable_reg);
3271
3272         icl_dpll_write(dev_priv, pll);
3273
3274         /*
3275          * DVFS pre sequence would be here, but in our driver the cdclk code
3276          * paths should already be setting the appropriate voltage, hence we do
3277          * nothing here.
3278          */
3279
3280         icl_pll_enable(dev_priv, pll, enable_reg);
3281
3282         /* DVFS post sequence would be here. See the comment above. */
3283 }
3284
3285 static void tbt_pll_enable(struct drm_i915_private *dev_priv,
3286                            struct intel_shared_dpll *pll)
3287 {
3288         icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE);
3289
3290         icl_dpll_write(dev_priv, pll);
3291
3292         /*
3293          * DVFS pre sequence would be here, but in our driver the cdclk code
3294          * paths should already be setting the appropriate voltage, hence we do
3295          * nothing here.
3296          */
3297
3298         icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE);
3299
3300         /* DVFS post sequence would be here. See the comment above. */
3301 }
3302
3303 static void mg_pll_enable(struct drm_i915_private *dev_priv,
3304                           struct intel_shared_dpll *pll)
3305 {
3306         i915_reg_t enable_reg =
3307                 MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
3308
3309         icl_pll_power_enable(dev_priv, pll, enable_reg);
3310
3311         icl_mg_pll_write(dev_priv, pll);
3312
3313         /*
3314          * DVFS pre sequence would be here, but in our driver the cdclk code
3315          * paths should already be setting the appropriate voltage, hence we do
3316          * nothing here.
3317          */
3318
3319         icl_pll_enable(dev_priv, pll, enable_reg);
3320
3321         /* DVFS post sequence would be here. See the comment above. */
3322 }
3323
3324 static void icl_pll_disable(struct drm_i915_private *dev_priv,
3325                             struct intel_shared_dpll *pll,
3326                             i915_reg_t enable_reg)
3327 {
3328         u32 val;
3329
3330         /* The first steps are done by intel_ddi_post_disable(). */
3331
3332         /*
3333          * DVFS pre sequence would be here, but in our driver the cdclk code
3334          * paths should already be setting the appropriate voltage, hence we do
3335          * nothign here.
3336          */
3337
3338         val = I915_READ(enable_reg);
3339         val &= ~PLL_ENABLE;
3340         I915_WRITE(enable_reg, val);
3341
3342         /* Timeout is actually 1us. */
3343         if (intel_wait_for_register(&dev_priv->uncore,
3344                                     enable_reg, PLL_LOCK, 0, 1))
3345                 DRM_ERROR("PLL %d locked\n", pll->info->id);
3346
3347         /* DVFS post sequence would be here. See the comment above. */
3348
3349         val = I915_READ(enable_reg);
3350         val &= ~PLL_POWER_ENABLE;
3351         I915_WRITE(enable_reg, val);
3352
3353         /*
3354          * The spec says we need to "wait" but it also says it should be
3355          * immediate.
3356          */
3357         if (intel_wait_for_register(&dev_priv->uncore,
3358                                     enable_reg, PLL_POWER_STATE, 0, 1))
3359                 DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
3360 }
3361
3362 static void combo_pll_disable(struct drm_i915_private *dev_priv,
3363                               struct intel_shared_dpll *pll)
3364 {
3365         i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
3366
3367         if (IS_ELKHARTLAKE(dev_priv) &&
3368             pll->info->id == DPLL_ID_EHL_DPLL4) {
3369                 enable_reg = MG_PLL_ENABLE(0);
3370                 icl_pll_disable(dev_priv, pll, enable_reg);
3371
3372                 intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
3373                                         pll->wakeref);
3374                 return;
3375         }
3376
3377         icl_pll_disable(dev_priv, pll, enable_reg);
3378 }
3379
3380 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
3381                             struct intel_shared_dpll *pll)
3382 {
3383         icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
3384 }
3385
3386 static void mg_pll_disable(struct drm_i915_private *dev_priv,
3387                            struct intel_shared_dpll *pll)
3388 {
3389         i915_reg_t enable_reg =
3390                 MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
3391
3392         icl_pll_disable(dev_priv, pll, enable_reg);
3393 }
3394
3395 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
3396                               const struct intel_dpll_hw_state *hw_state)
3397 {
3398         DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
3399                       "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
3400                       "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
3401                       "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
3402                       "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
3403                       "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3404                       hw_state->cfgcr0, hw_state->cfgcr1,
3405                       hw_state->mg_refclkin_ctl,
3406                       hw_state->mg_clktop2_coreclkctl1,
3407                       hw_state->mg_clktop2_hsclkctl,
3408                       hw_state->mg_pll_div0,
3409                       hw_state->mg_pll_div1,
3410                       hw_state->mg_pll_lf,
3411                       hw_state->mg_pll_frac_lock,
3412                       hw_state->mg_pll_ssc,
3413                       hw_state->mg_pll_bias,
3414                       hw_state->mg_pll_tdc_coldst_bias);
3415 }
3416
3417 static const struct intel_shared_dpll_funcs combo_pll_funcs = {
3418         .enable = combo_pll_enable,
3419         .disable = combo_pll_disable,
3420         .get_hw_state = combo_pll_get_hw_state,
3421 };
3422
3423 static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
3424         .enable = tbt_pll_enable,
3425         .disable = tbt_pll_disable,
3426         .get_hw_state = tbt_pll_get_hw_state,
3427 };
3428
3429 static const struct intel_shared_dpll_funcs mg_pll_funcs = {
3430         .enable = mg_pll_enable,
3431         .disable = mg_pll_disable,
3432         .get_hw_state = mg_pll_get_hw_state,
3433 };
3434
3435 static const struct dpll_info icl_plls[] = {
3436         { "DPLL 0",   &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
3437         { "DPLL 1",   &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
3438         { "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
3439         { "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
3440         { "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
3441         { "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
3442         { "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
3443         { },
3444 };
3445
3446 static const struct intel_dpll_mgr icl_pll_mgr = {
3447         .dpll_info = icl_plls,
3448         .get_dplls = icl_get_dplls,
3449         .put_dplls = icl_put_dplls,
3450         .update_active_dpll = icl_update_active_dpll,
3451         .dump_hw_state = icl_dump_hw_state,
3452 };
3453
3454 static const struct dpll_info ehl_plls[] = {
3455         { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3456         { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
3457         { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
3458         { },
3459 };
3460
3461 static const struct intel_dpll_mgr ehl_pll_mgr = {
3462         .dpll_info = ehl_plls,
3463         .get_dplls = icl_get_dplls,
3464         .put_dplls = icl_put_dplls,
3465         .dump_hw_state = icl_dump_hw_state,
3466 };
3467
3468 /**
3469  * intel_shared_dpll_init - Initialize shared DPLLs
3470  * @dev: drm device
3471  *
3472  * Initialize shared DPLLs for @dev.
3473  */
3474 void intel_shared_dpll_init(struct drm_device *dev)
3475 {
3476         struct drm_i915_private *dev_priv = to_i915(dev);
3477         const struct intel_dpll_mgr *dpll_mgr = NULL;
3478         const struct dpll_info *dpll_info;
3479         int i;
3480
3481         if (IS_ELKHARTLAKE(dev_priv))
3482                 dpll_mgr = &ehl_pll_mgr;
3483         else if (INTEL_GEN(dev_priv) >= 11)
3484                 dpll_mgr = &icl_pll_mgr;
3485         else if (IS_CANNONLAKE(dev_priv))
3486                 dpll_mgr = &cnl_pll_mgr;
3487         else if (IS_GEN9_BC(dev_priv))
3488                 dpll_mgr = &skl_pll_mgr;
3489         else if (IS_GEN9_LP(dev_priv))
3490                 dpll_mgr = &bxt_pll_mgr;
3491         else if (HAS_DDI(dev_priv))
3492                 dpll_mgr = &hsw_pll_mgr;
3493         else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
3494                 dpll_mgr = &pch_pll_mgr;
3495
3496         if (!dpll_mgr) {
3497                 dev_priv->num_shared_dpll = 0;
3498                 return;
3499         }
3500
3501         dpll_info = dpll_mgr->dpll_info;
3502
3503         for (i = 0; dpll_info[i].name; i++) {
3504                 WARN_ON(i != dpll_info[i].id);
3505                 dev_priv->shared_dplls[i].info = &dpll_info[i];
3506         }
3507
3508         dev_priv->dpll_mgr = dpll_mgr;
3509         dev_priv->num_shared_dpll = i;
3510         mutex_init(&dev_priv->dpll_lock);
3511
3512         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
3513 }
3514
3515 /**
3516  * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
3517  * @state: atomic state
3518  * @crtc: CRTC to reserve DPLLs for
3519  * @encoder: encoder
3520  *
3521  * This function reserves all required DPLLs for the given CRTC and encoder
3522  * combination in the current atomic commit @state and the new @crtc atomic
3523  * state.
3524  *
3525  * The new configuration in the atomic commit @state is made effective by
3526  * calling intel_shared_dpll_swap_state().
3527  *
3528  * The reserved DPLLs should be released by calling
3529  * intel_release_shared_dplls().
3530  *
3531  * Returns:
3532  * True if all required DPLLs were successfully reserved.
3533  */
3534 bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
3535                                 struct intel_crtc *crtc,
3536                                 struct intel_encoder *encoder)
3537 {
3538         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3539         const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3540
3541         if (WARN_ON(!dpll_mgr))
3542                 return false;
3543
3544         return dpll_mgr->get_dplls(state, crtc, encoder);
3545 }
3546
3547 /**
3548  * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
3549  * @state: atomic state
3550  * @crtc: crtc from which the DPLLs are to be released
3551  *
3552  * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
3553  * from the current atomic commit @state and the old @crtc atomic state.
3554  *
3555  * The new configuration in the atomic commit @state is made effective by
3556  * calling intel_shared_dpll_swap_state().
3557  */
3558 void intel_release_shared_dplls(struct intel_atomic_state *state,
3559                                 struct intel_crtc *crtc)
3560 {
3561         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3562         const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3563
3564         /*
3565          * FIXME: this function is called for every platform having a
3566          * compute_clock hook, even though the platform doesn't yet support
3567          * the shared DPLL framework and intel_reserve_shared_dplls() is not
3568          * called on those.
3569          */
3570         if (!dpll_mgr)
3571                 return;
3572
3573         dpll_mgr->put_dplls(state, crtc);
3574 }
3575
3576 /**
3577  * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
3578  * @state: atomic state
3579  * @crtc: the CRTC for which to update the active DPLL
3580  * @encoder: encoder determining the type of port DPLL
3581  *
3582  * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
3583  * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
3584  * DPLL selected will be based on the current mode of the encoder's port.
3585  */
3586 void intel_update_active_dpll(struct intel_atomic_state *state,
3587                               struct intel_crtc *crtc,
3588                               struct intel_encoder *encoder)
3589 {
3590         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3591         const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3592
3593         if (WARN_ON(!dpll_mgr))
3594                 return;
3595
3596         dpll_mgr->update_active_dpll(state, crtc, encoder);
3597 }
3598
3599 /**
3600  * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
3601  * @dev_priv: i915 drm device
3602  * @hw_state: hw state to be written to the log
3603  *
3604  * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
3605  */
3606 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
3607                               const struct intel_dpll_hw_state *hw_state)
3608 {
3609         if (dev_priv->dpll_mgr) {
3610                 dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
3611         } else {
3612                 /* fallback for platforms that don't use the shared dpll
3613                  * infrastructure
3614                  */
3615                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
3616                               "fp0: 0x%x, fp1: 0x%x\n",
3617                               hw_state->dpll,
3618                               hw_state->dpll_md,
3619                               hw_state->fp0,
3620                               hw_state->fp1);
3621         }
3622 }