1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Hisilicon Hibmc SoC drm driver
4 * Based on the bochs drm driver.
6 * Copyright (c) 2016 Huawei Limited.
9 * Rongrong Zou <zourongrong@huawei.com>
10 * Rongrong Zou <zourongrong@gmail.com>
11 * Jianhua Li <lijianhua@huawei.com>
14 #include <linux/console.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_drv.h>
20 #include <drm/drm_gem_vram_helper.h>
21 #include <drm/drm_irq.h>
22 #include <drm/drm_print.h>
23 #include <drm/drm_probe_helper.h>
24 #include <drm/drm_vblank.h>
26 #include "hibmc_drm_drv.h"
27 #include "hibmc_drm_regs.h"
29 DEFINE_DRM_GEM_FOPS(hibmc_fops);
31 static irqreturn_t hibmc_drm_interrupt(int irq, void *arg)
33 struct drm_device *dev = (struct drm_device *)arg;
34 struct hibmc_drm_private *priv =
35 (struct hibmc_drm_private *)dev->dev_private;
38 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT);
40 if (status & HIBMC_RAW_INTERRUPT_VBLANK(1)) {
41 writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
42 priv->mmio + HIBMC_RAW_INTERRUPT);
43 drm_handle_vblank(dev, 0);
49 static struct drm_driver hibmc_driver = {
50 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
54 .desc = "hibmc drm driver",
57 .dumb_create = hibmc_dumb_create,
58 .dumb_map_offset = drm_gem_vram_driver_dumb_mmap_offset,
59 .gem_prime_mmap = drm_gem_prime_mmap,
60 .irq_handler = hibmc_drm_interrupt,
63 static int __maybe_unused hibmc_pm_suspend(struct device *dev)
65 struct drm_device *drm_dev = dev_get_drvdata(dev);
67 return drm_mode_config_helper_suspend(drm_dev);
70 static int __maybe_unused hibmc_pm_resume(struct device *dev)
72 struct drm_device *drm_dev = dev_get_drvdata(dev);
74 return drm_mode_config_helper_resume(drm_dev);
77 static const struct dev_pm_ops hibmc_pm_ops = {
78 SET_SYSTEM_SLEEP_PM_OPS(hibmc_pm_suspend,
82 static int hibmc_kms_init(struct hibmc_drm_private *priv)
86 drm_mode_config_init(priv->dev);
87 priv->mode_config_initialized = true;
89 priv->dev->mode_config.min_width = 0;
90 priv->dev->mode_config.min_height = 0;
91 priv->dev->mode_config.max_width = 1920;
92 priv->dev->mode_config.max_height = 1440;
94 priv->dev->mode_config.fb_base = priv->fb_base;
95 priv->dev->mode_config.preferred_depth = 24;
96 priv->dev->mode_config.prefer_shadow = 0;
98 priv->dev->mode_config.funcs = (void *)&hibmc_mode_funcs;
100 ret = hibmc_de_init(priv);
102 DRM_ERROR("failed to init de: %d\n", ret);
106 ret = hibmc_vdac_init(priv);
108 DRM_ERROR("failed to init vdac: %d\n", ret);
115 static void hibmc_kms_fini(struct hibmc_drm_private *priv)
117 if (priv->mode_config_initialized) {
118 drm_mode_config_cleanup(priv->dev);
119 priv->mode_config_initialized = false;
124 * It can operate in one of three modes: 0, 1 or Sleep.
126 void hibmc_set_power_mode(struct hibmc_drm_private *priv,
127 unsigned int power_mode)
129 unsigned int control_value = 0;
130 void __iomem *mmio = priv->mmio;
131 unsigned int input = 1;
133 if (power_mode > HIBMC_PW_MODE_CTL_MODE_SLEEP)
136 if (power_mode == HIBMC_PW_MODE_CTL_MODE_SLEEP)
139 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
140 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
141 HIBMC_PW_MODE_CTL_OSC_INPUT_MASK);
142 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
143 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
144 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
147 void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate)
149 unsigned int gate_reg;
151 void __iomem *mmio = priv->mmio;
153 /* Get current power mode. */
154 mode = (readl(mmio + HIBMC_POWER_MODE_CTRL) &
155 HIBMC_PW_MODE_CTL_MODE_MASK) >> HIBMC_PW_MODE_CTL_MODE_SHIFT;
158 case HIBMC_PW_MODE_CTL_MODE_MODE0:
159 gate_reg = HIBMC_MODE0_GATE;
162 case HIBMC_PW_MODE_CTL_MODE_MODE1:
163 gate_reg = HIBMC_MODE1_GATE;
167 gate_reg = HIBMC_MODE0_GATE;
170 writel(gate, mmio + gate_reg);
173 static void hibmc_hw_config(struct hibmc_drm_private *priv)
177 /* On hardware reset, power mode 0 is default. */
178 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0);
180 /* Enable display power gate & LOCALMEM power gate*/
181 reg = readl(priv->mmio + HIBMC_CURRENT_GATE);
182 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK;
183 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK;
184 reg |= HIBMC_CURR_GATE_DISPLAY(1);
185 reg |= HIBMC_CURR_GATE_LOCALMEM(1);
187 hibmc_set_current_gate(priv, reg);
190 * Reset the memory controller. If the memory controller
191 * is not reset in chip,the system might hang when sw accesses
192 * the memory.The memory should be resetted after
193 * changing the MXCLK.
195 reg = readl(priv->mmio + HIBMC_MISC_CTRL);
196 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
197 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0);
198 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
200 reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK;
201 reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1);
203 writel(reg, priv->mmio + HIBMC_MISC_CTRL);
206 static int hibmc_hw_map(struct hibmc_drm_private *priv)
208 struct drm_device *dev = priv->dev;
209 struct pci_dev *pdev = dev->pdev;
210 resource_size_t addr, size, ioaddr, iosize;
212 ioaddr = pci_resource_start(pdev, 1);
213 iosize = pci_resource_len(pdev, 1);
214 priv->mmio = devm_ioremap_nocache(dev->dev, ioaddr, iosize);
216 DRM_ERROR("Cannot map mmio region\n");
220 addr = pci_resource_start(pdev, 0);
221 size = pci_resource_len(pdev, 0);
222 priv->fb_map = devm_ioremap(dev->dev, addr, size);
224 DRM_ERROR("Cannot map framebuffer\n");
227 priv->fb_base = addr;
228 priv->fb_size = size;
233 static int hibmc_hw_init(struct hibmc_drm_private *priv)
237 ret = hibmc_hw_map(priv);
241 hibmc_hw_config(priv);
246 static int hibmc_unload(struct drm_device *dev)
248 struct hibmc_drm_private *priv = dev->dev_private;
250 hibmc_fbdev_fini(priv);
252 drm_atomic_helper_shutdown(dev);
254 if (dev->irq_enabled)
255 drm_irq_uninstall(dev);
256 if (priv->msi_enabled)
257 pci_disable_msi(dev->pdev);
259 hibmc_kms_fini(priv);
261 dev->dev_private = NULL;
265 static int hibmc_load(struct drm_device *dev)
267 struct hibmc_drm_private *priv;
270 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
272 DRM_ERROR("no memory to allocate for hibmc_drm_private\n");
275 dev->dev_private = priv;
278 ret = hibmc_hw_init(priv);
282 ret = hibmc_mm_init(priv);
286 ret = hibmc_kms_init(priv);
290 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
292 DRM_ERROR("failed to initialize vblank: %d\n", ret);
296 priv->msi_enabled = 0;
297 ret = pci_enable_msi(dev->pdev);
299 DRM_WARN("enabling MSI failed: %d\n", ret);
301 priv->msi_enabled = 1;
302 ret = drm_irq_install(dev, dev->pdev->irq);
304 DRM_WARN("install irq failed: %d\n", ret);
307 /* reset all the states of crtc/plane/encoder/connector */
308 drm_mode_config_reset(dev);
310 ret = hibmc_fbdev_init(priv);
312 DRM_ERROR("failed to initialize fbdev: %d\n", ret);
320 DRM_ERROR("failed to initialize drm driver: %d\n", ret);
324 static int hibmc_pci_probe(struct pci_dev *pdev,
325 const struct pci_device_id *ent)
327 struct drm_device *dev;
330 dev = drm_dev_alloc(&hibmc_driver, &pdev->dev);
332 DRM_ERROR("failed to allocate drm_device\n");
337 pci_set_drvdata(pdev, dev);
339 ret = pci_enable_device(pdev);
341 DRM_ERROR("failed to enable pci device: %d\n", ret);
345 ret = hibmc_load(dev);
347 DRM_ERROR("failed to load hibmc: %d\n", ret);
351 ret = drm_dev_register(dev, 0);
353 DRM_ERROR("failed to register drv for userspace access: %d\n",
362 pci_disable_device(pdev);
369 static void hibmc_pci_remove(struct pci_dev *pdev)
371 struct drm_device *dev = pci_get_drvdata(pdev);
373 drm_dev_unregister(dev);
378 static struct pci_device_id hibmc_pci_table[] = {
379 { PCI_VDEVICE(HUAWEI, 0x1711) },
383 static struct pci_driver hibmc_pci_driver = {
385 .id_table = hibmc_pci_table,
386 .probe = hibmc_pci_probe,
387 .remove = hibmc_pci_remove,
388 .driver.pm = &hibmc_pm_ops,
391 module_pci_driver(hibmc_pci_driver);
393 MODULE_DEVICE_TABLE(pci, hibmc_pci_table);
394 MODULE_AUTHOR("RongrongZou <zourongrong@huawei.com>");
395 MODULE_DESCRIPTION("DRM Driver for Hisilicon Hibmc");
396 MODULE_LICENSE("GPL v2");