drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/of_graph.h>
  22 #include <linux/gpio.h>
  23 #include <linux/component.h>
  24 #include <linux/phy/phy.h>
  25 #include <video/of_display_timing.h>
  26 #include <video/of_videomode.h>
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/drm_panel.h>
  32 #include <drm/bridge/ptn3460.h>
  33
  34 #include "exynos_dp_core.h"
  35
  36 #define ctx_from_connector(c)   container_of(c, struct exynos_dp_device, \
  37                                         connector)
  38
  39 static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
  40 {
  41         return to_exynos_crtc(dp->encoder->crtc);
  42 }
  43
  44 static inline struct exynos_dp_device *
  45 display_to_dp(struct exynos_drm_display *d)
  46 {
  47         return container_of(d, struct exynos_dp_device, display);
  48 }
  49
  50 struct bridge_init {
  51         struct i2c_client *client;
  52         struct device_node *node;
  53 };
  54
  55 static void exynos_dp_init_dp(struct exynos_dp_device *dp)
  56 {
  57         exynos_dp_reset(dp);
  58
  59         exynos_dp_swreset(dp);
  60
  61         exynos_dp_init_analog_param(dp);
  62         exynos_dp_init_interrupt(dp);
  63
  64         /* SW defined function Normal operation */
  65         exynos_dp_enable_sw_function(dp);
  66
  67         exynos_dp_config_interrupt(dp);
  68         exynos_dp_init_analog_func(dp);
  69
  70         exynos_dp_init_hpd(dp);
  71         exynos_dp_init_aux(dp);
  72 }
  73
  74 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  75 {
  76         int timeout_loop = 0;
  77
  78         while (exynos_dp_get_plug_in_status(dp) != 0) {
  79                 timeout_loop++;
  80                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  81                         dev_err(dp->dev, "failed to get hpd plug status\n");
  82                         return -ETIMEDOUT;
  83                 }
  84                 usleep_range(10, 11);
  85         }
  86
  87         return 0;
  88 }
  89
  90 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  91 {
  92         int i;
  93         unsigned char sum = 0;
  94
  95         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  96                 sum = sum + edid_data[i];
  97
  98         return sum;
  99 }
 100
 101 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
 102 {
 103         unsigned char edid[EDID_BLOCK_LENGTH * 2];
 104         unsigned int extend_block = 0;
 105         unsigned char sum;
 106         unsigned char test_vector;
 107         int retval;
 108
 109         /*
 110          * EDID device address is 0x50.
 111          * However, if necessary, you must have set upper address
 112          * into E-EDID in I2C device, 0x30.
 113          */
 114
 115         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 116         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 117                                 EDID_EXTENSION_FLAG,
 118                                 &extend_block);
 119         if (retval)
 120                 return retval;
 121
 122         if (extend_block > 0) {
 123                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 124
 125                 /* Read EDID data */
 126                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 127                                                 EDID_HEADER_PATTERN,
 128                                                 EDID_BLOCK_LENGTH,
 129                                                 &edid[EDID_HEADER_PATTERN]);
 130                 if (retval != 0) {
 131                         dev_err(dp->dev, "EDID Read failed!\n");
 132                         return -EIO;
 133                 }
 134                 sum = exynos_dp_calc_edid_check_sum(edid);
 135                 if (sum != 0) {
 136                         dev_err(dp->dev, "EDID bad checksum!\n");
 137                         return -EIO;
 138                 }
 139
 140                 /* Read additional EDID data */
 141                 retval = exynos_dp_read_bytes_from_i2c(dp,
 142                                 I2C_EDID_DEVICE_ADDR,
 143                                 EDID_BLOCK_LENGTH,
 144                                 EDID_BLOCK_LENGTH,
 145                                 &edid[EDID_BLOCK_LENGTH]);
 146                 if (retval != 0) {
 147                         dev_err(dp->dev, "EDID Read failed!\n");
 148                         return -EIO;
 149                 }
 150                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 151                 if (sum != 0) {
 152                         dev_err(dp->dev, "EDID bad checksum!\n");
 153                         return -EIO;
 154                 }
 155
 156                 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 157                                         &test_vector);
 158                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 159                         exynos_dp_write_byte_to_dpcd(dp,
 160                                 DP_TEST_EDID_CHECKSUM,
 161                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 162                         exynos_dp_write_byte_to_dpcd(dp,
 163                                 DP_TEST_RESPONSE,
 164                                 DP_TEST_EDID_CHECKSUM_WRITE);
 165                 }
 166         } else {
 167                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 168
 169                 /* Read EDID data */
 170                 retval = exynos_dp_read_bytes_from_i2c(dp,
 171                                 I2C_EDID_DEVICE_ADDR,
 172                                 EDID_HEADER_PATTERN,
 173                                 EDID_BLOCK_LENGTH,
 174                                 &edid[EDID_HEADER_PATTERN]);
 175                 if (retval != 0) {
 176                         dev_err(dp->dev, "EDID Read failed!\n");
 177                         return -EIO;
 178                 }
 179                 sum = exynos_dp_calc_edid_check_sum(edid);
 180                 if (sum != 0) {
 181                         dev_err(dp->dev, "EDID bad checksum!\n");
 182                         return -EIO;
 183                 }
 184
 185                 exynos_dp_read_byte_from_dpcd(dp,
 186                         DP_TEST_REQUEST,
 187                         &test_vector);
 188                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 189                         exynos_dp_write_byte_to_dpcd(dp,
 190                                 DP_TEST_EDID_CHECKSUM,
 191                                 edid[EDID_CHECKSUM]);
 192                         exynos_dp_write_byte_to_dpcd(dp,
 193                                 DP_TEST_RESPONSE,
 194                                 DP_TEST_EDID_CHECKSUM_WRITE);
 195                 }
 196         }
 197
 198         dev_dbg(dp->dev, "EDID Read success!\n");
 199         return 0;
 200 }
 201
 202 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 203 {
 204         u8 buf[12];
 205         int i;
 206         int retval;
 207
 208         /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 209         retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 210                                 12, buf);
 211         if (retval)
 212                 return retval;
 213
 214         /* Read EDID */
 215         for (i = 0; i < 3; i++) {
 216                 retval = exynos_dp_read_edid(dp);
 217                 if (!retval)
 218                         break;
 219         }
 220
 221         return retval;
 222 }
 223
 224 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 225                                                 bool enable)
 226 {
 227         u8 data;
 228
 229         exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 230
 231         if (enable)
 232                 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 233                         DP_LANE_COUNT_ENHANCED_FRAME_EN |
 234                         DPCD_LANE_COUNT_SET(data));
 235         else
 236                 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 237                         DPCD_LANE_COUNT_SET(data));
 238 }
 239
 240 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 241 {
 242         u8 data;
 243         int retval;
 244
 245         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 246         retval = DPCD_ENHANCED_FRAME_CAP(data);
 247
 248         return retval;
 249 }
 250
 251 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 252 {
 253         u8 data;
 254
 255         data = exynos_dp_is_enhanced_mode_available(dp);
 256         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 257         exynos_dp_enable_enhanced_mode(dp, data);
 258 }
 259
 260 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 261 {
 262         exynos_dp_set_training_pattern(dp, DP_NONE);
 263
 264         exynos_dp_write_byte_to_dpcd(dp,
 265                 DP_TRAINING_PATTERN_SET,
 266                 DP_TRAINING_PATTERN_DISABLE);
 267 }
 268
 269 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 270                                         int pre_emphasis, int lane)
 271 {
 272         switch (lane) {
 273         case 0:
 274                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 275                 break;
 276         case 1:
 277                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 278                 break;
 279
 280         case 2:
 281                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 282                 break;
 283
 284         case 3:
 285                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 286                 break;
 287         }
 288 }
 289
 290 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 291 {
 292         u8 buf[4];
 293         int lane, lane_count, pll_tries, retval;
 294
 295         lane_count = dp->link_train.lane_count;
 296
 297         dp->link_train.lt_state = CLOCK_RECOVERY;
 298         dp->link_train.eq_loop = 0;
 299
 300         for (lane = 0; lane < lane_count; lane++)
 301                 dp->link_train.cr_loop[lane] = 0;
 302
 303         /* Set link rate and count as you want to establish*/
 304         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 305         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 306
 307         /* Setup RX configuration */
 308         buf[0] = dp->link_train.link_rate;
 309         buf[1] = dp->link_train.lane_count;
 310         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 311                                 2, buf);
 312         if (retval)
 313                 return retval;
 314
 315         /* Set TX pre-emphasis to minimum */
 316         for (lane = 0; lane < lane_count; lane++)
 317                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 318                         PRE_EMPHASIS_LEVEL_0, lane);
 319
 320         /* Wait for PLL lock */
 321         pll_tries = 0;
 322         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 323                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 324                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 325                         return -ETIMEDOUT;
 326                 }
 327
 328                 pll_tries++;
 329                 usleep_range(90, 120);
 330         }
 331
 332         /* Set training pattern 1 */
 333         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 334
 335         /* Set RX training pattern */
 336         retval = exynos_dp_write_byte_to_dpcd(dp,
 337                         DP_TRAINING_PATTERN_SET,
 338                         DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 339         if (retval)
 340                 return retval;
 341
 342         for (lane = 0; lane < lane_count; lane++)
 343                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 344                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 345
 346         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 347                         lane_count, buf);
 348
 349         return retval;
 350 }
 351
 352 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 353 {
 354         int shift = (lane & 1) * 4;
 355         u8 link_value = link_status[lane>>1];
 356
 357         return (link_value >> shift) & 0xf;
 358 }
 359
 360 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 361 {
 362         int lane;
 363         u8 lane_status;
 364
 365         for (lane = 0; lane < lane_count; lane++) {
 366                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 367                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 368                         return -EINVAL;
 369         }
 370         return 0;
 371 }
 372
 373 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 374                                 int lane_count)
 375 {
 376         int lane;
 377         u8 lane_status;
 378
 379         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 380                 return -EINVAL;
 381
 382         for (lane = 0; lane < lane_count; lane++) {
 383                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 384                 lane_status &= DP_CHANNEL_EQ_BITS;
 385                 if (lane_status != DP_CHANNEL_EQ_BITS)
 386                         return -EINVAL;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 393                                                         int lane)
 394 {
 395         int shift = (lane & 1) * 4;
 396         u8 link_value = adjust_request[lane>>1];
 397
 398         return (link_value >> shift) & 0x3;
 399 }
 400
 401 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 402                                         u8 adjust_request[2],
 403                                         int lane)
 404 {
 405         int shift = (lane & 1) * 4;
 406         u8 link_value = adjust_request[lane>>1];
 407
 408         return ((link_value >> shift) & 0xc) >> 2;
 409 }
 410
 411 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 412                                         u8 training_lane_set, int lane)
 413 {
 414         switch (lane) {
 415         case 0:
 416                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 417                 break;
 418         case 1:
 419                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 420                 break;
 421
 422         case 2:
 423                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 424                 break;
 425
 426         case 3:
 427                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 428                 break;
 429         }
 430 }
 431
 432 static unsigned int exynos_dp_get_lane_link_training(
 433                                 struct exynos_dp_device *dp,
 434                                 int lane)
 435 {
 436         u32 reg;
 437
 438         switch (lane) {
 439         case 0:
 440                 reg = exynos_dp_get_lane0_link_training(dp);
 441                 break;
 442         case 1:
 443                 reg = exynos_dp_get_lane1_link_training(dp);
 444                 break;
 445         case 2:
 446                 reg = exynos_dp_get_lane2_link_training(dp);
 447                 break;
 448         case 3:
 449                 reg = exynos_dp_get_lane3_link_training(dp);
 450                 break;
 451         default:
 452                 WARN_ON(1);
 453                 return 0;
 454         }
 455
 456         return reg;
 457 }
 458
 459 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 460 {
 461         exynos_dp_training_pattern_dis(dp);
 462         exynos_dp_set_enhanced_mode(dp);
 463
 464         dp->link_train.lt_state = FAILED;
 465 }
 466
 467 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 468                                         u8 adjust_request[2])
 469 {
 470         int lane, lane_count;
 471         u8 voltage_swing, pre_emphasis, training_lane;
 472
 473         lane_count = dp->link_train.lane_count;
 474         for (lane = 0; lane < lane_count; lane++) {
 475                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 476                                                 adjust_request, lane);
 477                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 478                                                 adjust_request, lane);
 479                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 480                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 481
 482                 if (voltage_swing == VOLTAGE_LEVEL_3)
 483                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 484                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 485                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 486
 487                 dp->link_train.training_lane[lane] = training_lane;
 488         }
 489 }
 490
 491 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 492 {
 493         int lane, lane_count, retval;
 494         u8 voltage_swing, pre_emphasis, training_lane;
 495         u8 link_status[2], adjust_request[2];
 496
 497         usleep_range(100, 101);
 498
 499         lane_count = dp->link_train.lane_count;
 500
 501         retval =  exynos_dp_read_bytes_from_dpcd(dp,
 502                         DP_LANE0_1_STATUS, 2, link_status);
 503         if (retval)
 504                 return retval;
 505
 506         retval =  exynos_dp_read_bytes_from_dpcd(dp,
 507                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 508         if (retval)
 509                 return retval;
 510
 511         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 512                 /* set training pattern 2 for EQ */
 513                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 514
 515                 retval = exynos_dp_write_byte_to_dpcd(dp,
 516                                 DP_TRAINING_PATTERN_SET,
 517                                 DP_LINK_SCRAMBLING_DISABLE |
 518                                 DP_TRAINING_PATTERN_2);
 519                 if (retval)
 520                         return retval;
 521
 522                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 523                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 524         } else {
 525                 for (lane = 0; lane < lane_count; lane++) {
 526                         training_lane = exynos_dp_get_lane_link_training(
 527                                                         dp, lane);
 528                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 529                                                         adjust_request, lane);
 530                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 531                                                         adjust_request, lane);
 532
 533                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 534                                         voltage_swing &&
 535                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 536                                         pre_emphasis)
 537                                 dp->link_train.cr_loop[lane]++;
 538
 539                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 540                             voltage_swing == VOLTAGE_LEVEL_3 ||
 541                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 542                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 543                                         dp->link_train.cr_loop[lane],
 544                                         voltage_swing, pre_emphasis);
 545                                 exynos_dp_reduce_link_rate(dp);
 546                                 return -EIO;
 547                         }
 548                 }
 549         }
 550
 551         exynos_dp_get_adjust_training_lane(dp, adjust_request);
 552
 553         for (lane = 0; lane < lane_count; lane++)
 554                 exynos_dp_set_lane_link_training(dp,
 555                         dp->link_train.training_lane[lane], lane);
 556
 557         retval = exynos_dp_write_bytes_to_dpcd(dp,
 558                         DP_TRAINING_LANE0_SET, lane_count,
 559                         dp->link_train.training_lane);
 560         if (retval)
 561                 return retval;
 562
 563         return retval;
 564 }
 565
 566 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 567 {
 568         int lane, lane_count, retval;
 569         u32 reg;
 570         u8 link_align, link_status[2], adjust_request[2];
 571
 572         usleep_range(400, 401);
 573
 574         lane_count = dp->link_train.lane_count;
 575
 576         retval = exynos_dp_read_bytes_from_dpcd(dp,
 577                         DP_LANE0_1_STATUS, 2, link_status);
 578         if (retval)
 579                 return retval;
 580
 581         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 582                 exynos_dp_reduce_link_rate(dp);
 583                 return -EIO;
 584         }
 585
 586         retval = exynos_dp_read_bytes_from_dpcd(dp,
 587                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 588         if (retval)
 589                 return retval;
 590
 591         retval = exynos_dp_read_byte_from_dpcd(dp,
 592                         DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 593         if (retval)
 594                 return retval;
 595
 596         exynos_dp_get_adjust_training_lane(dp, adjust_request);
 597
 598         if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 599                 /* traing pattern Set to Normal */
 600                 exynos_dp_training_pattern_dis(dp);
 601
 602                 dev_info(dp->dev, "Link Training success!\n");
 603
 604                 exynos_dp_get_link_bandwidth(dp, &reg);
 605                 dp->link_train.link_rate = reg;
 606                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 607                         dp->link_train.link_rate);
 608
 609                 exynos_dp_get_lane_count(dp, &reg);
 610                 dp->link_train.lane_count = reg;
 611                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 612                         dp->link_train.lane_count);
 613
 614                 /* set enhanced mode if available */
 615                 exynos_dp_set_enhanced_mode(dp);
 616                 dp->link_train.lt_state = FINISHED;
 617
 618                 return 0;
 619         }
 620
 621         /* not all locked */
 622         dp->link_train.eq_loop++;
 623
 624         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 625                 dev_err(dp->dev, "EQ Max loop\n");
 626                 exynos_dp_reduce_link_rate(dp);
 627                 return -EIO;
 628         }
 629
 630         for (lane = 0; lane < lane_count; lane++)
 631                 exynos_dp_set_lane_link_training(dp,
 632                         dp->link_train.training_lane[lane], lane);
 633
 634         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 635                         lane_count, dp->link_train.training_lane);
 636
 637         return retval;
 638 }
 639
 640 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 641                                         u8 *bandwidth)
 642 {
 643         u8 data;
 644
 645         /*
 646          * For DP rev.1.1, Maximum link rate of Main Link lanes
 647          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 648          */
 649         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 650         *bandwidth = data;
 651 }
 652
 653 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 654                                         u8 *lane_count)
 655 {
 656         u8 data;
 657
 658         /*
 659          * For DP rev.1.1, Maximum number of Main Link lanes
 660          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 661          */
 662         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 663         *lane_count = DPCD_MAX_LANE_COUNT(data);
 664 }
 665
 666 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 667                         enum link_lane_count_type max_lane,
 668                         enum link_rate_type max_rate)
 669 {
 670         /*
 671          * MACRO_RST must be applied after the PLL_LOCK to avoid
 672          * the DP inter pair skew issue for at least 10 us
 673          */
 674         exynos_dp_reset_macro(dp);
 675
 676         /* Initialize by reading RX's DPCD */
 677         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 678         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 679
 680         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 681            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 682                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 683                         dp->link_train.link_rate);
 684                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 685         }
 686
 687         if (dp->link_train.lane_count == 0) {
 688                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 689                         dp->link_train.lane_count);
 690                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 691         }
 692
 693         /* Setup TX lane count & rate */
 694         if (dp->link_train.lane_count > max_lane)
 695                 dp->link_train.lane_count = max_lane;
 696         if (dp->link_train.link_rate > max_rate)
 697                 dp->link_train.link_rate = max_rate;
 698
 699         /* All DP analog module power up */
 700         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 701 }
 702
 703 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 704 {
 705         int retval = 0, training_finished = 0;
 706
 707         dp->link_train.lt_state = START;
 708
 709         /* Process here */
 710         while (!retval && !training_finished) {
 711                 switch (dp->link_train.lt_state) {
 712                 case START:
 713                         retval = exynos_dp_link_start(dp);
 714                         if (retval)
 715                                 dev_err(dp->dev, "LT link start failed!\n");
 716                         break;
 717                 case CLOCK_RECOVERY:
 718                         retval = exynos_dp_process_clock_recovery(dp);
 719                         if (retval)
 720                                 dev_err(dp->dev, "LT CR failed!\n");
 721                         break;
 722                 case EQUALIZER_TRAINING:
 723                         retval = exynos_dp_process_equalizer_training(dp);
 724                         if (retval)
 725                                 dev_err(dp->dev, "LT EQ failed!\n");
 726                         break;
 727                 case FINISHED:
 728                         training_finished = 1;
 729                         break;
 730                 case FAILED:
 731                         return -EREMOTEIO;
 732                 }
 733         }
 734         if (retval)
 735                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 736
 737         return retval;
 738 }
 739
 740 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 741                                 u32 count,
 742                                 u32 bwtype)
 743 {
 744         int i;
 745         int retval;
 746
 747         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 748                 exynos_dp_init_training(dp, count, bwtype);
 749                 retval = exynos_dp_sw_link_training(dp);
 750                 if (retval == 0)
 751                         break;
 752
 753                 usleep_range(100, 110);
 754         }
 755
 756         return retval;
 757 }
 758
 759 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 760 {
 761         int retval = 0;
 762         int timeout_loop = 0;
 763         int done_count = 0;
 764
 765         exynos_dp_config_video_slave_mode(dp);
 766
 767         exynos_dp_set_video_color_format(dp);
 768
 769         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 770                 dev_err(dp->dev, "PLL is not locked yet.\n");
 771                 return -EINVAL;
 772         }
 773
 774         for (;;) {
 775                 timeout_loop++;
 776                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 777                         break;
 778                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 779                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 780                         return -ETIMEDOUT;
 781                 }
 782
 783                 usleep_range(1, 2);
 784         }
 785
 786         /* Set to use the register calculated M/N video */
 787         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 788
 789         /* For video bist, Video timing must be generated by register */
 790         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 791
 792         /* Disable video mute */
 793         exynos_dp_enable_video_mute(dp, 0);
 794
 795         /* Configure video slave mode */
 796         exynos_dp_enable_video_master(dp, 0);
 797
 798         /* Enable video */
 799         exynos_dp_start_video(dp);
 800
 801         timeout_loop = 0;
 802
 803         for (;;) {
 804                 timeout_loop++;
 805                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 806                         done_count++;
 807                         if (done_count > 10)
 808                                 break;
 809                 } else if (done_count) {
 810                         done_count = 0;
 811                 }
 812                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 813                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 814                         return -ETIMEDOUT;
 815                 }
 816
 817                 usleep_range(1000, 1001);
 818         }
 819
 820         if (retval != 0)
 821                 dev_err(dp->dev, "Video stream is not detected!\n");
 822
 823         return retval;
 824 }
 825
 826 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 827 {
 828         u8 data;
 829
 830         if (enable) {
 831                 exynos_dp_enable_scrambling(dp);
 832
 833                 exynos_dp_read_byte_from_dpcd(dp,
 834                         DP_TRAINING_PATTERN_SET,
 835                         &data);
 836                 exynos_dp_write_byte_to_dpcd(dp,
 837                         DP_TRAINING_PATTERN_SET,
 838                         (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 839         } else {
 840                 exynos_dp_disable_scrambling(dp);
 841
 842                 exynos_dp_read_byte_from_dpcd(dp,
 843                         DP_TRAINING_PATTERN_SET,
 844                         &data);
 845                 exynos_dp_write_byte_to_dpcd(dp,
 846                         DP_TRAINING_PATTERN_SET,
 847                         (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 848         }
 849 }
 850
 851 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 852 {
 853         struct exynos_dp_device *dp = arg;
 854
 855         enum dp_irq_type irq_type;
 856
 857         irq_type = exynos_dp_get_irq_type(dp);
 858         switch (irq_type) {
 859         case DP_IRQ_TYPE_HP_CABLE_IN:
 860                 dev_dbg(dp->dev, "Received irq - cable in\n");
 861                 schedule_work(&dp->hotplug_work);
 862                 exynos_dp_clear_hotplug_interrupts(dp);
 863                 break;
 864         case DP_IRQ_TYPE_HP_CABLE_OUT:
 865                 dev_dbg(dp->dev, "Received irq - cable out\n");
 866                 exynos_dp_clear_hotplug_interrupts(dp);
 867                 break;
 868         case DP_IRQ_TYPE_HP_CHANGE:
 869                 /*
 870                  * We get these change notifications once in a while, but there
 871                  * is nothing we can do with them. Just ignore it for now and
 872                  * only handle cable changes.
 873                  */
 874                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 875                 exynos_dp_clear_hotplug_interrupts(dp);
 876                 break;
 877         default:
 878                 dev_err(dp->dev, "Received irq - unknown type!\n");
 879                 break;
 880         }
 881         return IRQ_HANDLED;
 882 }
 883
 884 static void exynos_dp_hotplug(struct work_struct *work)
 885 {
 886         struct exynos_dp_device *dp;
 887
 888         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 889
 890         if (dp->drm_dev)
 891                 drm_helper_hpd_irq_event(dp->drm_dev);
 892 }
 893
 894 static void exynos_dp_commit(struct exynos_drm_display *display)
 895 {
 896         struct exynos_dp_device *dp = display_to_dp(display);
 897         int ret;
 898
 899         /* Keep the panel disabled while we configure video */
 900         if (dp->panel) {
 901                 if (drm_panel_disable(dp->panel))
 902                         DRM_ERROR("failed to disable the panel\n");
 903         }
 904
 905         ret = exynos_dp_detect_hpd(dp);
 906         if (ret) {
 907                 /* Cable has been disconnected, we're done */
 908                 return;
 909         }
 910
 911         ret = exynos_dp_handle_edid(dp);
 912         if (ret) {
 913                 dev_err(dp->dev, "unable to handle edid\n");
 914                 return;
 915         }
 916
 917         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 918                                         dp->video_info->link_rate);
 919         if (ret) {
 920                 dev_err(dp->dev, "unable to do link train\n");
 921                 return;
 922         }
 923
 924         exynos_dp_enable_scramble(dp, 1);
 925         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 926         exynos_dp_enable_enhanced_mode(dp, 1);
 927
 928         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 929         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 930
 931         exynos_dp_init_video(dp);
 932         ret = exynos_dp_config_video(dp);
 933         if (ret)
 934                 dev_err(dp->dev, "unable to config video\n");
 935
 936         /* Safe to enable the panel now */
 937         if (dp->panel) {
 938                 if (drm_panel_enable(dp->panel))
 939                         DRM_ERROR("failed to enable the panel\n");
 940         }
 941 }
 942
 943 static enum drm_connector_status exynos_dp_detect(
 944                                 struct drm_connector *connector, bool force)
 945 {
 946         return connector_status_connected;
 947 }
 948
 949 static void exynos_dp_connector_destroy(struct drm_connector *connector)
 950 {
 951         drm_connector_unregister(connector);
 952         drm_connector_cleanup(connector);
 953 }
 954
 955 static struct drm_connector_funcs exynos_dp_connector_funcs = {
 956         .dpms = drm_helper_connector_dpms,
 957         .fill_modes = drm_helper_probe_single_connector_modes,
 958         .detect = exynos_dp_detect,
 959         .destroy = exynos_dp_connector_destroy,
 960 };
 961
 962 static int exynos_dp_get_modes(struct drm_connector *connector)
 963 {
 964         struct exynos_dp_device *dp = ctx_from_connector(connector);
 965         struct drm_display_mode *mode;
 966
 967         if (dp->panel)
 968                 return drm_panel_get_modes(dp->panel);
 969
 970         mode = drm_mode_create(connector->dev);
 971         if (!mode) {
 972                 DRM_ERROR("failed to create a new display mode.\n");
 973                 return 0;
 974         }
 975
 976         drm_display_mode_from_videomode(&dp->priv.vm, mode);
 977         mode->width_mm = dp->priv.width_mm;
 978         mode->height_mm = dp->priv.height_mm;
 979         connector->display_info.width_mm = mode->width_mm;
 980         connector->display_info.height_mm = mode->height_mm;
 981
 982         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 983         drm_mode_set_name(mode);
 984         drm_mode_probed_add(connector, mode);
 985
 986         return 1;
 987 }
 988
 989 static struct drm_encoder *exynos_dp_best_encoder(
 990                         struct drm_connector *connector)
 991 {
 992         struct exynos_dp_device *dp = ctx_from_connector(connector);
 993
 994         return dp->encoder;
 995 }
 996
 997 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
 998         .get_modes = exynos_dp_get_modes,
 999         .best_encoder = exynos_dp_best_encoder,
1000 };
1001
1002 /* returns the number of bridges attached */
1003 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
1004                 struct drm_encoder *encoder)
1005 {
1006         int ret;
1007
1008         encoder->bridge = dp->bridge;
1009         dp->bridge->encoder = encoder;
1010         ret = drm_bridge_attach(encoder->dev, dp->bridge);
1011         if (ret) {
1012                 DRM_ERROR("Failed to attach bridge to drm\n");
1013                 return ret;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int exynos_dp_create_connector(struct exynos_drm_display *display,
1020                                 struct drm_encoder *encoder)
1021 {
1022         struct exynos_dp_device *dp = display_to_dp(display);
1023         struct drm_connector *connector = &dp->connector;
1024         int ret;
1025
1026         dp->encoder = encoder;
1027
1028         /* Pre-empt DP connector creation if there's a bridge */
1029         if (dp->bridge) {
1030                 ret = exynos_drm_attach_lcd_bridge(dp, encoder);
1031                 if (!ret)
1032                         return 0;
1033         }
1034
1035         connector->polled = DRM_CONNECTOR_POLL_HPD;
1036
1037         ret = drm_connector_init(dp->drm_dev, connector,
1038                         &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1039         if (ret) {
1040                 DRM_ERROR("Failed to initialize connector with drm\n");
1041                 return ret;
1042         }
1043
1044         drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1045         drm_connector_register(connector);
1046         drm_mode_connector_attach_encoder(connector, encoder);
1047
1048         if (dp->panel)
1049                 ret = drm_panel_attach(dp->panel, &dp->connector);
1050
1051         return ret;
1052 }
1053
1054 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1055 {
1056         if (dp->phy)
1057                 phy_power_on(dp->phy);
1058 }
1059
1060 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1061 {
1062         if (dp->phy)
1063                 phy_power_off(dp->phy);
1064 }
1065
1066 static void exynos_dp_poweron(struct exynos_dp_device *dp)
1067 {
1068         struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1069
1070         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1071                 return;
1072
1073         if (dp->panel) {
1074                 if (drm_panel_prepare(dp->panel)) {
1075                         DRM_ERROR("failed to setup the panel\n");
1076                         return;
1077                 }
1078         }
1079
1080         if (crtc->ops->clock_enable)
1081                 crtc->ops->clock_enable(dp_to_crtc(dp), true);
1082
1083         clk_prepare_enable(dp->clock);
1084         exynos_dp_phy_init(dp);
1085         exynos_dp_init_dp(dp);
1086         enable_irq(dp->irq);
1087         exynos_dp_commit(&dp->display);
1088 }
1089
1090 static void exynos_dp_poweroff(struct exynos_dp_device *dp)
1091 {
1092         struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1093
1094         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1095                 return;
1096
1097         if (dp->panel) {
1098                 if (drm_panel_disable(dp->panel)) {
1099                         DRM_ERROR("failed to disable the panel\n");
1100                         return;
1101                 }
1102         }
1103
1104         disable_irq(dp->irq);
1105         flush_work(&dp->hotplug_work);
1106         exynos_dp_phy_exit(dp);
1107         clk_disable_unprepare(dp->clock);
1108
1109         if (crtc->ops->clock_enable)
1110                 crtc->ops->clock_enable(dp_to_crtc(dp), false);
1111
1112         if (dp->panel) {
1113                 if (drm_panel_unprepare(dp->panel))
1114                         DRM_ERROR("failed to turnoff the panel\n");
1115         }
1116 }
1117
1118 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1119 {
1120         struct exynos_dp_device *dp = display_to_dp(display);
1121
1122         switch (mode) {
1123         case DRM_MODE_DPMS_ON:
1124                 exynos_dp_poweron(dp);
1125                 break;
1126         case DRM_MODE_DPMS_STANDBY:
1127         case DRM_MODE_DPMS_SUSPEND:
1128         case DRM_MODE_DPMS_OFF:
1129                 exynos_dp_poweroff(dp);
1130                 break;
1131         default:
1132                 break;
1133         }
1134         dp->dpms_mode = mode;
1135 }
1136
1137 static struct exynos_drm_display_ops exynos_dp_display_ops = {
1138         .create_connector = exynos_dp_create_connector,
1139         .dpms = exynos_dp_dpms,
1140         .commit = exynos_dp_commit,
1141 };
1142
1143 static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
1144 {
1145         struct device_node *dp_node = dev->of_node;
1146         struct video_info *dp_video_config;
1147
1148         dp_video_config = devm_kzalloc(dev,
1149                                 sizeof(*dp_video_config), GFP_KERNEL);
1150         if (!dp_video_config)
1151                 return ERR_PTR(-ENOMEM);
1152
1153         dp_video_config->h_sync_polarity =
1154                 of_property_read_bool(dp_node, "hsync-active-high");
1155
1156         dp_video_config->v_sync_polarity =
1157                 of_property_read_bool(dp_node, "vsync-active-high");
1158
1159         dp_video_config->interlaced =
1160                 of_property_read_bool(dp_node, "interlaced");
1161
1162         if (of_property_read_u32(dp_node, "samsung,color-space",
1163                                 &dp_video_config->color_space)) {
1164                 dev_err(dev, "failed to get color-space\n");
1165                 return ERR_PTR(-EINVAL);
1166         }
1167
1168         if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1169                                 &dp_video_config->dynamic_range)) {
1170                 dev_err(dev, "failed to get dynamic-range\n");
1171                 return ERR_PTR(-EINVAL);
1172         }
1173
1174         if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1175                                 &dp_video_config->ycbcr_coeff)) {
1176                 dev_err(dev, "failed to get ycbcr-coeff\n");
1177                 return ERR_PTR(-EINVAL);
1178         }
1179
1180         if (of_property_read_u32(dp_node, "samsung,color-depth",
1181                                 &dp_video_config->color_depth)) {
1182                 dev_err(dev, "failed to get color-depth\n");
1183                 return ERR_PTR(-EINVAL);
1184         }
1185
1186         if (of_property_read_u32(dp_node, "samsung,link-rate",
1187                                 &dp_video_config->link_rate)) {
1188                 dev_err(dev, "failed to get link-rate\n");
1189                 return ERR_PTR(-EINVAL);
1190         }
1191
1192         if (of_property_read_u32(dp_node, "samsung,lane-count",
1193                                 &dp_video_config->lane_count)) {
1194                 dev_err(dev, "failed to get lane-count\n");
1195                 return ERR_PTR(-EINVAL);
1196         }
1197
1198         return dp_video_config;
1199 }
1200
1201 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1202 {
1203         int ret;
1204
1205         ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1206                         OF_USE_NATIVE_MODE);
1207         if (ret) {
1208                 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1209                 return ret;
1210         }
1211         return 0;
1212 }
1213
1214 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
1215 {
1216         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1217         struct platform_device *pdev = to_platform_device(dev);
1218         struct drm_device *drm_dev = data;
1219         struct resource *res;
1220         unsigned int irq_flags;
1221         int ret = 0;
1222
1223         dp->dev = &pdev->dev;
1224         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1225
1226         dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1227         if (IS_ERR(dp->video_info))
1228                 return PTR_ERR(dp->video_info);
1229
1230         dp->phy = devm_phy_get(dp->dev, "dp");
1231         if (IS_ERR(dp->phy)) {
1232                 dev_err(dp->dev, "no DP phy configured\n");
1233                 ret = PTR_ERR(dp->phy);
1234                 if (ret) {
1235                         /*
1236                          * phy itself is not enabled, so we can move forward
1237                          * assigning NULL to phy pointer.
1238                          */
1239                         if (ret == -ENOSYS || ret == -ENODEV)
1240                                 dp->phy = NULL;
1241                         else
1242                                 return ret;
1243                 }
1244         }
1245
1246         if (!dp->panel && !dp->bridge) {
1247                 ret = exynos_dp_dt_parse_panel(dp);
1248                 if (ret)
1249                         return ret;
1250         }
1251
1252         dp->clock = devm_clk_get(&pdev->dev, "dp");
1253         if (IS_ERR(dp->clock)) {
1254                 dev_err(&pdev->dev, "failed to get clock\n");
1255                 return PTR_ERR(dp->clock);
1256         }
1257
1258         clk_prepare_enable(dp->clock);
1259
1260         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261
1262         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1263         if (IS_ERR(dp->reg_base))
1264                 return PTR_ERR(dp->reg_base);
1265
1266         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1267
1268         if (gpio_is_valid(dp->hpd_gpio)) {
1269                 /*
1270                  * Set up the hotplug GPIO from the device tree as an interrupt.
1271                  * Simply specifying a different interrupt in the device tree
1272                  * doesn't work since we handle hotplug rather differently when
1273                  * using a GPIO.  We also need the actual GPIO specifier so
1274                  * that we can get the current state of the GPIO.
1275                  */
1276                 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1277                                             "hpd_gpio");
1278                 if (ret) {
1279                         dev_err(&pdev->dev, "failed to get hpd gpio\n");
1280                         return ret;
1281                 }
1282                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1283                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1284         } else {
1285                 dp->hpd_gpio = -ENODEV;
1286                 dp->irq = platform_get_irq(pdev, 0);
1287                 irq_flags = 0;
1288         }
1289
1290         if (dp->irq == -ENXIO) {
1291                 dev_err(&pdev->dev, "failed to get irq\n");
1292                 return -ENODEV;
1293         }
1294
1295         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1296
1297         exynos_dp_phy_init(dp);
1298
1299         exynos_dp_init_dp(dp);
1300
1301         ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1302                         irq_flags, "exynos-dp", dp);
1303         if (ret) {
1304                 dev_err(&pdev->dev, "failed to request irq\n");
1305                 return ret;
1306         }
1307         disable_irq(dp->irq);
1308
1309         dp->drm_dev = drm_dev;
1310
1311         return exynos_drm_create_enc_conn(drm_dev, &dp->display);
1312 }
1313
1314 static void exynos_dp_unbind(struct device *dev, struct device *master,
1315                                 void *data)
1316 {
1317         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1318
1319         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1320 }
1321
1322 static const struct component_ops exynos_dp_ops = {
1323         .bind   = exynos_dp_bind,
1324         .unbind = exynos_dp_unbind,
1325 };
1326
1327 static int exynos_dp_probe(struct platform_device *pdev)
1328 {
1329         struct device *dev = &pdev->dev;
1330         struct device_node *panel_node, *bridge_node, *endpoint;
1331         struct exynos_dp_device *dp;
1332         int ret;
1333
1334         dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1335                                 GFP_KERNEL);
1336         if (!dp)
1337                 return -ENOMEM;
1338
1339         dp->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1340         dp->display.ops = &exynos_dp_display_ops;
1341         platform_set_drvdata(pdev, dp);
1342
1343         ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1344                                         dp->display.type);
1345         if (ret)
1346                 return ret;
1347
1348         panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1349         if (panel_node) {
1350                 dp->panel = of_drm_find_panel(panel_node);
1351                 of_node_put(panel_node);
1352                 if (!dp->panel)
1353                         return -EPROBE_DEFER;
1354         }
1355
1356         endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1357         if (endpoint) {
1358                 bridge_node = of_graph_get_remote_port_parent(endpoint);
1359                 if (bridge_node) {
1360                         dp->bridge = of_drm_find_bridge(bridge_node);
1361                         of_node_put(bridge_node);
1362                         if (!dp->bridge)
1363                                 return -EPROBE_DEFER;
1364                 } else
1365                         return -EPROBE_DEFER;
1366         }
1367
1368         ret = component_add(&pdev->dev, &exynos_dp_ops);
1369         if (ret)
1370                 exynos_drm_component_del(&pdev->dev,
1371                                                 EXYNOS_DEVICE_TYPE_CONNECTOR);
1372
1373         return ret;
1374 }
1375
1376 static int exynos_dp_remove(struct platform_device *pdev)
1377 {
1378         component_del(&pdev->dev, &exynos_dp_ops);
1379         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1380
1381         return 0;
1382 }
1383
1384 #ifdef CONFIG_PM_SLEEP
1385 static int exynos_dp_suspend(struct device *dev)
1386 {
1387         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1388
1389         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1390         return 0;
1391 }
1392
1393 static int exynos_dp_resume(struct device *dev)
1394 {
1395         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1396
1397         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_ON);
1398         return 0;
1399 }
1400 #endif
1401
1402 static const struct dev_pm_ops exynos_dp_pm_ops = {
1403         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1404 };
1405
1406 static const struct of_device_id exynos_dp_match[] = {
1407         { .compatible = "samsung,exynos5-dp" },
1408         {},
1409 };
1410 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1411
1412 struct platform_driver dp_driver = {
1413         .probe          = exynos_dp_probe,
1414         .remove         = exynos_dp_remove,
1415         .driver         = {
1416                 .name   = "exynos-dp",
1417                 .owner  = THIS_MODULE,
1418                 .pm     = &exynos_dp_pm_ops,
1419                 .of_match_table = exynos_dp_match,
1420         },
1421 };
1422
1423 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1424 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1425 MODULE_LICENSE("GPL v2");