drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/irq.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29 #include "regs-decon5433.h"
  30
  31 #define DSD_CFG_MUX 0x1004
  32 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  33
  34 #define WINDOWS_NR      5
  35 #define PRIMARY_WIN     2
  36 #define CURSON_WIN      4
  37
  38 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  39
  40 #define I80_HW_TRG      (1 << 0)
  41 #define IFTYPE_HDMI     (1 << 1)
  42
  43 static const char * const decon_clks_name[] = {
  44         "pclk",
  45         "aclk_decon",
  46         "aclk_smmu_decon0x",
  47         "aclk_xiu_decon0x",
  48         "pclk_smmu_decon0x",
  49         "aclk_smmu_decon1x",
  50         "aclk_xiu_decon1x",
  51         "pclk_smmu_decon1x",
  52         "sclk_decon_vclk",
  53         "sclk_decon_eclk",
  54 };
  55
  56 struct decon_context {
  57         struct device                   *dev;
  58         struct drm_device               *drm_dev;
  59         struct exynos_drm_crtc          *crtc;
  60         struct exynos_drm_plane         planes[WINDOWS_NR];
  61         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  62         void __iomem                    *addr;
  63         struct regmap                   *sysreg;
  64         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  65         unsigned int                    irq;
  66         unsigned int                    irq_vsync;
  67         unsigned int                    irq_lcd_sys;
  68         unsigned int                    te_irq;
  69         unsigned long                   out_type;
  70         int                             first_win;
  71         spinlock_t                      vblank_lock;
  72         u32                             frame_id;
  73 };
  74
  75 static const uint32_t decon_formats[] = {
  76         DRM_FORMAT_XRGB1555,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  83         [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
  84         [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
  85 };
  86
  87 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  88                                   u32 val)
  89 {
  90         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  91         writel(val, ctx->addr + reg);
  92 }
  93
  94 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  95 {
  96         struct decon_context *ctx = crtc->ctx;
  97         u32 val;
  98
  99         val = VIDINTCON0_INTEN;
 100         if (crtc->i80_mode)
 101                 val |= VIDINTCON0_FRAMEDONE;
 102         else
 103                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 104
 105         writel(val, ctx->addr + DECON_VIDINTCON0);
 106
 107         enable_irq(ctx->irq);
 108         if (!(ctx->out_type & I80_HW_TRG))
 109                 enable_irq(ctx->te_irq);
 110
 111         return 0;
 112 }
 113
 114 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 115 {
 116         struct decon_context *ctx = crtc->ctx;
 117
 118         if (!(ctx->out_type & I80_HW_TRG))
 119                 disable_irq_nosync(ctx->te_irq);
 120         disable_irq_nosync(ctx->irq);
 121
 122         writel(0, ctx->addr + DECON_VIDINTCON0);
 123 }
 124
 125 /* return number of starts/ends of frame transmissions since reset */
 126 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 127 {
 128         u32 frm, pfrm, status, cnt = 2;
 129
 130         /* To get consistent result repeat read until frame id is stable.
 131          * Usually the loop will be executed once, in rare cases when the loop
 132          * is executed at frame change time 2nd pass will be needed.
 133          */
 134         frm = readl(ctx->addr + DECON_CRFMID);
 135         do {
 136                 status = readl(ctx->addr + DECON_VIDCON1);
 137                 pfrm = frm;
 138                 frm = readl(ctx->addr + DECON_CRFMID);
 139         } while (frm != pfrm && --cnt);
 140
 141         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 142          * of RGB, it should be taken into account.
 143          */
 144         if (!frm)
 145                 return 0;
 146
 147         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 148         case VIDCON1_VSTATUS_VS:
 149                 if (!(ctx->crtc->i80_mode))
 150                         --frm;
 151                 break;
 152         case VIDCON1_VSTATUS_BP:
 153                 --frm;
 154                 break;
 155         case VIDCON1_I80_ACTIVE:
 156         case VIDCON1_VSTATUS_AC:
 157                 if (end)
 158                         --frm;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         return frm;
 165 }
 166
 167 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 168 {
 169         struct decon_context *ctx = crtc->ctx;
 170
 171         return decon_get_frame_count(ctx, false);
 172 }
 173
 174 static void decon_setup_trigger(struct decon_context *ctx)
 175 {
 176         if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
 177                 return;
 178
 179         if (!(ctx->out_type & I80_HW_TRG)) {
 180                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 181                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 182                        ctx->addr + DECON_TRIGCON);
 183                 return;
 184         }
 185
 186         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 187                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 188
 189         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 190                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 191                 DRM_ERROR("Cannot update sysreg.\n");
 192 }
 193
 194 static void decon_commit(struct exynos_drm_crtc *crtc)
 195 {
 196         struct decon_context *ctx = crtc->ctx;
 197         struct drm_display_mode *m = &crtc->base.mode;
 198         bool interlaced = false;
 199         u32 val;
 200
 201         if (ctx->out_type & IFTYPE_HDMI) {
 202                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 203                 m->crtc_hsync_end = m->crtc_htotal - 92;
 204                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 205                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 206                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 207                         interlaced = true;
 208         }
 209
 210         decon_setup_trigger(ctx);
 211
 212         /* lcd on and use command if */
 213         val = VIDOUT_LCD_ON;
 214         if (interlaced)
 215                 val |= VIDOUT_INTERLACE_EN_F;
 216         if (crtc->i80_mode) {
 217                 val |= VIDOUT_COMMAND_IF;
 218         } else {
 219                 val |= VIDOUT_RGB_IF;
 220         }
 221
 222         writel(val, ctx->addr + DECON_VIDOUTCON0);
 223
 224         if (interlaced)
 225                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 226                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 227         else
 228                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 229                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 230         writel(val, ctx->addr + DECON_VIDTCON2);
 231
 232         if (!crtc->i80_mode) {
 233                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 234                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 235
 236                 if (interlaced)
 237                         vbp = vbp / 2 - 1;
 238                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 239                 writel(val, ctx->addr + DECON_VIDTCON00);
 240
 241                 val = VIDTCON01_VSPW_F(
 242                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 243                 writel(val, ctx->addr + DECON_VIDTCON01);
 244
 245                 val = VIDTCON10_HBPD_F(
 246                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 247                         VIDTCON10_HFPD_F(
 248                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 249                 writel(val, ctx->addr + DECON_VIDTCON10);
 250
 251                 val = VIDTCON11_HSPW_F(
 252                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 253                 writel(val, ctx->addr + DECON_VIDTCON11);
 254         }
 255
 256         /* enable output and display signal */
 257         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 258
 259         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 260 }
 261
 262 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 263                                  struct drm_framebuffer *fb)
 264 {
 265         unsigned long val;
 266
 267         val = readl(ctx->addr + DECON_WINCONx(win));
 268         val &= WINCONx_ENWIN_F;
 269
 270         switch (fb->format->format) {
 271         case DRM_FORMAT_XRGB1555:
 272                 val |= WINCONx_BPPMODE_16BPP_I1555;
 273                 val |= WINCONx_HAWSWP_F;
 274                 val |= WINCONx_BURSTLEN_16WORD;
 275                 break;
 276         case DRM_FORMAT_RGB565:
 277                 val |= WINCONx_BPPMODE_16BPP_565;
 278                 val |= WINCONx_HAWSWP_F;
 279                 val |= WINCONx_BURSTLEN_16WORD;
 280                 break;
 281         case DRM_FORMAT_XRGB8888:
 282                 val |= WINCONx_BPPMODE_24BPP_888;
 283                 val |= WINCONx_WSWP_F;
 284                 val |= WINCONx_BURSTLEN_16WORD;
 285                 break;
 286         case DRM_FORMAT_ARGB8888:
 287         default:
 288                 val |= WINCONx_BPPMODE_32BPP_A8888;
 289                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 290                 val |= WINCONx_BURSTLEN_16WORD;
 291                 break;
 292         }
 293
 294         DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]);
 295
 296         /*
 297          * In case of exynos, setting dma-burst to 16Word causes permanent
 298          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 299          * switching which is based on plane size is not recommended as
 300          * plane size varies a lot towards the end of the screen and rapid
 301          * movement causes unstable DMA which results into iommu crash/tear.
 302          */
 303
 304         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 305                 val &= ~WINCONx_BURSTLEN_MASK;
 306                 val |= WINCONx_BURSTLEN_8WORD;
 307         }
 308
 309         writel(val, ctx->addr + DECON_WINCONx(win));
 310 }
 311
 312 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
 313 {
 314         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
 315                        protect ? ~0 : 0);
 316 }
 317
 318 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 319 {
 320         struct decon_context *ctx = crtc->ctx;
 321
 322         decon_shadow_protect(ctx, true);
 323 }
 324
 325 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 326 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 327 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 328
 329 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 330                                struct exynos_drm_plane *plane)
 331 {
 332         struct exynos_drm_plane_state *state =
 333                                 to_exynos_plane_state(plane->base.state);
 334         struct decon_context *ctx = crtc->ctx;
 335         struct drm_framebuffer *fb = state->base.fb;
 336         unsigned int win = plane->index;
 337         unsigned int cpp = fb->format->cpp[0];
 338         unsigned int pitch = fb->pitches[0];
 339         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 340         u32 val;
 341
 342         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 343                 val = COORDINATE_X(state->crtc.x) |
 344                         COORDINATE_Y(state->crtc.y / 2);
 345                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 346
 347                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 348                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 349                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 350         } else {
 351                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 352                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 353
 354                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 355                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 356                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 357         }
 358
 359         val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
 360                 VIDOSD_Wx_ALPHA_B_F(0xff);
 361         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 362
 363         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 364                 VIDOSD_Wx_ALPHA_B_F(0x0);
 365         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 366
 367         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 368
 369         val = dma_addr + pitch * state->src.h;
 370         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 371
 372         if (!(ctx->out_type & IFTYPE_HDMI))
 373                 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
 374                         | BIT_VAL(state->crtc.w * cpp, 13, 0);
 375         else
 376                 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
 377                         | BIT_VAL(state->crtc.w * cpp, 14, 0);
 378         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 379
 380         decon_win_set_pixfmt(ctx, win, fb);
 381
 382         /* window enable */
 383         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 384 }
 385
 386 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 387                                 struct exynos_drm_plane *plane)
 388 {
 389         struct decon_context *ctx = crtc->ctx;
 390         unsigned int win = plane->index;
 391
 392         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 393 }
 394
 395 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 396 {
 397         struct decon_context *ctx = crtc->ctx;
 398         unsigned long flags;
 399
 400         spin_lock_irqsave(&ctx->vblank_lock, flags);
 401
 402         decon_shadow_protect(ctx, false);
 403
 404         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 405
 406         ctx->frame_id = decon_get_frame_count(ctx, true);
 407
 408         exynos_crtc_handle_event(crtc);
 409
 410         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 411 }
 412
 413 static void decon_swreset(struct decon_context *ctx)
 414 {
 415         unsigned long flags;
 416         u32 val;
 417         int ret;
 418
 419         writel(0, ctx->addr + DECON_VIDCON0);
 420         readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 421                            ~val & VIDCON0_STOP_STATUS, 12, 20000);
 422
 423         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 424         ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 425                                  ~val & VIDCON0_SWRESET, 12, 20000);
 426
 427         WARN(ret < 0, "failed to software reset DECON\n");
 428
 429         spin_lock_irqsave(&ctx->vblank_lock, flags);
 430         ctx->frame_id = 0;
 431         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 432
 433         if (!(ctx->out_type & IFTYPE_HDMI))
 434                 return;
 435
 436         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 437         decon_set_bits(ctx, DECON_CMU,
 438                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 439         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 440         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 441                ctx->addr + DECON_CRCCTRL);
 442 }
 443
 444 static void decon_enable(struct exynos_drm_crtc *crtc)
 445 {
 446         struct decon_context *ctx = crtc->ctx;
 447
 448         pm_runtime_get_sync(ctx->dev);
 449
 450         exynos_drm_pipe_clk_enable(crtc, true);
 451
 452         decon_swreset(ctx);
 453
 454         decon_commit(ctx->crtc);
 455 }
 456
 457 static void decon_disable(struct exynos_drm_crtc *crtc)
 458 {
 459         struct decon_context *ctx = crtc->ctx;
 460         int i;
 461
 462         if (!(ctx->out_type & I80_HW_TRG))
 463                 synchronize_irq(ctx->te_irq);
 464         synchronize_irq(ctx->irq);
 465
 466         /*
 467          * We need to make sure that all windows are disabled before we
 468          * suspend that connector. Otherwise we might try to scan from
 469          * a destroyed buffer later.
 470          */
 471         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 472                 decon_disable_plane(crtc, &ctx->planes[i]);
 473
 474         decon_swreset(ctx);
 475
 476         exynos_drm_pipe_clk_enable(crtc, false);
 477
 478         pm_runtime_put_sync(ctx->dev);
 479 }
 480
 481 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
 482 {
 483         struct decon_context *ctx = dev_id;
 484
 485         decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 486
 487         return IRQ_HANDLED;
 488 }
 489
 490 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 491 {
 492         struct decon_context *ctx = crtc->ctx;
 493         int win, i, ret;
 494
 495         DRM_DEBUG_KMS("%s\n", __FILE__);
 496
 497         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 498                 ret = clk_prepare_enable(ctx->clks[i]);
 499                 if (ret < 0)
 500                         goto err;
 501         }
 502
 503         decon_shadow_protect(ctx, true);
 504         for (win = 0; win < WINDOWS_NR; win++)
 505                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 506         decon_shadow_protect(ctx, false);
 507
 508         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 509
 510         /* TODO: wait for possible vsync */
 511         msleep(50);
 512
 513 err:
 514         while (--i >= 0)
 515                 clk_disable_unprepare(ctx->clks[i]);
 516 }
 517
 518 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
 519                 const struct drm_display_mode *mode)
 520 {
 521         struct decon_context *ctx = crtc->ctx;
 522
 523         ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
 524
 525         if (ctx->irq)
 526                 return MODE_OK;
 527
 528         dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
 529                         crtc->i80_mode ? "command" : "video");
 530
 531         return MODE_BAD;
 532 }
 533
 534 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 535         .enable                 = decon_enable,
 536         .disable                = decon_disable,
 537         .enable_vblank          = decon_enable_vblank,
 538         .disable_vblank         = decon_disable_vblank,
 539         .get_vblank_counter     = decon_get_vblank_counter,
 540         .atomic_begin           = decon_atomic_begin,
 541         .update_plane           = decon_update_plane,
 542         .disable_plane          = decon_disable_plane,
 543         .mode_valid             = decon_mode_valid,
 544         .atomic_flush           = decon_atomic_flush,
 545 };
 546
 547 static int decon_bind(struct device *dev, struct device *master, void *data)
 548 {
 549         struct decon_context *ctx = dev_get_drvdata(dev);
 550         struct drm_device *drm_dev = data;
 551         struct exynos_drm_plane *exynos_plane;
 552         enum exynos_drm_output_type out_type;
 553         unsigned int win;
 554         int ret;
 555
 556         ctx->drm_dev = drm_dev;
 557         drm_dev->max_vblank_count = 0xffffffff;
 558
 559         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 560                 ctx->configs[win].pixel_formats = decon_formats;
 561                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 562                 ctx->configs[win].zpos = win - ctx->first_win;
 563                 ctx->configs[win].type = decon_win_types[win];
 564
 565                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 566                                         &ctx->configs[win]);
 567                 if (ret)
 568                         return ret;
 569         }
 570
 571         exynos_plane = &ctx->planes[PRIMARY_WIN];
 572         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 573                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 574         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 575                         out_type, &decon_crtc_ops, ctx);
 576         if (IS_ERR(ctx->crtc))
 577                 return PTR_ERR(ctx->crtc);
 578
 579         decon_clear_channels(ctx->crtc);
 580
 581         return drm_iommu_attach_device(drm_dev, dev);
 582 }
 583
 584 static void decon_unbind(struct device *dev, struct device *master, void *data)
 585 {
 586         struct decon_context *ctx = dev_get_drvdata(dev);
 587
 588         decon_disable(ctx->crtc);
 589
 590         /* detach this sub driver from iommu mapping if supported. */
 591         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 592 }
 593
 594 static const struct component_ops decon_component_ops = {
 595         .bind   = decon_bind,
 596         .unbind = decon_unbind,
 597 };
 598
 599 static void decon_handle_vblank(struct decon_context *ctx)
 600 {
 601         u32 frm;
 602
 603         spin_lock(&ctx->vblank_lock);
 604
 605         frm = decon_get_frame_count(ctx, true);
 606
 607         if (frm != ctx->frame_id) {
 608                 /* handle only if incremented, take care of wrap-around */
 609                 if ((s32)(frm - ctx->frame_id) > 0)
 610                         drm_crtc_handle_vblank(&ctx->crtc->base);
 611                 ctx->frame_id = frm;
 612         }
 613
 614         spin_unlock(&ctx->vblank_lock);
 615 }
 616
 617 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 618 {
 619         struct decon_context *ctx = dev_id;
 620         u32 val;
 621
 622         val = readl(ctx->addr + DECON_VIDINTCON1);
 623         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 624
 625         if (val) {
 626                 writel(val, ctx->addr + DECON_VIDINTCON1);
 627                 if (ctx->out_type & IFTYPE_HDMI) {
 628                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 629                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 630                         if (val ==
 631                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 632                                 return IRQ_HANDLED;
 633                 }
 634                 decon_handle_vblank(ctx);
 635         }
 636
 637         return IRQ_HANDLED;
 638 }
 639
 640 #ifdef CONFIG_PM
 641 static int exynos5433_decon_suspend(struct device *dev)
 642 {
 643         struct decon_context *ctx = dev_get_drvdata(dev);
 644         int i = ARRAY_SIZE(decon_clks_name);
 645
 646         while (--i >= 0)
 647                 clk_disable_unprepare(ctx->clks[i]);
 648
 649         return 0;
 650 }
 651
 652 static int exynos5433_decon_resume(struct device *dev)
 653 {
 654         struct decon_context *ctx = dev_get_drvdata(dev);
 655         int i, ret;
 656
 657         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 658                 ret = clk_prepare_enable(ctx->clks[i]);
 659                 if (ret < 0)
 660                         goto err;
 661         }
 662
 663         return 0;
 664
 665 err:
 666         while (--i >= 0)
 667                 clk_disable_unprepare(ctx->clks[i]);
 668
 669         return ret;
 670 }
 671 #endif
 672
 673 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 674         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 675                            NULL)
 676         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 677                                      pm_runtime_force_resume)
 678 };
 679
 680 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 681         {
 682                 .compatible = "samsung,exynos5433-decon",
 683                 .data = (void *)I80_HW_TRG
 684         },
 685         {
 686                 .compatible = "samsung,exynos5433-decon-tv",
 687                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 688         },
 689         {},
 690 };
 691 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 692
 693 static int decon_conf_irq(struct decon_context *ctx, const char *name,
 694                 irq_handler_t handler, unsigned long int flags)
 695 {
 696         struct platform_device *pdev = to_platform_device(ctx->dev);
 697         int ret, irq = platform_get_irq_byname(pdev, name);
 698
 699         if (irq < 0) {
 700                 switch (irq) {
 701                 case -EPROBE_DEFER:
 702                         return irq;
 703                 case -ENODATA:
 704                 case -ENXIO:
 705                         return 0;
 706                 default:
 707                         dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
 708                         return irq;
 709                 }
 710         }
 711         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 712         ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
 713         if (ret < 0) {
 714                 dev_err(ctx->dev, "IRQ %s request failed\n", name);
 715                 return ret;
 716         }
 717
 718         return irq;
 719 }
 720
 721 static int exynos5433_decon_probe(struct platform_device *pdev)
 722 {
 723         struct device *dev = &pdev->dev;
 724         struct decon_context *ctx;
 725         struct resource *res;
 726         int ret;
 727         int i;
 728
 729         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 730         if (!ctx)
 731                 return -ENOMEM;
 732
 733         ctx->dev = dev;
 734         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 735         spin_lock_init(&ctx->vblank_lock);
 736
 737         if (ctx->out_type & IFTYPE_HDMI)
 738                 ctx->first_win = 1;
 739
 740         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 741                 struct clk *clk;
 742
 743                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 744                 if (IS_ERR(clk))
 745                         return PTR_ERR(clk);
 746
 747                 ctx->clks[i] = clk;
 748         }
 749
 750         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 751         ctx->addr = devm_ioremap_resource(dev, res);
 752         if (IS_ERR(ctx->addr)) {
 753                 dev_err(dev, "ioremap failed\n");
 754                 return PTR_ERR(ctx->addr);
 755         }
 756
 757         ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
 758         if (ret < 0)
 759                 return ret;
 760         ctx->irq_vsync = ret;
 761
 762         ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
 763         if (ret < 0)
 764                 return ret;
 765         ctx->irq_lcd_sys = ret;
 766
 767         ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
 768                         IRQF_TRIGGER_RISING);
 769         if (ret < 0)
 770                         return ret;
 771         if (ret) {
 772                 ctx->te_irq = ret;
 773                 ctx->out_type &= ~I80_HW_TRG;
 774         }
 775
 776         if (ctx->out_type & I80_HW_TRG) {
 777                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 778                                                         "samsung,disp-sysreg");
 779                 if (IS_ERR(ctx->sysreg)) {
 780                         dev_err(dev, "failed to get system register\n");
 781                         return PTR_ERR(ctx->sysreg);
 782                 }
 783         }
 784
 785         platform_set_drvdata(pdev, ctx);
 786
 787         pm_runtime_enable(dev);
 788
 789         ret = component_add(dev, &decon_component_ops);
 790         if (ret)
 791                 goto err_disable_pm_runtime;
 792
 793         return 0;
 794
 795 err_disable_pm_runtime:
 796         pm_runtime_disable(dev);
 797
 798         return ret;
 799 }
 800
 801 static int exynos5433_decon_remove(struct platform_device *pdev)
 802 {
 803         pm_runtime_disable(&pdev->dev);
 804
 805         component_del(&pdev->dev, &decon_component_ops);
 806
 807         return 0;
 808 }
 809
 810 struct platform_driver exynos5433_decon_driver = {
 811         .probe          = exynos5433_decon_probe,
 812         .remove         = exynos5433_decon_remove,
 813         .driver         = {
 814                 .name   = "exynos5433-decon",
 815                 .pm     = &exynos5433_decon_pm_ops,
 816                 .of_match_table = exynos5433_decon_driver_dt_match,
 817         },
 818 };