drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2015-2018 Etnaviv Project
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/dma-fence.h>
   9 #include <linux/moduleparam.h>
  10 #include <linux/of_device.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/thermal.h>
  13
  14 #include "etnaviv_cmdbuf.h"
  15 #include "etnaviv_dump.h"
  16 #include "etnaviv_gpu.h"
  17 #include "etnaviv_gem.h"
  18 #include "etnaviv_mmu.h"
  19 #include "etnaviv_perfmon.h"
  20 #include "etnaviv_sched.h"
  21 #include "common.xml.h"
  22 #include "state.xml.h"
  23 #include "state_hi.xml.h"
  24 #include "cmdstream.xml.h"
  25
  26 #ifndef PHYS_OFFSET
  27 #define PHYS_OFFSET 0
  28 #endif
  29
  30 static const struct platform_device_id gpu_ids[] = {
  31         { .name = "etnaviv-gpu,2d" },
  32         { },
  33 };
  34
  35 /*
  36  * Driver functions:
  37  */
  38
  39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  40 {
  41         switch (param) {
  42         case ETNAVIV_PARAM_GPU_MODEL:
  43                 *value = gpu->identity.model;
  44                 break;
  45
  46         case ETNAVIV_PARAM_GPU_REVISION:
  47                 *value = gpu->identity.revision;
  48                 break;
  49
  50         case ETNAVIV_PARAM_GPU_FEATURES_0:
  51                 *value = gpu->identity.features;
  52                 break;
  53
  54         case ETNAVIV_PARAM_GPU_FEATURES_1:
  55                 *value = gpu->identity.minor_features0;
  56                 break;
  57
  58         case ETNAVIV_PARAM_GPU_FEATURES_2:
  59                 *value = gpu->identity.minor_features1;
  60                 break;
  61
  62         case ETNAVIV_PARAM_GPU_FEATURES_3:
  63                 *value = gpu->identity.minor_features2;
  64                 break;
  65
  66         case ETNAVIV_PARAM_GPU_FEATURES_4:
  67                 *value = gpu->identity.minor_features3;
  68                 break;
  69
  70         case ETNAVIV_PARAM_GPU_FEATURES_5:
  71                 *value = gpu->identity.minor_features4;
  72                 break;
  73
  74         case ETNAVIV_PARAM_GPU_FEATURES_6:
  75                 *value = gpu->identity.minor_features5;
  76                 break;
  77
  78         case ETNAVIV_PARAM_GPU_FEATURES_7:
  79                 *value = gpu->identity.minor_features6;
  80                 break;
  81
  82         case ETNAVIV_PARAM_GPU_FEATURES_8:
  83                 *value = gpu->identity.minor_features7;
  84                 break;
  85
  86         case ETNAVIV_PARAM_GPU_FEATURES_9:
  87                 *value = gpu->identity.minor_features8;
  88                 break;
  89
  90         case ETNAVIV_PARAM_GPU_FEATURES_10:
  91                 *value = gpu->identity.minor_features9;
  92                 break;
  93
  94         case ETNAVIV_PARAM_GPU_FEATURES_11:
  95                 *value = gpu->identity.minor_features10;
  96                 break;
  97
  98         case ETNAVIV_PARAM_GPU_FEATURES_12:
  99                 *value = gpu->identity.minor_features11;
 100                 break;
 101
 102         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 103                 *value = gpu->identity.stream_count;
 104                 break;
 105
 106         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 107                 *value = gpu->identity.register_max;
 108                 break;
 109
 110         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 111                 *value = gpu->identity.thread_count;
 112                 break;
 113
 114         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 115                 *value = gpu->identity.vertex_cache_size;
 116                 break;
 117
 118         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 119                 *value = gpu->identity.shader_core_count;
 120                 break;
 121
 122         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 123                 *value = gpu->identity.pixel_pipes;
 124                 break;
 125
 126         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 127                 *value = gpu->identity.vertex_output_buffer_size;
 128                 break;
 129
 130         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 131                 *value = gpu->identity.buffer_size;
 132                 break;
 133
 134         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 135                 *value = gpu->identity.instruction_count;
 136                 break;
 137
 138         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 139                 *value = gpu->identity.num_constants;
 140                 break;
 141
 142         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 143                 *value = gpu->identity.varyings_count;
 144                 break;
 145
 146         default:
 147                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 148                 return -EINVAL;
 149         }
 150
 151         return 0;
 152 }
 153
 154
 155 #define etnaviv_is_model_rev(gpu, mod, rev) \
 156         ((gpu)->identity.model == chipModel_##mod && \
 157          (gpu)->identity.revision == rev)
 158 #define etnaviv_field(val, field) \
 159         (((val) & field##__MASK) >> field##__SHIFT)
 160
 161 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 162 {
 163         if (gpu->identity.minor_features0 &
 164             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 165                 u32 specs[4];
 166                 unsigned int streams;
 167
 168                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 169                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 170                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 171                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 172
 173                 gpu->identity.stream_count = etnaviv_field(specs[0],
 174                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 175                 gpu->identity.register_max = etnaviv_field(specs[0],
 176                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 177                 gpu->identity.thread_count = etnaviv_field(specs[0],
 178                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 179                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 180                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 181                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 182                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 183                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 184                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 185                 gpu->identity.vertex_output_buffer_size =
 186                         etnaviv_field(specs[0],
 187                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 188
 189                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 190                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 191                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 192                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 193                 gpu->identity.num_constants = etnaviv_field(specs[1],
 194                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 195
 196                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 197                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 198
 199                 /* This overrides the value from older register if non-zero */
 200                 streams = etnaviv_field(specs[3],
 201                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 202                 if (streams)
 203                         gpu->identity.stream_count = streams;
 204         }
 205
 206         /* Fill in the stream count if not specified */
 207         if (gpu->identity.stream_count == 0) {
 208                 if (gpu->identity.model >= 0x1000)
 209                         gpu->identity.stream_count = 4;
 210                 else
 211                         gpu->identity.stream_count = 1;
 212         }
 213
 214         /* Convert the register max value */
 215         if (gpu->identity.register_max)
 216                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 217         else if (gpu->identity.model == chipModel_GC400)
 218                 gpu->identity.register_max = 32;
 219         else
 220                 gpu->identity.register_max = 64;
 221
 222         /* Convert thread count */
 223         if (gpu->identity.thread_count)
 224                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 225         else if (gpu->identity.model == chipModel_GC400)
 226                 gpu->identity.thread_count = 64;
 227         else if (gpu->identity.model == chipModel_GC500 ||
 228                  gpu->identity.model == chipModel_GC530)
 229                 gpu->identity.thread_count = 128;
 230         else
 231                 gpu->identity.thread_count = 256;
 232
 233         if (gpu->identity.vertex_cache_size == 0)
 234                 gpu->identity.vertex_cache_size = 8;
 235
 236         if (gpu->identity.shader_core_count == 0) {
 237                 if (gpu->identity.model >= 0x1000)
 238                         gpu->identity.shader_core_count = 2;
 239                 else
 240                         gpu->identity.shader_core_count = 1;
 241         }
 242
 243         if (gpu->identity.pixel_pipes == 0)
 244                 gpu->identity.pixel_pipes = 1;
 245
 246         /* Convert virtex buffer size */
 247         if (gpu->identity.vertex_output_buffer_size) {
 248                 gpu->identity.vertex_output_buffer_size =
 249                         1 << gpu->identity.vertex_output_buffer_size;
 250         } else if (gpu->identity.model == chipModel_GC400) {
 251                 if (gpu->identity.revision < 0x4000)
 252                         gpu->identity.vertex_output_buffer_size = 512;
 253                 else if (gpu->identity.revision < 0x4200)
 254                         gpu->identity.vertex_output_buffer_size = 256;
 255                 else
 256                         gpu->identity.vertex_output_buffer_size = 128;
 257         } else {
 258                 gpu->identity.vertex_output_buffer_size = 512;
 259         }
 260
 261         switch (gpu->identity.instruction_count) {
 262         case 0:
 263                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 264                     gpu->identity.model == chipModel_GC880)
 265                         gpu->identity.instruction_count = 512;
 266                 else
 267                         gpu->identity.instruction_count = 256;
 268                 break;
 269
 270         case 1:
 271                 gpu->identity.instruction_count = 1024;
 272                 break;
 273
 274         case 2:
 275                 gpu->identity.instruction_count = 2048;
 276                 break;
 277
 278         default:
 279                 gpu->identity.instruction_count = 256;
 280                 break;
 281         }
 282
 283         if (gpu->identity.num_constants == 0)
 284                 gpu->identity.num_constants = 168;
 285
 286         if (gpu->identity.varyings_count == 0) {
 287                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 288                         gpu->identity.varyings_count = 12;
 289                 else
 290                         gpu->identity.varyings_count = 8;
 291         }
 292
 293         /*
 294          * For some cores, two varyings are consumed for position, so the
 295          * maximum varying count needs to be reduced by one.
 296          */
 297         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 298             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 299             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 300             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 301             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 302             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 303             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 304             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 305             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 306             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 307             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 308                 gpu->identity.varyings_count -= 1;
 309 }
 310
 311 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 312 {
 313         u32 chipIdentity;
 314
 315         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 316
 317         /* Special case for older graphic cores. */
 318         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 319                 gpu->identity.model    = chipModel_GC500;
 320                 gpu->identity.revision = etnaviv_field(chipIdentity,
 321                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 322         } else {
 323
 324                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 325                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 326
 327                 /*
 328                  * !!!! HACK ALERT !!!!
 329                  * Because people change device IDs without letting software
 330                  * know about it - here is the hack to make it all look the
 331                  * same.  Only for GC400 family.
 332                  */
 333                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 334                     gpu->identity.model != chipModel_GC420) {
 335                         gpu->identity.model = gpu->identity.model & 0x0400;
 336                 }
 337
 338                 /* Another special case */
 339                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 340                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 341                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 342
 343                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 344                                 /*
 345                                  * This IP has an ECO; put the correct
 346                                  * revision in it.
 347                                  */
 348                                 gpu->identity.revision = 0x1051;
 349                         }
 350                 }
 351
 352                 /*
 353                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 354                  * reality it's just a re-branded GC3000. We can identify this
 355                  * core by the upper half of the revision register being all 1.
 356                  * Fix model/rev here, so all other places can refer to this
 357                  * core by its real identity.
 358                  */
 359                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 360                         gpu->identity.model = chipModel_GC3000;
 361                         gpu->identity.revision &= 0xffff;
 362                 }
 363         }
 364
 365         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 366                  gpu->identity.model, gpu->identity.revision);
 367
 368         gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 369         /*
 370          * If there is a match in the HWDB, we aren't interested in the
 371          * remaining register values, as they might be wrong.
 372          */
 373         if (etnaviv_fill_identity_from_hwdb(gpu))
 374                 return;
 375
 376         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 377
 378         /* Disable fast clear on GC700. */
 379         if (gpu->identity.model == chipModel_GC700)
 380                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 381
 382         if ((gpu->identity.model == chipModel_GC500 &&
 383              gpu->identity.revision < 2) ||
 384             (gpu->identity.model == chipModel_GC300 &&
 385              gpu->identity.revision < 0x2000)) {
 386
 387                 /*
 388                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 389                  * registers.
 390                  */
 391                 gpu->identity.minor_features0 = 0;
 392                 gpu->identity.minor_features1 = 0;
 393                 gpu->identity.minor_features2 = 0;
 394                 gpu->identity.minor_features3 = 0;
 395                 gpu->identity.minor_features4 = 0;
 396                 gpu->identity.minor_features5 = 0;
 397         } else
 398                 gpu->identity.minor_features0 =
 399                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 400
 401         if (gpu->identity.minor_features0 &
 402             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 403                 gpu->identity.minor_features1 =
 404                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 405                 gpu->identity.minor_features2 =
 406                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 407                 gpu->identity.minor_features3 =
 408                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 409                 gpu->identity.minor_features4 =
 410                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 411                 gpu->identity.minor_features5 =
 412                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 413         }
 414
 415         /* GC600 idle register reports zero bits where modules aren't present */
 416         if (gpu->identity.model == chipModel_GC600)
 417                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 418                                  VIVS_HI_IDLE_STATE_RA |
 419                                  VIVS_HI_IDLE_STATE_SE |
 420                                  VIVS_HI_IDLE_STATE_PA |
 421                                  VIVS_HI_IDLE_STATE_SH |
 422                                  VIVS_HI_IDLE_STATE_PE |
 423                                  VIVS_HI_IDLE_STATE_DE |
 424                                  VIVS_HI_IDLE_STATE_FE;
 425
 426         etnaviv_hw_specs(gpu);
 427 }
 428
 429 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 430 {
 431         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 432                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 433         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 434 }
 435
 436 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 437 {
 438         if (gpu->identity.minor_features2 &
 439             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 440                 clk_set_rate(gpu->clk_core,
 441                              gpu->base_rate_core >> gpu->freq_scale);
 442                 clk_set_rate(gpu->clk_shader,
 443                              gpu->base_rate_shader >> gpu->freq_scale);
 444         } else {
 445                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 446                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 447
 448                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 449                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 450                 etnaviv_gpu_load_clock(gpu, clock);
 451         }
 452 }
 453
 454 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 455 {
 456         u32 control, idle;
 457         unsigned long timeout;
 458         bool failed = true;
 459
 460         /* We hope that the GPU resets in under one second */
 461         timeout = jiffies + msecs_to_jiffies(1000);
 462
 463         while (time_is_after_jiffies(timeout)) {
 464                 /* enable clock */
 465                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 466                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 467                 etnaviv_gpu_load_clock(gpu, control);
 468
 469                 /* isolate the GPU. */
 470                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 471                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 472
 473                 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 474                         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 475                                   VIVS_MMUv2_AHB_CONTROL_RESET);
 476                 } else {
 477                         /* set soft reset. */
 478                         control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 479                         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 480                 }
 481
 482                 /* wait for reset. */
 483                 usleep_range(10, 20);
 484
 485                 /* reset soft reset bit. */
 486                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 487                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 488
 489                 /* reset GPU isolation. */
 490                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 491                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 492
 493                 /* read idle register. */
 494                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 495
 496                 /* try reseting again if FE it not idle */
 497                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 498                         dev_dbg(gpu->dev, "FE is not idle\n");
 499                         continue;
 500                 }
 501
 502                 /* read reset register. */
 503                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 504
 505                 /* is the GPU idle? */
 506                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 507                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 508                         dev_dbg(gpu->dev, "GPU is not idle\n");
 509                         continue;
 510                 }
 511
 512                 /* disable debug registers, as they are not normally needed */
 513                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 514                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 515
 516                 failed = false;
 517                 break;
 518         }
 519
 520         if (failed) {
 521                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 522                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 523
 524                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 525                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 526                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 527                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 528
 529                 return -EBUSY;
 530         }
 531
 532         /* We rely on the GPU running, so program the clock */
 533         etnaviv_gpu_update_clock(gpu);
 534
 535         return 0;
 536 }
 537
 538 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 539 {
 540         u32 pmc, ppc;
 541
 542         /* enable clock gating */
 543         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 544         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 545
 546         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 547         if (gpu->identity.revision == 0x4301 ||
 548             gpu->identity.revision == 0x4302)
 549                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 550
 551         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 552
 553         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 554
 555         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 556         if (gpu->identity.model >= chipModel_GC400 &&
 557             gpu->identity.model != chipModel_GC420 &&
 558             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 559                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 560
 561         /*
 562          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 563          * present without a bug fix.
 564          */
 565         if (gpu->identity.revision < 0x5000 &&
 566             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 567             !(gpu->identity.minor_features1 &
 568               chipMinorFeatures1_DISABLE_PE_GATING))
 569                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 570
 571         if (gpu->identity.revision < 0x5422)
 572                 pmc |= BIT(15); /* Unknown bit */
 573
 574         /* Disable TX clock gating on affected core revisions. */
 575         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 576             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
 577                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 578
 579         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 580         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 581
 582         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 583 }
 584
 585 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 586 {
 587         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 588         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 589                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 590                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 591
 592         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 593                 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 594                           VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 595                           VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 596         }
 597 }
 598
 599 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 600 {
 601         /*
 602          * Base value for VIVS_PM_PULSE_EATER register on models where it
 603          * cannot be read, extracted from vivante kernel driver.
 604          */
 605         u32 pulse_eater = 0x01590880;
 606
 607         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 608             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 609                 pulse_eater |= BIT(23);
 610
 611         }
 612
 613         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 614             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 615                 pulse_eater &= ~BIT(16);
 616                 pulse_eater |= BIT(17);
 617         }
 618
 619         if ((gpu->identity.revision > 0x5420) &&
 620             (gpu->identity.features & chipFeatures_PIPE_3D))
 621         {
 622                 /* Performance fix: disable internal DFS */
 623                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 624                 pulse_eater |= BIT(18);
 625         }
 626
 627         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 628 }
 629
 630 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 631 {
 632         u16 prefetch;
 633
 634         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 635              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 636             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 637                 u32 mc_memory_debug;
 638
 639                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 640
 641                 if (gpu->identity.revision == 0x5007)
 642                         mc_memory_debug |= 0x0c;
 643                 else
 644                         mc_memory_debug |= 0x08;
 645
 646                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 647         }
 648
 649         /* enable module-level clock gating */
 650         etnaviv_gpu_enable_mlcg(gpu);
 651
 652         /*
 653          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 654          * This is necessary to prevent the iMX6 SoC locking up.
 655          */
 656         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 657                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 658                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 659
 660         /* GC2000 rev 5108 needs a special bus config */
 661         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 662                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 663                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 664                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 665                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 666                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 667                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 668         }
 669
 670         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 671                 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 672                 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 673                 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 674         }
 675
 676         /* setup the pulse eater */
 677         etnaviv_gpu_setup_pulse_eater(gpu);
 678
 679         /* setup the MMU */
 680         etnaviv_iommu_restore(gpu);
 681
 682         /* Start command processor */
 683         prefetch = etnaviv_buffer_init(gpu);
 684
 685         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 686         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
 687                              prefetch);
 688 }
 689
 690 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 691 {
 692         int ret, i;
 693
 694         ret = pm_runtime_get_sync(gpu->dev);
 695         if (ret < 0) {
 696                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 697                 return ret;
 698         }
 699
 700         etnaviv_hw_identify(gpu);
 701
 702         if (gpu->identity.model == 0) {
 703                 dev_err(gpu->dev, "Unknown GPU model\n");
 704                 ret = -ENXIO;
 705                 goto fail;
 706         }
 707
 708         /* Exclude VG cores with FE2.0 */
 709         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 710             gpu->identity.features & chipFeatures_FE20) {
 711                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 712                 ret = -ENXIO;
 713                 goto fail;
 714         }
 715
 716         /*
 717          * Set the GPU linear window to be at the end of the DMA window, where
 718          * the CMA area is likely to reside. This ensures that we are able to
 719          * map the command buffers while having the linear window overlap as
 720          * much RAM as possible, so we can optimize mappings for other buffers.
 721          *
 722          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 723          * to different views of the memory on the individual engines.
 724          */
 725         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 726             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 727                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 728                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 729                         gpu->memory_base = PHYS_OFFSET;
 730                 else
 731                         gpu->memory_base = dma_mask - SZ_2G + 1;
 732         } else if (PHYS_OFFSET >= SZ_2G) {
 733                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 734                 gpu->memory_base = PHYS_OFFSET;
 735                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 736         }
 737
 738         /*
 739          * On cores with security features supported, we claim control over the
 740          * security states.
 741          */
 742         if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 743             (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 744                 gpu->sec_mode = ETNA_SEC_KERNEL;
 745
 746         ret = etnaviv_hw_reset(gpu);
 747         if (ret) {
 748                 dev_err(gpu->dev, "GPU reset failed\n");
 749                 goto fail;
 750         }
 751
 752         gpu->mmu = etnaviv_iommu_new(gpu);
 753         if (IS_ERR(gpu->mmu)) {
 754                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 755                 ret = PTR_ERR(gpu->mmu);
 756                 goto fail;
 757         }
 758
 759         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 760         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 761                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 762                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 763                 goto fail;
 764         }
 765
 766         /* Create buffer: */
 767         ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
 768                                   PAGE_SIZE);
 769         if (ret) {
 770                 dev_err(gpu->dev, "could not create command buffer\n");
 771                 goto destroy_iommu;
 772         }
 773
 774         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 775             etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
 776                 ret = -EINVAL;
 777                 dev_err(gpu->dev,
 778                         "command buffer outside valid memory window\n");
 779                 goto free_buffer;
 780         }
 781
 782         /* Setup event management */
 783         spin_lock_init(&gpu->event_spinlock);
 784         init_completion(&gpu->event_free);
 785         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 786         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 787                 complete(&gpu->event_free);
 788
 789         /* Now program the hardware */
 790         mutex_lock(&gpu->lock);
 791         etnaviv_gpu_hw_init(gpu);
 792         gpu->exec_state = -1;
 793         mutex_unlock(&gpu->lock);
 794
 795         pm_runtime_mark_last_busy(gpu->dev);
 796         pm_runtime_put_autosuspend(gpu->dev);
 797
 798         return 0;
 799
 800 free_buffer:
 801         etnaviv_cmdbuf_free(&gpu->buffer);
 802         gpu->buffer.suballoc = NULL;
 803 destroy_iommu:
 804         etnaviv_iommu_destroy(gpu->mmu);
 805         gpu->mmu = NULL;
 806 fail:
 807         pm_runtime_mark_last_busy(gpu->dev);
 808         pm_runtime_put_autosuspend(gpu->dev);
 809
 810         return ret;
 811 }
 812
 813 #ifdef CONFIG_DEBUG_FS
 814 struct dma_debug {
 815         u32 address[2];
 816         u32 state[2];
 817 };
 818
 819 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 820 {
 821         u32 i;
 822
 823         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 824         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 825
 826         for (i = 0; i < 500; i++) {
 827                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 828                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 829
 830                 if (debug->address[0] != debug->address[1])
 831                         break;
 832
 833                 if (debug->state[0] != debug->state[1])
 834                         break;
 835         }
 836 }
 837
 838 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 839 {
 840         struct dma_debug debug;
 841         u32 dma_lo, dma_hi, axi, idle;
 842         int ret;
 843
 844         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 845
 846         ret = pm_runtime_get_sync(gpu->dev);
 847         if (ret < 0)
 848                 return ret;
 849
 850         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 851         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 852         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 853         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 854
 855         verify_dma(gpu, &debug);
 856
 857         seq_puts(m, "\tfeatures\n");
 858         seq_printf(m, "\t major_features: 0x%08x\n",
 859                    gpu->identity.features);
 860         seq_printf(m, "\t minor_features0: 0x%08x\n",
 861                    gpu->identity.minor_features0);
 862         seq_printf(m, "\t minor_features1: 0x%08x\n",
 863                    gpu->identity.minor_features1);
 864         seq_printf(m, "\t minor_features2: 0x%08x\n",
 865                    gpu->identity.minor_features2);
 866         seq_printf(m, "\t minor_features3: 0x%08x\n",
 867                    gpu->identity.minor_features3);
 868         seq_printf(m, "\t minor_features4: 0x%08x\n",
 869                    gpu->identity.minor_features4);
 870         seq_printf(m, "\t minor_features5: 0x%08x\n",
 871                    gpu->identity.minor_features5);
 872         seq_printf(m, "\t minor_features6: 0x%08x\n",
 873                    gpu->identity.minor_features6);
 874         seq_printf(m, "\t minor_features7: 0x%08x\n",
 875                    gpu->identity.minor_features7);
 876         seq_printf(m, "\t minor_features8: 0x%08x\n",
 877                    gpu->identity.minor_features8);
 878         seq_printf(m, "\t minor_features9: 0x%08x\n",
 879                    gpu->identity.minor_features9);
 880         seq_printf(m, "\t minor_features10: 0x%08x\n",
 881                    gpu->identity.minor_features10);
 882         seq_printf(m, "\t minor_features11: 0x%08x\n",
 883                    gpu->identity.minor_features11);
 884
 885         seq_puts(m, "\tspecs\n");
 886         seq_printf(m, "\t stream_count:  %d\n",
 887                         gpu->identity.stream_count);
 888         seq_printf(m, "\t register_max: %d\n",
 889                         gpu->identity.register_max);
 890         seq_printf(m, "\t thread_count: %d\n",
 891                         gpu->identity.thread_count);
 892         seq_printf(m, "\t vertex_cache_size: %d\n",
 893                         gpu->identity.vertex_cache_size);
 894         seq_printf(m, "\t shader_core_count: %d\n",
 895                         gpu->identity.shader_core_count);
 896         seq_printf(m, "\t pixel_pipes: %d\n",
 897                         gpu->identity.pixel_pipes);
 898         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 899                         gpu->identity.vertex_output_buffer_size);
 900         seq_printf(m, "\t buffer_size: %d\n",
 901                         gpu->identity.buffer_size);
 902         seq_printf(m, "\t instruction_count: %d\n",
 903                         gpu->identity.instruction_count);
 904         seq_printf(m, "\t num_constants: %d\n",
 905                         gpu->identity.num_constants);
 906         seq_printf(m, "\t varyings_count: %d\n",
 907                         gpu->identity.varyings_count);
 908
 909         seq_printf(m, "\taxi: 0x%08x\n", axi);
 910         seq_printf(m, "\tidle: 0x%08x\n", idle);
 911         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 912         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 913                 seq_puts(m, "\t FE is not idle\n");
 914         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 915                 seq_puts(m, "\t DE is not idle\n");
 916         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 917                 seq_puts(m, "\t PE is not idle\n");
 918         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 919                 seq_puts(m, "\t SH is not idle\n");
 920         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 921                 seq_puts(m, "\t PA is not idle\n");
 922         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 923                 seq_puts(m, "\t SE is not idle\n");
 924         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 925                 seq_puts(m, "\t RA is not idle\n");
 926         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 927                 seq_puts(m, "\t TX is not idle\n");
 928         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 929                 seq_puts(m, "\t VG is not idle\n");
 930         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 931                 seq_puts(m, "\t IM is not idle\n");
 932         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 933                 seq_puts(m, "\t FP is not idle\n");
 934         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 935                 seq_puts(m, "\t TS is not idle\n");
 936         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 937                 seq_puts(m, "\t AXI low power mode\n");
 938
 939         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 940                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 941                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 942                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 943
 944                 seq_puts(m, "\tMC\n");
 945                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 946                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 947                 seq_printf(m, "\t write: 0x%08x\n", write);
 948         }
 949
 950         seq_puts(m, "\tDMA ");
 951
 952         if (debug.address[0] == debug.address[1] &&
 953             debug.state[0] == debug.state[1]) {
 954                 seq_puts(m, "seems to be stuck\n");
 955         } else if (debug.address[0] == debug.address[1]) {
 956                 seq_puts(m, "address is constant\n");
 957         } else {
 958                 seq_puts(m, "is running\n");
 959         }
 960
 961         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 962         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 963         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 964         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 965         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 966                    dma_lo, dma_hi);
 967
 968         ret = 0;
 969
 970         pm_runtime_mark_last_busy(gpu->dev);
 971         pm_runtime_put_autosuspend(gpu->dev);
 972
 973         return ret;
 974 }
 975 #endif
 976
 977 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
 978 {
 979         unsigned int i = 0;
 980
 981         dev_err(gpu->dev, "recover hung GPU!\n");
 982
 983         if (pm_runtime_get_sync(gpu->dev) < 0)
 984                 return;
 985
 986         mutex_lock(&gpu->lock);
 987
 988         etnaviv_hw_reset(gpu);
 989
 990         /* complete all events, the GPU won't do it after the reset */
 991         spin_lock(&gpu->event_spinlock);
 992         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
 993                 complete(&gpu->event_free);
 994         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 995         spin_unlock(&gpu->event_spinlock);
 996
 997         etnaviv_gpu_hw_init(gpu);
 998         gpu->exec_state = -1;
 999
1000         mutex_unlock(&gpu->lock);
1001         pm_runtime_mark_last_busy(gpu->dev);
1002         pm_runtime_put_autosuspend(gpu->dev);
1003 }
1004
1005 /* fence object management */
1006 struct etnaviv_fence {
1007         struct etnaviv_gpu *gpu;
1008         struct dma_fence base;
1009 };
1010
1011 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1012 {
1013         return container_of(fence, struct etnaviv_fence, base);
1014 }
1015
1016 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1017 {
1018         return "etnaviv";
1019 }
1020
1021 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1022 {
1023         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1024
1025         return dev_name(f->gpu->dev);
1026 }
1027
1028 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1029 {
1030         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1031
1032         return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1033 }
1034
1035 static void etnaviv_fence_release(struct dma_fence *fence)
1036 {
1037         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1038
1039         kfree_rcu(f, base.rcu);
1040 }
1041
1042 static const struct dma_fence_ops etnaviv_fence_ops = {
1043         .get_driver_name = etnaviv_fence_get_driver_name,
1044         .get_timeline_name = etnaviv_fence_get_timeline_name,
1045         .signaled = etnaviv_fence_signaled,
1046         .release = etnaviv_fence_release,
1047 };
1048
1049 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1050 {
1051         struct etnaviv_fence *f;
1052
1053         /*
1054          * GPU lock must already be held, otherwise fence completion order might
1055          * not match the seqno order assigned here.
1056          */
1057         lockdep_assert_held(&gpu->lock);
1058
1059         f = kzalloc(sizeof(*f), GFP_KERNEL);
1060         if (!f)
1061                 return NULL;
1062
1063         f->gpu = gpu;
1064
1065         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1066                        gpu->fence_context, ++gpu->next_fence);
1067
1068         return &f->base;
1069 }
1070
1071 /* returns true if fence a comes after fence b */
1072 static inline bool fence_after(u32 a, u32 b)
1073 {
1074         return (s32)(a - b) > 0;
1075 }
1076
1077 /*
1078  * event management:
1079  */
1080
1081 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1082         unsigned int *events)
1083 {
1084         unsigned long timeout = msecs_to_jiffies(10 * 10000);
1085         unsigned i, acquired = 0;
1086
1087         for (i = 0; i < nr_events; i++) {
1088                 unsigned long ret;
1089
1090                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1091
1092                 if (!ret) {
1093                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1094                         goto out;
1095                 }
1096
1097                 acquired++;
1098                 timeout = ret;
1099         }
1100
1101         spin_lock(&gpu->event_spinlock);
1102
1103         for (i = 0; i < nr_events; i++) {
1104                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1105
1106                 events[i] = event;
1107                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1108                 set_bit(event, gpu->event_bitmap);
1109         }
1110
1111         spin_unlock(&gpu->event_spinlock);
1112
1113         return 0;
1114
1115 out:
1116         for (i = 0; i < acquired; i++)
1117                 complete(&gpu->event_free);
1118
1119         return -EBUSY;
1120 }
1121
1122 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1123 {
1124         if (!test_bit(event, gpu->event_bitmap)) {
1125                 dev_warn(gpu->dev, "event %u is already marked as free",
1126                          event);
1127         } else {
1128                 clear_bit(event, gpu->event_bitmap);
1129                 complete(&gpu->event_free);
1130         }
1131 }
1132
1133 /*
1134  * Cmdstream submission/retirement:
1135  */
1136 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1137         u32 id, struct timespec *timeout)
1138 {
1139         struct dma_fence *fence;
1140         int ret;
1141
1142         /*
1143          * Look up the fence and take a reference. We might still find a fence
1144          * whose refcount has already dropped to zero. dma_fence_get_rcu
1145          * pretends we didn't find a fence in that case.
1146          */
1147         rcu_read_lock();
1148         fence = idr_find(&gpu->fence_idr, id);
1149         if (fence)
1150                 fence = dma_fence_get_rcu(fence);
1151         rcu_read_unlock();
1152
1153         if (!fence)
1154                 return 0;
1155
1156         if (!timeout) {
1157                 /* No timeout was requested: just test for completion */
1158                 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1159         } else {
1160                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1161
1162                 ret = dma_fence_wait_timeout(fence, true, remaining);
1163                 if (ret == 0)
1164                         ret = -ETIMEDOUT;
1165                 else if (ret != -ERESTARTSYS)
1166                         ret = 0;
1167
1168         }
1169
1170         dma_fence_put(fence);
1171         return ret;
1172 }
1173
1174 /*
1175  * Wait for an object to become inactive.  This, on it's own, is not race
1176  * free: the object is moved by the scheduler off the active list, and
1177  * then the iova is put.  Moreover, the object could be re-submitted just
1178  * after we notice that it's become inactive.
1179  *
1180  * Although the retirement happens under the gpu lock, we don't want to hold
1181  * that lock in this function while waiting.
1182  */
1183 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1184         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1185 {
1186         unsigned long remaining;
1187         long ret;
1188
1189         if (!timeout)
1190                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1191
1192         remaining = etnaviv_timeout_to_jiffies(timeout);
1193
1194         ret = wait_event_interruptible_timeout(gpu->fence_event,
1195                                                !is_active(etnaviv_obj),
1196                                                remaining);
1197         if (ret > 0)
1198                 return 0;
1199         else if (ret == -ERESTARTSYS)
1200                 return -ERESTARTSYS;
1201         else
1202                 return -ETIMEDOUT;
1203 }
1204
1205 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1206         struct etnaviv_event *event, unsigned int flags)
1207 {
1208         const struct etnaviv_gem_submit *submit = event->submit;
1209         unsigned int i;
1210
1211         for (i = 0; i < submit->nr_pmrs; i++) {
1212                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1213
1214                 if (pmr->flags == flags)
1215                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1216         }
1217 }
1218
1219 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1220         struct etnaviv_event *event)
1221 {
1222         u32 val;
1223
1224         /* disable clock gating */
1225         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1226         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1227         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1228
1229         /* enable debug register */
1230         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1231         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1232         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1233
1234         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1235 }
1236
1237 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1238         struct etnaviv_event *event)
1239 {
1240         const struct etnaviv_gem_submit *submit = event->submit;
1241         unsigned int i;
1242         u32 val;
1243
1244         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1245
1246         for (i = 0; i < submit->nr_pmrs; i++) {
1247                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1248
1249                 *pmr->bo_vma = pmr->sequence;
1250         }
1251
1252         /* disable debug register */
1253         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1254         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1255         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1256
1257         /* enable clock gating */
1258         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1259         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1260         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1261 }
1262
1263
1264 /* add bo's to gpu's ring, and kick gpu: */
1265 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1266 {
1267         struct etnaviv_gpu *gpu = submit->gpu;
1268         struct dma_fence *gpu_fence;
1269         unsigned int i, nr_events = 1, event[3];
1270         int ret;
1271
1272         if (!submit->runtime_resumed) {
1273                 ret = pm_runtime_get_sync(gpu->dev);
1274                 if (ret < 0)
1275                         return NULL;
1276                 submit->runtime_resumed = true;
1277         }
1278
1279         /*
1280          * if there are performance monitor requests we need to have
1281          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1282          *   requests.
1283          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1284          *   and update the sequence number for userspace.
1285          */
1286         if (submit->nr_pmrs)
1287                 nr_events = 3;
1288
1289         ret = event_alloc(gpu, nr_events, event);
1290         if (ret) {
1291                 DRM_ERROR("no free events\n");
1292                 return NULL;
1293         }
1294
1295         mutex_lock(&gpu->lock);
1296
1297         gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1298         if (!gpu_fence) {
1299                 for (i = 0; i < nr_events; i++)
1300                         event_free(gpu, event[i]);
1301
1302                 goto out_unlock;
1303         }
1304
1305         if (submit->nr_pmrs) {
1306                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1307                 kref_get(&submit->refcount);
1308                 gpu->event[event[1]].submit = submit;
1309                 etnaviv_sync_point_queue(gpu, event[1]);
1310         }
1311
1312         gpu->event[event[0]].fence = gpu_fence;
1313         submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1314         etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1315                              &submit->cmdbuf);
1316
1317         if (submit->nr_pmrs) {
1318                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1319                 kref_get(&submit->refcount);
1320                 gpu->event[event[2]].submit = submit;
1321                 etnaviv_sync_point_queue(gpu, event[2]);
1322         }
1323
1324 out_unlock:
1325         mutex_unlock(&gpu->lock);
1326
1327         return gpu_fence;
1328 }
1329
1330 static void sync_point_worker(struct work_struct *work)
1331 {
1332         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1333                                                sync_point_work);
1334         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1335         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1336
1337         event->sync_point(gpu, event);
1338         etnaviv_submit_put(event->submit);
1339         event_free(gpu, gpu->sync_point_event);
1340
1341         /* restart FE last to avoid GPU and IRQ racing against this worker */
1342         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1343 }
1344
1345 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1346 {
1347         u32 status_reg, status;
1348         int i;
1349
1350         if (gpu->sec_mode == ETNA_SEC_NONE)
1351                 status_reg = VIVS_MMUv2_STATUS;
1352         else
1353                 status_reg = VIVS_MMUv2_SEC_STATUS;
1354
1355         status = gpu_read(gpu, status_reg);
1356         dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1357
1358         for (i = 0; i < 4; i++) {
1359                 u32 address_reg;
1360
1361                 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1362                         continue;
1363
1364                 if (gpu->sec_mode == ETNA_SEC_NONE)
1365                         address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1366                 else
1367                         address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1368
1369                 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1370                                     gpu_read(gpu, address_reg));
1371         }
1372 }
1373
1374 static irqreturn_t irq_handler(int irq, void *data)
1375 {
1376         struct etnaviv_gpu *gpu = data;
1377         irqreturn_t ret = IRQ_NONE;
1378
1379         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1380
1381         if (intr != 0) {
1382                 int event;
1383
1384                 pm_runtime_mark_last_busy(gpu->dev);
1385
1386                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1387
1388                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1389                         dev_err(gpu->dev, "AXI bus error\n");
1390                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1391                 }
1392
1393                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1394                         dump_mmu_fault(gpu);
1395                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1396                 }
1397
1398                 while ((event = ffs(intr)) != 0) {
1399                         struct dma_fence *fence;
1400
1401                         event -= 1;
1402
1403                         intr &= ~(1 << event);
1404
1405                         dev_dbg(gpu->dev, "event %u\n", event);
1406
1407                         if (gpu->event[event].sync_point) {
1408                                 gpu->sync_point_event = event;
1409                                 queue_work(gpu->wq, &gpu->sync_point_work);
1410                         }
1411
1412                         fence = gpu->event[event].fence;
1413                         if (!fence)
1414                                 continue;
1415
1416                         gpu->event[event].fence = NULL;
1417
1418                         /*
1419                          * Events can be processed out of order.  Eg,
1420                          * - allocate and queue event 0
1421                          * - allocate event 1
1422                          * - event 0 completes, we process it
1423                          * - allocate and queue event 0
1424                          * - event 1 and event 0 complete
1425                          * we can end up processing event 0 first, then 1.
1426                          */
1427                         if (fence_after(fence->seqno, gpu->completed_fence))
1428                                 gpu->completed_fence = fence->seqno;
1429                         dma_fence_signal(fence);
1430
1431                         event_free(gpu, event);
1432                 }
1433
1434                 ret = IRQ_HANDLED;
1435         }
1436
1437         return ret;
1438 }
1439
1440 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1441 {
1442         int ret;
1443
1444         if (gpu->clk_reg) {
1445                 ret = clk_prepare_enable(gpu->clk_reg);
1446                 if (ret)
1447                         return ret;
1448         }
1449
1450         if (gpu->clk_bus) {
1451                 ret = clk_prepare_enable(gpu->clk_bus);
1452                 if (ret)
1453                         return ret;
1454         }
1455
1456         if (gpu->clk_core) {
1457                 ret = clk_prepare_enable(gpu->clk_core);
1458                 if (ret)
1459                         goto disable_clk_bus;
1460         }
1461
1462         if (gpu->clk_shader) {
1463                 ret = clk_prepare_enable(gpu->clk_shader);
1464                 if (ret)
1465                         goto disable_clk_core;
1466         }
1467
1468         return 0;
1469
1470 disable_clk_core:
1471         if (gpu->clk_core)
1472                 clk_disable_unprepare(gpu->clk_core);
1473 disable_clk_bus:
1474         if (gpu->clk_bus)
1475                 clk_disable_unprepare(gpu->clk_bus);
1476
1477         return ret;
1478 }
1479
1480 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1481 {
1482         if (gpu->clk_shader)
1483                 clk_disable_unprepare(gpu->clk_shader);
1484         if (gpu->clk_core)
1485                 clk_disable_unprepare(gpu->clk_core);
1486         if (gpu->clk_bus)
1487                 clk_disable_unprepare(gpu->clk_bus);
1488         if (gpu->clk_reg)
1489                 clk_disable_unprepare(gpu->clk_reg);
1490
1491         return 0;
1492 }
1493
1494 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1495 {
1496         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1497
1498         do {
1499                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1500
1501                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1502                         return 0;
1503
1504                 if (time_is_before_jiffies(timeout)) {
1505                         dev_warn(gpu->dev,
1506                                  "timed out waiting for idle: idle=0x%x\n",
1507                                  idle);
1508                         return -ETIMEDOUT;
1509                 }
1510
1511                 udelay(5);
1512         } while (1);
1513 }
1514
1515 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1516 {
1517         if (gpu->buffer.suballoc) {
1518                 /* Replace the last WAIT with END */
1519                 mutex_lock(&gpu->lock);
1520                 etnaviv_buffer_end(gpu);
1521                 mutex_unlock(&gpu->lock);
1522
1523                 /*
1524                  * We know that only the FE is busy here, this should
1525                  * happen quickly (as the WAIT is only 200 cycles).  If
1526                  * we fail, just warn and continue.
1527                  */
1528                 etnaviv_gpu_wait_idle(gpu, 100);
1529         }
1530
1531         return etnaviv_gpu_clk_disable(gpu);
1532 }
1533
1534 #ifdef CONFIG_PM
1535 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1536 {
1537         int ret;
1538
1539         ret = mutex_lock_killable(&gpu->lock);
1540         if (ret)
1541                 return ret;
1542
1543         etnaviv_gpu_update_clock(gpu);
1544         etnaviv_gpu_hw_init(gpu);
1545
1546         gpu->exec_state = -1;
1547
1548         mutex_unlock(&gpu->lock);
1549
1550         return 0;
1551 }
1552 #endif
1553
1554 static int
1555 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1556                                   unsigned long *state)
1557 {
1558         *state = 6;
1559
1560         return 0;
1561 }
1562
1563 static int
1564 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1565                                   unsigned long *state)
1566 {
1567         struct etnaviv_gpu *gpu = cdev->devdata;
1568
1569         *state = gpu->freq_scale;
1570
1571         return 0;
1572 }
1573
1574 static int
1575 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1576                                   unsigned long state)
1577 {
1578         struct etnaviv_gpu *gpu = cdev->devdata;
1579
1580         mutex_lock(&gpu->lock);
1581         gpu->freq_scale = state;
1582         if (!pm_runtime_suspended(gpu->dev))
1583                 etnaviv_gpu_update_clock(gpu);
1584         mutex_unlock(&gpu->lock);
1585
1586         return 0;
1587 }
1588
1589 static struct thermal_cooling_device_ops cooling_ops = {
1590         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1591         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1592         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1593 };
1594
1595 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1596         void *data)
1597 {
1598         struct drm_device *drm = data;
1599         struct etnaviv_drm_private *priv = drm->dev_private;
1600         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1601         int ret;
1602
1603         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1604                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1605                                 (char *)dev_name(dev), gpu, &cooling_ops);
1606                 if (IS_ERR(gpu->cooling))
1607                         return PTR_ERR(gpu->cooling);
1608         }
1609
1610         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1611         if (!gpu->wq) {
1612                 ret = -ENOMEM;
1613                 goto out_thermal;
1614         }
1615
1616         ret = etnaviv_sched_init(gpu);
1617         if (ret)
1618                 goto out_workqueue;
1619
1620 #ifdef CONFIG_PM
1621         ret = pm_runtime_get_sync(gpu->dev);
1622 #else
1623         ret = etnaviv_gpu_clk_enable(gpu);
1624 #endif
1625         if (ret < 0)
1626                 goto out_sched;
1627
1628
1629         gpu->drm = drm;
1630         gpu->fence_context = dma_fence_context_alloc(1);
1631         idr_init(&gpu->fence_idr);
1632         spin_lock_init(&gpu->fence_spinlock);
1633
1634         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1635         init_waitqueue_head(&gpu->fence_event);
1636
1637         priv->gpu[priv->num_gpus++] = gpu;
1638
1639         pm_runtime_mark_last_busy(gpu->dev);
1640         pm_runtime_put_autosuspend(gpu->dev);
1641
1642         return 0;
1643
1644 out_sched:
1645         etnaviv_sched_fini(gpu);
1646
1647 out_workqueue:
1648         destroy_workqueue(gpu->wq);
1649
1650 out_thermal:
1651         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1652                 thermal_cooling_device_unregister(gpu->cooling);
1653
1654         return ret;
1655 }
1656
1657 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1658         void *data)
1659 {
1660         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1661
1662         DBG("%s", dev_name(gpu->dev));
1663
1664         flush_workqueue(gpu->wq);
1665         destroy_workqueue(gpu->wq);
1666
1667         etnaviv_sched_fini(gpu);
1668
1669 #ifdef CONFIG_PM
1670         pm_runtime_get_sync(gpu->dev);
1671         pm_runtime_put_sync_suspend(gpu->dev);
1672 #else
1673         etnaviv_gpu_hw_suspend(gpu);
1674 #endif
1675
1676         if (gpu->buffer.suballoc)
1677                 etnaviv_cmdbuf_free(&gpu->buffer);
1678
1679         if (gpu->cmdbuf_suballoc) {
1680                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1681                 gpu->cmdbuf_suballoc = NULL;
1682         }
1683
1684         if (gpu->mmu) {
1685                 etnaviv_iommu_destroy(gpu->mmu);
1686                 gpu->mmu = NULL;
1687         }
1688
1689         gpu->drm = NULL;
1690         idr_destroy(&gpu->fence_idr);
1691
1692         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1693                 thermal_cooling_device_unregister(gpu->cooling);
1694         gpu->cooling = NULL;
1695 }
1696
1697 static const struct component_ops gpu_ops = {
1698         .bind = etnaviv_gpu_bind,
1699         .unbind = etnaviv_gpu_unbind,
1700 };
1701
1702 static const struct of_device_id etnaviv_gpu_match[] = {
1703         {
1704                 .compatible = "vivante,gc"
1705         },
1706         { /* sentinel */ }
1707 };
1708 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1709
1710 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1711 {
1712         struct device *dev = &pdev->dev;
1713         struct etnaviv_gpu *gpu;
1714         struct resource *res;
1715         int err;
1716
1717         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1718         if (!gpu)
1719                 return -ENOMEM;
1720
1721         gpu->dev = &pdev->dev;
1722         mutex_init(&gpu->lock);
1723         mutex_init(&gpu->fence_lock);
1724
1725         /* Map registers: */
1726         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727         gpu->mmio = devm_ioremap_resource(&pdev->dev, res);
1728         if (IS_ERR(gpu->mmio))
1729                 return PTR_ERR(gpu->mmio);
1730
1731         /* Get Interrupt: */
1732         gpu->irq = platform_get_irq(pdev, 0);
1733         if (gpu->irq < 0) {
1734                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1735                 return gpu->irq;
1736         }
1737
1738         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1739                                dev_name(gpu->dev), gpu);
1740         if (err) {
1741                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1742                 return err;
1743         }
1744
1745         /* Get Clocks: */
1746         gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1747         DBG("clk_reg: %p", gpu->clk_reg);
1748         if (IS_ERR(gpu->clk_reg))
1749                 gpu->clk_reg = NULL;
1750
1751         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1752         DBG("clk_bus: %p", gpu->clk_bus);
1753         if (IS_ERR(gpu->clk_bus))
1754                 gpu->clk_bus = NULL;
1755
1756         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1757         DBG("clk_core: %p", gpu->clk_core);
1758         if (IS_ERR(gpu->clk_core))
1759                 gpu->clk_core = NULL;
1760         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1761
1762         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1763         DBG("clk_shader: %p", gpu->clk_shader);
1764         if (IS_ERR(gpu->clk_shader))
1765                 gpu->clk_shader = NULL;
1766         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1767
1768         /* TODO: figure out max mapped size */
1769         dev_set_drvdata(dev, gpu);
1770
1771         /*
1772          * We treat the device as initially suspended.  The runtime PM
1773          * autosuspend delay is rather arbitary: no measurements have
1774          * yet been performed to determine an appropriate value.
1775          */
1776         pm_runtime_use_autosuspend(gpu->dev);
1777         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1778         pm_runtime_enable(gpu->dev);
1779
1780         err = component_add(&pdev->dev, &gpu_ops);
1781         if (err < 0) {
1782                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1783                 return err;
1784         }
1785
1786         return 0;
1787 }
1788
1789 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1790 {
1791         component_del(&pdev->dev, &gpu_ops);
1792         pm_runtime_disable(&pdev->dev);
1793         return 0;
1794 }
1795
1796 #ifdef CONFIG_PM
1797 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1798 {
1799         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1800         u32 idle, mask;
1801
1802         /* If there are any jobs in the HW queue, we're not idle */
1803         if (atomic_read(&gpu->sched.hw_rq_count))
1804                 return -EBUSY;
1805
1806         /* Check whether the hardware (except FE) is idle */
1807         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1808         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1809         if (idle != mask)
1810                 return -EBUSY;
1811
1812         return etnaviv_gpu_hw_suspend(gpu);
1813 }
1814
1815 static int etnaviv_gpu_rpm_resume(struct device *dev)
1816 {
1817         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1818         int ret;
1819
1820         ret = etnaviv_gpu_clk_enable(gpu);
1821         if (ret)
1822                 return ret;
1823
1824         /* Re-initialise the basic hardware state */
1825         if (gpu->drm && gpu->buffer.suballoc) {
1826                 ret = etnaviv_gpu_hw_resume(gpu);
1827                 if (ret) {
1828                         etnaviv_gpu_clk_disable(gpu);
1829                         return ret;
1830                 }
1831         }
1832
1833         return 0;
1834 }
1835 #endif
1836
1837 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1838         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1839                            NULL)
1840 };
1841
1842 struct platform_driver etnaviv_gpu_driver = {
1843         .driver = {
1844                 .name = "etnaviv-gpu",
1845                 .owner = THIS_MODULE,
1846                 .pm = &etnaviv_gpu_pm_ops,
1847                 .of_match_table = etnaviv_gpu_match,
1848         },
1849         .probe = etnaviv_gpu_platform_probe,
1850         .remove = etnaviv_gpu_platform_remove,
1851         .id_table = gpu_ids,
1852 };