2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
119 /* Belinea 10 15 55 */
120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
123 /* Envision Peripherals, Inc. EN-7100e */
124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
125 /* Envision EN2028 */
126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
128 /* Funai Electronics PM36B */
129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
130 EDID_QUIRK_DETAILED_IN_CM },
132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
135 /* LG Philips LCD LP154W01-A5 */
136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
139 /* Philips 107p5 CRT */
140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
145 /* Samsung SyncMaster 205BW. Note: irony */
146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
147 /* Samsung SyncMaster 22[5-6]BW */
148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
154 /* ViewSonic VA2026w */
155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
157 /* Medion MD 30217 PG */
158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
166 /* HTC Vive VR Headset */
167 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
171 * Autogenerated from the DMT spec.
172 * This table is copied from xfree86/modes/xf86EdidModes.c.
174 static const struct drm_display_mode drm_dmt_modes[] = {
175 /* 0x01 - 640x350@85Hz */
176 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
177 736, 832, 0, 350, 382, 385, 445, 0,
178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
179 /* 0x02 - 640x400@85Hz */
180 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
181 736, 832, 0, 400, 401, 404, 445, 0,
182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
183 /* 0x03 - 720x400@85Hz */
184 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
185 828, 936, 0, 400, 401, 404, 446, 0,
186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
187 /* 0x04 - 640x480@60Hz */
188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
189 752, 800, 0, 480, 490, 492, 525, 0,
190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
191 /* 0x05 - 640x480@72Hz */
192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
193 704, 832, 0, 480, 489, 492, 520, 0,
194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
195 /* 0x06 - 640x480@75Hz */
196 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
197 720, 840, 0, 480, 481, 484, 500, 0,
198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
199 /* 0x07 - 640x480@85Hz */
200 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
201 752, 832, 0, 480, 481, 484, 509, 0,
202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
203 /* 0x08 - 800x600@56Hz */
204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
205 896, 1024, 0, 600, 601, 603, 625, 0,
206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
207 /* 0x09 - 800x600@60Hz */
208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
209 968, 1056, 0, 600, 601, 605, 628, 0,
210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
211 /* 0x0a - 800x600@72Hz */
212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
213 976, 1040, 0, 600, 637, 643, 666, 0,
214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
215 /* 0x0b - 800x600@75Hz */
216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
217 896, 1056, 0, 600, 601, 604, 625, 0,
218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
219 /* 0x0c - 800x600@85Hz */
220 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
221 896, 1048, 0, 600, 601, 604, 631, 0,
222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
223 /* 0x0d - 800x600@120Hz RB */
224 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
225 880, 960, 0, 600, 603, 607, 636, 0,
226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
227 /* 0x0e - 848x480@60Hz */
228 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
229 976, 1088, 0, 480, 486, 494, 517, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
231 /* 0x0f - 1024x768@43Hz, interlace */
232 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
233 1208, 1264, 0, 768, 768, 776, 817, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
235 DRM_MODE_FLAG_INTERLACE) },
236 /* 0x10 - 1024x768@60Hz */
237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
238 1184, 1344, 0, 768, 771, 777, 806, 0,
239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 0x11 - 1024x768@70Hz */
241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
242 1184, 1328, 0, 768, 771, 777, 806, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x12 - 1024x768@75Hz */
245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
246 1136, 1312, 0, 768, 769, 772, 800, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
248 /* 0x13 - 1024x768@85Hz */
249 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
250 1168, 1376, 0, 768, 769, 772, 808, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
252 /* 0x14 - 1024x768@120Hz RB */
253 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
254 1104, 1184, 0, 768, 771, 775, 813, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 0x15 - 1152x864@75Hz */
257 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
258 1344, 1600, 0, 864, 865, 868, 900, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 0x55 - 1280x720@60Hz */
261 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
262 1430, 1650, 0, 720, 725, 730, 750, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x16 - 1280x768@60Hz RB */
265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
266 1360, 1440, 0, 768, 771, 778, 790, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 0x17 - 1280x768@60Hz */
269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
270 1472, 1664, 0, 768, 771, 778, 798, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 0x18 - 1280x768@75Hz */
273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
274 1488, 1696, 0, 768, 771, 778, 805, 0,
275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 0x19 - 1280x768@85Hz */
277 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
278 1496, 1712, 0, 768, 771, 778, 809, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x1a - 1280x768@120Hz RB */
281 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
282 1360, 1440, 0, 768, 771, 778, 813, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x1b - 1280x800@60Hz RB */
285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
286 1360, 1440, 0, 800, 803, 809, 823, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
288 /* 0x1c - 1280x800@60Hz */
289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
290 1480, 1680, 0, 800, 803, 809, 831, 0,
291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x1d - 1280x800@75Hz */
293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
294 1488, 1696, 0, 800, 803, 809, 838, 0,
295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x1e - 1280x800@85Hz */
297 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
298 1496, 1712, 0, 800, 803, 809, 843, 0,
299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x1f - 1280x800@120Hz RB */
301 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
302 1360, 1440, 0, 800, 803, 809, 847, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
304 /* 0x20 - 1280x960@60Hz */
305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
306 1488, 1800, 0, 960, 961, 964, 1000, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
308 /* 0x21 - 1280x960@85Hz */
309 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
310 1504, 1728, 0, 960, 961, 964, 1011, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x22 - 1280x960@120Hz RB */
313 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
314 1360, 1440, 0, 960, 963, 967, 1017, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
316 /* 0x23 - 1280x1024@60Hz */
317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
318 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 0x24 - 1280x1024@75Hz */
321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
322 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x25 - 1280x1024@85Hz */
325 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
326 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
328 /* 0x26 - 1280x1024@120Hz RB */
329 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
330 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
332 /* 0x27 - 1360x768@60Hz */
333 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
334 1536, 1792, 0, 768, 771, 777, 795, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x28 - 1360x768@120Hz RB */
337 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
338 1440, 1520, 0, 768, 771, 776, 813, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
340 /* 0x51 - 1366x768@60Hz */
341 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
342 1579, 1792, 0, 768, 771, 774, 798, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x56 - 1366x768@60Hz */
345 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
346 1436, 1500, 0, 768, 769, 772, 800, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x29 - 1400x1050@60Hz RB */
349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
350 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
352 /* 0x2a - 1400x1050@60Hz */
353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
354 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
356 /* 0x2b - 1400x1050@75Hz */
357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
358 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
360 /* 0x2c - 1400x1050@85Hz */
361 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
362 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x2d - 1400x1050@120Hz RB */
365 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
366 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368 /* 0x2e - 1440x900@60Hz RB */
369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
370 1520, 1600, 0, 900, 903, 909, 926, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
372 /* 0x2f - 1440x900@60Hz */
373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
374 1672, 1904, 0, 900, 903, 909, 934, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
376 /* 0x30 - 1440x900@75Hz */
377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
378 1688, 1936, 0, 900, 903, 909, 942, 0,
379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 0x31 - 1440x900@85Hz */
381 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
382 1696, 1952, 0, 900, 903, 909, 948, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x32 - 1440x900@120Hz RB */
385 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
386 1520, 1600, 0, 900, 903, 909, 953, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 0x53 - 1600x900@60Hz */
389 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
390 1704, 1800, 0, 900, 901, 904, 1000, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x33 - 1600x1200@60Hz */
393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 0x34 - 1600x1200@65Hz */
397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400 /* 0x35 - 1600x1200@70Hz */
401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
404 /* 0x36 - 1600x1200@75Hz */
405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
406 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 0x37 - 1600x1200@85Hz */
409 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
410 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
412 /* 0x38 - 1600x1200@120Hz RB */
413 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
414 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416 /* 0x39 - 1680x1050@60Hz RB */
417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
418 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
420 /* 0x3a - 1680x1050@60Hz */
421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
422 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
424 /* 0x3b - 1680x1050@75Hz */
425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
426 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x3c - 1680x1050@85Hz */
429 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
430 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x3d - 1680x1050@120Hz RB */
433 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
434 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
436 /* 0x3e - 1792x1344@60Hz */
437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
438 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 0x3f - 1792x1344@75Hz */
441 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
442 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
444 /* 0x40 - 1792x1344@120Hz RB */
445 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
446 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 0x41 - 1856x1392@60Hz */
449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
450 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 0x42 - 1856x1392@75Hz */
453 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
454 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 0x43 - 1856x1392@120Hz RB */
457 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
458 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
460 /* 0x52 - 1920x1080@60Hz */
461 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
462 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
464 /* 0x44 - 1920x1200@60Hz RB */
465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
466 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
468 /* 0x45 - 1920x1200@60Hz */
469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
470 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 0x46 - 1920x1200@75Hz */
473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
474 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 0x47 - 1920x1200@85Hz */
477 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
478 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x48 - 1920x1200@120Hz RB */
481 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
482 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
484 /* 0x49 - 1920x1440@60Hz */
485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
486 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
488 /* 0x4a - 1920x1440@75Hz */
489 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
490 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
492 /* 0x4b - 1920x1440@120Hz RB */
493 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
494 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
496 /* 0x54 - 2048x1152@60Hz */
497 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
498 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x4c - 2560x1600@60Hz RB */
501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
502 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
504 /* 0x4d - 2560x1600@60Hz */
505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
506 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
508 /* 0x4e - 2560x1600@75Hz */
509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
510 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 0x4f - 2560x1600@85Hz */
513 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
514 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516 /* 0x50 - 2560x1600@120Hz RB */
517 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
518 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
520 /* 0x57 - 4096x2160@60Hz RB */
521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
522 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 0x58 - 4096x2160@59.94Hz RB */
525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
526 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 * These more or less come from the DMT spec. The 720x400 modes are
532 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
533 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
534 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
537 * The DMT modes have been fact-checked; the rest are mild guesses.
539 static const struct drm_display_mode edid_est_modes[] = {
540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
541 968, 1056, 0, 600, 601, 605, 628, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
543 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
544 896, 1024, 0, 600, 601, 603, 625, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
547 720, 840, 0, 480, 481, 484, 500, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
550 704, 832, 0, 480, 489, 492, 520, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
553 768, 864, 0, 480, 483, 486, 525, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
555 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
556 752, 800, 0, 480, 490, 492, 525, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
559 846, 900, 0, 400, 421, 423, 449, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
561 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
562 846, 900, 0, 400, 412, 414, 449, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
564 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
565 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
568 1136, 1312, 0, 768, 769, 772, 800, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
571 1184, 1328, 0, 768, 771, 777, 806, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
573 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
574 1184, 1344, 0, 768, 771, 777, 806, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
576 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
577 1208, 1264, 0, 768, 768, 776, 817, 0,
578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
579 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
580 928, 1152, 0, 624, 625, 628, 667, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
583 896, 1056, 0, 600, 601, 604, 625, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
585 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
586 976, 1040, 0, 600, 637, 643, 666, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
588 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
589 1344, 1600, 0, 864, 865, 868, 900, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
600 static const struct minimode est3_modes[] = {
608 { 1024, 768, 85, 0 },
609 { 1152, 864, 75, 0 },
611 { 1280, 768, 60, 1 },
612 { 1280, 768, 60, 0 },
613 { 1280, 768, 75, 0 },
614 { 1280, 768, 85, 0 },
615 { 1280, 960, 60, 0 },
616 { 1280, 960, 85, 0 },
617 { 1280, 1024, 60, 0 },
618 { 1280, 1024, 85, 0 },
620 { 1360, 768, 60, 0 },
621 { 1440, 900, 60, 1 },
622 { 1440, 900, 60, 0 },
623 { 1440, 900, 75, 0 },
624 { 1440, 900, 85, 0 },
625 { 1400, 1050, 60, 1 },
626 { 1400, 1050, 60, 0 },
627 { 1400, 1050, 75, 0 },
629 { 1400, 1050, 85, 0 },
630 { 1680, 1050, 60, 1 },
631 { 1680, 1050, 60, 0 },
632 { 1680, 1050, 75, 0 },
633 { 1680, 1050, 85, 0 },
634 { 1600, 1200, 60, 0 },
635 { 1600, 1200, 65, 0 },
636 { 1600, 1200, 70, 0 },
638 { 1600, 1200, 75, 0 },
639 { 1600, 1200, 85, 0 },
640 { 1792, 1344, 60, 0 },
641 { 1792, 1344, 75, 0 },
642 { 1856, 1392, 60, 0 },
643 { 1856, 1392, 75, 0 },
644 { 1920, 1200, 60, 1 },
645 { 1920, 1200, 60, 0 },
647 { 1920, 1200, 75, 0 },
648 { 1920, 1200, 85, 0 },
649 { 1920, 1440, 60, 0 },
650 { 1920, 1440, 75, 0 },
653 static const struct minimode extra_modes[] = {
654 { 1024, 576, 60, 0 },
655 { 1366, 768, 60, 0 },
656 { 1600, 900, 60, 0 },
657 { 1680, 945, 60, 0 },
658 { 1920, 1080, 60, 0 },
659 { 2048, 1152, 60, 0 },
660 { 2048, 1536, 60, 0 },
664 * Probably taken from CEA-861 spec.
665 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
667 * Index using the VIC.
669 static const struct drm_display_mode edid_cea_modes[] = {
670 /* 0 - dummy, VICs start at 1 */
672 /* 1 - 640x480@60Hz */
673 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
674 752, 800, 0, 480, 490, 492, 525, 0,
675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
677 /* 2 - 720x480@60Hz */
678 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
679 798, 858, 0, 480, 489, 495, 525, 0,
680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
682 /* 3 - 720x480@60Hz */
683 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
684 798, 858, 0, 480, 489, 495, 525, 0,
685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
687 /* 4 - 1280x720@60Hz */
688 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
689 1430, 1650, 0, 720, 725, 730, 750, 0,
690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
692 /* 5 - 1920x1080i@60Hz */
693 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
694 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
696 DRM_MODE_FLAG_INTERLACE),
697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
698 /* 6 - 720(1440)x480i@60Hz */
699 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
700 801, 858, 0, 480, 488, 494, 525, 0,
701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
702 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
704 /* 7 - 720(1440)x480i@60Hz */
705 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
706 801, 858, 0, 480, 488, 494, 525, 0,
707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
708 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
710 /* 8 - 720(1440)x240@60Hz */
711 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
712 801, 858, 0, 240, 244, 247, 262, 0,
713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
714 DRM_MODE_FLAG_DBLCLK),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
716 /* 9 - 720(1440)x240@60Hz */
717 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
718 801, 858, 0, 240, 244, 247, 262, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
720 DRM_MODE_FLAG_DBLCLK),
721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
722 /* 10 - 2880x480i@60Hz */
723 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 480, 488, 494, 525, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
726 DRM_MODE_FLAG_INTERLACE),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728 /* 11 - 2880x480i@60Hz */
729 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
730 3204, 3432, 0, 480, 488, 494, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
732 DRM_MODE_FLAG_INTERLACE),
733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 12 - 2880x240@60Hz */
735 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
736 3204, 3432, 0, 240, 244, 247, 262, 0,
737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
739 /* 13 - 2880x240@60Hz */
740 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
741 3204, 3432, 0, 240, 244, 247, 262, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 14 - 1440x480@60Hz */
745 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
746 1596, 1716, 0, 480, 489, 495, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
749 /* 15 - 1440x480@60Hz */
750 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
751 1596, 1716, 0, 480, 489, 495, 525, 0,
752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754 /* 16 - 1920x1080@60Hz */
755 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
756 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 17 - 720x576@50Hz */
760 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
761 796, 864, 0, 576, 581, 586, 625, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
764 /* 18 - 720x576@50Hz */
765 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
766 796, 864, 0, 576, 581, 586, 625, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 19 - 1280x720@50Hz */
770 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
771 1760, 1980, 0, 720, 725, 730, 750, 0,
772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 20 - 1920x1080i@50Hz */
775 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
776 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
778 DRM_MODE_FLAG_INTERLACE),
779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780 /* 21 - 720(1440)x576i@50Hz */
781 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
782 795, 864, 0, 576, 580, 586, 625, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 22 - 720(1440)x576i@50Hz */
787 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
788 795, 864, 0, 576, 580, 586, 625, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
792 /* 23 - 720(1440)x288@50Hz */
793 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
794 795, 864, 0, 288, 290, 293, 312, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_DBLCLK),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 24 - 720(1440)x288@50Hz */
799 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
800 795, 864, 0, 288, 290, 293, 312, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
802 DRM_MODE_FLAG_DBLCLK),
803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
804 /* 25 - 2880x576i@50Hz */
805 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 576, 580, 586, 625, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
808 DRM_MODE_FLAG_INTERLACE),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810 /* 26 - 2880x576i@50Hz */
811 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
812 3180, 3456, 0, 576, 580, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
814 DRM_MODE_FLAG_INTERLACE),
815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 27 - 2880x288@50Hz */
817 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
818 3180, 3456, 0, 288, 290, 293, 312, 0,
819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
821 /* 28 - 2880x288@50Hz */
822 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
823 3180, 3456, 0, 288, 290, 293, 312, 0,
824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 29 - 1440x576@50Hz */
827 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
828 1592, 1728, 0, 576, 581, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
830 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
831 /* 30 - 1440x576@50Hz */
832 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
833 1592, 1728, 0, 576, 581, 586, 625, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
836 /* 31 - 1920x1080@50Hz */
837 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
838 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 32 - 1920x1080@24Hz */
842 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
843 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
845 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846 /* 33 - 1920x1080@25Hz */
847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
848 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
850 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 34 - 1920x1080@30Hz */
852 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
853 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
855 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
856 /* 35 - 2880x480@60Hz */
857 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
858 3192, 3432, 0, 480, 489, 495, 525, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
860 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
861 /* 36 - 2880x480@60Hz */
862 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
863 3192, 3432, 0, 480, 489, 495, 525, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
865 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
866 /* 37 - 2880x576@50Hz */
867 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
868 3184, 3456, 0, 576, 581, 586, 625, 0,
869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
870 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
871 /* 38 - 2880x576@50Hz */
872 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
873 3184, 3456, 0, 576, 581, 586, 625, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 39 - 1920x1080i@50Hz */
877 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
878 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
880 DRM_MODE_FLAG_INTERLACE),
881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 40 - 1920x1080i@100Hz */
883 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
886 DRM_MODE_FLAG_INTERLACE),
887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 41 - 1280x720@100Hz */
889 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
890 1760, 1980, 0, 720, 725, 730, 750, 0,
891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
892 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 42 - 720x576@100Hz */
894 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
895 796, 864, 0, 576, 581, 586, 625, 0,
896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
898 /* 43 - 720x576@100Hz */
899 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
900 796, 864, 0, 576, 581, 586, 625, 0,
901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 44 - 720(1440)x576i@100Hz */
904 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
905 795, 864, 0, 576, 580, 586, 625, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
908 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
909 /* 45 - 720(1440)x576i@100Hz */
910 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
911 795, 864, 0, 576, 580, 586, 625, 0,
912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
914 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 46 - 1920x1080i@120Hz */
916 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
917 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
919 DRM_MODE_FLAG_INTERLACE),
920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 47 - 1280x720@120Hz */
922 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
923 1430, 1650, 0, 720, 725, 730, 750, 0,
924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
925 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
926 /* 48 - 720x480@120Hz */
927 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
928 798, 858, 0, 480, 489, 495, 525, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
931 /* 49 - 720x480@120Hz */
932 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
933 798, 858, 0, 480, 489, 495, 525, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 50 - 720(1440)x480i@120Hz */
937 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
938 801, 858, 0, 480, 488, 494, 525, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
940 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
941 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
942 /* 51 - 720(1440)x480i@120Hz */
943 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
944 801, 858, 0, 480, 488, 494, 525, 0,
945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
946 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
947 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 52 - 720x576@200Hz */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 53 - 720x576@200Hz */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 54 - 720(1440)x576i@200Hz */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 55 - 720(1440)x576i@200Hz */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 56 - 720x480@240Hz */
971 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
972 798, 858, 0, 480, 489, 495, 525, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
975 /* 57 - 720x480@240Hz */
976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
977 798, 858, 0, 480, 489, 495, 525, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980 /* 58 - 720(1440)x480i@240Hz */
981 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
982 801, 858, 0, 480, 488, 494, 525, 0,
983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 59 - 720(1440)x480i@240Hz */
987 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
988 801, 858, 0, 480, 488, 494, 525, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
991 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992 /* 60 - 1280x720@24Hz */
993 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
994 3080, 3300, 0, 720, 725, 730, 750, 0,
995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
996 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
997 /* 61 - 1280x720@25Hz */
998 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
999 3740, 3960, 0, 720, 725, 730, 750, 0,
1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1001 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002 /* 62 - 1280x720@30Hz */
1003 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1004 3080, 3300, 0, 720, 725, 730, 750, 0,
1005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1006 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1007 /* 63 - 1920x1080@120Hz */
1008 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1009 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1011 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1012 /* 64 - 1920x1080@100Hz */
1013 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1014 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1016 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 65 - 1280x720@24Hz */
1018 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1019 3080, 3300, 0, 720, 725, 730, 750, 0,
1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1021 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1022 /* 66 - 1280x720@25Hz */
1023 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1024 3740, 3960, 0, 720, 725, 730, 750, 0,
1025 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1026 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1027 /* 67 - 1280x720@30Hz */
1028 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1029 3080, 3300, 0, 720, 725, 730, 750, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1031 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1032 /* 68 - 1280x720@50Hz */
1033 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1034 1760, 1980, 0, 720, 725, 730, 750, 0,
1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1036 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1037 /* 69 - 1280x720@60Hz */
1038 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1039 1430, 1650, 0, 720, 725, 730, 750, 0,
1040 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1041 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1042 /* 70 - 1280x720@100Hz */
1043 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1044 1760, 1980, 0, 720, 725, 730, 750, 0,
1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1046 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1047 /* 71 - 1280x720@120Hz */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1049 1430, 1650, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1052 /* 72 - 1920x1080@24Hz */
1053 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1054 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1057 /* 73 - 1920x1080@25Hz */
1058 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1059 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1062 /* 74 - 1920x1080@30Hz */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1067 /* 75 - 1920x1080@50Hz */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1072 /* 76 - 1920x1080@60Hz */
1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1074 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 77 - 1920x1080@100Hz */
1078 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1079 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 78 - 1920x1080@120Hz */
1083 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1084 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 79 - 1680x720@24Hz */
1088 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 80 - 1680x720@25Hz */
1093 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1094 2948, 3168, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 81 - 1680x720@30Hz */
1098 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1099 2420, 2640, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 82 - 1680x720@50Hz */
1103 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1104 1980, 2200, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 83 - 1680x720@60Hz */
1108 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1109 1980, 2200, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 84 - 1680x720@100Hz */
1113 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1114 1780, 2000, 0, 720, 725, 730, 825, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 85 - 1680x720@120Hz */
1118 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1119 1780, 2000, 0, 720, 725, 730, 825, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 86 - 2560x1080@24Hz */
1123 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1124 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 87 - 2560x1080@25Hz */
1128 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1129 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 88 - 2560x1080@30Hz */
1133 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1134 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 89 - 2560x1080@50Hz */
1138 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1139 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 90 - 2560x1080@60Hz */
1143 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1144 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 91 - 2560x1080@100Hz */
1148 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1149 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 92 - 2560x1080@120Hz */
1153 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1154 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 93 - 3840x2160p@24Hz 16:9 */
1158 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1159 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1162 /* 94 - 3840x2160p@25Hz 16:9 */
1163 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1164 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1167 /* 95 - 3840x2160p@30Hz 16:9 */
1168 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1169 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1172 /* 96 - 3840x2160p@50Hz 16:9 */
1173 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1174 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1177 /* 97 - 3840x2160p@60Hz 16:9 */
1178 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1179 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1182 /* 98 - 4096x2160p@24Hz 256:135 */
1183 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1184 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1187 /* 99 - 4096x2160p@25Hz 256:135 */
1188 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1189 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1192 /* 100 - 4096x2160p@30Hz 256:135 */
1193 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1194 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1197 /* 101 - 4096x2160p@50Hz 256:135 */
1198 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1199 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1202 /* 102 - 4096x2160p@60Hz 256:135 */
1203 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1204 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1207 /* 103 - 3840x2160p@24Hz 64:27 */
1208 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1209 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 104 - 3840x2160p@25Hz 64:27 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1214 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1217 /* 105 - 3840x2160p@30Hz 64:27 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1219 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1222 /* 106 - 3840x2160p@50Hz 64:27 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1227 /* 107 - 3840x2160p@60Hz 64:27 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235 * HDMI 1.4 4k modes. Index using the VIC.
1237 static const struct drm_display_mode edid_4k_modes[] = {
1238 /* 0 - dummy, VICs start at 1 */
1240 /* 1 - 3840x2160@30Hz */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1242 3840, 4016, 4104, 4400, 0,
1243 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 /* 2 - 3840x2160@25Hz */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1248 3840, 4896, 4984, 5280, 0,
1249 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 /* 3 - 3840x2160@24Hz */
1253 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1254 3840, 5116, 5204, 5500, 0,
1255 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 /* 4 - 4096x2160@24Hz (SMPTE) */
1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1260 4096, 5116, 5204, 5500, 0,
1261 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1266 /*** DDC fetch and block validation ***/
1268 static const u8 edid_header[] = {
1269 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1273 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1274 * @raw_edid: pointer to raw base EDID block
1276 * Sanity check the header of the base EDID block.
1278 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1280 int drm_edid_header_is_valid(const u8 *raw_edid)
1284 for (i = 0; i < sizeof(edid_header); i++)
1285 if (raw_edid[i] == edid_header[i])
1290 EXPORT_SYMBOL(drm_edid_header_is_valid);
1292 static int edid_fixup __read_mostly = 6;
1293 module_param_named(edid_fixup, edid_fixup, int, 0400);
1294 MODULE_PARM_DESC(edid_fixup,
1295 "Minimum number of valid EDID header bytes (0-8, default 6)");
1297 static void drm_get_displayid(struct drm_connector *connector,
1300 static int drm_edid_block_checksum(const u8 *raw_edid)
1304 for (i = 0; i < EDID_LENGTH; i++)
1305 csum += raw_edid[i];
1310 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1312 if (memchr_inv(in_edid, 0, length))
1319 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1320 * @raw_edid: pointer to raw EDID block
1321 * @block: type of block to validate (0 for base, extension otherwise)
1322 * @print_bad_edid: if true, dump bad EDID blocks to the console
1323 * @edid_corrupt: if true, the header or checksum is invalid
1325 * Validate a base or extension EDID block and optionally dump bad blocks to
1328 * Return: True if the block is valid, false otherwise.
1330 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1334 struct edid *edid = (struct edid *)raw_edid;
1336 if (WARN_ON(!raw_edid))
1339 if (edid_fixup > 8 || edid_fixup < 0)
1343 int score = drm_edid_header_is_valid(raw_edid);
1346 *edid_corrupt = false;
1347 } else if (score >= edid_fixup) {
1348 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1349 * The corrupt flag needs to be set here otherwise, the
1350 * fix-up code here will correct the problem, the
1351 * checksum is correct and the test fails
1354 *edid_corrupt = true;
1355 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1356 memcpy(raw_edid, edid_header, sizeof(edid_header));
1359 *edid_corrupt = true;
1364 csum = drm_edid_block_checksum(raw_edid);
1367 *edid_corrupt = true;
1369 /* allow CEA to slide through, switches mangle this */
1370 if (raw_edid[0] == CEA_EXT) {
1371 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1372 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1375 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1381 /* per-block-type checks */
1382 switch (raw_edid[0]) {
1384 if (edid->version != 1) {
1385 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1389 if (edid->revision > 4)
1390 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1400 if (print_bad_edid) {
1401 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1402 pr_notice("EDID block is all zeroes\n");
1404 pr_notice("Raw EDID:\n");
1405 print_hex_dump(KERN_NOTICE,
1406 " \t", DUMP_PREFIX_NONE, 16, 1,
1407 raw_edid, EDID_LENGTH, false);
1412 EXPORT_SYMBOL(drm_edid_block_valid);
1415 * drm_edid_is_valid - sanity check EDID data
1418 * Sanity-check an entire EDID record (including extensions)
1420 * Return: True if the EDID data is valid, false otherwise.
1422 bool drm_edid_is_valid(struct edid *edid)
1425 u8 *raw = (u8 *)edid;
1430 for (i = 0; i <= edid->extensions; i++)
1431 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1436 EXPORT_SYMBOL(drm_edid_is_valid);
1438 #define DDC_SEGMENT_ADDR 0x30
1440 * drm_do_probe_ddc_edid() - get EDID information via I2C
1441 * @data: I2C device adapter
1442 * @buf: EDID data buffer to be filled
1443 * @block: 128 byte EDID block to start fetching from
1444 * @len: EDID data buffer length to fetch
1446 * Try to fetch EDID information by calling I2C driver functions.
1448 * Return: 0 on success or -1 on failure.
1451 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1453 struct i2c_adapter *adapter = data;
1454 unsigned char start = block * EDID_LENGTH;
1455 unsigned char segment = block >> 1;
1456 unsigned char xfers = segment ? 3 : 2;
1457 int ret, retries = 5;
1460 * The core I2C driver will automatically retry the transfer if the
1461 * adapter reports EAGAIN. However, we find that bit-banging transfers
1462 * are susceptible to errors under a heavily loaded machine and
1463 * generate spurious NAKs and timeouts. Retrying the transfer
1464 * of the individual block a few times seems to overcome this.
1467 struct i2c_msg msgs[] = {
1469 .addr = DDC_SEGMENT_ADDR,
1487 * Avoid sending the segment addr to not upset non-compliant
1490 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1492 if (ret == -ENXIO) {
1493 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1497 } while (ret != xfers && --retries);
1499 return ret == xfers ? 0 : -1;
1502 static void connector_bad_edid(struct drm_connector *connector,
1503 u8 *edid, int num_blocks)
1507 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1510 dev_warn(connector->dev->dev,
1511 "%s: EDID is invalid:\n",
1513 for (i = 0; i < num_blocks; i++) {
1514 u8 *block = edid + i * EDID_LENGTH;
1517 if (drm_edid_is_zero(block, EDID_LENGTH))
1518 sprintf(prefix, "\t[%02x] ZERO ", i);
1519 else if (!drm_edid_block_valid(block, i, false, NULL))
1520 sprintf(prefix, "\t[%02x] BAD ", i);
1522 sprintf(prefix, "\t[%02x] GOOD ", i);
1524 print_hex_dump(KERN_WARNING,
1525 prefix, DUMP_PREFIX_NONE, 16, 1,
1526 block, EDID_LENGTH, false);
1531 * drm_do_get_edid - get EDID data using a custom EDID block read function
1532 * @connector: connector we're probing
1533 * @get_edid_block: EDID block read function
1534 * @data: private data passed to the block read function
1536 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1537 * exposes a different interface to read EDID blocks this function can be used
1538 * to get EDID data using a custom block read function.
1540 * As in the general case the DDC bus is accessible by the kernel at the I2C
1541 * level, drivers must make all reasonable efforts to expose it as an I2C
1542 * adapter and use drm_get_edid() instead of abusing this function.
1544 * The EDID may be overridden using debugfs override_edid or firmare EDID
1545 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1546 * order. Having either of them bypasses actual EDID reads.
1548 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1550 struct edid *drm_do_get_edid(struct drm_connector *connector,
1551 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1555 int i, j = 0, valid_extensions = 0;
1557 struct edid *override = NULL;
1559 if (connector->override_edid)
1560 override = drm_edid_duplicate((const struct edid *)
1561 connector->edid_blob_ptr->data);
1564 override = drm_load_edid_firmware(connector);
1566 if (!IS_ERR_OR_NULL(override))
1569 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1572 /* base block fetch */
1573 for (i = 0; i < 4; i++) {
1574 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1576 if (drm_edid_block_valid(edid, 0, false,
1577 &connector->edid_corrupt))
1579 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1580 connector->null_edid_counter++;
1587 /* if there's no extensions, we're done */
1588 valid_extensions = edid[0x7e];
1589 if (valid_extensions == 0)
1590 return (struct edid *)edid;
1592 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1597 for (j = 1; j <= edid[0x7e]; j++) {
1598 u8 *block = edid + j * EDID_LENGTH;
1600 for (i = 0; i < 4; i++) {
1601 if (get_edid_block(data, block, j, EDID_LENGTH))
1603 if (drm_edid_block_valid(block, j, false, NULL))
1611 if (valid_extensions != edid[0x7e]) {
1614 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1616 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1617 edid[0x7e] = valid_extensions;
1619 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1624 for (i = 0; i <= edid[0x7e]; i++) {
1625 u8 *block = edid + i * EDID_LENGTH;
1627 if (!drm_edid_block_valid(block, i, false, NULL))
1630 memcpy(base, block, EDID_LENGTH);
1631 base += EDID_LENGTH;
1638 return (struct edid *)edid;
1641 connector_bad_edid(connector, edid, 1);
1646 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1649 * drm_probe_ddc() - probe DDC presence
1650 * @adapter: I2C adapter to probe
1652 * Return: True on success, false on failure.
1655 drm_probe_ddc(struct i2c_adapter *adapter)
1659 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1661 EXPORT_SYMBOL(drm_probe_ddc);
1664 * drm_get_edid - get EDID data, if available
1665 * @connector: connector we're probing
1666 * @adapter: I2C adapter to use for DDC
1668 * Poke the given I2C channel to grab EDID data if possible. If found,
1669 * attach it to the connector.
1671 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1673 struct edid *drm_get_edid(struct drm_connector *connector,
1674 struct i2c_adapter *adapter)
1678 if (connector->force == DRM_FORCE_OFF)
1681 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1684 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1686 drm_get_displayid(connector, edid);
1689 EXPORT_SYMBOL(drm_get_edid);
1692 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1693 * @connector: connector we're probing
1694 * @adapter: I2C adapter to use for DDC
1696 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1697 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1698 * switch DDC to the GPU which is retrieving EDID.
1700 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1702 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1703 struct i2c_adapter *adapter)
1705 struct pci_dev *pdev = connector->dev->pdev;
1708 vga_switcheroo_lock_ddc(pdev);
1709 edid = drm_get_edid(connector, adapter);
1710 vga_switcheroo_unlock_ddc(pdev);
1714 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1717 * drm_edid_duplicate - duplicate an EDID and the extensions
1718 * @edid: EDID to duplicate
1720 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1722 struct edid *drm_edid_duplicate(const struct edid *edid)
1724 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1726 EXPORT_SYMBOL(drm_edid_duplicate);
1728 /*** EDID parsing ***/
1731 * edid_vendor - match a string against EDID's obfuscated vendor field
1732 * @edid: EDID to match
1733 * @vendor: vendor string
1735 * Returns true if @vendor is in @edid, false otherwise
1737 static bool edid_vendor(const struct edid *edid, const char *vendor)
1739 char edid_vendor[3];
1741 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1742 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1743 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1744 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1746 return !strncmp(edid_vendor, vendor, 3);
1750 * edid_get_quirks - return quirk flags for a given EDID
1751 * @edid: EDID to process
1753 * This tells subsequent routines what fixes they need to apply.
1755 static u32 edid_get_quirks(const struct edid *edid)
1757 const struct edid_quirk *quirk;
1760 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1761 quirk = &edid_quirk_list[i];
1763 if (edid_vendor(edid, quirk->vendor) &&
1764 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1765 return quirk->quirks;
1771 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1772 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1775 * edid_fixup_preferred - set preferred modes based on quirk list
1776 * @connector: has mode list to fix up
1777 * @quirks: quirks list
1779 * Walk the mode list for @connector, clearing the preferred status
1780 * on existing modes and setting it anew for the right mode ala @quirks.
1782 static void edid_fixup_preferred(struct drm_connector *connector,
1785 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1786 int target_refresh = 0;
1787 int cur_vrefresh, preferred_vrefresh;
1789 if (list_empty(&connector->probed_modes))
1792 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1793 target_refresh = 60;
1794 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1795 target_refresh = 75;
1797 preferred_mode = list_first_entry(&connector->probed_modes,
1798 struct drm_display_mode, head);
1800 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1801 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1803 if (cur_mode == preferred_mode)
1806 /* Largest mode is preferred */
1807 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1808 preferred_mode = cur_mode;
1810 cur_vrefresh = cur_mode->vrefresh ?
1811 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1812 preferred_vrefresh = preferred_mode->vrefresh ?
1813 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1814 /* At a given size, try to get closest to target refresh */
1815 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1816 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1817 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1818 preferred_mode = cur_mode;
1822 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1826 mode_is_rb(const struct drm_display_mode *mode)
1828 return (mode->htotal - mode->hdisplay == 160) &&
1829 (mode->hsync_end - mode->hdisplay == 80) &&
1830 (mode->hsync_end - mode->hsync_start == 32) &&
1831 (mode->vsync_start - mode->vdisplay == 3);
1835 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1836 * @dev: Device to duplicate against
1837 * @hsize: Mode width
1838 * @vsize: Mode height
1839 * @fresh: Mode refresh rate
1840 * @rb: Mode reduced-blanking-ness
1842 * Walk the DMT mode list looking for a match for the given parameters.
1844 * Return: A newly allocated copy of the mode, or NULL if not found.
1846 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1847 int hsize, int vsize, int fresh,
1852 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1853 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1854 if (hsize != ptr->hdisplay)
1856 if (vsize != ptr->vdisplay)
1858 if (fresh != drm_mode_vrefresh(ptr))
1860 if (rb != mode_is_rb(ptr))
1863 return drm_mode_duplicate(dev, ptr);
1868 EXPORT_SYMBOL(drm_mode_find_dmt);
1870 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1873 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1877 u8 *det_base = ext + d;
1880 for (i = 0; i < n; i++)
1881 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1885 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1887 unsigned int i, n = min((int)ext[0x02], 6);
1888 u8 *det_base = ext + 5;
1891 return; /* unknown version */
1893 for (i = 0; i < n; i++)
1894 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1898 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1901 struct edid *edid = (struct edid *)raw_edid;
1906 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1907 cb(&(edid->detailed_timings[i]), closure);
1909 for (i = 1; i <= raw_edid[0x7e]; i++) {
1910 u8 *ext = raw_edid + (i * EDID_LENGTH);
1913 cea_for_each_detailed_block(ext, cb, closure);
1916 vtb_for_each_detailed_block(ext, cb, closure);
1925 is_rb(struct detailed_timing *t, void *data)
1928 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1930 *(bool *)data = true;
1933 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1935 drm_monitor_supports_rb(struct edid *edid)
1937 if (edid->revision >= 4) {
1939 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1943 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1947 find_gtf2(struct detailed_timing *t, void *data)
1950 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1954 /* Secondary GTF curve kicks in above some break frequency */
1956 drm_gtf2_hbreak(struct edid *edid)
1959 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1960 return r ? (r[12] * 2) : 0;
1964 drm_gtf2_2c(struct edid *edid)
1967 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1968 return r ? r[13] : 0;
1972 drm_gtf2_m(struct edid *edid)
1975 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1976 return r ? (r[15] << 8) + r[14] : 0;
1980 drm_gtf2_k(struct edid *edid)
1983 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1984 return r ? r[16] : 0;
1988 drm_gtf2_2j(struct edid *edid)
1991 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1992 return r ? r[17] : 0;
1996 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1997 * @edid: EDID block to scan
1999 static int standard_timing_level(struct edid *edid)
2001 if (edid->revision >= 2) {
2002 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2004 if (drm_gtf2_hbreak(edid))
2012 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2013 * monitors fill with ascii space (0x20) instead.
2016 bad_std_timing(u8 a, u8 b)
2018 return (a == 0x00 && b == 0x00) ||
2019 (a == 0x01 && b == 0x01) ||
2020 (a == 0x20 && b == 0x20);
2024 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2025 * @connector: connector of for the EDID block
2026 * @edid: EDID block to scan
2027 * @t: standard timing params
2029 * Take the standard timing params (in this case width, aspect, and refresh)
2030 * and convert them into a real mode using CVT/GTF/DMT.
2032 static struct drm_display_mode *
2033 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2034 struct std_timing *t)
2036 struct drm_device *dev = connector->dev;
2037 struct drm_display_mode *m, *mode = NULL;
2040 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2041 >> EDID_TIMING_ASPECT_SHIFT;
2042 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2043 >> EDID_TIMING_VFREQ_SHIFT;
2044 int timing_level = standard_timing_level(edid);
2046 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2049 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2050 hsize = t->hsize * 8 + 248;
2051 /* vrefresh_rate = vfreq + 60 */
2052 vrefresh_rate = vfreq + 60;
2053 /* the vdisplay is calculated based on the aspect ratio */
2054 if (aspect_ratio == 0) {
2055 if (edid->revision < 3)
2058 vsize = (hsize * 10) / 16;
2059 } else if (aspect_ratio == 1)
2060 vsize = (hsize * 3) / 4;
2061 else if (aspect_ratio == 2)
2062 vsize = (hsize * 4) / 5;
2064 vsize = (hsize * 9) / 16;
2066 /* HDTV hack, part 1 */
2067 if (vrefresh_rate == 60 &&
2068 ((hsize == 1360 && vsize == 765) ||
2069 (hsize == 1368 && vsize == 769))) {
2075 * If this connector already has a mode for this size and refresh
2076 * rate (because it came from detailed or CVT info), use that
2077 * instead. This way we don't have to guess at interlace or
2080 list_for_each_entry(m, &connector->probed_modes, head)
2081 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2082 drm_mode_vrefresh(m) == vrefresh_rate)
2085 /* HDTV hack, part 2 */
2086 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2087 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2089 mode->hdisplay = 1366;
2090 mode->hsync_start = mode->hsync_start - 1;
2091 mode->hsync_end = mode->hsync_end - 1;
2095 /* check whether it can be found in default mode table */
2096 if (drm_monitor_supports_rb(edid)) {
2097 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2102 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2106 /* okay, generate it */
2107 switch (timing_level) {
2111 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2115 * This is potentially wrong if there's ever a monitor with
2116 * more than one ranges section, each claiming a different
2117 * secondary GTF curve. Please don't do that.
2119 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2122 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2123 drm_mode_destroy(dev, mode);
2124 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2125 vrefresh_rate, 0, 0,
2133 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2141 * EDID is delightfully ambiguous about how interlaced modes are to be
2142 * encoded. Our internal representation is of frame height, but some
2143 * HDTV detailed timings are encoded as field height.
2145 * The format list here is from CEA, in frame size. Technically we
2146 * should be checking refresh rate too. Whatever.
2149 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2150 struct detailed_pixel_timing *pt)
2153 static const struct {
2155 } cea_interlaced[] = {
2165 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2168 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2169 if ((mode->hdisplay == cea_interlaced[i].w) &&
2170 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2171 mode->vdisplay *= 2;
2172 mode->vsync_start *= 2;
2173 mode->vsync_end *= 2;
2179 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2183 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2184 * @dev: DRM device (needed to create new mode)
2186 * @timing: EDID detailed timing info
2187 * @quirks: quirks to apply
2189 * An EDID detailed timing block contains enough info for us to create and
2190 * return a new struct drm_display_mode.
2192 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2194 struct detailed_timing *timing,
2197 struct drm_display_mode *mode;
2198 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2199 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2200 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2201 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2202 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2203 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2204 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2205 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2206 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2208 /* ignore tiny modes */
2209 if (hactive < 64 || vactive < 64)
2212 if (pt->misc & DRM_EDID_PT_STEREO) {
2213 DRM_DEBUG_KMS("stereo mode not supported\n");
2216 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2217 DRM_DEBUG_KMS("composite sync not supported\n");
2220 /* it is incorrect if hsync/vsync width is zero */
2221 if (!hsync_pulse_width || !vsync_pulse_width) {
2222 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2223 "Wrong Hsync/Vsync pulse width\n");
2227 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2228 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2235 mode = drm_mode_create(dev);
2239 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2240 timing->pixel_clock = cpu_to_le16(1088);
2242 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2244 mode->hdisplay = hactive;
2245 mode->hsync_start = mode->hdisplay + hsync_offset;
2246 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2247 mode->htotal = mode->hdisplay + hblank;
2249 mode->vdisplay = vactive;
2250 mode->vsync_start = mode->vdisplay + vsync_offset;
2251 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2252 mode->vtotal = mode->vdisplay + vblank;
2254 /* Some EDIDs have bogus h/vtotal values */
2255 if (mode->hsync_end > mode->htotal)
2256 mode->htotal = mode->hsync_end + 1;
2257 if (mode->vsync_end > mode->vtotal)
2258 mode->vtotal = mode->vsync_end + 1;
2260 drm_mode_do_interlace_quirk(mode, pt);
2262 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2263 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2266 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2267 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2268 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2269 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2272 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2273 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2275 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2276 mode->width_mm *= 10;
2277 mode->height_mm *= 10;
2280 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2281 mode->width_mm = edid->width_cm * 10;
2282 mode->height_mm = edid->height_cm * 10;
2285 mode->type = DRM_MODE_TYPE_DRIVER;
2286 mode->vrefresh = drm_mode_vrefresh(mode);
2287 drm_mode_set_name(mode);
2293 mode_in_hsync_range(const struct drm_display_mode *mode,
2294 struct edid *edid, u8 *t)
2296 int hsync, hmin, hmax;
2299 if (edid->revision >= 4)
2300 hmin += ((t[4] & 0x04) ? 255 : 0);
2302 if (edid->revision >= 4)
2303 hmax += ((t[4] & 0x08) ? 255 : 0);
2304 hsync = drm_mode_hsync(mode);
2306 return (hsync <= hmax && hsync >= hmin);
2310 mode_in_vsync_range(const struct drm_display_mode *mode,
2311 struct edid *edid, u8 *t)
2313 int vsync, vmin, vmax;
2316 if (edid->revision >= 4)
2317 vmin += ((t[4] & 0x01) ? 255 : 0);
2319 if (edid->revision >= 4)
2320 vmax += ((t[4] & 0x02) ? 255 : 0);
2321 vsync = drm_mode_vrefresh(mode);
2323 return (vsync <= vmax && vsync >= vmin);
2327 range_pixel_clock(struct edid *edid, u8 *t)
2330 if (t[9] == 0 || t[9] == 255)
2333 /* 1.4 with CVT support gives us real precision, yay */
2334 if (edid->revision >= 4 && t[10] == 0x04)
2335 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2337 /* 1.3 is pathetic, so fuzz up a bit */
2338 return t[9] * 10000 + 5001;
2342 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2343 struct detailed_timing *timing)
2346 u8 *t = (u8 *)timing;
2348 if (!mode_in_hsync_range(mode, edid, t))
2351 if (!mode_in_vsync_range(mode, edid, t))
2354 if ((max_clock = range_pixel_clock(edid, t)))
2355 if (mode->clock > max_clock)
2358 /* 1.4 max horizontal check */
2359 if (edid->revision >= 4 && t[10] == 0x04)
2360 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2363 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2369 static bool valid_inferred_mode(const struct drm_connector *connector,
2370 const struct drm_display_mode *mode)
2372 const struct drm_display_mode *m;
2375 list_for_each_entry(m, &connector->probed_modes, head) {
2376 if (mode->hdisplay == m->hdisplay &&
2377 mode->vdisplay == m->vdisplay &&
2378 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2379 return false; /* duplicated */
2380 if (mode->hdisplay <= m->hdisplay &&
2381 mode->vdisplay <= m->vdisplay)
2388 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2389 struct detailed_timing *timing)
2392 struct drm_display_mode *newmode;
2393 struct drm_device *dev = connector->dev;
2395 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2396 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2397 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2398 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2400 drm_mode_probed_add(connector, newmode);
2409 /* fix up 1366x768 mode from 1368x768;
2410 * GFT/CVT can't express 1366 width which isn't dividable by 8
2412 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2414 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2415 mode->hdisplay = 1366;
2416 mode->hsync_start--;
2418 drm_mode_set_name(mode);
2423 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2424 struct detailed_timing *timing)
2427 struct drm_display_mode *newmode;
2428 struct drm_device *dev = connector->dev;
2430 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2431 const struct minimode *m = &extra_modes[i];
2432 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2436 drm_mode_fixup_1366x768(newmode);
2437 if (!mode_in_range(newmode, edid, timing) ||
2438 !valid_inferred_mode(connector, newmode)) {
2439 drm_mode_destroy(dev, newmode);
2443 drm_mode_probed_add(connector, newmode);
2451 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2452 struct detailed_timing *timing)
2455 struct drm_display_mode *newmode;
2456 struct drm_device *dev = connector->dev;
2457 bool rb = drm_monitor_supports_rb(edid);
2459 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2460 const struct minimode *m = &extra_modes[i];
2461 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2465 drm_mode_fixup_1366x768(newmode);
2466 if (!mode_in_range(newmode, edid, timing) ||
2467 !valid_inferred_mode(connector, newmode)) {
2468 drm_mode_destroy(dev, newmode);
2472 drm_mode_probed_add(connector, newmode);
2480 do_inferred_modes(struct detailed_timing *timing, void *c)
2482 struct detailed_mode_closure *closure = c;
2483 struct detailed_non_pixel *data = &timing->data.other_data;
2484 struct detailed_data_monitor_range *range = &data->data.range;
2486 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2489 closure->modes += drm_dmt_modes_for_range(closure->connector,
2493 if (!version_greater(closure->edid, 1, 1))
2494 return; /* GTF not defined yet */
2496 switch (range->flags) {
2497 case 0x02: /* secondary gtf, XXX could do more */
2498 case 0x00: /* default gtf */
2499 closure->modes += drm_gtf_modes_for_range(closure->connector,
2503 case 0x04: /* cvt, only in 1.4+ */
2504 if (!version_greater(closure->edid, 1, 3))
2507 closure->modes += drm_cvt_modes_for_range(closure->connector,
2511 case 0x01: /* just the ranges, no formula */
2518 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2520 struct detailed_mode_closure closure = {
2521 .connector = connector,
2525 if (version_greater(edid, 1, 0))
2526 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2529 return closure.modes;
2533 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2535 int i, j, m, modes = 0;
2536 struct drm_display_mode *mode;
2537 u8 *est = ((u8 *)timing) + 6;
2539 for (i = 0; i < 6; i++) {
2540 for (j = 7; j >= 0; j--) {
2541 m = (i * 8) + (7 - j);
2542 if (m >= ARRAY_SIZE(est3_modes))
2544 if (est[i] & (1 << j)) {
2545 mode = drm_mode_find_dmt(connector->dev,
2551 drm_mode_probed_add(connector, mode);
2562 do_established_modes(struct detailed_timing *timing, void *c)
2564 struct detailed_mode_closure *closure = c;
2565 struct detailed_non_pixel *data = &timing->data.other_data;
2567 if (data->type == EDID_DETAIL_EST_TIMINGS)
2568 closure->modes += drm_est3_modes(closure->connector, timing);
2572 * add_established_modes - get est. modes from EDID and add them
2573 * @connector: connector to add mode(s) to
2574 * @edid: EDID block to scan
2576 * Each EDID block contains a bitmap of the supported "established modes" list
2577 * (defined above). Tease them out and add them to the global modes list.
2580 add_established_modes(struct drm_connector *connector, struct edid *edid)
2582 struct drm_device *dev = connector->dev;
2583 unsigned long est_bits = edid->established_timings.t1 |
2584 (edid->established_timings.t2 << 8) |
2585 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2587 struct detailed_mode_closure closure = {
2588 .connector = connector,
2592 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2593 if (est_bits & (1<<i)) {
2594 struct drm_display_mode *newmode;
2595 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2597 drm_mode_probed_add(connector, newmode);
2603 if (version_greater(edid, 1, 0))
2604 drm_for_each_detailed_block((u8 *)edid,
2605 do_established_modes, &closure);
2607 return modes + closure.modes;
2611 do_standard_modes(struct detailed_timing *timing, void *c)
2613 struct detailed_mode_closure *closure = c;
2614 struct detailed_non_pixel *data = &timing->data.other_data;
2615 struct drm_connector *connector = closure->connector;
2616 struct edid *edid = closure->edid;
2618 if (data->type == EDID_DETAIL_STD_MODES) {
2620 for (i = 0; i < 6; i++) {
2621 struct std_timing *std;
2622 struct drm_display_mode *newmode;
2624 std = &data->data.timings[i];
2625 newmode = drm_mode_std(connector, edid, std);
2627 drm_mode_probed_add(connector, newmode);
2635 * add_standard_modes - get std. modes from EDID and add them
2636 * @connector: connector to add mode(s) to
2637 * @edid: EDID block to scan
2639 * Standard modes can be calculated using the appropriate standard (DMT,
2640 * GTF or CVT. Grab them from @edid and add them to the list.
2643 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2646 struct detailed_mode_closure closure = {
2647 .connector = connector,
2651 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2652 struct drm_display_mode *newmode;
2654 newmode = drm_mode_std(connector, edid,
2655 &edid->standard_timings[i]);
2657 drm_mode_probed_add(connector, newmode);
2662 if (version_greater(edid, 1, 0))
2663 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2666 /* XXX should also look for standard codes in VTB blocks */
2668 return modes + closure.modes;
2671 static int drm_cvt_modes(struct drm_connector *connector,
2672 struct detailed_timing *timing)
2674 int i, j, modes = 0;
2675 struct drm_display_mode *newmode;
2676 struct drm_device *dev = connector->dev;
2677 struct cvt_timing *cvt;
2678 const int rates[] = { 60, 85, 75, 60, 50 };
2679 const u8 empty[3] = { 0, 0, 0 };
2681 for (i = 0; i < 4; i++) {
2682 int uninitialized_var(width), height;
2683 cvt = &(timing->data.other_data.data.cvt[i]);
2685 if (!memcmp(cvt->code, empty, 3))
2688 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2689 switch (cvt->code[1] & 0x0c) {
2691 width = height * 4 / 3;
2694 width = height * 16 / 9;
2697 width = height * 16 / 10;
2700 width = height * 15 / 9;
2704 for (j = 1; j < 5; j++) {
2705 if (cvt->code[2] & (1 << j)) {
2706 newmode = drm_cvt_mode(dev, width, height,
2710 drm_mode_probed_add(connector, newmode);
2721 do_cvt_mode(struct detailed_timing *timing, void *c)
2723 struct detailed_mode_closure *closure = c;
2724 struct detailed_non_pixel *data = &timing->data.other_data;
2726 if (data->type == EDID_DETAIL_CVT_3BYTE)
2727 closure->modes += drm_cvt_modes(closure->connector, timing);
2731 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2733 struct detailed_mode_closure closure = {
2734 .connector = connector,
2738 if (version_greater(edid, 1, 2))
2739 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2741 /* XXX should also look for CVT codes in VTB blocks */
2743 return closure.modes;
2746 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2749 do_detailed_mode(struct detailed_timing *timing, void *c)
2751 struct detailed_mode_closure *closure = c;
2752 struct drm_display_mode *newmode;
2754 if (timing->pixel_clock) {
2755 newmode = drm_mode_detailed(closure->connector->dev,
2756 closure->edid, timing,
2761 if (closure->preferred)
2762 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2765 * Detailed modes are limited to 10kHz pixel clock resolution,
2766 * so fix up anything that looks like CEA/HDMI mode, but the clock
2767 * is just slightly off.
2769 fixup_detailed_cea_mode_clock(newmode);
2771 drm_mode_probed_add(closure->connector, newmode);
2773 closure->preferred = 0;
2778 * add_detailed_modes - Add modes from detailed timings
2779 * @connector: attached connector
2780 * @edid: EDID block to scan
2781 * @quirks: quirks to apply
2784 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2787 struct detailed_mode_closure closure = {
2788 .connector = connector,
2794 if (closure.preferred && !version_greater(edid, 1, 3))
2796 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2798 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2800 return closure.modes;
2803 #define AUDIO_BLOCK 0x01
2804 #define VIDEO_BLOCK 0x02
2805 #define VENDOR_BLOCK 0x03
2806 #define SPEAKER_BLOCK 0x04
2807 #define USE_EXTENDED_TAG 0x07
2808 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2809 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2810 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2811 #define EDID_BASIC_AUDIO (1 << 6)
2812 #define EDID_CEA_YCRCB444 (1 << 5)
2813 #define EDID_CEA_YCRCB422 (1 << 4)
2814 #define EDID_CEA_VCDB_QS (1 << 6)
2817 * Search EDID for CEA extension block.
2819 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2821 u8 *edid_ext = NULL;
2824 /* No EDID or EDID extensions */
2825 if (edid == NULL || edid->extensions == 0)
2828 /* Find CEA extension */
2829 for (i = 0; i < edid->extensions; i++) {
2830 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2831 if (edid_ext[0] == ext_id)
2835 if (i == edid->extensions)
2841 static u8 *drm_find_cea_extension(const struct edid *edid)
2843 return drm_find_edid_extension(edid, CEA_EXT);
2846 static u8 *drm_find_displayid_extension(const struct edid *edid)
2848 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2852 * Calculate the alternate clock for the CEA mode
2853 * (60Hz vs. 59.94Hz etc.)
2856 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2858 unsigned int clock = cea_mode->clock;
2860 if (cea_mode->vrefresh % 6 != 0)
2864 * edid_cea_modes contains the 59.94Hz
2865 * variant for 240 and 480 line modes,
2866 * and the 60Hz variant otherwise.
2868 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2869 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2871 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2877 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2880 * For certain VICs the spec allows the vertical
2881 * front porch to vary by one or two lines.
2883 * cea_modes[] stores the variant with the shortest
2884 * vertical front porch. We can adjust the mode to
2885 * get the other variants by simply increasing the
2886 * vertical front porch length.
2888 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2889 edid_cea_modes[9].vtotal != 262 ||
2890 edid_cea_modes[12].vtotal != 262 ||
2891 edid_cea_modes[13].vtotal != 262 ||
2892 edid_cea_modes[23].vtotal != 312 ||
2893 edid_cea_modes[24].vtotal != 312 ||
2894 edid_cea_modes[27].vtotal != 312 ||
2895 edid_cea_modes[28].vtotal != 312);
2897 if (((vic == 8 || vic == 9 ||
2898 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2899 ((vic == 23 || vic == 24 ||
2900 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2901 mode->vsync_start++;
2911 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2912 unsigned int clock_tolerance)
2916 if (!to_match->clock)
2919 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2920 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2921 unsigned int clock1, clock2;
2923 /* Check both 60Hz and 59.94Hz */
2924 clock1 = cea_mode.clock;
2925 clock2 = cea_mode_alternate_clock(&cea_mode);
2927 if (abs(to_match->clock - clock1) > clock_tolerance &&
2928 abs(to_match->clock - clock2) > clock_tolerance)
2932 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2934 } while (cea_mode_alternate_timings(vic, &cea_mode));
2941 * drm_match_cea_mode - look for a CEA mode matching given mode
2942 * @to_match: display mode
2944 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2947 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2951 if (!to_match->clock)
2954 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2955 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2956 unsigned int clock1, clock2;
2958 /* Check both 60Hz and 59.94Hz */
2959 clock1 = cea_mode.clock;
2960 clock2 = cea_mode_alternate_clock(&cea_mode);
2962 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2963 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2967 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2969 } while (cea_mode_alternate_timings(vic, &cea_mode));
2974 EXPORT_SYMBOL(drm_match_cea_mode);
2976 static bool drm_valid_cea_vic(u8 vic)
2978 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2982 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2983 * the input VIC from the CEA mode list
2984 * @video_code: ID given to each of the CEA modes
2986 * Returns picture aspect ratio
2988 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2990 return edid_cea_modes[video_code].picture_aspect_ratio;
2992 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2995 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2998 * It's almost like cea_mode_alternate_clock(), we just need to add an
2999 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3003 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3005 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3006 return hdmi_mode->clock;
3008 return cea_mode_alternate_clock(hdmi_mode);
3011 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3012 unsigned int clock_tolerance)
3016 if (!to_match->clock)
3019 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3020 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3021 unsigned int clock1, clock2;
3023 /* Make sure to also match alternate clocks */
3024 clock1 = hdmi_mode->clock;
3025 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3027 if (abs(to_match->clock - clock1) > clock_tolerance &&
3028 abs(to_match->clock - clock2) > clock_tolerance)
3031 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3039 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3040 * @to_match: display mode
3042 * An HDMI mode is one defined in the HDMI vendor specific block.
3044 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3046 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3050 if (!to_match->clock)
3053 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3054 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3055 unsigned int clock1, clock2;
3057 /* Make sure to also match alternate clocks */
3058 clock1 = hdmi_mode->clock;
3059 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3061 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3062 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3063 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3069 static bool drm_valid_hdmi_vic(u8 vic)
3071 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3075 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3077 struct drm_device *dev = connector->dev;
3078 struct drm_display_mode *mode, *tmp;
3082 /* Don't add CEA modes if the CEA extension block is missing */
3083 if (!drm_find_cea_extension(edid))
3087 * Go through all probed modes and create a new mode
3088 * with the alternate clock for certain CEA modes.
3090 list_for_each_entry(mode, &connector->probed_modes, head) {
3091 const struct drm_display_mode *cea_mode = NULL;
3092 struct drm_display_mode *newmode;
3093 u8 vic = drm_match_cea_mode(mode);
3094 unsigned int clock1, clock2;
3096 if (drm_valid_cea_vic(vic)) {
3097 cea_mode = &edid_cea_modes[vic];
3098 clock2 = cea_mode_alternate_clock(cea_mode);
3100 vic = drm_match_hdmi_mode(mode);
3101 if (drm_valid_hdmi_vic(vic)) {
3102 cea_mode = &edid_4k_modes[vic];
3103 clock2 = hdmi_mode_alternate_clock(cea_mode);
3110 clock1 = cea_mode->clock;
3112 if (clock1 == clock2)
3115 if (mode->clock != clock1 && mode->clock != clock2)
3118 newmode = drm_mode_duplicate(dev, cea_mode);
3122 /* Carry over the stereo flags */
3123 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3126 * The current mode could be either variant. Make
3127 * sure to pick the "other" clock for the new mode.
3129 if (mode->clock != clock1)
3130 newmode->clock = clock1;
3132 newmode->clock = clock2;
3134 list_add_tail(&newmode->head, &list);
3137 list_for_each_entry_safe(mode, tmp, &list, head) {
3138 list_del(&mode->head);
3139 drm_mode_probed_add(connector, mode);
3146 static u8 svd_to_vic(u8 svd)
3148 /* 0-6 bit vic, 7th bit native mode indicator */
3149 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3155 static struct drm_display_mode *
3156 drm_display_mode_from_vic_index(struct drm_connector *connector,
3157 const u8 *video_db, u8 video_len,
3160 struct drm_device *dev = connector->dev;
3161 struct drm_display_mode *newmode;
3164 if (video_db == NULL || video_index >= video_len)
3167 /* CEA modes are numbered 1..127 */
3168 vic = svd_to_vic(video_db[video_index]);
3169 if (!drm_valid_cea_vic(vic))
3172 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3176 newmode->vrefresh = 0;
3182 * do_y420vdb_modes - Parse YCBCR 420 only modes
3183 * @connector: connector corresponding to the HDMI sink
3184 * @svds: start of the data block of CEA YCBCR 420 VDB
3185 * @len: length of the CEA YCBCR 420 VDB
3187 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3188 * which contains modes which can be supported in YCBCR 420
3189 * output format only.
3191 static int do_y420vdb_modes(struct drm_connector *connector,
3192 const u8 *svds, u8 svds_len)
3195 struct drm_device *dev = connector->dev;
3196 struct drm_display_info *info = &connector->display_info;
3197 struct drm_hdmi_info *hdmi = &info->hdmi;
3199 for (i = 0; i < svds_len; i++) {
3200 u8 vic = svd_to_vic(svds[i]);
3201 struct drm_display_mode *newmode;
3203 if (!drm_valid_cea_vic(vic))
3206 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3209 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3210 drm_mode_probed_add(connector, newmode);
3215 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3220 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3221 * @connector: connector corresponding to the HDMI sink
3222 * @vic: CEA vic for the video mode to be added in the map
3224 * Makes an entry for a videomode in the YCBCR 420 bitmap
3227 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3229 u8 vic = svd_to_vic(svd);
3230 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3232 if (!drm_valid_cea_vic(vic))
3235 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3239 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3242 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3244 for (i = 0; i < len; i++) {
3245 struct drm_display_mode *mode;
3246 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3249 * YCBCR420 capability block contains a bitmap which
3250 * gives the index of CEA modes from CEA VDB, which
3251 * can support YCBCR 420 sampling output also (apart
3252 * from RGB/YCBCR444 etc).
3253 * For example, if the bit 0 in bitmap is set,
3254 * first mode in VDB can support YCBCR420 output too.
3255 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3257 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3258 drm_add_cmdb_modes(connector, db[i]);
3260 drm_mode_probed_add(connector, mode);
3268 struct stereo_mandatory_mode {
3269 int width, height, vrefresh;
3273 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3274 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3275 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3280 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3281 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3282 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3283 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3287 stereo_match_mandatory(const struct drm_display_mode *mode,
3288 const struct stereo_mandatory_mode *stereo_mode)
3290 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3292 return mode->hdisplay == stereo_mode->width &&
3293 mode->vdisplay == stereo_mode->height &&
3294 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3295 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3298 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3300 struct drm_device *dev = connector->dev;
3301 const struct drm_display_mode *mode;
3302 struct list_head stereo_modes;
3305 INIT_LIST_HEAD(&stereo_modes);
3307 list_for_each_entry(mode, &connector->probed_modes, head) {
3308 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3309 const struct stereo_mandatory_mode *mandatory;
3310 struct drm_display_mode *new_mode;
3312 if (!stereo_match_mandatory(mode,
3313 &stereo_mandatory_modes[i]))
3316 mandatory = &stereo_mandatory_modes[i];
3317 new_mode = drm_mode_duplicate(dev, mode);
3321 new_mode->flags |= mandatory->flags;
3322 list_add_tail(&new_mode->head, &stereo_modes);
3327 list_splice_tail(&stereo_modes, &connector->probed_modes);
3332 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3334 struct drm_device *dev = connector->dev;
3335 struct drm_display_mode *newmode;
3337 if (!drm_valid_hdmi_vic(vic)) {
3338 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3342 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3346 drm_mode_probed_add(connector, newmode);
3351 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3352 const u8 *video_db, u8 video_len, u8 video_index)
3354 struct drm_display_mode *newmode;
3357 if (structure & (1 << 0)) {
3358 newmode = drm_display_mode_from_vic_index(connector, video_db,
3362 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3363 drm_mode_probed_add(connector, newmode);
3367 if (structure & (1 << 6)) {
3368 newmode = drm_display_mode_from_vic_index(connector, video_db,
3372 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3373 drm_mode_probed_add(connector, newmode);
3377 if (structure & (1 << 8)) {
3378 newmode = drm_display_mode_from_vic_index(connector, video_db,
3382 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3383 drm_mode_probed_add(connector, newmode);
3392 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3393 * @connector: connector corresponding to the HDMI sink
3394 * @db: start of the CEA vendor specific block
3395 * @len: length of the CEA block payload, ie. one can access up to db[len]
3397 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3398 * also adds the stereo 3d modes when applicable.
3401 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3402 const u8 *video_db, u8 video_len)
3404 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3405 u8 vic_len, hdmi_3d_len = 0;
3412 /* no HDMI_Video_Present */
3413 if (!(db[8] & (1 << 5)))
3416 /* Latency_Fields_Present */
3417 if (db[8] & (1 << 7))
3420 /* I_Latency_Fields_Present */
3421 if (db[8] & (1 << 6))
3424 /* the declared length is not long enough for the 2 first bytes
3425 * of additional video format capabilities */
3426 if (len < (8 + offset + 2))
3431 if (db[8 + offset] & (1 << 7)) {
3432 modes += add_hdmi_mandatory_stereo_modes(connector);
3434 /* 3D_Multi_present */
3435 multi_present = (db[8 + offset] & 0x60) >> 5;
3439 vic_len = db[8 + offset] >> 5;
3440 hdmi_3d_len = db[8 + offset] & 0x1f;
3442 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3445 vic = db[9 + offset + i];
3446 modes += add_hdmi_mode(connector, vic);
3448 offset += 1 + vic_len;
3450 if (multi_present == 1)
3452 else if (multi_present == 2)
3457 if (len < (8 + offset + hdmi_3d_len - 1))
3460 if (hdmi_3d_len < multi_len)
3463 if (multi_present == 1 || multi_present == 2) {
3464 /* 3D_Structure_ALL */
3465 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3467 /* check if 3D_MASK is present */
3468 if (multi_present == 2)
3469 mask = (db[10 + offset] << 8) | db[11 + offset];
3473 for (i = 0; i < 16; i++) {
3474 if (mask & (1 << i))
3475 modes += add_3d_struct_modes(connector,
3482 offset += multi_len;
3484 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3486 struct drm_display_mode *newmode = NULL;
3487 unsigned int newflag = 0;
3488 bool detail_present;
3490 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3492 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3495 /* 2D_VIC_order_X */
3496 vic_index = db[8 + offset + i] >> 4;
3498 /* 3D_Structure_X */
3499 switch (db[8 + offset + i] & 0x0f) {
3501 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3504 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3508 if ((db[9 + offset + i] >> 4) == 1)
3509 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3514 newmode = drm_display_mode_from_vic_index(connector,
3520 newmode->flags |= newflag;
3521 drm_mode_probed_add(connector, newmode);
3535 cea_db_payload_len(const u8 *db)
3537 return db[0] & 0x1f;
3541 cea_db_extended_tag(const u8 *db)
3547 cea_db_tag(const u8 *db)
3553 cea_revision(const u8 *cea)
3559 cea_db_offsets(const u8 *cea, int *start, int *end)
3561 /* Data block offset in CEA extension block */
3566 if (*end < 4 || *end > 127)
3571 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3575 if (cea_db_tag(db) != VENDOR_BLOCK)
3578 if (cea_db_payload_len(db) < 5)
3581 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3583 return hdmi_id == HDMI_IEEE_OUI;
3586 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3590 if (cea_db_tag(db) != VENDOR_BLOCK)
3593 if (cea_db_payload_len(db) < 7)
3596 oui = db[3] << 16 | db[2] << 8 | db[1];
3598 return oui == HDMI_FORUM_IEEE_OUI;
3601 static bool cea_db_is_y420cmdb(const u8 *db)
3603 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3606 if (!cea_db_payload_len(db))
3609 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3615 static bool cea_db_is_y420vdb(const u8 *db)
3617 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3620 if (!cea_db_payload_len(db))
3623 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3629 #define for_each_cea_db(cea, i, start, end) \
3630 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3632 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3635 struct drm_display_info *info = &connector->display_info;
3636 struct drm_hdmi_info *hdmi = &info->hdmi;
3637 u8 map_len = cea_db_payload_len(db) - 1;
3642 /* All CEA modes support ycbcr420 sampling also.*/
3643 hdmi->y420_cmdb_map = U64_MAX;
3644 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3649 * This map indicates which of the existing CEA block modes
3650 * from VDB can support YCBCR420 output too. So if bit=0 is
3651 * set, first mode from VDB can support YCBCR420 output too.
3652 * We will parse and keep this map, before parsing VDB itself
3653 * to avoid going through the same block again and again.
3655 * Spec is not clear about max possible size of this block.
3656 * Clamping max bitmap block size at 8 bytes. Every byte can
3657 * address 8 CEA modes, in this way this map can address
3658 * 8*8 = first 64 SVDs.
3660 if (WARN_ON_ONCE(map_len > 8))
3663 for (count = 0; count < map_len; count++)
3664 map |= (u64)db[2 + count] << (8 * count);
3667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3669 hdmi->y420_cmdb_map = map;
3673 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3675 const u8 *cea = drm_find_cea_extension(edid);
3676 const u8 *db, *hdmi = NULL, *video = NULL;
3677 u8 dbl, hdmi_len, video_len = 0;
3680 if (cea && cea_revision(cea) >= 3) {
3683 if (cea_db_offsets(cea, &start, &end))
3686 for_each_cea_db(cea, i, start, end) {
3688 dbl = cea_db_payload_len(db);
3690 if (cea_db_tag(db) == VIDEO_BLOCK) {
3693 modes += do_cea_modes(connector, video, dbl);
3694 } else if (cea_db_is_hdmi_vsdb(db)) {
3697 } else if (cea_db_is_y420vdb(db)) {
3698 const u8 *vdb420 = &db[2];
3700 /* Add 4:2:0(only) modes present in EDID */
3701 modes += do_y420vdb_modes(connector,
3709 * We parse the HDMI VSDB after having added the cea modes as we will
3710 * be patching their flags when the sink supports stereo 3D.
3713 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3719 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3721 const struct drm_display_mode *cea_mode;
3722 int clock1, clock2, clock;
3727 * allow 5kHz clock difference either way to account for
3728 * the 10kHz clock resolution limit of detailed timings.
3730 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3731 if (drm_valid_cea_vic(vic)) {
3733 cea_mode = &edid_cea_modes[vic];
3734 clock1 = cea_mode->clock;
3735 clock2 = cea_mode_alternate_clock(cea_mode);
3737 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3738 if (drm_valid_hdmi_vic(vic)) {
3740 cea_mode = &edid_4k_modes[vic];
3741 clock1 = cea_mode->clock;
3742 clock2 = hdmi_mode_alternate_clock(cea_mode);
3748 /* pick whichever is closest */
3749 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3754 if (mode->clock == clock)
3757 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3758 type, vic, mode->clock, clock);
3759 mode->clock = clock;
3763 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3765 u8 len = cea_db_payload_len(db);
3768 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3770 connector->latency_present[0] = db[8] >> 7;
3771 connector->latency_present[1] = (db[8] >> 6) & 1;
3774 connector->video_latency[0] = db[9];
3776 connector->audio_latency[0] = db[10];
3778 connector->video_latency[1] = db[11];
3780 connector->audio_latency[1] = db[12];
3782 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3783 "video latency %d %d, "
3784 "audio latency %d %d\n",
3785 connector->latency_present[0],
3786 connector->latency_present[1],
3787 connector->video_latency[0],
3788 connector->video_latency[1],
3789 connector->audio_latency[0],
3790 connector->audio_latency[1]);
3794 monitor_name(struct detailed_timing *t, void *data)
3796 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3797 *(u8 **)data = t->data.other_data.data.str.str;
3800 static int get_monitor_name(struct edid *edid, char name[13])
3802 char *edid_name = NULL;
3808 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3809 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3810 if (edid_name[mnl] == 0x0a)
3813 name[mnl] = edid_name[mnl];
3820 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3821 * @edid: monitor EDID information
3822 * @name: pointer to a character array to hold the name of the monitor
3823 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3826 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3834 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3835 memcpy(name, buf, name_length);
3836 name[name_length] = '\0';
3838 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3841 * drm_edid_to_eld - build ELD from EDID
3842 * @connector: connector corresponding to the HDMI/DP sink
3843 * @edid: EDID to parse
3845 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3846 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3849 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3851 uint8_t *eld = connector->eld;
3854 int total_sad_count = 0;
3858 memset(eld, 0, sizeof(connector->eld));
3860 connector->latency_present[0] = false;
3861 connector->latency_present[1] = false;
3862 connector->video_latency[0] = 0;
3863 connector->audio_latency[0] = 0;
3864 connector->video_latency[1] = 0;
3865 connector->audio_latency[1] = 0;
3870 cea = drm_find_cea_extension(edid);
3872 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3876 mnl = get_monitor_name(edid, eld + 20);
3878 eld[4] = (cea[1] << 5) | mnl;
3879 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3881 eld[0] = 2 << 3; /* ELD version: 2 */
3883 eld[16] = edid->mfg_id[0];
3884 eld[17] = edid->mfg_id[1];
3885 eld[18] = edid->prod_code[0];
3886 eld[19] = edid->prod_code[1];
3888 if (cea_revision(cea) >= 3) {
3891 if (cea_db_offsets(cea, &start, &end)) {
3896 for_each_cea_db(cea, i, start, end) {
3898 dbl = cea_db_payload_len(db);
3900 switch (cea_db_tag(db)) {
3904 /* Audio Data Block, contains SADs */
3905 sad_count = min(dbl / 3, 15 - total_sad_count);
3907 memcpy(eld + 20 + mnl + total_sad_count * 3,
3908 &db[1], sad_count * 3);
3909 total_sad_count += sad_count;
3912 /* Speaker Allocation Data Block */
3917 /* HDMI Vendor-Specific Data Block */
3918 if (cea_db_is_hdmi_vsdb(db))
3919 drm_parse_hdmi_vsdb_audio(connector, db);
3926 eld[5] |= total_sad_count << 4;
3928 eld[DRM_ELD_BASELINE_ELD_LEN] =
3929 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3931 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3932 drm_eld_size(eld), total_sad_count);
3934 EXPORT_SYMBOL(drm_edid_to_eld);
3937 * drm_edid_to_sad - extracts SADs from EDID
3938 * @edid: EDID to parse
3939 * @sads: pointer that will be set to the extracted SADs
3941 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3943 * Note: The returned pointer needs to be freed using kfree().
3945 * Return: The number of found SADs or negative number on error.
3947 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3950 int i, start, end, dbl;
3953 cea = drm_find_cea_extension(edid);
3955 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3959 if (cea_revision(cea) < 3) {
3960 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3964 if (cea_db_offsets(cea, &start, &end)) {
3965 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3969 for_each_cea_db(cea, i, start, end) {
3972 if (cea_db_tag(db) == AUDIO_BLOCK) {
3974 dbl = cea_db_payload_len(db);
3976 count = dbl / 3; /* SAD is 3B */
3977 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3980 for (j = 0; j < count; j++) {
3981 u8 *sad = &db[1 + j * 3];
3983 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3984 (*sads)[j].channels = sad[0] & 0x7;
3985 (*sads)[j].freq = sad[1] & 0x7F;
3986 (*sads)[j].byte2 = sad[2];
3994 EXPORT_SYMBOL(drm_edid_to_sad);
3997 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3998 * @edid: EDID to parse
3999 * @sadb: pointer to the speaker block
4001 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4003 * Note: The returned pointer needs to be freed using kfree().
4005 * Return: The number of found Speaker Allocation Blocks or negative number on
4008 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4011 int i, start, end, dbl;
4014 cea = drm_find_cea_extension(edid);
4016 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4020 if (cea_revision(cea) < 3) {
4021 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4025 if (cea_db_offsets(cea, &start, &end)) {
4026 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4030 for_each_cea_db(cea, i, start, end) {
4031 const u8 *db = &cea[i];
4033 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4034 dbl = cea_db_payload_len(db);
4036 /* Speaker Allocation Data Block */
4038 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4049 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4052 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4053 * @connector: connector associated with the HDMI/DP sink
4054 * @mode: the display mode
4056 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4057 * the sink doesn't support audio or video.
4059 int drm_av_sync_delay(struct drm_connector *connector,
4060 const struct drm_display_mode *mode)
4062 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4065 if (!connector->latency_present[0])
4067 if (!connector->latency_present[1])
4070 a = connector->audio_latency[i];
4071 v = connector->video_latency[i];
4074 * HDMI/DP sink doesn't support audio or video?
4076 if (a == 255 || v == 255)
4080 * Convert raw EDID values to millisecond.
4081 * Treat unknown latency as 0ms.
4084 a = min(2 * (a - 1), 500);
4086 v = min(2 * (v - 1), 500);
4088 return max(v - a, 0);
4090 EXPORT_SYMBOL(drm_av_sync_delay);
4093 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4094 * @edid: monitor EDID information
4096 * Parse the CEA extension according to CEA-861-B.
4098 * Return: True if the monitor is HDMI, false if not or unknown.
4100 bool drm_detect_hdmi_monitor(struct edid *edid)
4104 int start_offset, end_offset;
4106 edid_ext = drm_find_cea_extension(edid);
4110 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4114 * Because HDMI identifier is in Vendor Specific Block,
4115 * search it from all data blocks of CEA extension.
4117 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4118 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4124 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4127 * drm_detect_monitor_audio - check monitor audio capability
4128 * @edid: EDID block to scan
4130 * Monitor should have CEA extension block.
4131 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4132 * audio' only. If there is any audio extension block and supported
4133 * audio format, assume at least 'basic audio' support, even if 'basic
4134 * audio' is not defined in EDID.
4136 * Return: True if the monitor supports audio, false otherwise.
4138 bool drm_detect_monitor_audio(struct edid *edid)
4142 bool has_audio = false;
4143 int start_offset, end_offset;
4145 edid_ext = drm_find_cea_extension(edid);
4149 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4152 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4156 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4159 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4160 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4162 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4163 DRM_DEBUG_KMS("CEA audio format %d\n",
4164 (edid_ext[i + j] >> 3) & 0xf);
4171 EXPORT_SYMBOL(drm_detect_monitor_audio);
4174 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4175 * @edid: EDID block to scan
4177 * Check whether the monitor reports the RGB quantization range selection
4178 * as supported. The AVI infoframe can then be used to inform the monitor
4179 * which quantization range (full or limited) is used.
4181 * Return: True if the RGB quantization range is selectable, false otherwise.
4183 bool drm_rgb_quant_range_selectable(struct edid *edid)
4188 edid_ext = drm_find_cea_extension(edid);
4192 if (cea_db_offsets(edid_ext, &start, &end))
4195 for_each_cea_db(edid_ext, i, start, end) {
4196 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4197 cea_db_payload_len(&edid_ext[i]) == 2 &&
4198 cea_db_extended_tag(&edid_ext[i]) ==
4199 EXT_VIDEO_CAPABILITY_BLOCK) {
4200 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4201 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4207 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4210 * drm_default_rgb_quant_range - default RGB quantization range
4211 * @mode: display mode
4213 * Determine the default RGB quantization range for the mode,
4214 * as specified in CEA-861.
4216 * Return: The default RGB quantization range for the mode
4218 enum hdmi_quantization_range
4219 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4221 /* All CEA modes other than VIC 1 use limited quantization range. */
4222 return drm_match_cea_mode(mode) > 1 ?
4223 HDMI_QUANTIZATION_RANGE_LIMITED :
4224 HDMI_QUANTIZATION_RANGE_FULL;
4226 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4228 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4232 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4234 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4235 hdmi->y420_dc_modes |= dc_mask;
4238 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4241 struct drm_display_info *display = &connector->display_info;
4242 struct drm_hdmi_info *hdmi = &display->hdmi;
4244 if (hf_vsdb[6] & 0x80) {
4245 hdmi->scdc.supported = true;
4246 if (hf_vsdb[6] & 0x40)
4247 hdmi->scdc.read_request = true;
4251 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4252 * And as per the spec, three factors confirm this:
4253 * * Availability of a HF-VSDB block in EDID (check)
4254 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4255 * * SCDC support available (let's check)
4256 * Lets check it out.
4260 /* max clock is 5000 KHz times block value */
4261 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4262 struct drm_scdc *scdc = &hdmi->scdc;
4264 if (max_tmds_clock > 340000) {
4265 display->max_tmds_clock = max_tmds_clock;
4266 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4267 display->max_tmds_clock);
4270 if (scdc->supported) {
4271 scdc->scrambling.supported = true;
4273 /* Few sinks support scrambling for cloks < 340M */
4274 if ((hf_vsdb[6] & 0x8))
4275 scdc->scrambling.low_rates = true;
4279 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4282 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4285 struct drm_display_info *info = &connector->display_info;
4286 unsigned int dc_bpc = 0;
4288 /* HDMI supports at least 8 bpc */
4291 if (cea_db_payload_len(hdmi) < 6)
4294 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4296 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4297 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4301 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4303 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4304 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4308 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4310 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4311 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4316 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4321 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4322 connector->name, dc_bpc);
4326 * Deep color support mandates RGB444 support for all video
4327 * modes and forbids YCRCB422 support for all video modes per
4330 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4332 /* YCRCB444 is optional according to spec. */
4333 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4334 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4335 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4340 * Spec says that if any deep color mode is supported at all,
4341 * then deep color 36 bit must be supported.
4343 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4344 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4350 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4352 struct drm_display_info *info = &connector->display_info;
4353 u8 len = cea_db_payload_len(db);
4356 info->dvi_dual = db[6] & 1;
4358 info->max_tmds_clock = db[7] * 5000;
4360 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4361 "max TMDS clock %d kHz\n",
4363 info->max_tmds_clock);
4365 drm_parse_hdmi_deep_color_info(connector, db);
4368 static void drm_parse_cea_ext(struct drm_connector *connector,
4369 const struct edid *edid)
4371 struct drm_display_info *info = &connector->display_info;
4375 edid_ext = drm_find_cea_extension(edid);
4379 info->cea_rev = edid_ext[1];
4381 /* The existence of a CEA block should imply RGB support */
4382 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4383 if (edid_ext[3] & EDID_CEA_YCRCB444)
4384 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4385 if (edid_ext[3] & EDID_CEA_YCRCB422)
4386 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4388 if (cea_db_offsets(edid_ext, &start, &end))
4391 for_each_cea_db(edid_ext, i, start, end) {
4392 const u8 *db = &edid_ext[i];
4394 if (cea_db_is_hdmi_vsdb(db))
4395 drm_parse_hdmi_vsdb_video(connector, db);
4396 if (cea_db_is_hdmi_forum_vsdb(db))
4397 drm_parse_hdmi_forum_vsdb(connector, db);
4398 if (cea_db_is_y420cmdb(db))
4399 drm_parse_y420cmdb_bitmap(connector, db);
4403 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4404 * all of the values which would have been set from EDID
4407 drm_reset_display_info(struct drm_connector *connector)
4409 struct drm_display_info *info = &connector->display_info;
4412 info->height_mm = 0;
4415 info->color_formats = 0;
4417 info->max_tmds_clock = 0;
4418 info->dvi_dual = false;
4420 info->non_desktop = 0;
4422 EXPORT_SYMBOL_GPL(drm_reset_display_info);
4424 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4426 struct drm_display_info *info = &connector->display_info;
4428 u32 quirks = edid_get_quirks(edid);
4430 info->width_mm = edid->width_cm * 10;
4431 info->height_mm = edid->height_cm * 10;
4433 /* driver figures it out in this case */
4435 info->color_formats = 0;
4437 info->max_tmds_clock = 0;
4438 info->dvi_dual = false;
4440 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4442 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4444 if (edid->revision < 3)
4447 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4450 drm_parse_cea_ext(connector, edid);
4453 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4455 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4456 * tells us to assume 8 bpc color depth if the EDID doesn't have
4457 * extensions which tell otherwise.
4459 if ((info->bpc == 0) && (edid->revision < 4) &&
4460 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4462 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4463 connector->name, info->bpc);
4466 /* Only defined for 1.4 with digital displays */
4467 if (edid->revision < 4)
4470 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4471 case DRM_EDID_DIGITAL_DEPTH_6:
4474 case DRM_EDID_DIGITAL_DEPTH_8:
4477 case DRM_EDID_DIGITAL_DEPTH_10:
4480 case DRM_EDID_DIGITAL_DEPTH_12:
4483 case DRM_EDID_DIGITAL_DEPTH_14:
4486 case DRM_EDID_DIGITAL_DEPTH_16:
4489 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4495 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4496 connector->name, info->bpc);
4498 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4499 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4500 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4501 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4502 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4505 EXPORT_SYMBOL_GPL(drm_add_display_info);
4507 static int validate_displayid(u8 *displayid, int length, int idx)
4511 struct displayid_hdr *base;
4513 base = (struct displayid_hdr *)&displayid[idx];
4515 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4516 base->rev, base->bytes, base->prod_id, base->ext_count);
4518 if (base->bytes + 5 > length - idx)
4520 for (i = idx; i <= base->bytes + 5; i++) {
4521 csum += displayid[i];
4524 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4530 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4531 struct displayid_detailed_timings_1 *timings)
4533 struct drm_display_mode *mode;
4534 unsigned pixel_clock = (timings->pixel_clock[0] |
4535 (timings->pixel_clock[1] << 8) |
4536 (timings->pixel_clock[2] << 16));
4537 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4538 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4539 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4540 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4541 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4542 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4543 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4544 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4545 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4546 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4547 mode = drm_mode_create(dev);
4551 mode->clock = pixel_clock * 10;
4552 mode->hdisplay = hactive;
4553 mode->hsync_start = mode->hdisplay + hsync;
4554 mode->hsync_end = mode->hsync_start + hsync_width;
4555 mode->htotal = mode->hdisplay + hblank;
4557 mode->vdisplay = vactive;
4558 mode->vsync_start = mode->vdisplay + vsync;
4559 mode->vsync_end = mode->vsync_start + vsync_width;
4560 mode->vtotal = mode->vdisplay + vblank;
4563 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4564 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4565 mode->type = DRM_MODE_TYPE_DRIVER;
4567 if (timings->flags & 0x80)
4568 mode->type |= DRM_MODE_TYPE_PREFERRED;
4569 mode->vrefresh = drm_mode_vrefresh(mode);
4570 drm_mode_set_name(mode);
4575 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4576 struct displayid_block *block)
4578 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4581 struct drm_display_mode *newmode;
4583 /* blocks must be multiple of 20 bytes length */
4584 if (block->num_bytes % 20)
4587 num_timings = block->num_bytes / 20;
4588 for (i = 0; i < num_timings; i++) {
4589 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4591 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4595 drm_mode_probed_add(connector, newmode);
4601 static int add_displayid_detailed_modes(struct drm_connector *connector,
4607 int length = EDID_LENGTH;
4608 struct displayid_block *block;
4611 displayid = drm_find_displayid_extension(edid);
4615 ret = validate_displayid(displayid, length, idx);
4619 idx += sizeof(struct displayid_hdr);
4620 while (block = (struct displayid_block *)&displayid[idx],
4621 idx + sizeof(struct displayid_block) <= length &&
4622 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4623 block->num_bytes > 0) {
4624 idx += block->num_bytes + sizeof(struct displayid_block);
4625 switch (block->tag) {
4626 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4627 num_modes += add_displayid_detailed_1_modes(connector, block);
4635 * drm_add_edid_modes - add modes from EDID data, if available
4636 * @connector: connector we're probing
4639 * Add the specified modes to the connector's mode list. Also fills out the
4640 * &drm_display_info structure in @connector with any information which can be
4641 * derived from the edid.
4643 * Return: The number of modes added or 0 if we couldn't find any.
4645 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4653 if (!drm_edid_is_valid(edid)) {
4654 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4660 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4661 * To avoid multiple parsing of same block, lets parse that map
4662 * from sink info, before parsing CEA modes.
4664 quirks = drm_add_display_info(connector, edid);
4667 * EDID spec says modes should be preferred in this order:
4668 * - preferred detailed mode
4669 * - other detailed modes from base block
4670 * - detailed modes from extension blocks
4671 * - CVT 3-byte code modes
4672 * - standard timing codes
4673 * - established timing codes
4674 * - modes inferred from GTF or CVT range information
4676 * We get this pretty much right.
4678 * XXX order for additional mode types in extension blocks?
4680 num_modes += add_detailed_modes(connector, edid, quirks);
4681 num_modes += add_cvt_modes(connector, edid);
4682 num_modes += add_standard_modes(connector, edid);
4683 num_modes += add_established_modes(connector, edid);
4684 num_modes += add_cea_modes(connector, edid);
4685 num_modes += add_alternate_cea_modes(connector, edid);
4686 num_modes += add_displayid_detailed_modes(connector, edid);
4687 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4688 num_modes += add_inferred_modes(connector, edid);
4690 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4691 edid_fixup_preferred(connector, quirks);
4693 if (quirks & EDID_QUIRK_FORCE_6BPC)
4694 connector->display_info.bpc = 6;
4696 if (quirks & EDID_QUIRK_FORCE_8BPC)
4697 connector->display_info.bpc = 8;
4699 if (quirks & EDID_QUIRK_FORCE_10BPC)
4700 connector->display_info.bpc = 10;
4702 if (quirks & EDID_QUIRK_FORCE_12BPC)
4703 connector->display_info.bpc = 12;
4707 EXPORT_SYMBOL(drm_add_edid_modes);
4710 * drm_add_modes_noedid - add modes for the connectors without EDID
4711 * @connector: connector we're probing
4712 * @hdisplay: the horizontal display limit
4713 * @vdisplay: the vertical display limit
4715 * Add the specified modes to the connector's mode list. Only when the
4716 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4718 * Return: The number of modes added or 0 if we couldn't find any.
4720 int drm_add_modes_noedid(struct drm_connector *connector,
4721 int hdisplay, int vdisplay)
4723 int i, count, num_modes = 0;
4724 struct drm_display_mode *mode;
4725 struct drm_device *dev = connector->dev;
4727 count = ARRAY_SIZE(drm_dmt_modes);
4733 for (i = 0; i < count; i++) {
4734 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4735 if (hdisplay && vdisplay) {
4737 * Only when two are valid, they will be used to check
4738 * whether the mode should be added to the mode list of
4741 if (ptr->hdisplay > hdisplay ||
4742 ptr->vdisplay > vdisplay)
4745 if (drm_mode_vrefresh(ptr) > 61)
4747 mode = drm_mode_duplicate(dev, ptr);
4749 drm_mode_probed_add(connector, mode);
4755 EXPORT_SYMBOL(drm_add_modes_noedid);
4758 * drm_set_preferred_mode - Sets the preferred mode of a connector
4759 * @connector: connector whose mode list should be processed
4760 * @hpref: horizontal resolution of preferred mode
4761 * @vpref: vertical resolution of preferred mode
4763 * Marks a mode as preferred if it matches the resolution specified by @hpref
4766 void drm_set_preferred_mode(struct drm_connector *connector,
4767 int hpref, int vpref)
4769 struct drm_display_mode *mode;
4771 list_for_each_entry(mode, &connector->probed_modes, head) {
4772 if (mode->hdisplay == hpref &&
4773 mode->vdisplay == vpref)
4774 mode->type |= DRM_MODE_TYPE_PREFERRED;
4777 EXPORT_SYMBOL(drm_set_preferred_mode);
4780 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4781 * data from a DRM display mode
4782 * @frame: HDMI AVI infoframe
4783 * @mode: DRM display mode
4784 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4786 * Return: 0 on success or a negative error code on failure.
4789 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4790 const struct drm_display_mode *mode,
4795 if (!frame || !mode)
4798 err = hdmi_avi_infoframe_init(frame);
4802 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4803 frame->pixel_repeat = 1;
4805 frame->video_code = drm_match_cea_mode(mode);
4808 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4809 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4810 * have to make sure we dont break HDMI 1.4 sinks.
4812 if (!is_hdmi2_sink && frame->video_code > 64)
4813 frame->video_code = 0;
4816 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4817 * we should send its VIC in vendor infoframes, else send the
4818 * VIC in AVI infoframes. Lets check if this mode is present in
4819 * HDMI 1.4b 4K modes
4821 if (frame->video_code) {
4822 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4823 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4825 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4826 frame->video_code = 0;
4829 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4832 * Populate picture aspect ratio from either
4833 * user input (if specified) or from the CEA mode list.
4835 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4836 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4837 frame->picture_aspect = mode->picture_aspect_ratio;
4838 else if (frame->video_code > 0)
4839 frame->picture_aspect = drm_get_cea_aspect_ratio(
4842 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4843 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4847 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4850 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4851 * quantization range information
4852 * @frame: HDMI AVI infoframe
4853 * @mode: DRM display mode
4854 * @rgb_quant_range: RGB quantization range (Q)
4855 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4858 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4859 const struct drm_display_mode *mode,
4860 enum hdmi_quantization_range rgb_quant_range,
4861 bool rgb_quant_range_selectable,
4866 * "A Source shall not send a non-zero Q value that does not correspond
4867 * to the default RGB Quantization Range for the transmitted Picture
4868 * unless the Sink indicates support for the Q bit in a Video
4869 * Capabilities Data Block."
4871 * HDMI 2.0 recommends sending non-zero Q when it does match the
4872 * default RGB quantization range for the mode, even when QS=0.
4874 if (rgb_quant_range_selectable ||
4875 rgb_quant_range == drm_default_rgb_quant_range(mode))
4876 frame->quantization_range = rgb_quant_range;
4878 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4882 * "When transmitting any RGB colorimetry, the Source should set the
4883 * YQ-field to match the RGB Quantization Range being transmitted
4884 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4885 * set YQ=1) and the Sink shall ignore the YQ-field."
4887 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4888 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4889 * good way to tell which version of CEA-861 the sink supports, so
4890 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4893 if (!is_hdmi2_sink ||
4894 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4895 frame->ycc_quantization_range =
4896 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4898 frame->ycc_quantization_range =
4899 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4901 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4903 static enum hdmi_3d_structure
4904 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4906 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4909 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4910 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4911 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4912 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4913 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4914 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4915 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4916 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4917 case DRM_MODE_FLAG_3D_L_DEPTH:
4918 return HDMI_3D_STRUCTURE_L_DEPTH;
4919 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4920 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4921 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4922 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4923 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4924 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4926 return HDMI_3D_STRUCTURE_INVALID;
4931 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4932 * data from a DRM display mode
4933 * @frame: HDMI vendor infoframe
4934 * @mode: DRM display mode
4936 * Note that there's is a need to send HDMI vendor infoframes only when using a
4937 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4938 * function will return -EINVAL, error that can be safely ignored.
4940 * Return: 0 on success or a negative error code on failure.
4943 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4944 const struct drm_display_mode *mode)
4950 if (!frame || !mode)
4953 vic = drm_match_hdmi_mode(mode);
4954 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4956 if (!vic && !s3d_flags)
4959 if (vic && s3d_flags)
4962 err = hdmi_vendor_infoframe_init(frame);
4969 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4973 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4975 static int drm_parse_tiled_block(struct drm_connector *connector,
4976 struct displayid_block *block)
4978 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4980 u8 tile_v_loc, tile_h_loc;
4981 u8 num_v_tile, num_h_tile;
4982 struct drm_tile_group *tg;
4984 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4985 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4987 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4988 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4989 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4990 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4992 connector->has_tile = true;
4993 if (tile->tile_cap & 0x80)
4994 connector->tile_is_single_monitor = true;
4996 connector->num_h_tile = num_h_tile + 1;
4997 connector->num_v_tile = num_v_tile + 1;
4998 connector->tile_h_loc = tile_h_loc;
4999 connector->tile_v_loc = tile_v_loc;
5000 connector->tile_h_size = w + 1;
5001 connector->tile_v_size = h + 1;
5003 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5004 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5005 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5006 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5007 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5009 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5011 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5016 if (connector->tile_group != tg) {
5017 /* if we haven't got a pointer,
5018 take the reference, drop ref to old tile group */
5019 if (connector->tile_group) {
5020 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5022 connector->tile_group = tg;
5024 /* if same tile group, then release the ref we just took. */
5025 drm_mode_put_tile_group(connector->dev, tg);
5029 static int drm_parse_display_id(struct drm_connector *connector,
5030 u8 *displayid, int length,
5031 bool is_edid_extension)
5033 /* if this is an EDID extension the first byte will be 0x70 */
5035 struct displayid_block *block;
5038 if (is_edid_extension)
5041 ret = validate_displayid(displayid, length, idx);
5045 idx += sizeof(struct displayid_hdr);
5046 while (block = (struct displayid_block *)&displayid[idx],
5047 idx + sizeof(struct displayid_block) <= length &&
5048 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5049 block->num_bytes > 0) {
5050 idx += block->num_bytes + sizeof(struct displayid_block);
5051 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5052 block->tag, block->rev, block->num_bytes);
5054 switch (block->tag) {
5055 case DATA_BLOCK_TILED_DISPLAY:
5056 ret = drm_parse_tiled_block(connector, block);
5060 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5061 /* handled in mode gathering code. */
5064 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5071 static void drm_get_displayid(struct drm_connector *connector,
5074 void *displayid = NULL;
5076 connector->has_tile = false;
5077 displayid = drm_find_displayid_extension(edid);
5079 /* drop reference to any tile group we had */
5083 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5086 if (!connector->has_tile)
5090 if (connector->tile_group) {
5091 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5092 connector->tile_group = NULL;
git.samba.org / sfrench / cifs-2.6.git / blob