treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
[sfrench/cifs-2.6.git] / drivers / gpu / drm / bridge / tc358767.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * tc358767 eDP bridge driver
4  *
5  * Copyright (C) 2016 CogentEmbedded Inc
6  * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
7  *
8  * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
9  *
10  * Copyright (C) 2016 Zodiac Inflight Innovations
11  *
12  * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
13  *
14  * Copyright (C) 2012 Texas Instruments
15  * Author: Rob Clark <robdclark@gmail.com>
16  */
17
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_helper.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_probe_helper.h>
33
34 /* Registers */
35
36 /* Display Parallel Interface */
37 #define DPIPXLFMT               0x0440
38 #define VS_POL_ACTIVE_LOW               (1 << 10)
39 #define HS_POL_ACTIVE_LOW               (1 << 9)
40 #define DE_POL_ACTIVE_HIGH              (0 << 8)
41 #define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
42 #define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
43 #define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
44 #define DPI_BPP_RGB888                  (0 << 0)
45 #define DPI_BPP_RGB666                  (1 << 0)
46 #define DPI_BPP_RGB565                  (2 << 0)
47
48 /* Video Path */
49 #define VPCTRL0                 0x0450
50 #define OPXLFMT_RGB666                  (0 << 8)
51 #define OPXLFMT_RGB888                  (1 << 8)
52 #define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
53 #define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
54 #define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
55 #define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
56 #define HTIM01                  0x0454
57 #define HTIM02                  0x0458
58 #define VTIM01                  0x045c
59 #define VTIM02                  0x0460
60 #define VFUEN0                  0x0464
61 #define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
62
63 /* System */
64 #define TC_IDREG                0x0500
65 #define SYSCTRL                 0x0510
66 #define DP0_AUDSRC_NO_INPUT             (0 << 3)
67 #define DP0_AUDSRC_I2S_RX               (1 << 3)
68 #define DP0_VIDSRC_NO_INPUT             (0 << 0)
69 #define DP0_VIDSRC_DSI_RX               (1 << 0)
70 #define DP0_VIDSRC_DPI_RX               (2 << 0)
71 #define DP0_VIDSRC_COLOR_BAR            (3 << 0)
72
73 /* Control */
74 #define DP0CTL                  0x0600
75 #define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
76 #define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
77 #define VID_EN                          BIT(1)   /* Video transmission enable */
78 #define DP_EN                           BIT(0)   /* Enable DPTX function */
79
80 /* Clocks */
81 #define DP0_VIDMNGEN0           0x0610
82 #define DP0_VIDMNGEN1           0x0614
83 #define DP0_VMNGENSTATUS        0x0618
84
85 /* Main Channel */
86 #define DP0_SECSAMPLE           0x0640
87 #define DP0_VIDSYNCDELAY        0x0644
88 #define DP0_TOTALVAL            0x0648
89 #define DP0_STARTVAL            0x064c
90 #define DP0_ACTIVEVAL           0x0650
91 #define DP0_SYNCVAL             0x0654
92 #define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
93 #define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
94 #define DP0_MISC                0x0658
95 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
96 #define BPC_6                           (0 << 5)
97 #define BPC_8                           (1 << 5)
98
99 /* AUX channel */
100 #define DP0_AUXCFG0             0x0660
101 #define DP0_AUXCFG1             0x0664
102 #define AUX_RX_FILTER_EN                BIT(16)
103
104 #define DP0_AUXADDR             0x0668
105 #define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
106 #define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
107 #define DP0_AUXSTATUS           0x068c
108 #define AUX_STATUS_MASK                 0xf0
109 #define AUX_STATUS_SHIFT                4
110 #define AUX_TIMEOUT                     BIT(1)
111 #define AUX_BUSY                        BIT(0)
112 #define DP0_AUXI2CADR           0x0698
113
114 /* Link Training */
115 #define DP0_SRCCTRL             0x06a0
116 #define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
117 #define DP0_SRCCTRL_EN810B              BIT(12)
118 #define DP0_SRCCTRL_NOTP                (0 << 8)
119 #define DP0_SRCCTRL_TP1                 (1 << 8)
120 #define DP0_SRCCTRL_TP2                 (2 << 8)
121 #define DP0_SRCCTRL_LANESKEW            BIT(7)
122 #define DP0_SRCCTRL_SSCG                BIT(3)
123 #define DP0_SRCCTRL_LANES_1             (0 << 2)
124 #define DP0_SRCCTRL_LANES_2             (1 << 2)
125 #define DP0_SRCCTRL_BW27                (1 << 1)
126 #define DP0_SRCCTRL_BW162               (0 << 1)
127 #define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
128 #define DP0_LTSTAT              0x06d0
129 #define LT_LOOPDONE                     BIT(13)
130 #define LT_STATUS_MASK                  (0x1f << 8)
131 #define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
132 #define LT_INTERLANE_ALIGN_DONE         BIT(3)
133 #define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
134 #define DP0_SNKLTCHGREQ         0x06d4
135 #define DP0_LTLOOPCTRL          0x06d8
136 #define DP0_SNKLTCTRL           0x06e4
137
138 #define DP1_SRCCTRL             0x07a0
139
140 /* PHY */
141 #define DP_PHY_CTRL             0x0800
142 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
143 #define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
144 #define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
145 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
146 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
147 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
148 #define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
149 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
150 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
151
152 /* PLL */
153 #define DP0_PLLCTRL             0x0900
154 #define DP1_PLLCTRL             0x0904  /* not defined in DS */
155 #define PXL_PLLCTRL             0x0908
156 #define PLLUPDATE                       BIT(2)
157 #define PLLBYP                          BIT(1)
158 #define PLLEN                           BIT(0)
159 #define PXL_PLLPARAM            0x0914
160 #define IN_SEL_REFCLK                   (0 << 14)
161 #define SYS_PLLPARAM            0x0918
162 #define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
163 #define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
164 #define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
165 #define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
166 #define SYSCLK_SEL_LSCLK                (0 << 4)
167 #define LSCLK_DIV_1                     (0 << 0)
168 #define LSCLK_DIV_2                     (1 << 0)
169
170 /* Test & Debug */
171 #define TSTCTL                  0x0a00
172 #define PLL_DBG                 0x0a04
173
174 static bool tc_test_pattern;
175 module_param_named(test, tc_test_pattern, bool, 0644);
176
177 struct tc_edp_link {
178         struct drm_dp_link      base;
179         u8                      assr;
180         int                     scrambler_dis;
181         int                     spread;
182         int                     coding8b10b;
183         u8                      swing;
184         u8                      preemp;
185 };
186
187 struct tc_data {
188         struct device           *dev;
189         struct regmap           *regmap;
190         struct drm_dp_aux       aux;
191
192         struct drm_bridge       bridge;
193         struct drm_connector    connector;
194         struct drm_panel        *panel;
195
196         /* link settings */
197         struct tc_edp_link      link;
198
199         /* display edid */
200         struct edid             *edid;
201         /* current mode */
202         const struct drm_display_mode   *mode;
203
204         u32                     rev;
205         u8                      assr;
206
207         struct gpio_desc        *sd_gpio;
208         struct gpio_desc        *reset_gpio;
209         struct clk              *refclk;
210 };
211
212 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
213 {
214         return container_of(a, struct tc_data, aux);
215 }
216
217 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
218 {
219         return container_of(b, struct tc_data, bridge);
220 }
221
222 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
223 {
224         return container_of(c, struct tc_data, connector);
225 }
226
227 /* Simple macros to avoid repeated error checks */
228 #define tc_write(reg, var)                                      \
229         do {                                                    \
230                 ret = regmap_write(tc->regmap, reg, var);       \
231                 if (ret)                                        \
232                         goto err;                               \
233         } while (0)
234 #define tc_read(reg, var)                                       \
235         do {                                                    \
236                 ret = regmap_read(tc->regmap, reg, var);        \
237                 if (ret)                                        \
238                         goto err;                               \
239         } while (0)
240
241 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
242                                   unsigned int cond_mask,
243                                   unsigned int cond_value,
244                                   unsigned long sleep_us, u64 timeout_us)
245 {
246         ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
247         unsigned int val;
248         int ret;
249
250         for (;;) {
251                 ret = regmap_read(map, addr, &val);
252                 if (ret)
253                         break;
254                 if ((val & cond_mask) == cond_value)
255                         break;
256                 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
257                         ret = regmap_read(map, addr, &val);
258                         break;
259                 }
260                 if (sleep_us)
261                         usleep_range((sleep_us >> 2) + 1, sleep_us);
262         }
263         return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
264 }
265
266 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
267 {
268         return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
269                                1000, 1000 * timeout_ms);
270 }
271
272 static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
273 {
274         int ret;
275         u32 value;
276
277         ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
278         if (ret < 0)
279                 return ret;
280         if (value & AUX_BUSY) {
281                 if (value & AUX_TIMEOUT) {
282                         dev_err(tc->dev, "i2c access timeout!\n");
283                         return -ETIMEDOUT;
284                 }
285                 return -EBUSY;
286         }
287
288         *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
289         return 0;
290 }
291
292 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
293                                struct drm_dp_aux_msg *msg)
294 {
295         struct tc_data *tc = aux_to_tc(aux);
296         size_t size = min_t(size_t, 8, msg->size);
297         u8 request = msg->request & ~DP_AUX_I2C_MOT;
298         u8 *buf = msg->buffer;
299         u32 tmp = 0;
300         int i = 0;
301         int ret;
302
303         if (size == 0)
304                 return 0;
305
306         ret = tc_aux_wait_busy(tc, 100);
307         if (ret)
308                 goto err;
309
310         if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
311                 /* Store data */
312                 while (i < size) {
313                         if (request == DP_AUX_NATIVE_WRITE)
314                                 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
315                         else
316                                 tmp = (tmp << 8) | buf[i];
317                         i++;
318                         if (((i % 4) == 0) || (i == size)) {
319                                 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
320                                 tmp = 0;
321                         }
322                 }
323         } else if (request != DP_AUX_I2C_READ &&
324                    request != DP_AUX_NATIVE_READ) {
325                 return -EINVAL;
326         }
327
328         /* Store address */
329         tc_write(DP0_AUXADDR, msg->address);
330         /* Start transfer */
331         tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
332
333         ret = tc_aux_wait_busy(tc, 100);
334         if (ret)
335                 goto err;
336
337         ret = tc_aux_get_status(tc, &msg->reply);
338         if (ret)
339                 goto err;
340
341         if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
342                 /* Read data */
343                 while (i < size) {
344                         if ((i % 4) == 0)
345                                 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
346                         buf[i] = tmp & 0xff;
347                         tmp = tmp >> 8;
348                         i++;
349                 }
350         }
351
352         return size;
353 err:
354         return ret;
355 }
356
357 static const char * const training_pattern1_errors[] = {
358         "No errors",
359         "Aux write error",
360         "Aux read error",
361         "Max voltage reached error",
362         "Loop counter expired error",
363         "res", "res", "res"
364 };
365
366 static const char * const training_pattern2_errors[] = {
367         "No errors",
368         "Aux write error",
369         "Aux read error",
370         "Clock recovery failed error",
371         "Loop counter expired error",
372         "res", "res", "res"
373 };
374
375 static u32 tc_srcctrl(struct tc_data *tc)
376 {
377         /*
378          * No training pattern, skew lane 1 data by two LSCLK cycles with
379          * respect to lane 0 data, AutoCorrect Mode = 0
380          */
381         u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
382
383         if (tc->link.scrambler_dis)
384                 reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
385         if (tc->link.coding8b10b)
386                 /* Enable 8/10B Encoder (TxData[19:16] not used) */
387                 reg |= DP0_SRCCTRL_EN810B;
388         if (tc->link.spread)
389                 reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
390         if (tc->link.base.num_lanes == 2)
391                 reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
392         if (tc->link.base.rate != 162000)
393                 reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
394         return reg;
395 }
396
397 static void tc_wait_pll_lock(struct tc_data *tc)
398 {
399         /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
400         usleep_range(3000, 6000);
401 }
402
403 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
404 {
405         int ret;
406         int i_pre, best_pre = 1;
407         int i_post, best_post = 1;
408         int div, best_div = 1;
409         int mul, best_mul = 1;
410         int delta, best_delta;
411         int ext_div[] = {1, 2, 3, 5, 7};
412         int best_pixelclock = 0;
413         int vco_hi = 0;
414
415         dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
416                 refclk);
417         best_delta = pixelclock;
418         /* Loop over all possible ext_divs, skipping invalid configurations */
419         for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
420                 /*
421                  * refclk / ext_pre_div should be in the 1 to 200 MHz range.
422                  * We don't allow any refclk > 200 MHz, only check lower bounds.
423                  */
424                 if (refclk / ext_div[i_pre] < 1000000)
425                         continue;
426                 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
427                         for (div = 1; div <= 16; div++) {
428                                 u32 clk;
429                                 u64 tmp;
430
431                                 tmp = pixelclock * ext_div[i_pre] *
432                                       ext_div[i_post] * div;
433                                 do_div(tmp, refclk);
434                                 mul = tmp;
435
436                                 /* Check limits */
437                                 if ((mul < 1) || (mul > 128))
438                                         continue;
439
440                                 clk = (refclk / ext_div[i_pre] / div) * mul;
441                                 /*
442                                  * refclk * mul / (ext_pre_div * pre_div)
443                                  * should be in the 150 to 650 MHz range
444                                  */
445                                 if ((clk > 650000000) || (clk < 150000000))
446                                         continue;
447
448                                 clk = clk / ext_div[i_post];
449                                 delta = clk - pixelclock;
450
451                                 if (abs(delta) < abs(best_delta)) {
452                                         best_pre = i_pre;
453                                         best_post = i_post;
454                                         best_div = div;
455                                         best_mul = mul;
456                                         best_delta = delta;
457                                         best_pixelclock = clk;
458                                 }
459                         }
460                 }
461         }
462         if (best_pixelclock == 0) {
463                 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
464                         pixelclock);
465                 return -EINVAL;
466         }
467
468         dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
469                 best_delta);
470         dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
471                 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
472
473         /* if VCO >= 300 MHz */
474         if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
475                 vco_hi = 1;
476         /* see DS */
477         if (best_div == 16)
478                 best_div = 0;
479         if (best_mul == 128)
480                 best_mul = 0;
481
482         /* Power up PLL and switch to bypass */
483         tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
484
485         tc_write(PXL_PLLPARAM,
486                  (vco_hi << 24) |               /* For PLL VCO >= 300 MHz = 1 */
487                  (ext_div[best_pre] << 20) |    /* External Pre-divider */
488                  (ext_div[best_post] << 16) |   /* External Post-divider */
489                  IN_SEL_REFCLK |                /* Use RefClk as PLL input */
490                  (best_div << 8) |              /* Divider for PLL RefClk */
491                  (best_mul << 0));              /* Multiplier for PLL */
492
493         /* Force PLL parameter update and disable bypass */
494         tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
495
496         tc_wait_pll_lock(tc);
497
498         return 0;
499 err:
500         return ret;
501 }
502
503 static int tc_pxl_pll_dis(struct tc_data *tc)
504 {
505         /* Enable PLL bypass, power down PLL */
506         return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
507 }
508
509 static int tc_stream_clock_calc(struct tc_data *tc)
510 {
511         int ret;
512         /*
513          * If the Stream clock and Link Symbol clock are
514          * asynchronous with each other, the value of M changes over
515          * time. This way of generating link clock and stream
516          * clock is called Asynchronous Clock mode. The value M
517          * must change while the value N stays constant. The
518          * value of N in this Asynchronous Clock mode must be set
519          * to 2^15 or 32,768.
520          *
521          * LSCLK = 1/10 of high speed link clock
522          *
523          * f_STRMCLK = M/N * f_LSCLK
524          * M/N = f_STRMCLK / f_LSCLK
525          *
526          */
527         tc_write(DP0_VIDMNGEN1, 32768);
528
529         return 0;
530 err:
531         return ret;
532 }
533
534 static int tc_aux_link_setup(struct tc_data *tc)
535 {
536         unsigned long rate;
537         u32 value;
538         int ret;
539         u32 dp_phy_ctrl;
540
541         rate = clk_get_rate(tc->refclk);
542         switch (rate) {
543         case 38400000:
544                 value = REF_FREQ_38M4;
545                 break;
546         case 26000000:
547                 value = REF_FREQ_26M;
548                 break;
549         case 19200000:
550                 value = REF_FREQ_19M2;
551                 break;
552         case 13000000:
553                 value = REF_FREQ_13M;
554                 break;
555         default:
556                 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
557                 return -EINVAL;
558         }
559
560         /* Setup DP-PHY / PLL */
561         value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
562         tc_write(SYS_PLLPARAM, value);
563
564         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
565         if (tc->link.base.num_lanes == 2)
566                 dp_phy_ctrl |= PHY_2LANE;
567         tc_write(DP_PHY_CTRL, dp_phy_ctrl);
568
569         /*
570          * Initially PLLs are in bypass. Force PLL parameter update,
571          * disable PLL bypass, enable PLL
572          */
573         tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
574         tc_wait_pll_lock(tc);
575
576         tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
577         tc_wait_pll_lock(tc);
578
579         ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
580                               1000);
581         if (ret == -ETIMEDOUT) {
582                 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
583                 return ret;
584         } else if (ret)
585                 goto err;
586
587         /* Setup AUX link */
588         tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
589                  (0x06 << 8) |  /* Aux Bit Period Calculator Threshold */
590                  (0x3f << 0));  /* Aux Response Timeout Timer */
591
592         return 0;
593 err:
594         dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
595         return ret;
596 }
597
598 static int tc_get_display_props(struct tc_data *tc)
599 {
600         int ret;
601         /* temp buffer */
602         u8 tmp[8];
603
604         /* Read DP Rx Link Capability */
605         ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
606         if (ret < 0)
607                 goto err_dpcd_read;
608         if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
609                 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
610                 tc->link.base.rate = 270000;
611         }
612
613         if (tc->link.base.num_lanes > 2) {
614                 dev_dbg(tc->dev, "Falling to 2 lanes\n");
615                 tc->link.base.num_lanes = 2;
616         }
617
618         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
619         if (ret < 0)
620                 goto err_dpcd_read;
621         tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
622
623         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
624         if (ret < 0)
625                 goto err_dpcd_read;
626         tc->link.coding8b10b = tmp[0] & BIT(0);
627         tc->link.scrambler_dis = 0;
628         /* read assr */
629         ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
630         if (ret < 0)
631                 goto err_dpcd_read;
632         tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
633
634         dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
635                 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
636                 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
637                 tc->link.base.num_lanes,
638                 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
639                 "enhanced" : "non-enhanced");
640         dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
641         dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
642                 tc->link.assr, tc->assr);
643
644         return 0;
645
646 err_dpcd_read:
647         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
648         return ret;
649 }
650
651 static int tc_set_video_mode(struct tc_data *tc,
652                              const struct drm_display_mode *mode)
653 {
654         int ret;
655         int vid_sync_dly;
656         int max_tu_symbol;
657
658         int left_margin = mode->htotal - mode->hsync_end;
659         int right_margin = mode->hsync_start - mode->hdisplay;
660         int hsync_len = mode->hsync_end - mode->hsync_start;
661         int upper_margin = mode->vtotal - mode->vsync_end;
662         int lower_margin = mode->vsync_start - mode->vdisplay;
663         int vsync_len = mode->vsync_end - mode->vsync_start;
664
665         /*
666          * Recommended maximum number of symbols transferred in a transfer unit:
667          * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
668          *              (output active video bandwidth in bytes))
669          * Must be less than tu_size.
670          */
671         max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
672
673         dev_dbg(tc->dev, "set mode %dx%d\n",
674                 mode->hdisplay, mode->vdisplay);
675         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
676                 left_margin, right_margin, hsync_len);
677         dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
678                 upper_margin, lower_margin, vsync_len);
679         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
680
681
682         /*
683          * LCD Ctl Frame Size
684          * datasheet is not clear of vsdelay in case of DPI
685          * assume we do not need any delay when DPI is a source of
686          * sync signals
687          */
688         tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
689                  OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
690         tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
691                          (ALIGN(hsync_len, 2) << 0));    /* Hsync */
692         tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) |  /* H front porch */
693                          (ALIGN(mode->hdisplay, 2) << 0)); /* width */
694         tc_write(VTIM01, (upper_margin << 16) |         /* V back porch */
695                          (vsync_len << 0));             /* Vsync */
696         tc_write(VTIM02, (lower_margin << 16) |         /* V front porch */
697                          (mode->vdisplay << 0));        /* height */
698         tc_write(VFUEN0, VFUEN);                /* update settings */
699
700         /* Test pattern settings */
701         tc_write(TSTCTL,
702                  (120 << 24) |  /* Red Color component value */
703                  (20 << 16) |   /* Green Color component value */
704                  (99 << 8) |    /* Blue Color component value */
705                  (1 << 4) |     /* Enable I2C Filter */
706                  (2 << 0) |     /* Color bar Mode */
707                  0);
708
709         /* DP Main Stream Attributes */
710         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
711         tc_write(DP0_VIDSYNCDELAY,
712                  (max_tu_symbol << 16) |        /* thresh_dly */
713                  (vid_sync_dly << 0));
714
715         tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
716
717         tc_write(DP0_STARTVAL,
718                  ((upper_margin + vsync_len) << 16) |
719                  ((left_margin + hsync_len) << 0));
720
721         tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
722
723         tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
724                  ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
725                  ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
726
727         tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
728                  DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
729
730         tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
731                            BPC_8);
732
733         return 0;
734 err:
735         return ret;
736 }
737
738 static int tc_link_training(struct tc_data *tc, int pattern)
739 {
740         const char * const *errors;
741         u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
742                       DP0_SRCCTRL_AUTOCORRECT;
743         int timeout;
744         int retry;
745         u32 value;
746         int ret;
747
748         if (pattern == DP_TRAINING_PATTERN_1) {
749                 srcctrl |= DP0_SRCCTRL_TP1;
750                 errors = training_pattern1_errors;
751         } else {
752                 srcctrl |= DP0_SRCCTRL_TP2;
753                 errors = training_pattern2_errors;
754         }
755
756         /* Set DPCD 0x102 for Training Part 1 or 2 */
757         tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
758
759         tc_write(DP0_LTLOOPCTRL,
760                  (0x0f << 28) | /* Defer Iteration Count */
761                  (0x0f << 24) | /* Loop Iteration Count */
762                  (0x0d << 0));  /* Loop Timer Delay */
763
764         retry = 5;
765         do {
766                 /* Set DP0 Training Pattern */
767                 tc_write(DP0_SRCCTRL, srcctrl);
768
769                 /* Enable DP0 to start Link Training */
770                 tc_write(DP0CTL, DP_EN);
771
772                 /* wait */
773                 timeout = 1000;
774                 do {
775                         tc_read(DP0_LTSTAT, &value);
776                         udelay(1);
777                 } while ((!(value & LT_LOOPDONE)) && (--timeout));
778                 if (timeout == 0) {
779                         dev_err(tc->dev, "Link training timeout!\n");
780                 } else {
781                         int pattern = (value >> 11) & 0x3;
782                         int error = (value >> 8) & 0x7;
783
784                         dev_dbg(tc->dev,
785                                 "Link training phase %d done after %d uS: %s\n",
786                                 pattern, 1000 - timeout, errors[error]);
787                         if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
788                                 break;
789                         if (pattern == DP_TRAINING_PATTERN_2) {
790                                 value &= LT_CHANNEL1_EQ_BITS |
791                                          LT_INTERLANE_ALIGN_DONE |
792                                          LT_CHANNEL0_EQ_BITS;
793                                 /* in case of two lanes */
794                                 if ((tc->link.base.num_lanes == 2) &&
795                                     (value == (LT_CHANNEL1_EQ_BITS |
796                                                LT_INTERLANE_ALIGN_DONE |
797                                                LT_CHANNEL0_EQ_BITS)))
798                                         break;
799                                 /* in case of one line */
800                                 if ((tc->link.base.num_lanes == 1) &&
801                                     (value == (LT_INTERLANE_ALIGN_DONE |
802                                                LT_CHANNEL0_EQ_BITS)))
803                                         break;
804                         }
805                 }
806                 /* restart */
807                 tc_write(DP0CTL, 0);
808                 usleep_range(10, 20);
809         } while (--retry);
810         if (retry == 0) {
811                 dev_err(tc->dev, "Failed to finish training phase %d\n",
812                         pattern);
813         }
814
815         return 0;
816 err:
817         return ret;
818 }
819
820 static int tc_main_link_setup(struct tc_data *tc)
821 {
822         struct drm_dp_aux *aux = &tc->aux;
823         struct device *dev = tc->dev;
824         unsigned int rate;
825         u32 dp_phy_ctrl;
826         int timeout;
827         u32 value;
828         int ret;
829         u8 tmp[8];
830
831         /* display mode should be set at this point */
832         if (!tc->mode)
833                 return -EINVAL;
834
835         tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
836         /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
837         tc_write(DP1_SRCCTRL,
838                  (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
839                  ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
840
841         rate = clk_get_rate(tc->refclk);
842         switch (rate) {
843         case 38400000:
844                 value = REF_FREQ_38M4;
845                 break;
846         case 26000000:
847                 value = REF_FREQ_26M;
848                 break;
849         case 19200000:
850                 value = REF_FREQ_19M2;
851                 break;
852         case 13000000:
853                 value = REF_FREQ_13M;
854                 break;
855         default:
856                 return -EINVAL;
857         }
858         value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
859         tc_write(SYS_PLLPARAM, value);
860
861         /* Setup Main Link */
862         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
863         if (tc->link.base.num_lanes == 2)
864                 dp_phy_ctrl |= PHY_2LANE;
865         tc_write(DP_PHY_CTRL, dp_phy_ctrl);
866         msleep(100);
867
868         /* PLL setup */
869         tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
870         tc_wait_pll_lock(tc);
871
872         tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
873         tc_wait_pll_lock(tc);
874
875         /* PXL PLL setup */
876         if (tc_test_pattern) {
877                 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
878                                     1000 * tc->mode->clock);
879                 if (ret)
880                         goto err;
881         }
882
883         /* Reset/Enable Main Links */
884         dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
885         tc_write(DP_PHY_CTRL, dp_phy_ctrl);
886         usleep_range(100, 200);
887         dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
888         tc_write(DP_PHY_CTRL, dp_phy_ctrl);
889
890         timeout = 1000;
891         do {
892                 tc_read(DP_PHY_CTRL, &value);
893                 udelay(1);
894         } while ((!(value & PHY_RDY)) && (--timeout));
895
896         if (timeout == 0) {
897                 dev_err(dev, "timeout waiting for phy become ready");
898                 return -ETIMEDOUT;
899         }
900
901         /* Set misc: 8 bits per color */
902         ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
903         if (ret)
904                 goto err;
905
906         /*
907          * ASSR mode
908          * on TC358767 side ASSR configured through strap pin
909          * seems there is no way to change this setting from SW
910          *
911          * check is tc configured for same mode
912          */
913         if (tc->assr != tc->link.assr) {
914                 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
915                         tc->assr);
916                 /* try to set ASSR on display side */
917                 tmp[0] = tc->assr;
918                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
919                 if (ret < 0)
920                         goto err_dpcd_read;
921                 /* read back */
922                 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
923                 if (ret < 0)
924                         goto err_dpcd_read;
925
926                 if (tmp[0] != tc->assr) {
927                         dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
928                                  tc->assr);
929                         /* trying with disabled scrambler */
930                         tc->link.scrambler_dis = 1;
931                 }
932         }
933
934         /* Setup Link & DPRx Config for Training */
935         ret = drm_dp_link_configure(aux, &tc->link.base);
936         if (ret < 0)
937                 goto err_dpcd_write;
938
939         /* DOWNSPREAD_CTRL */
940         tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
941         /* MAIN_LINK_CHANNEL_CODING_SET */
942         tmp[1] =  tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
943         ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
944         if (ret < 0)
945                 goto err_dpcd_write;
946
947         ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
948         if (ret)
949                 goto err;
950
951         ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
952         if (ret)
953                 goto err;
954
955         /* Clear DPCD 0x102 */
956         /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
957         tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
958         ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
959         if (ret < 0)
960                 goto err_dpcd_write;
961
962         /* Clear Training Pattern, set AutoCorrect Mode = 1 */
963         tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
964
965         /* Wait */
966         timeout = 100;
967         do {
968                 udelay(1);
969                 /* Read DPCD 0x202-0x207 */
970                 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
971                 if (ret < 0)
972                         goto err_dpcd_read;
973         } while ((--timeout) &&
974                  !(drm_dp_channel_eq_ok(tmp + 2,  tc->link.base.num_lanes)));
975
976         if (timeout == 0) {
977                 /* Read DPCD 0x200-0x201 */
978                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
979                 if (ret < 0)
980                         goto err_dpcd_read;
981                 dev_err(dev, "channel(s) EQ not ok\n");
982                 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
983                 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
984                          tmp[1]);
985                 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
986                 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
987                          tmp[4]);
988                 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
989                 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
990                          tmp[6]);
991
992                 return -EAGAIN;
993         }
994
995         ret = tc_set_video_mode(tc, tc->mode);
996         if (ret)
997                 goto err;
998
999         /* Set M/N */
1000         ret = tc_stream_clock_calc(tc);
1001         if (ret)
1002                 goto err;
1003
1004         return 0;
1005 err_dpcd_read:
1006         dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1007         return ret;
1008 err_dpcd_write:
1009         dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1010 err:
1011         return ret;
1012 }
1013
1014 static int tc_main_link_stream(struct tc_data *tc, int state)
1015 {
1016         int ret;
1017         u32 value;
1018
1019         dev_dbg(tc->dev, "stream: %d\n", state);
1020
1021         if (state) {
1022                 value = VID_MN_GEN | DP_EN;
1023                 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1024                         value |= EF_EN;
1025                 tc_write(DP0CTL, value);
1026                 /*
1027                  * VID_EN assertion should be delayed by at least N * LSCLK
1028                  * cycles from the time VID_MN_GEN is enabled in order to
1029                  * generate stable values for VID_M. LSCLK is 270 MHz or
1030                  * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1031                  * so a delay of at least 203 us should suffice.
1032                  */
1033                 usleep_range(500, 1000);
1034                 value |= VID_EN;
1035                 tc_write(DP0CTL, value);
1036                 /* Set input interface */
1037                 value = DP0_AUDSRC_NO_INPUT;
1038                 if (tc_test_pattern)
1039                         value |= DP0_VIDSRC_COLOR_BAR;
1040                 else
1041                         value |= DP0_VIDSRC_DPI_RX;
1042                 tc_write(SYSCTRL, value);
1043         } else {
1044                 tc_write(DP0CTL, 0);
1045         }
1046
1047         return 0;
1048 err:
1049         return ret;
1050 }
1051
1052 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1053 {
1054         struct tc_data *tc = bridge_to_tc(bridge);
1055
1056         drm_panel_prepare(tc->panel);
1057 }
1058
1059 static void tc_bridge_enable(struct drm_bridge *bridge)
1060 {
1061         struct tc_data *tc = bridge_to_tc(bridge);
1062         int ret;
1063
1064         ret = tc_main_link_setup(tc);
1065         if (ret < 0) {
1066                 dev_err(tc->dev, "main link setup error: %d\n", ret);
1067                 return;
1068         }
1069
1070         ret = tc_main_link_stream(tc, 1);
1071         if (ret < 0) {
1072                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1073                 return;
1074         }
1075
1076         drm_panel_enable(tc->panel);
1077 }
1078
1079 static void tc_bridge_disable(struct drm_bridge *bridge)
1080 {
1081         struct tc_data *tc = bridge_to_tc(bridge);
1082         int ret;
1083
1084         drm_panel_disable(tc->panel);
1085
1086         ret = tc_main_link_stream(tc, 0);
1087         if (ret < 0)
1088                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1089 }
1090
1091 static void tc_bridge_post_disable(struct drm_bridge *bridge)
1092 {
1093         struct tc_data *tc = bridge_to_tc(bridge);
1094
1095         drm_panel_unprepare(tc->panel);
1096 }
1097
1098 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1099                                  const struct drm_display_mode *mode,
1100                                  struct drm_display_mode *adj)
1101 {
1102         /* Fixup sync polarities, both hsync and vsync are active low */
1103         adj->flags = mode->flags;
1104         adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1105         adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1106
1107         return true;
1108 }
1109
1110 static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
1111                                    struct drm_display_mode *mode)
1112 {
1113         struct tc_data *tc = connector_to_tc(connector);
1114         u32 req, avail;
1115         u32 bits_per_pixel = 24;
1116
1117         /* DPI interface clock limitation: upto 154 MHz */
1118         if (mode->clock > 154000)
1119                 return MODE_CLOCK_HIGH;
1120
1121         req = mode->clock * bits_per_pixel / 8;
1122         avail = tc->link.base.num_lanes * tc->link.base.rate;
1123
1124         if (req > avail)
1125                 return MODE_BAD;
1126
1127         return MODE_OK;
1128 }
1129
1130 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1131                                const struct drm_display_mode *mode,
1132                                const struct drm_display_mode *adj)
1133 {
1134         struct tc_data *tc = bridge_to_tc(bridge);
1135
1136         tc->mode = mode;
1137 }
1138
1139 static int tc_connector_get_modes(struct drm_connector *connector)
1140 {
1141         struct tc_data *tc = connector_to_tc(connector);
1142         struct edid *edid;
1143         unsigned int count;
1144
1145         if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1146                 count = tc->panel->funcs->get_modes(tc->panel);
1147                 if (count > 0)
1148                         return count;
1149         }
1150
1151         edid = drm_get_edid(connector, &tc->aux.ddc);
1152
1153         kfree(tc->edid);
1154         tc->edid = edid;
1155         if (!edid)
1156                 return 0;
1157
1158         drm_connector_update_edid_property(connector, edid);
1159         count = drm_add_edid_modes(connector, edid);
1160
1161         return count;
1162 }
1163
1164 static void tc_connector_set_polling(struct tc_data *tc,
1165                                      struct drm_connector *connector)
1166 {
1167         /* TODO: add support for HPD */
1168         connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1169                             DRM_CONNECTOR_POLL_DISCONNECT;
1170 }
1171
1172 static struct drm_encoder *
1173 tc_connector_best_encoder(struct drm_connector *connector)
1174 {
1175         struct tc_data *tc = connector_to_tc(connector);
1176
1177         return tc->bridge.encoder;
1178 }
1179
1180 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1181         .get_modes = tc_connector_get_modes,
1182         .mode_valid = tc_connector_mode_valid,
1183         .best_encoder = tc_connector_best_encoder,
1184 };
1185
1186 static const struct drm_connector_funcs tc_connector_funcs = {
1187         .fill_modes = drm_helper_probe_single_connector_modes,
1188         .destroy = drm_connector_cleanup,
1189         .reset = drm_atomic_helper_connector_reset,
1190         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1191         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1192 };
1193
1194 static int tc_bridge_attach(struct drm_bridge *bridge)
1195 {
1196         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1197         struct tc_data *tc = bridge_to_tc(bridge);
1198         struct drm_device *drm = bridge->dev;
1199         int ret;
1200
1201         /* Create eDP connector */
1202         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1203         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1204                                  tc->panel ? DRM_MODE_CONNECTOR_eDP :
1205                                  DRM_MODE_CONNECTOR_DisplayPort);
1206         if (ret)
1207                 return ret;
1208
1209         if (tc->panel)
1210                 drm_panel_attach(tc->panel, &tc->connector);
1211
1212         drm_display_info_set_bus_formats(&tc->connector.display_info,
1213                                          &bus_format, 1);
1214         tc->connector.display_info.bus_flags =
1215                 DRM_BUS_FLAG_DE_HIGH |
1216                 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1217                 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1218         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1219
1220         return 0;
1221 }
1222
1223 static const struct drm_bridge_funcs tc_bridge_funcs = {
1224         .attach = tc_bridge_attach,
1225         .mode_set = tc_bridge_mode_set,
1226         .pre_enable = tc_bridge_pre_enable,
1227         .enable = tc_bridge_enable,
1228         .disable = tc_bridge_disable,
1229         .post_disable = tc_bridge_post_disable,
1230         .mode_fixup = tc_bridge_mode_fixup,
1231 };
1232
1233 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1234 {
1235         return reg != SYSCTRL;
1236 }
1237
1238 static const struct regmap_range tc_volatile_ranges[] = {
1239         regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1240         regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1241         regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1242         regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1243         regmap_reg_range(VFUEN0, VFUEN0),
1244 };
1245
1246 static const struct regmap_access_table tc_volatile_table = {
1247         .yes_ranges = tc_volatile_ranges,
1248         .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1249 };
1250
1251 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1252 {
1253         return (reg != TC_IDREG) &&
1254                (reg != DP0_LTSTAT) &&
1255                (reg != DP0_SNKLTCHGREQ);
1256 }
1257
1258 static const struct regmap_config tc_regmap_config = {
1259         .name = "tc358767",
1260         .reg_bits = 16,
1261         .val_bits = 32,
1262         .reg_stride = 4,
1263         .max_register = PLL_DBG,
1264         .cache_type = REGCACHE_RBTREE,
1265         .readable_reg = tc_readable_reg,
1266         .volatile_table = &tc_volatile_table,
1267         .writeable_reg = tc_writeable_reg,
1268         .reg_format_endian = REGMAP_ENDIAN_BIG,
1269         .val_format_endian = REGMAP_ENDIAN_LITTLE,
1270 };
1271
1272 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1273 {
1274         struct device *dev = &client->dev;
1275         struct tc_data *tc;
1276         int ret;
1277
1278         tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1279         if (!tc)
1280                 return -ENOMEM;
1281
1282         tc->dev = dev;
1283
1284         /* port@2 is the output port */
1285         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1286         if (ret && ret != -ENODEV)
1287                 return ret;
1288
1289         /* Shut down GPIO is optional */
1290         tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1291         if (IS_ERR(tc->sd_gpio))
1292                 return PTR_ERR(tc->sd_gpio);
1293
1294         if (tc->sd_gpio) {
1295                 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1296                 usleep_range(5000, 10000);
1297         }
1298
1299         /* Reset GPIO is optional */
1300         tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1301         if (IS_ERR(tc->reset_gpio))
1302                 return PTR_ERR(tc->reset_gpio);
1303
1304         if (tc->reset_gpio) {
1305                 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1306                 usleep_range(5000, 10000);
1307         }
1308
1309         tc->refclk = devm_clk_get(dev, "ref");
1310         if (IS_ERR(tc->refclk)) {
1311                 ret = PTR_ERR(tc->refclk);
1312                 dev_err(dev, "Failed to get refclk: %d\n", ret);
1313                 return ret;
1314         }
1315
1316         tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1317         if (IS_ERR(tc->regmap)) {
1318                 ret = PTR_ERR(tc->regmap);
1319                 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1320                 return ret;
1321         }
1322
1323         ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1324         if (ret) {
1325                 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1326                 return ret;
1327         }
1328
1329         if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1330                 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1331                 return -EINVAL;
1332         }
1333
1334         tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1335
1336         ret = tc_aux_link_setup(tc);
1337         if (ret)
1338                 return ret;
1339
1340         /* Register DP AUX channel */
1341         tc->aux.name = "TC358767 AUX i2c adapter";
1342         tc->aux.dev = tc->dev;
1343         tc->aux.transfer = tc_aux_transfer;
1344         ret = drm_dp_aux_register(&tc->aux);
1345         if (ret)
1346                 return ret;
1347
1348         ret = tc_get_display_props(tc);
1349         if (ret)
1350                 goto err_unregister_aux;
1351
1352         tc_connector_set_polling(tc, &tc->connector);
1353
1354         tc->bridge.funcs = &tc_bridge_funcs;
1355         tc->bridge.of_node = dev->of_node;
1356         drm_bridge_add(&tc->bridge);
1357
1358         i2c_set_clientdata(client, tc);
1359
1360         return 0;
1361 err_unregister_aux:
1362         drm_dp_aux_unregister(&tc->aux);
1363         return ret;
1364 }
1365
1366 static int tc_remove(struct i2c_client *client)
1367 {
1368         struct tc_data *tc = i2c_get_clientdata(client);
1369
1370         drm_bridge_remove(&tc->bridge);
1371         drm_dp_aux_unregister(&tc->aux);
1372
1373         tc_pxl_pll_dis(tc);
1374
1375         return 0;
1376 }
1377
1378 static const struct i2c_device_id tc358767_i2c_ids[] = {
1379         { "tc358767", 0 },
1380         { }
1381 };
1382 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1383
1384 static const struct of_device_id tc358767_of_ids[] = {
1385         { .compatible = "toshiba,tc358767", },
1386         { }
1387 };
1388 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1389
1390 static struct i2c_driver tc358767_driver = {
1391         .driver = {
1392                 .name = "tc358767",
1393                 .of_match_table = tc358767_of_ids,
1394         },
1395         .id_table = tc358767_i2c_ids,
1396         .probe = tc_probe,
1397         .remove = tc_remove,
1398 };
1399 module_i2c_driver(tc358767_driver);
1400
1401 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1402 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1403 MODULE_LICENSE("GPL");